CN116544117A - VDMOS device with high EAS and preparation method thereof - Google Patents
VDMOS device with high EAS and preparation method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of VDMOS devices, and particularly discloses a VDMOS device with high EAS and a preparation method thereof, comprising the following steps: step 1, manufacturing an N-type epitaxial layer on an N-type substrate; step 2, implanting P-type ions on the N-type epitaxial layer to form P strips; step 3, repeating the steps 1 and 2, and performing high-temperature junction pushing on a plurality of P strips formed on the plurality of N-type epitaxial layers to form P columns, wherein the plurality of N-type epitaxial layers and the P columns are provided with drift regions with different doping concentrations; the drift region with different doping concentrations comprises a plurality of concentration regions, and the doping concentrations of the concentration regions gradually decrease from the substrate to one side of the grid electrode. When the drift region is close to the N-type substrate, the avalanche current is diverted from the P region to the N region, the turning point of the avalanche current is far away from the P body region, the current density of the P body region can be smaller, and the starting of the parasitic transistor is restrained by changing the current path, so that the avalanche energy is improved.
Description
Technical Field
The invention relates to the technical field of VDMOS devices, in particular to a VDMOS device with high EAS and a preparation method thereof.
Background
VDMOS is an acoustic effect power transistor device, and VDMOS devices with high EAS refer to acoustic effect power transistor devices with high avalanche energy; in actual use, a part of the reason for the failure of the VDMOS device is that the parasitic transistor is turned on due to avalanche current, as shown in FIG. 1When avalanche breakdown occurs, the VDMOS device breaks down in the area near the point a, avalanche current reaches the source metal layer through the point a via the P body region 8, after the parasitic transistor is started, the avalanche current is amplified, the leakage current is increased, the temperature is increased, the parasitic resistance in the transverse direction of the P body region 8 is increased, the parasitic resistance generates heat, and the temperature is further increased, so that the device is invalid. Therefore, in order to make the parasitic transistor difficult to turn on, it is necessary to propose a VDMOS device with high EAS and a method for manufacturing the same, so as to at least partially solve the problems existing in the prior art.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
To at least partially solve the above problems, the present invention provides a VDMOS device with high EAS and a method for manufacturing the same, including:
s100, manufacturing an N-type epitaxial layer on an N-type substrate;
s200, implanting P-type ions on the N-type epitaxial layer to form P strips;
s300, repeating the steps S100 and S200, and performing high-temperature junction pushing on a plurality of P strips formed on a plurality of N-type epitaxial layers to form P columns, wherein the N-type epitaxial layers and the P columns are provided with drift regions with different doping concentrations;
the drift region with different doping concentrations comprises a plurality of concentration regions, and the doping concentrations of the concentration regions gradually decrease from the substrate to one side of the grid electrode.
Preferably, the plurality of concentration regions include at least: the first concentration region and the second concentration region, the doping concentration of the N-type epitaxial layer in the first concentration region is larger than that of the N-type epitaxial layer in the second concentration region, and the P-type ion implantation concentration in the first concentration region is larger than that in the second concentration region.
Preferably, the preparation of the first concentration region includes:
sequentially manufacturing a plurality of N-type epitaxial layers with first doping concentration on an N-type substrate;
p-type ions with first concentration are implanted into each N-type epitaxial layer with first doping concentration by using a mask plate, and P strips with first concentration are formed on each N-type epitaxial layer with first doping concentration.
Preferably, the preparation of the second concentration region includes:
sequentially manufacturing a plurality of N-type epitaxial layers with second doping concentration on the surface of a first concentration area positioned on one side close to the grid electrode;
and implanting P-type ions with a second concentration on each N-type epitaxial layer with the second doping concentration by using a mask plate, and forming P strips with the second concentration on each N-type epitaxial layer with the second doping concentration.
Preferably, the number of the N-type epitaxial layers with the first doping concentration sequentially manufactured on the N-type substrate is three, wherein the thicknesses of the second layer and the third layer are smaller than that of the first layer.
Preferably, the number of N-type epitaxial layers with the second doping concentration sequentially formed on the surface of the first concentration region near one side of the gate electrode is four, wherein the thicknesses of the first layer, the second layer and the third layer are all larger than that of the fourth layer.
Preferably, the determining of the first doping concentration of the N-type epitaxial layer and the first concentration of the P-type ions includes:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance with respect to the first doping concentration through a process simulation result;
the first doping concentration and the change in the first concentration are increased or decreased by a multiple of the concentration in the charge balance state;
and determining a first doping concentration of the N-type epitaxial layer and a first concentration of the P-type ions, wherein the first doping concentration and the first concentration of the P-type ions enable the breakdown voltage to meet a preset allowance and enable the avalanche energy to be improved to be within a preset range.
Preferably, the determining of the second doping concentration of the N-type epitaxial layer and the second concentration of the P-type ions includes:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance about the second doping concentration through a process simulation result;
the second doping concentration and the change in the second concentration are increased or decreased by a multiple of the concentration in the charge balance state;
and determining a second doping concentration of the N-type epitaxial layer and a second concentration of the P-type ions, wherein the second doping concentration and the second concentration of the P-type ions enable the breakdown voltage to meet a preset allowance and enable the avalanche energy to be improved to be within a preset range.
Preferably, in S300, the temperature of performing high-temperature junction pushing on the P strips formed on the N-type epitaxial layers is determined by the following method:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
wherein the process parameters include: the junction pushing temperature at high temperature, the doping concentration and the P-type ion implantation concentration of the N-type epitaxial layer in a plurality of concentration areas, the gate thickness and the gate length;
outputting a relation curve between the breakdown voltage and the specific on-resistance with respect to the high-temperature junction pushing temperature through a process simulation result;
and determining the temperature of the high-temperature push junction by using a relation curve between the breakdown voltage and the specific on-resistance.
A high EAS VDMOS device comprising: the N-type substrate, the drift region, the P body region and the grid are sequentially arranged, and a source region is formed between the two grids; wherein, the drift region is by multilayer N type epitaxial layer and P cylindricality, the drift region includes: a plurality of concentration regions having a gradually decreasing doping concentration from the N-type substrate to the gate electrode side;
the surface of the N-type substrate, which is away from the drift region, is provided with a first metal layer, and the surface of the grid electrode is provided with a second metal layer.
Compared with the prior art, the invention at least comprises the following beneficial effects:
according to the VDMOS device with high EAS and the preparation method thereof, the drift region with gradually reduced doping concentration from the N-type substrate to one side of the grid electrode is formed by adopting the injection of manufacturing the N-type epitaxial layer and the P-type ions for many times; the total thickness of the N-type epitaxial layers meets the requirement of pressure resistance, and a plurality of P strips are formed into P columns through high-temperature push-junction; the ion implantation does not need higher temperature, and the lateral diffusion is smaller, thereby being beneficial to reducing the specific on-resistance of the device; the more the repetition times of the steps S100 and S200 are, the more uniform the doping concentration is obtained after the high-temperature junction pushing is carried out on the concentration region with the same doping concentration; according to the method, when the N-type epitaxial layer is manufactured and the P-type ions are injected each time, the doping concentration of the N-type epitaxial layer and the injection dosage of the P-type ions can be adjusted according to the needs, the design can be carried out according to the use needs of actual devices, and the design flexibility is improved;
the device formed by the method is subjected to process simulation, and the avalanche current is diverted from the P region to the N region when the drift region is close to the N-type substrate, namely, compared with the prior art, the avalanche current has the advantages that the turning point of the avalanche current is far away from the P body region, the current density of the P body region is smaller, the parasitic transistor is restrained from being started by changing the current path, and therefore avalanche energy can be improved.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
fig. 1 is a schematic diagram of an NPN transistor formed from a prior art VDMOS device;
fig. 2 is a schematic diagram of a structure of a drift region with uniform doping concentration of a VDMOS device in the prior art;
FIG. 3 is a flow chart of a method of fabricating a VDMOS device with high EAS according to the present invention;
fig. 4 is a schematic structural diagram of a first N-type epitaxial layer fabricated in the method for fabricating a high EAS VDMOS device according to the present invention;
fig. 5 is a schematic structural diagram of a pad oxide layer fabricated in the method for fabricating a high EAS VDMOS device according to the present invention;
fig. 6 is a schematic diagram of P-type ion implantation by using a mask plate in the method for manufacturing a VDMOS device with high EAS according to the present invention;
fig. 7 is a schematic diagram of P strips formed by first implanting P-type ions in the method for manufacturing a VDMOS device with high EAS according to the present invention;
fig. 8 is a schematic diagram showing that the first concentration region is manufactured in the method for manufacturing a VDMOS device with high EAS according to the present invention;
fig. 9 is a schematic diagram of a second concentration region fabricated in a method for fabricating a high EAS VDMOS device according to the present invention;
fig. 10 is a schematic diagram showing a second concentration region manufactured in the method for manufacturing a VDMOS device with high EAS according to the present invention;
fig. 11 is a schematic diagram of a P column formed by performing high-temperature junction pushing in the method for manufacturing a VDMOS device with high EAS according to the present invention;
fig. 12 is a schematic structural diagram of a VDMOS device with high EAS according to the present invention.
Detailed Description
The present invention is described in further detail below with reference to the drawings and examples to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
As shown in fig. 3, the present invention provides a method for preparing a VDMOS device with high EAS, which includes:
s100, manufacturing an N-type epitaxial layer 2 on an N-type substrate 1;
s200, implanting P-type ions on the N-type epitaxial layer 2 to form P strips 3;
s300, repeating the steps S100 and S200, and performing high-temperature junction pushing on the P strips 3 formed on the N-type epitaxial layers 2 to form P columns 4, wherein the N-type epitaxial layers 2 and the P columns 4 form drift regions 5 with different doping concentrations;
the drift region 5 with different doping concentrations comprises a plurality of concentration regions, and the doping concentration of the plurality of concentration regions gradually decreases from the N-type substrate 1 to one side of the grid electrode 6.
As shown in fig. 2, which is a schematic diagram of a drift region of a VDMOS device in the prior art, unlike the prior art, in the above method, N-type epitaxial layer 2 and P-type ions are fabricated multiple times and implanted to form a drift region 5 with a doping concentration gradually decreasing from N-type substrate 1 to a gate 6 side; the total thickness of the N-type epitaxial layers 2 meets the requirement of pressure resistance, and the P strips 3 are formed into P columns 4 through high-temperature push-junction; the ion implantation does not need higher temperature, and the lateral diffusion is smaller, thereby being beneficial to reducing the specific on-resistance of the device; the more the repetition times of the steps S100 and S200 are, the more uniform the doping concentration is obtained after the high-temperature junction pushing is carried out on the concentration region with the same doping concentration; according to the method, when the N-type epitaxial layer 2 is manufactured and the P-type ions are implanted each time, the doping concentration of the N-type epitaxial layer 2 and the implantation dosage of the P-type ions can be adjusted according to the needs, the design can be carried out according to the use needs of actual devices, and the design flexibility is improved;
the device formed by the method is subjected to process simulation, and the avalanche current is diverted from the P region to the N region when the drift region 5 is close to the N-type substrate 1, namely, compared with the prior art, the distance between the turning point of the avalanche current and the P body region 8 is far, so that the current density of the P body region 8 is smaller, the starting of a parasitic transistor is restrained by changing a current path, and the avalanche energy is improved.
As shown in fig. 10, in one embodiment, the plurality of concentration regions includes at least: the doping concentration of the N-type epitaxial layer 2 in the first concentration region 51 is greater than the doping concentration of the N-type epitaxial layer 2 in the second concentration region 52, and the P-type ion implantation concentration in the first concentration region 51 is greater than the P-type ion implantation concentration in the second concentration region 52.
At least two concentration areas are provided, and in this embodiment, two concentration areas are described as an example;
the first concentration region 51 is disposed close to the N-type substrate 1, so that the doping concentration of the N-type epitaxial layer 2 and the P-type ion implantation concentration in the first concentration region 51 are both greater than those in the second concentration region 52, which is beneficial to improving avalanche energy;
if the concentration areas are three, the doping concentration of the N-type epitaxial layer 2 and the P-type ion implantation concentration in the three concentration areas are gradually reduced from the N-type substrate 1 to one side of the gate electrode 6, which will change the avalanche current path in the VDMOS device, so that the current density in the P-body area 8 is smaller, and the avalanche energy is further improved.
Further, the preparation of the first concentration region 51 includes:
sequentially manufacturing a plurality of N-type epitaxial layers 2 with first doping concentration on an N-type substrate 1;
p-type ions with a first concentration are implanted on each of the N-type epitaxial layers 2 with the first doping concentration by using the mask plate 12, and P-stripes 3 with the first concentration are formed on each of the N-type epitaxial layers 2 with the first doping concentration.
The preparation of the second concentration region 52 includes:
sequentially manufacturing a plurality of N-type epitaxial layers 2 with second doping concentration on the surface of a first concentration area 51 positioned on one side close to a grid electrode 6;
p-type ions with a second concentration are implanted on each of the N-type epitaxial layers 2 with the second doping concentration by using the mask plate 12, and P-stripes 3 with the second concentration are formed on each of the N-type epitaxial layers 2 with the second doping concentration.
As shown in fig. 4 to 11, the preparation of the first concentration region 51 and the second concentration region 52 is continuous, an N-type substrate 1 is prepared, a first N-type epitaxial layer 2 is fabricated on the N-type substrate 1, then a pad oxide layer 11 is grown, photo-etched, a first P-type ion implantation is performed, then photoresist is removed, the pad oxide layer 11 is removed, the above steps are repeated (the concentration of each N-type epitaxial layer 2 fabrication and P-type ion implantation is performed according to a preset doping concentration) until the final layer fabrication is completed, then the fabrication of the N-type epitaxial layer 2 is performed again, then a high-temperature junction pushing is performed, a P column 4 is formed by the plurality of P strips 3, the P column 4 is the P region of the drift region 5, and the N-type epitaxial layers 2 on both sides of the P column 4 are N columns, namely the N region of the drift region 5.
The increase of the number of times of type ion implantation and the number of manufacturing layers of the N-type epitaxial layer 2 is beneficial to the reduction of the specific on-resistance of the VDMOS device, so that the overall performance of the device is improved, the avalanche energy of the device is improved, but the difficulty of aligning the P-type ion implantation window is improved along with the increase of the number of manufacturing layers, so that the more the number of manufacturing layers is, the better the more the process conditions are, and the number of manufacturing layers is determined under the condition that the process conditions are limited, under the condition that the ion implantation window can be aligned.
After the drift region 5 is manufactured, the prior art can be adopted to finish the subsequent preparation of the device, and the drift region 5 is sequentially subjected to field oxide layer deposition, source region 7 and field injection hole etching, gate oxide layer growth, polysilicon deposition, P-type ion implantation of a P body region 8 taking polysilicon as a mask plate, and,Source region 7 ion implantation, P-plus ion implantation, reflow, contact hole etching, front and back metal layer fabrication, thereby forming a VDMOS device.
Further, under the condition of limited process conditions, taking a concentration area as two examples, the total number of layers of the N-type epitaxial layer 2 is 7, and 6 times of P-type ion implantation are needed to form P strips 3;
as shown in fig. 8, the number of N-type epitaxial layers 2 with the first doping concentration sequentially fabricated on the N-type substrate 1 is three, wherein the thicknesses of the second layer and the third layer are smaller than the thickness of the first layer.
As shown in fig. 10, the number of N-type epitaxial layers 2 with the second doping concentration sequentially formed on the surface of the first concentration region 51 located near the gate electrode 6 is four, wherein the thicknesses of the first layer, the second layer and the third layer are all greater than the thickness of the fourth layer.
Preferably, taking 600V as an example of the device withstand voltage requirement, and taking 10% -20% of breakdown voltage design allowance, the thicknesses of the three N-type epitaxial layers 2 with the first doping concentration are 8 microns of the first layer, 7.2 microns of the second layer and the third layer in sequence; the thickness of the four N-type epitaxial layers 2 with the second doping concentration is 3 microns of the fourth layer, and 7.2 microns of the first layer, the second layer and the third layer are sequentially formed.
In one embodiment, the first doping concentration of the N-type epitaxial layer 2 and the first concentration of the P-type ions, the second doping concentration of the N-type epitaxial layer 2 and the second concentration of the P-type ions, and the temperature at which the plurality of P-stripes 3 formed on the plurality of N-type epitaxial layers 2 are subjected to high-temperature junction pushing can be determined by process simulation software; inputting preset process parameters into process simulation software for modeling, wherein the process parameters comprise: the temperature of the high temperature push junction, the doping concentration and P-type ion implantation concentration of the N-type epitaxial layer 2 in the plurality of concentration regions, the gate 6 thickness, and the gate 6 length.
Further, the determining the first doping concentration of the N-type epitaxial layer 2 and the first concentration of the P-type ions includes:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance with respect to the first doping concentration through a process simulation result;
the first doping concentration and the change in the first concentration are increased or decreased by a multiple of the concentration in the charge balance state;
determining a first doping concentration of the N-type epitaxial layer 2 and a first concentration of P-type ions, which enable the breakdown voltage to meet a preset allowance and enable the avalanche energy to be increased to be within a preset range, by utilizing the relation curve;
finally determining the first doping concentration asThe first concentration is->。
The determining of the second doping concentration of the N-type epitaxial layer 2 and the second concentration of the P-type ions includes:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance about the second doping concentration through a process simulation result;
the second doping concentration and the change in the second concentration are increased or decreased by a multiple of the concentration in the charge balance state;
the second doping concentration of the N-type epitaxial layer 2 and the second concentration of the P-type ions, which are such that the breakdown voltage meets a predetermined margin and the avalanche energy is raised to within a predetermined range, are determined by using this relation.
Finally determining the first doping concentration asThe first concentration is->。
In S300, the temperature of performing high-temperature junction pushing on the P strips 3 formed on the N-type epitaxial layers 2 is determined by the following method:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance with respect to the high-temperature junction pushing temperature through a process simulation result;
and determining the temperature of the high-temperature push junction by using a relation curve between the breakdown voltage and the specific on-resistance.
And finally determining that the junction pushing temperature is 1200 ℃.
As shown in fig. 12, the present invention further provides a VDMOS device with high EAS obtained by using the method for manufacturing a VDMOS device with high EAS, including: the N-type substrate 1, the drift region 5, the P body region 8 and the grid electrodes 6 are sequentially arranged, and a source region 7 is formed between the two grid electrodes 6; wherein the drift region 5 is formed by a plurality of N-type epitaxial layers 2 and P-pillars 4, the drift region 5 comprising: a plurality of concentration regions in which the doping concentration gradually decreases from the N-type substrate 1 to the gate electrode 6 side;
when the drift region 5 is close to the N-type substrate 1, the avalanche current is diverted from the P region to the N region, and the structure changes the avalanche current path to inhibit the starting of the parasitic transistor, so that the turning point of the avalanche current is far away from the P body region 8, the current density of the P body region 8 is smaller, and the avalanche energy can be improved;
the surface of the N-type substrate 1 facing away from the drift region 5 is provided with a first metal layer 9, and the surface of the gate electrode 6 is provided with a second metal layer 10.
The thickness of the first metal layer 9 is smaller than that of the second metal layer 10, which is beneficial to heat dissipation of the VDMOS device, and this will further increase avalanche energy of the device.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (10)
1. A method for manufacturing a high EAS VDMOS device, comprising:
s100, manufacturing an N-type epitaxial layer on an N-type substrate;
s200, implanting P-type ions on the N-type epitaxial layer to form P strips;
s300, repeating the steps S100 and S200, and performing high-temperature junction pushing on a plurality of P strips formed on a plurality of N-type epitaxial layers to form P columns, wherein the N-type epitaxial layers and the P columns are provided with drift regions with different doping concentrations;
the drift regions with different doping concentrations comprise a plurality of concentration regions, and the doping concentrations of the concentration regions gradually decrease from the N-type substrate to one side of the grid electrode.
2. The method of manufacturing a high EAS VDMOS device of claim 1, wherein the plurality of concentration regions comprises at least: the first concentration region and the second concentration region, the doping concentration of the N-type epitaxial layer in the first concentration region is larger than that of the N-type epitaxial layer in the second concentration region, and the P-type ion implantation concentration in the first concentration region is larger than that in the second concentration region.
3. The method of manufacturing a high EAS VDMOS device of claim 2, wherein the manufacturing of the first concentration region comprises:
sequentially manufacturing a plurality of N-type epitaxial layers with first doping concentration on an N-type substrate;
p-type ions with a first concentration are implanted on each N-type epitaxial layer with the first doping concentration, and P strips with the first concentration are formed on each N-type epitaxial layer with the first doping concentration.
4. The method of manufacturing a high EAS VDMOS device of claim 2, wherein the manufacturing of the second concentration region comprises:
sequentially manufacturing a plurality of N-type epitaxial layers with second doping concentration on the surface of a first concentration area positioned on one side close to the grid electrode;
p-type ions with a second concentration are implanted on each N-type epitaxial layer with the second doping concentration, and P strips with the second concentration are formed on each N-type epitaxial layer with the second doping concentration.
5. The method for manufacturing a high EAS VDMOS device according to claim 3, wherein the number of N-type epitaxial layers having the first doping concentration sequentially formed on the N-type substrate is three, wherein the thicknesses of the second layer and the third layer are smaller than the thickness of the first layer.
6. The method for manufacturing a high EAS VDMOS device according to claim 4, wherein the number of N-type epitaxial layers having the second doping concentration sequentially formed on the surface of the first concentration region located at a side close to the gate electrode is four, and wherein the thicknesses of the first layer, the second layer and the third layer are each greater than the thickness of the fourth layer.
7. The method of manufacturing a high EAS VDMOS device of claim 3, wherein determining the first doping concentration of the N-type epitaxial layer and the first concentration of P-type ions comprises:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance with respect to the first doping concentration through a process simulation result;
and determining a first doping concentration of the N-type epitaxial layer and a first concentration of the P-type ions, wherein the first doping concentration and the first concentration of the P-type ions enable the breakdown voltage to meet a preset allowance and enable the avalanche energy to be improved to be within a preset range.
8. The method of manufacturing a high EAS VDMOS device of claim 4, wherein determining the second doping concentration of the N-type epitaxial layer and the second concentration of P-type ions comprises:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance about the second doping concentration through a process simulation result;
and determining a second doping concentration of the N-type epitaxial layer and a second concentration of the P-type ions, wherein the second doping concentration and the second concentration of the P-type ions enable the breakdown voltage to meet a preset allowance and enable the avalanche energy to be improved to be within a preset range.
9. The method for manufacturing a VDMOS device of claim 2, wherein in S300, the temperature of performing high-temperature junction pushing on the P strips formed on the N-type epitaxial layers is determined by:
inputting preset technological parameters into technological simulation software for modeling, and carrying out simulation on the technology of the device;
outputting a relation curve between the breakdown voltage and the specific on-resistance with respect to the high-temperature junction pushing temperature through a process simulation result;
and determining the temperature of the high-temperature push junction by using a relation curve between the breakdown voltage and the specific on-resistance.
10. A high EAS VDMOS device obtainable by the method of manufacturing a high EAS VDMOS device as claimed in any one of claims 1 to 9, comprising: the N-type substrate, the drift region, the P body region and the grid are sequentially arranged, and a source region is formed between the two grids; wherein, the drift region is by multilayer N type epitaxial layer and P cylindricality, the drift region includes: a plurality of concentration regions having a gradually decreasing doping concentration from the N-type substrate to the gate electrode side;
the surface of the N-type substrate, which is away from the drift region, is provided with a first metal layer, and the surface of the grid electrode is provided with a second metal layer.
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