CN116543706A

CN116543706A - Shift register, gate driving circuit and display device

Info

Publication number: CN116543706A
Application number: CN202210092805.8A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-01-26
Filing date: 2022-01-26
Publication date: 2023-08-04

Abstract

The disclosed embodiments provide a shift register including: the device comprises a voltage regulating circuit, a luminous cascade output circuit, a first luminous drive output circuit and a second luminous drive output circuit; the first light emitting drive output circuit is configured to write corresponding signals to the light emitting control drive signal output end according to the voltages at the first node and the second node, and the second light emitting drive output circuit is configured to respond to control of signals provided by the forced output control end and write first working voltage provided by the first power supply end to the light emitting control drive signal output end so that the light emitting control drive signal output end outputs an effective level signal. The embodiment of the disclosure also provides a gate driving circuit and a display device.

Description

Shift register, gate driving circuit and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, and a display device.

Background

Active matrix organic light emitting diode panels (Active Matrix Organic Light Emitting Diode, abbreviated as AMOLED) are becoming increasingly popular. The pixel display device of the AMOLED is an Organic Light-Emitting Diode (OLED), and the AMOLED is capable of Emitting Light by driving a thin film transistor to generate a driving current in a saturated state, and the driving current drives the Light-Emitting device to emit Light.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a shift register, including:

the voltage regulating circuit is connected with the luminous signal input end, the first clock signal end, the second clock signal end, the first node and the second node and is configured to respond to the control of signals provided by the luminous signal input end, the first clock signal end and the second clock signal end and regulate the voltages at the first node and the second node;

a light emitting cascade output circuit connected to a first power supply terminal, a second power supply terminal, a light emitting cascade signal output terminal, a first node, and a second node, configured to write a second operating voltage provided by the second power supply terminal to the light emitting cascade signal output terminal in response to control of a voltage at the first node, and to write a first operating voltage provided by the first power supply terminal to the light emitting cascade signal output terminal in response to control of a voltage at the second node;

A first light emitting drive output circuit connected to a first power supply terminal, a second power supply, a light emitting control drive signal output terminal, a second node, and a sixth node, configured to write a second operating voltage provided by the second power supply terminal to the light emitting control drive signal output terminal in response to control of a voltage at the sixth node, and write a first operating voltage provided by the first power supply terminal to the light emitting control drive signal output terminal in response to control of a voltage at the second node; the sixth node is connected with the first node;

the second light-emitting driving output circuit is connected with the first power supply end, the light-emitting control driving signal output end and the forced output control end and is configured to respond to the control of the signals provided by the forced output control end and write the first working voltage provided by the first power supply end into the light-emitting control driving signal output end.

In some embodiments, the shift register further comprises: the node control circuit is positioned between the sixth node and the first node, and the sixth node is connected with the first node through the node control circuit;

the node control circuit is further connected with the second power supply end and the forced output control end, and is configured to respond to control of signals provided by the forced output control end, so that the sixth node is disconnected from the first node and the second working voltage provided by the second power supply end is written into the sixth node.

In some embodiments, the node control circuit includes a first write sub-circuit, a second write sub-circuit, a twenty-fourth transistor, and a twenty-fifth transistor;

the first writing sub-circuit is connected with a second power supply end, the forced output control end and the control electrode of the twenty-fourth transistor and is configured to respond to the control of the signal provided by the forced output control end and write the second working voltage provided by the second power supply end into the control electrode of the twenty-fourth transistor;

the second writing sub-circuit is connected with a second power supply, the forced output control end and the sixth node and is configured to respond to the control of the signal provided by the forced output control end and write a second working voltage provided by the second power supply end into the sixth node;

a first pole of the twenty-fourth transistor is connected to the first node, and a second pole of the twenty-fourth transistor is connected to the sixth node;

the control electrode of the twenty-fifth transistor is connected with the first power supply end or the second clock signal end, the first electrode of the twenty-fifth transistor is connected with the control electrode of the twenty-fifth transistor, and the second electrode of the twenty-fifth transistor is connected with the second electrode of the twenty-sixth transistor.

In some embodiments, the first write sub-circuit includes a twenty-sixth transistor and the second write sub-circuit includes a twenty-seventh transistor;

the control electrode of the twenty-sixth transistor is connected with the forced output control end, the first electrode of the twenty-sixth transistor is connected with the second power supply end, and the second electrode of the twenty-sixth transistor is connected with the control electrode of the twenty-fourth transistor;

the control electrode of the twenty-seventh transistor is connected with the forced output control end, the first electrode of the twenty-seventh transistor is connected with the second power supply end, and the second electrode of the twenty-seventh transistor is connected with the sixth node.

In some embodiments, the forced output control terminal includes a first control terminal and a second control terminal;

the first write sub-circuit includes: two twenty-sixth transistors connected in series between the second power supply terminal and the control electrode of the twenty-fourth transistor, the second write sub-circuit comprising: two twenty-seventh transistors connected in series between the second power supply terminal and the sixth node;

a control electrode of one twenty-sixth transistor of the two twenty-sixth transistors is connected with the first control end, and a control electrode of the other twenty-sixth transistor of the two twenty-sixth transistors is connected with the second control end;

A control electrode of one twenty-seventh transistor of the two twenty-seventh transistors is connected with the first control end, and a control electrode of the other twenty-seventh transistor of the two twenty-seventh transistors is connected with the second control end.

In some embodiments, a twenty eighth transistor is further included;

the control electrode of the twenty-eighth transistor is connected with the second node, the first electrode of the twenty-eighth transistor is connected with the second power supply end, and the second electrode of the twenty-eighth transistor is connected with the sixth node.

In some embodiments, the second light emitting drive output circuit includes a twenty-third transistor;

the control electrode of the twenty-third transistor is connected with the forced output control end, the first electrode of the twenty-third transistor is connected with the first power end, and the second electrode of the twenty-third transistor is connected with the light-emitting control driving signal output end.

the second light emission drive output circuit includes: two twenty-third transistors connected in series between the first power supply terminal and the light emission control driving signal output terminal,

A control electrode of one twenty-third transistor of the two twenty-third transistors is connected with the first control end, and a control electrode of the other twenty-third transistor of the two twenty-third transistors is connected with the second control end.

In some embodiments, the voltage regulating circuit comprises:

the first input circuit is connected with the luminous signal input end, the first clock signal end and the second node and is configured to respond to the control of the signal provided by the first clock signal end and write the signal provided by the luminous signal input end into the second node;

the second input circuit is connected with a first clock signal end, a first power end and a second node and is configured to write a first working voltage provided by the first power end into a third node in response to control of signals provided by the first clock signal end and write signals provided by the first clock signal end into the third node in response to control of voltages at the second node;

a first voltage control circuit connected to a second clock signal terminal, a second power supply terminal, a first node, a second node, and a third node, configured to write a signal provided by the second clock signal terminal to the first node in response to control of a voltage at the third node and a signal provided by the second clock signal terminal, and to write a second operating voltage provided by the second power supply terminal to the first node in response to control of a voltage at the second node;

And the second voltage control circuit is connected with a second clock signal end, a second power supply end and a third node and is configured to respond to the voltage at the third node and the signal provided by the second clock signal end to write the second working voltage provided by the second power supply end into the second node.

In some embodiments, the first input circuit includes a first transistor, the second input circuit includes a second transistor and a third transistor, the first voltage control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitance, the second voltage control circuit includes a seventh transistor and an eighth transistor, the light emitting cascode output circuit includes a ninth transistor and a tenth transistor, the first light emitting driving output circuit includes a twenty-first transistor and a twenty-second transistor;

the control electrode of the first transistor is connected with a first clock signal end, the first electrode of the first transistor is connected with a light-emitting signal input end, and the second electrode of the first transistor is connected with the second node;

the control electrode of the second transistor is connected with the first clock signal end, the first electrode of the second transistor is connected with the second power supply end, and the second electrode of the second transistor is connected with the third node;

A control electrode of the third transistor is electrically connected with the second node, a first electrode of the third transistor is connected with the third node, and a second electrode of the third transistor is connected with the first clock signal end;

the control electrode of the fourth transistor is connected with the third node, the first electrode of the fourth transistor is connected with the second clock signal end, and the second electrode of the fourth transistor is connected with the fourth node;

the control electrode of the fifth transistor is connected with the second clock signal end, the first electrode of the fifth transistor is connected with the fourth node, and the second electrode of the fifth transistor is connected with the first node;

the control electrode of the sixth transistor is connected with the second node, the first electrode of the sixth transistor is connected with the first node, and the second electrode of the sixth transistor is connected with the second power supply end;

the first end of the third capacitor is connected with the third node, and the second end of the third capacitor is connected with the fourth node;

a control electrode of the seventh transistor is connected with the third node, a first electrode of the seventh transistor is connected with a second power supply end, and a second electrode of the seventh transistor is connected with a first electrode of the eighth transistor;

The control electrode of the eighth transistor is connected with the second clock signal end, and the second electrode of the eighth transistor is connected with the second node;

the control electrode of the ninth transistor is connected with the first node, the first electrode of the ninth transistor is connected with the second power supply end, and the second electrode of the ninth transistor is connected with the light-emitting cascade signal output end;

the control electrode of the tenth transistor is connected with the second node, the first electrode of the tenth transistor is connected with the luminous cascade signal output end, and the second electrode of the tenth transistor is connected with the first power supply end;

the control electrode of the twenty-first transistor is connected with the sixth node, the first electrode of the twenty-first transistor is connected with the second power supply end, and the second electrode of the twenty-first transistor is connected with the light-emitting control driving signal output end;

the control electrode of the second transistor is connected with the second node, the first electrode of the second transistor is connected with the light-emitting control driving signal output end, and the second electrode of the second transistor is connected with the first power supply end.

In some embodiments, the voltage regulating circuit further includes a first anti-leakage circuit, the first input circuit, the second input circuit, and the second node control voltage are connected to a fifth node, the first anti-leakage circuit is located between the fifth node and the second node, and the first input circuit, the second input circuit, and the second voltage control circuit are all connected to the second node through the first anti-leakage circuit;

The first anti-leakage circuit is further connected with the first power end and the third power end, and is configured to write a third working voltage provided by the third power end into a first anti-leakage node under the control of the voltage at the second node, wherein the first anti-leakage node is positioned between the second node and the fifth node;

and/or the voltage regulating circuit further comprises a second anti-leakage circuit, the output circuit is connected with a second power supply end through the second anti-leakage circuit, and the output circuit and the second anti-leakage circuit are connected with a second anti-leakage node;

the second anti-leakage circuit is further connected with a first node, a first power end and a second power end, and is further connected with a light-emitting cascading signal output end or a light-emitting control driving signal output end, and the second anti-leakage circuit is configured to respond to the control of the voltage at the light-emitting cascading signal output end or the light-emitting control driving signal output end and write the first working voltage provided by the first power end into the second anti-leakage node;

and/or, the voltage regulating circuit further comprises: and the luminous global reset circuit is connected with the luminous global reset signal end, the first power end and the second node and is configured to respond to the control of signals provided by the luminous global reset signal end to write the first working voltage provided by the first power end into the second node.

In some embodiments, the first anti-leakage circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

the control electrode of the eleventh transistor is connected with the first power supply end, the first electrode of the eleventh transistor is connected with a fifth node, and the second electrode of the eleventh transistor is connected with the first anti-leakage node;

the control electrode of the twelfth transistor is connected with the first power supply end, the first electrode of the twelfth transistor is connected with the first anti-leakage node, and the second electrode of the twelfth transistor is connected with the second node;

the control electrode of the thirteenth transistor is connected with the second node, the first electrode of the thirteenth transistor is connected with the third power supply end, and the second electrode of the thirteenth transistor is connected with the first anti-leakage node;

the second anticreep circuit includes a fourteenth transistor and a fifteenth transistor;

a control electrode of the fourteenth transistor is connected with the first node, a first electrode of the fourteenth transistor is connected with the second power supply end, and a second electrode of the fourteenth transistor is connected with the second anti-leakage node;

The control electrode of the fifteenth transistor is connected with the light-emitting cascade signal output end or the light-emitting control driving signal output end, the first electrode of the fifteenth transistor is connected with the first power supply end, and the second electrode of the fifteenth transistor is connected with the second anti-leakage node;

the light-emitting global reset circuit includes a sixteenth transistor;

the control electrode of the sixteenth transistor is connected with the luminous global reset signal end, the first electrode of the sixteenth transistor is connected with the second node, and the second electrode of the sixteenth transistor is connected with the first power end.

In a second aspect, embodiments of the present disclosure further provide a gate driving circuit, including: a plurality of first shift registers in cascade, the first shift registers employing the shift registers provided in the first aspect described above;

the signal input end of the first shift register positioned at the first stage is connected with a light-emitting initial signal line, and the first shift registers of other stages except the first stage are connected with the light-emitting cascade signal output ends of the first shift registers of the respective previous stages;

the light emission control driving signal output end of each first shift register is connected with a corresponding light emission control signal line.

In a third aspect, an embodiment of the present disclosure further provides a display apparatus, including: the display area comprises a plurality of pixel units which are arranged in an array, wherein each row of pixel units is provided with a corresponding light-emitting control signal line, and the light-emitting control signal line is connected with a control electrode of a light-emitting control transistor in the corresponding pixel unit;

the peripheral region includes a first gate driving circuit, and the first gate driving circuit adopts the gate driving circuit provided in the second aspect.

In some embodiments, each row of pixel cells is further configured with a corresponding second gate line connected to a control electrode of a sense transistor within the corresponding pixel cell;

the peripheral region further includes a second gate driving circuit including: the cascade connection multiple second shift registers are provided with second grid driving signal output ends which are connected with the corresponding second grid lines;

the second shift register comprises a first display precharge reset circuit, a sensing cascade circuit, a first sensing precharge reset circuit, a first pull-down control circuit, a gate cascade output circuit and a second gate drive output circuit;

The first display precharge reset circuit, the first sensing precharge reset circuit, the first pull-down control circuit, the gate cascade output circuit and the second gate drive output circuit are connected to a first pull-up node, and the first pull-down control circuit, the gate cascade output circuit and the second gate drive output circuit are connected to a first pull-down node;

the first display precharge reset circuit is connected with a display signal input end, a display reset signal end and a fifth power end, and is configured to write a signal provided by the display signal input end into the first pull-up node in response to control of a signal provided by the display signal input end, and write a fifth working voltage provided by the fifth power end into the first pull-down node in response to control of a signal provided by the display reset signal end;

the sensing cascade circuit is connected with the sensing signal input end and the random signal end and is configured to respond to the control of the signals provided by the random signal end and write the signals provided by the sensing signal input end into the sensing cascade node;

The first sensing precharge reset circuit is connected with a third clock signal end, a sensing reset signal end and a fifth power supply end, and is configured to write a signal provided by the third clock signal end into a sensing precharge node in response to control of a voltage provided by the sensing cascade node, write the voltage provided by the sensing precharge node into the first pull-up node in response to control of the signal provided by the third clock signal end, and write a fifth working voltage provided by the fifth power supply end into the first pull-up node in response to control of the signal provided by the sensing reset signal end;

the first pull-down control circuit is connected with a fourth power end and a fifth power end and is configured to write a voltage which is opposite to the voltage at the first pull-up node into the first pull-down node;

the gate cascade output circuit is connected with a cascade clock signal end, a fifth power supply end and a gate cascade signal output end and is configured to write a signal provided by the cascade clock signal end into the gate cascade signal output end in response to the control of the voltage at the first pull-up node and write a fifth working voltage provided by the fifth power supply end into the gate cascade signal output end in response to the control of the voltage at the first pull-down node;

The second gate driving output circuit is connected with a second driving clock signal end and a sixth power end, and is configured to write a signal provided by the second driving clock signal end to the second gate driving signal output end in response to control of the voltage at the first pull-up node, and write a sixth working voltage provided by the sixth power end to the second gate driving signal output end in response to control of the voltage at the first pull-down node.

In some embodiments, in the first gate driving circuit, the forced output control terminal to which any one of the first shift registers is connected includes: a second gate driving signal output terminal or a gate cascade signal output terminal configured to correspond to a second shift register of the same row of pixel units as the first shift register;

alternatively, the first shift register is the shift register of claim 5 or 8, and in the first gate driving circuit, the first control terminal and the second control terminal connected to any one of the first shift registers are respectively: the sensing cascade node and a preconfigured fourth clock signal terminal inside a second shift register corresponding to the same row of pixel units as the first shift register.

In some embodiments, the second shift register is configured with a fourth gate driving signal output terminal connected to the corresponding second gate line;

the second shift register further comprises a second display precharge reset circuit, a second sensing precharge reset circuit, a second pull-down control circuit and a fourth gate drive output circuit; the second display precharge reset circuit, the second sensing precharge reset circuit, the second pull-down control circuit and the fourth gate drive output circuit are connected to a second pull-up node, and the second pull-down control circuit and the fourth gate drive output circuit are connected to a second pull-down node;

the second display precharge reset circuit is connected with a display signal input end, a display reset signal end and a fifth power end, and is configured to write a signal provided by the display signal input end into the second pull-up node in response to control of a signal provided by the display signal input end, and write a fifth working voltage provided by the fifth power end into the second pull-down node in response to control of a signal provided by the display reset signal end;

the second sensing precharge reset circuit is connected with a sensing precharge signal end, a third clock signal end, a sensing reset signal end and a fifth power supply end, and is configured to write a voltage at the sensing precharge node to the second pull-up node in response to control of a signal provided by the third clock signal end and write a fifth working voltage provided by the fifth power supply end to the second pull-up node in response to control of a signal provided by the sensing reset signal end;

The second pull-down control circuit is connected with a seventh power end and a fifth power end and is configured to write a voltage which is opposite to the voltage at the second pull-up node into the second pull-down node;

the fourth gate driving output circuit is connected with a fourth driving clock signal end and a sixth power end, and is configured to write a signal provided by the fourth driving clock signal end to the fourth gate driving signal output end in response to control of the voltage at the second pull-up node, and write a sixth working voltage provided by the sixth power end to the fourth gate driving signal output end in response to control of the voltage at the second pull-down node.

In some embodiments, the second shift register further comprises: a blank valid output circuit;

the blank effective output circuit is connected with the first pull-up node, the first pull-down node, a blank effective clock signal end, a blank effective signal output end and a sixth power end, and is configured to write a signal provided by the blank effective clock signal end into the blank effective signal output end in response to the control of the voltage at the first pull-up node and write a sixth working voltage provided by the sixth power end into the blank effective signal output end in response to the control of the voltage at the first pull-down node;

Or, the blank valid output circuit is connected with the second pull-up node, the second pull-down node, a blank valid clock signal end, a blank valid signal output end and a sixth power supply end, and is configured to write a signal provided by the blank valid clock signal end into the blank valid signal output end in response to control of a voltage at the second pull-up node, and write a sixth working voltage provided by the sixth power supply end into the blank valid signal output end in response to control of the voltage at the second pull-down node;

in the first gate driving circuit, the forced output control terminal to which any one of the first shift registers is connected includes: and the blank valid signal output end is configured by a second shift register corresponding to the pixel units in the same row as the first shift register.

In some embodiments, each row of pixel cells is further configured with a corresponding first gate line connected to a control electrode of a data writing transistor within the corresponding pixel cell;

the second shift register further comprises a first gate drive output circuit and a third gate drive output circuit;

the first gate driving output circuit is connected with the first pull-up node, the first pull-down node, a first gate driving signal output end, a first driving clock signal end and a sixth power end, and is configured to write a signal provided by the first driving clock signal end into the first gate driving signal output end in response to control of a voltage at the first pull-up node and write a sixth working voltage provided by the sixth power end into the first gate driving signal output end in response to control of the voltage at the first pull-down node;

The third gate driving output circuit is connected with the second pull-up node, the second pull-down node, a third gate driving signal output end, a third driving clock signal end and a sixth power end, and is configured to write a signal provided by the third driving clock signal end into the third gate driving signal output end in response to control of a voltage at the second pull-up node and write a sixth working voltage provided by the sixth power end into the third gate driving signal output end in response to control of the voltage at the second pull-down node;

the first gate driving signal output end and the third gate driving signal output end are respectively connected with the corresponding first gate lines.

Drawings

FIG. 1 is a schematic diagram of a circuit structure of a pixel unit in a display substrate according to the related art;

FIG. 2 is a timing diagram illustrating operation of the pixel unit shown in FIG. 1;

FIG. 3 is a schematic diagram of another circuit structure of a pixel unit in a display substrate according to the related art;

FIG. 4A is a timing diagram illustrating operation of the pixel unit shown in FIG. 3;

FIG. 4B is a timing diagram illustrating an operation of the pixel unit of FIG. 3 for performing external compensation sensing during a blank period;

FIG. 5 is a schematic circuit diagram of a first shift register according to an embodiment of the disclosure;

Fig. 6 is a driving timing chart of a light emission control gate driving circuit according to the related art;

FIG. 7 is a drive timing diagram of a light emitting control gate drive circuit according to the present disclosure;

FIG. 8 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 9 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 10 is a timing diagram illustrating operation of the first shift register of FIG. 9;

FIG. 11 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 12 is a timing diagram illustrating operation of the first shift register of FIG. 11;

FIG. 13 is a timing diagram illustrating another operation of the first shift register shown in FIG. 11;

FIG. 14 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 15 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 16 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 17 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 18 is a schematic diagram of another circuit configuration of the first shift register according to the embodiment of the disclosure;

FIG. 19 is a schematic diagram showing another circuit configuration of the first shift register according to the embodiment of the disclosure;

fig. 20 is a schematic circuit diagram of a gate driving circuit according to an embodiment of the disclosure;

fig. 21 is a schematic structural diagram of a display device according to an embodiment of the disclosure;

FIG. 22 is a schematic diagram of a circuit configuration of a second shift register according to an embodiment of the disclosure;

FIG. 23 is a schematic diagram showing another circuit configuration of the second shift register according to the embodiment of the disclosure;

FIG. 24 is a timing diagram illustrating operation of the second shift register of FIG. 23;

FIG. 25A is a timing diagram of one operation of the cascade clock signal terminal, the second drive clock signal terminal, the gate cascade signal output terminal, and the second gate drive signal output terminal in an embodiment of the present disclosure;

FIG. 25B is another operational timing diagram of the cascade clock signal terminal, the second driving clock signal terminal, the gate cascade signal output terminal, and the second gate driving signal output terminal in an embodiment of the disclosure;

FIG. 25C is a timing diagram illustrating operation of the sense cascode node, the fourth clock signal terminal, and the second gate drive signal output terminal according to an embodiment of the present disclosure;

FIG. 26 is a schematic diagram of a second shift register according to an embodiment of the present disclosure;

FIG. 27 is a timing diagram of the operation of the first driving clock signal terminal, the second driving clock signal terminal, the first gate driving signal output terminal, and the second gate driving signal output terminal according to the embodiment of the present disclosure;

FIG. 28 is a schematic diagram of a second shift register according to an embodiment of the present disclosure;

fig. 29 is a schematic diagram of still another circuit structure of the second shift register according to the embodiment of the disclosure;

fig. 30 is a schematic circuit diagram of a circuit structure in which two pixel units located in adjacent rows share the same light emission control transistor in an embodiment of the disclosure.

Detailed Description

In order to enable those skilled in the art to better understand the technical scheme of the present invention, a shift register, a gate driving circuit and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not limited to physical or mechanical coupling, but may include electrical connection, whether direct or indirect.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the drain and source of each transistor may be coupled interchangeably, so that the drain and source of each transistor are virtually indistinguishable in the embodiments of the present disclosure. Here, only in order to distinguish between two electrodes of a transistor except a control electrode (i.e., a gate electrode), one of the electrodes is called a drain electrode and the other is called a source electrode. The thin film transistor adopted in the embodiment of the disclosure may be an N-type transistor or a P-type transistor. In the embodiment of the disclosure, when an N-type thin film transistor is used, the first pole may be a source electrode and the second pole may be a drain electrode. In the following embodiments, a thin film transistor is described as an example of an N-type transistor.

In the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on after being input to the control electrode of the transistor, and a "inactive level signal" refers to a signal that can control the transistor to be turned off after being input to the control electrode of the transistor. For an N-type transistor, the high level signal is an active level signal, and the low level signal is an inactive level signal; for a P-type transistor, the low level signal is an active level signal and the high level signal is an inactive level signal.

In the following description, a transistor will be described as an example of an N-type transistor, where an active level signal means a high level signal and an inactive level signal means a low level signal. It is conceivable that when a P-type transistor is employed, the timing variation of the control signal needs to be adjusted accordingly. Specific details are not set forth herein but are intended to be within the scope of the present disclosure.

Fig. 1 is a schematic circuit diagram of a pixel unit in a display substrate according to the related art, and fig. 2 is a timing chart of operation of the pixel unit shown in fig. 1, and as shown in fig. 1 and 2, the pixel circuit has a 3T1C structure, i.e., includes three transistors (a data writing transistor QTFT, a driving transistor DTFT, a sensing transistor STFT) and 1 capacitor (a storage capacitor Cst). The control electrode of the DATA writing transistor QTFT is connected to the first gate line G1, the first electrode of the DATA writing transistor QTFT is connected to the DATA line DATA, the control electrode of the sensing transistor STFT is connected to the second gate line G2, and the first electrode of the sensing transistor STFT is connected to the sensing line SENCE.

For a single pixel cell, it needs to go through a write display data phase and a light emitting phase during one frame; during the stage of writing display Data, the first gate line G1 controls the Data writing transistor QTFT to be turned on, and the Data line Data writes the Data voltage Vdata to the control electrode of the driving transistor DTFT; in the light emitting stage, the driving transistor DTFT outputs a corresponding driving current according to the voltage at its own control electrode to drive the light emitting element OLED to emit light.

In addition, a Blank period (also referred to as a Blank period) is generally configured between two adjacent frames, and at this time, one frame includes a display driving period and a Blank period, and the Blank period is generally used for externally compensating and sensing a certain pixel unit row at random.

In the pixel unit shown in fig. 1, the display brightness of the light emitting element OLED in one frame can be controlled only by the data voltage Vdata, which is output from the IC, and the problem of low gray scale spread cannot be caused if the IC accuracy is insufficient. For example, the IC accuracy is 0.1V, and the data voltage of 0.1V corresponds to the gray level L20, and at this time, the IC cannot accurately output the gray levels L1 to L19.

In order to solve the above technical problems, the related art improves the circuit structure of the pixel unit. Fig. 3 is a schematic diagram of another circuit structure of a pixel unit in a display substrate according to the related art, fig. 4A is a timing chart of operation of the pixel unit shown in fig. 3, fig. 4B is a timing chart of operation of the pixel unit shown in fig. 3 for performing external compensation sensing in a blank period, and as shown in fig. 3 to fig. 4B, the new pixel unit provided in the related art is a 4T1C structure, which includes not only the data writing transistor QTFT, the driving transistor DTFT, the sensing transistor STFT, but also the light emission control transistor ETFT in fig. 1. As an example, referring to fig. 3, the light emission control transistor ETFT is disposed between the driving transistor DTFT and the power source terminal ELVDD, and a control electrode of the light emission control transistor ETFT is connected to a light emission control signal line. As yet another example, the light emission control transistor may be disposed between the driving transistor DTFT and the light emitting device OLED (the corresponding drawing is not given).

Referring to fig. 4A, for a single pixel unit, the light emission control transistor ETFT is controlled to be turned on or off through the light emission control signal line during the light emission period, so that the lighting time of the light emitting element OLED in the light emission period can be controlled, and thus the equivalent luminance (i.e., the luminance perceived by the human eye, also referred to as the sense luminance) of the light emitting element OLED in one frame can be controlled. Specifically, the light-emitting stage includes a lighting stage and a black insertion stage, and the light-emitting control signal includes a light-emitting drive signal and a black insertion drive signal; during the lighting stage, a lighting driving signal (namely an effective level signal) is provided by a lighting control signal line to control the lighting control transistor ETFT to be conducted, and at the moment, the driving transistor can normally output driving current, and the lighting element OLED emits light; the light emission control transistor ETFT is controlled to be turned off by providing a black insertion driving signal (i.e., a non-active level signal) through the light emission control signal line during the black insertion stage, and at this time, the driving transistor DTFT does not have a driving current output, and the light emitting element does not emit light. In general, the longer the total duration of the black insertion stage, the lower the equivalent luminance of the light emitting element.

Fig. 4A exemplarily shows a case where 2 black inserting stages are included in the light emitting stage, but of course, in practical application, the light emitting stage may also include 1 black inserting stage, 3 black inserting stages, or more black inserting stages.

As can be seen from the above, the light emitting element can display the brightness corresponding to the lower gray scale by setting the light emitting control transistor ETFT, so that the problem that the pixel unit cannot display the low gray scale brightness due to insufficient IC precision is effectively solved. However, in practical use, it has been found that since all shift registers inside a gate driving circuit (also commonly referred to as a light emission control gate driving circuit) for providing a black insertion driving signal are sequentially cascade-connected, the gate driving circuit for providing a black insertion driving signal outputs a black insertion driving signal to each light emission control signal line sequentially without interruption. At this time, it inevitably occurs that the time when the light emission control signal lines corresponding to some rows of pixel units receive the black insertion driving signal is within the blank period. As can be seen from the timing sequence shown in fig. 4B, when external compensation sensing is performed on a certain row of pixel units, the signal provided by the light-emitting control signal line connected to the row of pixel units is required to be a light-emitting driving signal (i.e. an active level signal) all the time. Therefore, external compensation sensing cannot be performed for the pixel cell rows that receive the black insertion driving signal in the blank period. That is, the related art cannot support random external compensation sensing in a blank period.

In order to effectively solve the problem that the related art cannot support random external compensation sensing in a blank period, embodiments of the present disclosure provide a shift register, and inventive principles of the present disclosure will be described in detail with reference to specific embodiments. It should be noted that, to distinguish the shift register from the shift registers in other gate driving circuits on the display device, the shift register in the light emission control gate driving circuit is referred to as a first shift register in this disclosure, and the first shift register may be used to provide the light emission control signal (including the light emission driving signal and the black insertion driving signal) to the corresponding light emission control signal line.

Fig. 5 is a schematic circuit diagram of a first shift register according to an embodiment of the disclosure, where, as shown in fig. 5, the first shift register includes: a voltage regulating circuit 20, a light emitting cascade output circuit 25, a first light emitting drive output circuit 29 and a second light emitting drive output circuit 30.

The voltage regulating circuit 20 is connected to the light emitting signal INPUT terminal INPUT, the first clock signal terminal CKA, the second clock signal terminal CKB, the first node N1, and the second node N2, and the voltage regulating circuit 20 is configured to regulate voltages at the first node N1 and the second node N2 in response to control signals provided by the light emitting signal INPUT terminal INPUT, the first clock signal terminal CKA, and the second clock signal terminal CKB.

The light emitting cascade output circuit 25 is connected to the first power source terminal, the second power source terminal, the light emitting cascade signal output terminal CR, the first node N1, and the second node N2, and the light emitting cascade output circuit 25 is configured to write the second operating voltage provided by the second power source terminal to the light emitting cascade signal output terminal CR in response to control of the voltage at the first node N1, and to write the first operating voltage provided by the first power source terminal to the light emitting cascade signal output terminal CR in response to control of the voltage at the second node N2.

The first light emitting driving output circuit 29 is connected to the first power supply terminal, the second power supply, the light emitting control driving signal output terminal OUT, the second node N2, and the sixth node N6, and the first light emitting driving output circuit 29 is configured to write the second operating voltage provided by the second power supply terminal into the light emitting control driving signal output terminal OUT in response to the control of the voltage at the sixth node N6, and write the first operating voltage provided by the first power supply terminal into the light emitting control driving signal output terminal OUT in response to the control of the voltage at the second node N2; the sixth node N6 is connected to the first node N1.

The second light emitting driving output circuit 30 is connected to the first power supply terminal, the light emitting control driving signal output terminal OUT, and the forced output control terminal CSD, and the second light emitting driving output circuit 30 is configured to write the first operating voltage provided by the first power supply terminal into the light emitting control driving signal output terminal OUT in response to control of the signal provided by the forced output control terminal CSD.

In the embodiment of the disclosure, the first working voltage provided by the first power supply terminal is an effective level signal, and when the second light-emitting driving circuit is in an operating state and writes the first working voltage into the light-emitting control driving signal output terminal OUT, no matter what voltage is output by the first light-emitting driving circuit to the light-emitting control driving signal output terminal OUT, the light-emitting control driving signal output terminal OUT always outputs a light-emitting driving signal (i.e., an effective level signal). When the second light-emitting driving circuit is in a non-working state, the signal output by the light-emitting control driving signal output end OUT is influenced by the first light-emitting driving circuit.

In the embodiment of the present disclosure, the light emission cascade signal output terminal CR and the light emission control driving signal output terminal OUT of the first shift register are respectively set, wherein the light emission cascade output circuit 25 is used for controlling the output of the light emission cascade signal output terminal CR, and the first light emission driving output circuit 29 and the second light emission driving output circuit 30 jointly control the output of the light emission control driving signal output terminal OUT; that is, the light emission cascade signal and the light emission control signal outputted from the first shift register may be controlled respectively; based on this, in the present disclosure, the light emission control signals output from the respective first shift registers can be independently controlled while ensuring the normal cascade of the first shift registers within the light emission control gate driving circuit.

When a certain row of pixel units need to perform external compensation sensing and if a conventional light-emitting control gate driving circuit is adopted to perform driving, the row of pixel units can receive a black insertion driving signal (i.e. a non-effective level signal) in a blank period, in the present disclosure, the light-emitting control driving signal output end OUT of the first shift register corresponding to the pixel unit row performing external compensation sensing can be controlled to forcedly output a light-emitting driving signal (i.e. an effective level signal) through the forced output control end CSD connected to the first shift register corresponding to the pixel unit row performing external compensation sensing, so that the light-emitting control signal received by the pixel unit row performing external compensation sensing in the blank period is the light-emitting driving signal. That is, the pixel cell row, which would receive the black insertion driving signal in the blank period and need to perform the external compensation sensing in the blank period, actually receives the light emission driving signal in the blank period, so that the external compensation sensing process of the pixel cell row can be ensured to be performed smoothly.

The technical solution of the present disclosure will be described in detail with reference to a specific example. Fig. 6 is a driving timing chart of a light emission control gate driving circuit according to the related art, fig. 7 is a driving timing chart of a light emission control gate driving circuit according to the present disclosure, and as shown in fig. 6 and 7, EM < i > in the drawings indicates an ith light emission control signal line, that is, a light emission control signal line configured by an ith row of pixel units, i is an integer, i is 1.ltoreq.i.ltoreq.n, and n is the total number of rows of pixel units. The m-th row of pixel units is a row of pixel units which need to be subjected to external compensation sensing.

Referring to fig. 6, assuming that the light emission control signal lines EM < m > corresponding to the m-th row of pixel units receive the black insertion driving signal in the blank period when the gate driving circuit provided in the related art is used to drive the light emission control signal lines (fig. 6 and 7 illustrate a case where each row of pixel units of one frame is configured with 2 black insertion stages, and each light emission control signal line theoretically receives 2 black insertion driving signals), at this time, since the light emission control signal lines EM < m > configured with the m-th row of pixel units receive the black insertion driving signal in the blank period, it is apparent that the m-th row of pixel units cannot normally perform external compensation sensing based on the foregoing.

Referring to fig. 7, in the embodiment of the disclosure, the emission cascade signal output end CR and the emission control driving signal output end OUT of each first shift register in the emission control gate driving circuit are respectively set, and under the condition of normal cascade of the first shift registers in the emission control gate driving circuit, the emission control signals output by each first shift register can be independently controlled, so that the second emission control driving circuit in the first shift register connected to the mth row of pixel units can be controlled to operate in a blank period, so that the emission control driving signal output end OUT of the first shift register connected to the mth row of pixel units always outputs an emission driving signal (i.e., an effective level signal) in the blank period, thereby ensuring that the mth row of pixel units can normally perform external compensation sensing. In addition, since the first shift register in the light emission control gate driving circuit maintains the normal cascade connection, the first shift register corresponding to the m+1th row pixel unit can normally output the black insertion driving signal in the blank period.

Fig. 8 is a schematic diagram of another circuit structure of the first shift register according to the embodiment of the disclosure, as shown in fig. 8, and in some embodiments, the voltage regulating circuit 20 in the first shift register includes a first input circuit 21, a second input circuit 22, a first voltage control circuit 23 and a second voltage control circuit 24.

The first INPUT circuit 21 is connected to the light-emitting signal INPUT terminal INPUT, the first clock signal terminal CKA, and the second node N2, and the first INPUT circuit 21 is configured to write a signal provided by the light-emitting signal INPUT terminal INPUT to the second node N2 in response to control of a signal provided by the first clock signal terminal CKA.

The second input circuit 22 is connected to the first clock signal terminal CKA, the first power source terminal and the second node N2, and the second input circuit 22 is configured to write the first operating voltage provided by the first power source terminal to the third node N3 in response to the control of the signal provided by the first clock signal terminal CKA, and to write the signal provided by the first clock signal terminal CKA to the third node in response to the control of the voltage at the second node N2.

The first voltage control circuit 23 is connected to the second clock signal terminal CKB, the second power source terminal, the first node N1, the second node N2, and the third node N3, and is configured to write the signal provided by the second clock signal terminal CKB to the first node N1 in response to the control of the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB, and to write the second operating voltage provided by the second power source terminal to the first node N1 in response to the control of the voltage at the second node N2.

The second voltage control circuit 24 is connected to the second clock signal terminal CKB, the second power supply terminal, and the third node, and the second voltage control circuit 24 is configured to write the second operating voltage provided by the second power supply terminal to the second node N2 in response to the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB.

Of course, the voltage regulating circuit 20 in the embodiment of the present disclosure is not limited to the case shown in fig. 8, and the circuit structure of the voltage regulating circuit 20 shown in fig. 8 is merely exemplary, and does not limit the technical solution of the present disclosure.

In some embodiments, the first shift register further includes a first anti-leakage circuit 26; the first input circuit 21, the second input circuit 22, and the second node N2 are connected to the fifth node N5 by controlling voltages, the first anti-leakage circuit 26 is located between the fifth node N5 and the second node N2, and the first input circuit 21, the second input circuit, and the second voltage control circuit 24 are all connected to the second node N2 through the first anti-leakage circuit 26. The first anti-leakage circuit 26 is further connected to the first power supply terminal and the third power supply terminal, and the first anti-leakage circuit 26 is configured to write the third operating voltage provided by the third power supply terminal into the first anti-leakage node OFF1 under the control of the voltage at the second node N2, where the first anti-leakage node OFF1 is located between the second node N2 and the fifth node N5.

In some embodiments, the first shift register further includes a second anti-leakage circuit 27; the output circuit is connected with a second power supply end through a second anti-leakage circuit 27, and the luminous cascade output circuit 25 and the second anti-leakage circuit 27 are connected with a second anti-leakage node OFF2; the second anti-leakage circuit 27 is further connected to the first node N1, the first power terminal, and the second power terminal, the second anti-leakage circuit 27 is further connected to the emission cascade signal output terminal CR or the emission control driving signal output terminal OUT, and the second anti-leakage circuit 27 is configured to write the first operating voltage provided by the first power terminal to the second anti-leakage node OFF2 in response to control of the voltage at the emission cascade signal output terminal CR or the emission control driving signal output terminal OUT.

Fig. 9 is a schematic circuit diagram of a first shift register according to an embodiment of the disclosure, as shown in fig. 9, in some embodiments, the first input circuit 21 includes a first transistor T1, the second input circuit 22 includes a second transistor T2 and a third transistor T3, the first voltage control circuit 23 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a third capacitor C3, the second voltage control circuit 24 includes a seventh transistor T7 and an eighth transistor T8, the light emitting cascade output circuit 25 includes a ninth transistor T9 and a tenth transistor T10, and the first light emitting drive output circuit 29 includes a twenty-first transistor T21 and a twenty-second transistor T22.

The control electrode of the first transistor T1 is connected to the first clock signal terminal CKA, the first electrode of the first transistor T1 is connected to the light-emitting signal INPUT terminal INPUT, and the second electrode of the first transistor T1 is connected to the second node N2.

The control electrode of the second transistor T2 is connected to the first clock signal terminal CKA, the first electrode of the second transistor T2 is connected to the second power supply terminal, and the second electrode of the second transistor T2 is connected to the third node N3.

The control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the first clock signal terminal CKA.

The control electrode of the fourth transistor T4 is connected to the third node N3, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CKB, and the second electrode of the fourth transistor T4 is connected to the fourth node N4.

The control electrode of the fifth transistor T5 is connected to the second clock signal terminal CKB, the first electrode of the fifth transistor T5 is connected to the fourth node N4, and the second electrode of the fifth transistor T5 is connected to the first node N1.

The control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the second power supply terminal.

The first end of the third capacitor C3 is connected to the third node N3, and the second end of the third capacitor C3 is connected to the fourth node N4.

The control electrode of the seventh transistor T7 is connected to the third node N3, the first electrode of the seventh transistor T7 is connected to the second power supply terminal, and the second electrode of the seventh transistor T7 is connected to the first electrode of the eighth transistor T8.

The gate of the eighth transistor T8 is connected to the second clock signal terminal CKB, and the second pole of the eighth transistor T8 is connected to the second node N2.

The control electrode of the ninth transistor T9 is connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the second power supply terminal, and the second electrode of the ninth transistor T9 is connected to the light emitting cascade signal output terminal.

The control electrode of the tenth transistor T10 is connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the light emitting cascade signal output terminal, and the second electrode of the tenth transistor T10 is connected to the first power supply terminal. .

The control electrode of the twenty-first transistor T21 is connected to the sixth node N6, the first electrode of the twenty-first transistor T21 is connected to the second power supply terminal, and the second electrode of the twenty-first transistor T21 is connected to the emission control driving signal output terminal OUT.

The control electrode of the second transistor T22 is connected to the second node, the first electrode of the second transistor T22 is connected to the emission control driving signal output terminal OUT, and the second electrode of the second transistor T22 is connected to the first power supply terminal.

In some embodiments, the light emitting cascode output circuit 25 further includes a first capacitance C1 and a second capacitance C2. The first end of the first capacitor C1 is connected to the first node N1, and the second end of the first capacitor C1 is connected to the second power supply end. The first end of the second capacitor C2 is connected with the light-emitting cascade signal output end, and the second end of the second capacitor C2 is connected with the second node N2. The first capacitor C1 and the second capacitor C2 are configured to promote voltage stabilization at the first node and the second node.

In some embodiments, the first light emitting driving output circuit 29 further includes a fourth capacitor C4 and a fifth capacitor C5. The first end of the fourth capacitor C4 is connected to the sixth node N6, and the second end of the fourth capacitor C4 is connected to the second power supply end. The first end of the fifth capacitor C5 is connected to the light emission control driving signal output end, and the second end of the fifth capacitor C5 is connected to the second node N2.

In some embodiments, the first anti-leakage circuit 26 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.

The control electrode of the eleventh transistor T11 is connected to the first power supply terminal, the first electrode of the eleventh transistor T11 is connected to the fifth node N5, and the second electrode of the eleventh transistor T11 is connected to the first anti-leakage node OFF 1.

The control electrode of the twelfth transistor T12 is connected to the first power supply terminal, the first electrode of the twelfth transistor T12 is connected to the first anti-leakage node OFF1, and the second electrode of the twelfth transistor T12 is connected to the second node N2.

The control electrode of the thirteenth transistor T13 is connected to the second node N2, the first electrode of the thirteenth transistor T13 is connected to the third power supply terminal, and the second electrode of the thirteenth transistor T13 is connected to the first anti-leakage node OFF 1.

In some embodiments, the second anti-leakage circuit 27 includes a fourteenth transistor T14 and a fifteenth transistor T15.

The control electrode of the fourteenth transistor T14 is connected to the first node N1, the first electrode of the fourteenth transistor T14 is connected to the second power supply terminal, and the second electrode of the fourteenth transistor T14 is connected to the second anti-leakage node OFF 2.

The control electrode of the fifteenth transistor T15 is connected to the emission cascade signal output terminal CR or the emission control driving signal output terminal OUT, the first electrode of the fifteenth transistor T15 is connected to the first power supply terminal, and the second electrode of the fifteenth transistor T15 is connected to the second anti-leakage node OFF 2. It should be noted that fig. 9 only illustrates a case where the control electrode of the fifteenth transistor T15 is connected to the emission cascade signal output terminal CR.

Fig. 10 is a timing chart of an operation of the first shift register shown in fig. 9, as shown in fig. 10, wherein the first operating voltage provided by the first power supply terminal is a high level operating voltage VGH1, the second operating voltage provided by the second power supply terminal is a low level operating voltage VGL, and the third operating voltage provided by the third power supply terminal is a high level operating voltage VGH2, wherein VGH2 is slightly greater than VGH1. The process of outputting the light emitting cascade signal from the first shift register through the light emitting cascade signal output terminal will be described in detail. The process of outputting the light emitting cascade signal by the first shift register shown in fig. 9 includes the following operation phases:

in the first stage t1, the light-emitting signal INPUT terminal INPUT provides a low level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 are all turned on; the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 are all turned off.

Specifically, the first clock signal terminal CKA provides a high level signal, the first transistor T1 and the second transistor T2 are both turned on, the low level signal provided by the light emitting signal INPUT terminal INPUT is written into the fifth node N5, at this time, the eleventh transistor T11 and the twelfth transistor T12 are both turned on, so that the low level signal is written into the second node N2 through the eleventh transistor T11 and the twelfth transistor T12, the second node N2 is in a low level state, and the sixth transistor T6, the thirteenth transistor T13 and the tenth transistor T10 are all turned off. Meanwhile, the first working voltage VGH1 is written into the third node N3 through the second transistor T2, the voltage at the third node N3 is in a high level state, the fourth transistor T4 is turned on, the low level signal provided by the second clock signal terminal CKB is written into the fourth node N4 through the fourth transistor T4, and the voltage at the fourth node N4 is in a low level state.

Since the second clock signal is in a low level state, the fifth transistor T5 is turned off. At this time, the first node N1 is in a floating state, and the voltage at the first node N1 maintains a low state of the previous stage. Since the ninth transistor T9 and the tenth transistor T10 are turned off, the light emitting cascade signal output terminal is in a floating state, and the light emitting cascade signal output terminal maintains a high state of the previous stage, i.e., the light emitting cascade signal output terminal CR outputs a high signal. At this time, the fifteenth transistor T15 is turned on, and the first operating voltage VGH1 is written into the second anti-leakage node OFF2 through the fifteenth transistor T15, so that the voltage at the light emitting cascade signal output end CR can be effectively prevented from generating leakage through the ninth transistor T9, which is beneficial to maintaining the stability of the voltage at the light emitting cascade signal output end.

The second phase t2 comprises two sub-phases s1, s2 which alternate.

In the sub-stage s1, the light-emitting signal INPUT terminal INPUT provides a low level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. The fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are all turned on; the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all turned off.

Specifically, when the first clock signal terminal CKA is in a low level state, the first transistor T1 and the second transistor T2 are turned off, the third node N3 is in a floating state and maintains a high level, the high level signal provided by the second clock signal terminal CKB is written into the fourth node N4 through the fourth transistor T4, the voltage at the fourth node N4 is changed from the low level state to the high level state, and the voltage at the third node N3 is further pulled up to a higher level under the bootstrap action of the third capacitor C3. Meanwhile, since the second clock signal terminal CKB provides the high level signal, the fifth transistor T5 and the eighth transistor T8 are turned on; since the seventh transistor T7 and the eighth transistor T8 are both turned on, the second operating voltage VGL1 is written to the fifth node N5 through the seventh transistor T7 and the eighth transistor T8, the fifth node N5 maintains a low state, and accordingly the eleventh transistor T11 and the twelfth transistor T12 are both turned on, the second node N2 also maintains a low state, and the sixth transistor T6, the tenth transistor T10 and the thirteenth transistor T13 are all maintained turned off.

Since the fifth transistor T5 is turned on, the high level signal at the fourth node N4 can be written into the first node N1 through the fifth transistor T5, the voltage at the first node N1 is in the high level state, at this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned on, the second operating voltage VGL is written into the emission cascade signal output terminal CR through the fourteenth transistor T14 and the ninth transistor T9, and the emission cascade signal output terminal CR outputs the low level signal. Accordingly, the fifteenth transistor T15 is turned off.

In the sub-stage s2, the light-emitting signal INPUT terminal INPUT provides a low level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal.

The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are all turned on; the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all turned off.

Specifically, the first clock signal terminal CKA provides a high level signal, and the first transistor T1 and the second transistor T2 are both turned on, the low level signal provided by the light emitting signal INPUT terminal INPUT is written into the fifth node N5, the fifth node N5 maintains a low level state, and accordingly the second node N2 maintains a low level state. The sixth transistor T6, the tenth transistor T10, and the thirteenth transistor T13 all remain turned off. Meanwhile, the first operating voltage is written into the third node N3 through the second transistor T2, the voltage at the third node N3 drops to VGH1, the voltage at the third node N3 is in a high level state, and the fourth transistor T4 is turned on. The low level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, the voltage at the fourth node N4 is in a low level state,

Since the second clock signal terminal CKB is in the low level state, the fifth transistor T5 and the eighth transistor T8 are turned off, the first node N1 is in the floating state, the first node N1 maintains the high level state of the previous node, the ninth transistor T9 and the fourteenth transistor T14 maintain the on state, and the light emitting cascade signal output terminal CR maintains to output the low level signal. Accordingly, the fifteenth transistor T15 remains turned off.

In the third stage t3, the light-emitting signal INPUT terminal INPUT provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. The fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are all turned on; the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all turned off.

The specific operation of the first shift register in the third stage t3 is the same as that in the sub-stage s1, and will not be described here again.

The fourth phase t4 comprises two sub-phases s3, s4 which alternate.

In the sub-stage s3, the light-emitting signal INPUT terminal INPUT provides a high level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal. The first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10, the thirteenth transistor T13, the fifteenth transistor T15 are all turned on, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the fourteenth transistor T14 are all turned off, and the eleventh transistor T11 and the twelfth transistor T12 are all turned on and then switched to an off state.

Specifically, the first clock signal terminal CKA is in a high level state, the first transistor T1 and the second transistor T2 are both turned on, the high level signal provided by the light emitting signal INPUT terminal INPUT is written to the fifth node N5 through the first transistor T1, and the eleventh transistor T11 and the twelfth transistor T12 are both turned on, so that the high level signal is written to the second node N2 through the eleventh transistor T11 and the twelfth transistor T12, and the second node N2 is in a low level state, so that the sixth transistor T6, the thirteenth transistor T13, and the tenth transistor T10 are all turned on. Since the thirteenth transistor T13 is turned on, the third operating voltage VGH2 is written to the first anti-leakage node OFF1 through the thirteenth transistor T13, and the voltages at the fifth node N5 and the second node N2 are pulled up through the eleventh transistor T11 and the twelfth transistor T12, respectively, at which time the gate-source voltages of the eleventh transistor T11 and the twelfth transistor T12 decrease until the gate-source voltage of the eleventh transistor T11 is equal to the threshold voltage of the eleventh transistor T11 and the gate-source voltage of the twelfth transistor T12 is equal to the threshold voltage of the twelfth transistor T12, and both the eleventh transistor T11 and the twelfth transistor T12 are turned OFF, at which time the first anti-leakage node OFF1 is in the floating state. Through the design, the second node N2 can be effectively prevented from generating electric leakage through other transistors, so that the voltage at the second node N2 is kept in a high-level state all the time. It should be noted that, in the process of charging the fifth node N5 and the second node N2 by the eleventh transistor T11 and the twelfth transistor T12 through the first anti-leakage node OFF1, the voltages at the fifth node N5 and the second node N2 are only slightly raised, so that the eleventh transistor T11 and the twelfth transistor T12 are turned OFF.

Meanwhile, the first working voltage VGH1 is written into the third node N3 through the second transistor T2, the voltage at the third node N3 is in a high level state, the fourth transistor T4 is turned on, the low level signal provided by the second clock signal terminal CKB is written into the fourth node N4 through the fourth transistor T4, and the voltage at the fourth node N4 is in a low level state.

Also, since the second clock signal is in a low level state, the fifth transistor T5 is turned off. At this time, since the sixth transistor T6 is turned on, the second operating voltage VGL is written to the first node N1 through the sixth transistor T6, and the voltage at the first node N1 is in a low level state. At this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned off.

In the case where the ninth transistor T9 is turned off and the tenth transistor T10 is turned on, the light emission cascade signal output terminal CR outputs a high level signal. Accordingly, the fifteenth transistor T15 is turned on.

In the sub-stage s4, the light-emitting signal INPUT terminal INPUT provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, the fifteenth transistor T15 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the fourteenth transistor T14 are all turned off, and the eleventh transistor T11 and the twelfth transistor T12 are all turned on and then switched to an off state.

Specifically, when the first clock signal terminal CKA is in a low level state, the first transistor T1 and the second transistor T2 are turned off, the fifth node N5 maintains the high level state of the previous stage, the third transistor T3 is turned on, the low level signal provided by the first clock signal terminal CKA is written into the third node N3 through the third transistor T3, the voltage at the third node N3 is in the low level state, and the fourth transistor T4 and the seventh transistor T7 are turned off.

Since the eleventh transistor T11 and the twelfth transistor T12 are turned off, the second node N2 is floated to maintain the high state of the previous stage, and the sixth transistor T6, the tenth transistor T10 and the thirteenth transistor T13 are turned on, the voltage at the first node N1 maintains the low state, and the ninth transistor T9 and the fourteenth transistor T14 maintain the turned-off state.

In the case where the ninth transistor T9 is turned off and the tenth transistor T10 is turned on, the light emission cascade signal output terminal CR maintains to output a high level signal. Accordingly, the fifteenth transistor T15 is turned on.

Subsequently, when the first clock signal terminal CKA provides a high level signal and the light-emitting signal INPUT terminal INPUT provides a low level signal, the first stage t1 of the next cycle is entered.

It should be noted that, the scheme of disposing the first anti-leakage circuit 26 and the second anti-leakage circuit 27 in the first shift register is a preferred embodiment in the present disclosure, the first anti-leakage circuit 26 may maintain the voltage at the second node N2 stable in the fourth stage t4, and the second anti-leakage circuit 27 may maintain the voltage at the light emitting cascade signal output terminal CR stable in the first stage t 1. It will be appreciated by those skilled in the art that the first shift register may optionally not include the first anti-leakage circuit 26 and/or the second anti-leakage circuit 27 in some embodiments.

Referring again to fig. 9, in some embodiments, the first shift register further comprises: and the luminous global reset circuit 28 is connected with the luminous global reset signal terminal TRST, the first power supply terminal and the second node N2, and is configured to respond to the control of the signal provided by the luminous global reset signal terminal TRST and write the first working voltage provided by the first power supply terminal into the second node N2.

Referring to fig. 9, in some embodiments, the light emitting global reset circuit 28 includes a sixteenth transistor T16; the control electrode of the sixteenth transistor T16 is connected to the light-emitting global reset signal terminal, the first electrode of the sixteenth transistor T16 is connected to the second node N2, and the second electrode of the sixteenth transistor T16 is connected to the first power supply terminal.

When global reset is required, the global reset signal terminal provides a high-level signal (i.e., an active level signal) to enable the sixteenth transistor T16 in the first shift register to be turned on, and at this time, the first working voltage VGH1 is written into the fifth node N5 through the sixteenth transistor T16, so that the second node N2 is always in a high-level state, so as to achieve the purpose of global reset. Currently, it will be appreciated by those skilled in the art that the first shift register may optionally not include a light emitting global reset circuit in some embodiments.

A process of the first shift register outputting the light emission control signal through the light emission control driving signal output terminal will be described in detail with several specific examples.

Fig. 11 is a schematic circuit diagram of a first shift register according to an embodiment of the disclosure, as shown in fig. 11, in some embodiments, the first node N1 is directly connected to the sixth node N6, the second light-emitting driving output circuit 30 includes a twenty-third transistor T23, a control electrode of the twenty-third transistor T23 is connected to the forced output control terminal CSD, a first electrode of the twenty-third transistor T23 is connected to the first power supply terminal, and a second electrode of the twenty-third transistor T23 is connected to the light-emitting control driving signal output terminal OUT.

Fig. 12 is a timing chart of an operation of the first shift register shown in fig. 11, as shown in fig. 12, as a scenario, when the first shift register is not required to forcibly output the active level signal, the low level signal (i.e. the inactive level signal) is continuously provided to the forced output control terminal CSD, and then the twenty-third transistor T23 is always turned off (the second light-emitting driving output circuit is in the inactive state) during the process of outputting the light-emitting cascade signal by the first shift register through the light-emitting cascade signal output terminal CR, and the signal output by the light-emitting control driving signal output terminal OUT is only affected by the first light-emitting driving output circuit 29. Since the operation state of the twenty-first transistor T21 is identical to the operation state of the ninth transistor T9 and the operation state of the twenty-second transistor T22 is identical to the operation state of the tenth transistor T10, the light emission control driving signal output terminal OUT output signal is identical to the signal output by the light emission cascade signal output terminal CR.

Fig. 13 is another operation timing diagram of the first shift register shown in fig. 11, as shown in fig. 13, as another scenario, when the first shift register is required to forcibly output the active level signal in a preset period (e.g., a blank period), the high level signal (i.e., the active level signal) may be continuously provided to the forced output control terminal CSD in the required period, and the low level signal (i.e., the inactive level signal) may be provided to the forced output control terminal CSD in other times except the preset period; therefore, the thirteenth transistor T23 clock is in the on state (the second light emission drive output circuit 30 is in the operating state) for the preset period, and the thirteenth transistor T23 clock is in the off state (the second light emission drive output circuit is in the non-operating state) for other times than the preset period. At this time, no matter what states the twenty-first transistor T21 and the twenty-second transistor T22 in the first light emitting driving output circuit are in, the light emitting control driving signal output terminal OUT always outputs a high level signal (i.e., an active level signal); at other times than the preset period, the signal output from the light emission control driving signal output terminal OUT is identical to the signal output from the light emission cascade signal output terminal CR.

In the scenario shown in fig. 13, since the first node N1 is directly connected to the sixth node N6, that is, the voltages of the first node N1 and the sixth node N6 are always consistent, there may be a case where the twenty-first transistor T21 and the twenty-third transistor T23 are turned on simultaneously, and in order to ensure that the light emission control driving signal output terminal OUT can output a high level signal, the channel width to length ratio of the twenty-third transistor T23 may be made larger than that of the twenty-first transistor T21.

FIG. 14 is a schematic diagram of another circuit configuration of the first shift register according to the embodiments of the present disclosure, as shown in FIG. 14, in some embodiments, the forced output control terminal includes a first control terminal and a second control terminal; the second light-emitting drive output circuit includes: two twenty-third transistors T23', T23″ connected in series between the first power supply terminal and the light emission control driving signal output terminal; the control electrode of one of the twenty-third transistors T23', T23 "is connected to the first control terminal CP1, and the control electrode of the other of the two twenty-third transistors T23', T23" is connected to the second control terminal CP 2.

That is, when the first control terminal CP1 and the second control terminal CP2 simultaneously supply the high level signal (active level signal), the two twenty-third transistors T23', T23″ are simultaneously turned on, and the second light emission driving output circuit 30 is in an operating state. That is, the period in which the first control terminal CP1 and the second control terminal CP2 simultaneously supply the active level signal is a period in which the first shift register is required to forcibly output the active level signal.

In some embodiments, the first control terminal and the second control terminal connected to the first shift register are respectively: displaying a sensing cascade node and a fourth clock signal end which are configured in advance in a second shift register of the pixel unit corresponding to the same row of the first shift register in the sensing grid driving circuit; for a specific description of the display sense gate driving circuit and the second shift register, reference will be made to the following.

Fig. 15 is a schematic circuit diagram of a first shift register according to an embodiment of the present disclosure, and as shown in fig. 15, the first shift register according to the embodiment shown in fig. 15 further includes a node control circuit 31, which is different from the previous embodiment; the node control circuit 31 is located between the sixth node N6 and the first node N1, the sixth node N6 is connected to the first node N1 through the node control circuit 31, the node control circuit 31 is further connected to the second power source terminal and the forced output control terminal CSD, and the node control circuit 31 is configured to respond to the control of the signal provided by the forced output control terminal CSD, so that the sixth node N6 is disconnected from the first node N1 and write the second working voltage provided by the second power source terminal into the sixth node N6.

In the embodiment of the present disclosure, when the forced output control terminal CSD provides the active level signal, the sixth node N6 and the first node N1 may be disconnected, and the inactive level signal may be written into the sixth node N6; by this design, the case where the first light emission drive output circuit 29 writes the second operating voltage to the light emission control drive signal output terminal OUT while the second light emission drive output circuit 30 writes the first operating voltage to the light emission control drive signal output terminal OUT can be effectively avoided.

Fig. 16 is a schematic diagram of still another circuit structure of the first shift register in the embodiment of the disclosure, as shown in fig. 16, in some embodiments, the node control circuit 31 includes a first write sub-circuit 311, a second write sub-circuit 312, a twenty-fourth transistor T24, and a twenty-fifth transistor T25.

The first writing sub-circuit 311 is connected to the second power supply terminal, the forced output control terminal CSD, and the control electrode of the twenty-fourth transistor T24, and the first writing sub-circuit 311 is configured to write the second operating voltage provided by the second power supply terminal to the control electrode of the twenty-fourth transistor T24 in response to the control of the signal provided by the forced output control terminal CSD.

The second writing sub-circuit 312 is connected to the second power source, the forced output control terminal CSD, and the sixth node N6, and the second writing sub-circuit 312 is configured to write the second operating voltage provided by the second power source terminal to the sixth node N6 in response to the control of the signal provided by the forced output control terminal CSD.

A first pole of the twenty-fourth transistor T24 is connected to the first node N1, and a second pole of the twenty-fourth transistor T24 is connected to the sixth node N6.

The control electrode of the twenty-fifth transistor T25 is connected to the first power supply terminal or the second clock signal terminal, the first electrode of the twenty-fifth transistor T25 is connected to the control electrode of the twenty-fifth transistor T25, and the second electrode of the twenty-fifth transistor T25 is connected to the second electrode of the twenty-sixth transistor T26.

Fig. 17 is a schematic diagram of still another circuit structure of the first shift register in the embodiment of the disclosure, as shown in fig. 17, in some embodiments, the first write sub-circuit 311 includes a twenty-sixth transistor T26, and the second write sub-circuit 312 includes a twenty-seventh transistor T27.

The control electrode of the twenty-sixth transistor T26 is connected to the forced output control terminal CSD, the first electrode of the twenty-sixth transistor T26 is connected to the second power supply terminal, and the second electrode of the twenty-sixth transistor T26 is connected to the control electrode of the twenty-fourth transistor T24.

The control electrode of the twenty-seventh transistor T27 is connected to the forced output control terminal CSD, the first electrode of the twenty-seventh transistor T27 is connected to the second power supply terminal, and the second electrode of the twenty-seventh transistor T27 is connected to the sixth node N6.

When the forced output control terminal CSD provides a high level signal (an active level signal), the twenty-sixth transistor and the twenty-seventh transistor are turned on, the first writing sub-circuit 311 and the second writing sub-circuit 312 are both in an operating state, and the second operating voltage can be written to the control electrode of the twenty-fourth transistor and the sixth node N6, respectively. At this time, the twenty-fourth transistor is turned off to open a circuit between the first node N1 and the sixth node N6. When the forced output control terminal CSD provides a low level signal (inactive level signal), the twenty-fifth transistor can write the active level signal to the control electrode of the twenty-fourth transistor, the twenty-fourth transistor is turned on, and the first node N1 and the sixth node N6 are connected, and the voltages of the first node N1 and the sixth node N6 are kept consistent.

Fig. 18 is a schematic diagram of still another circuit structure of the first shift register in the embodiment of the disclosure, as shown in fig. 18, and in some embodiments, the forced output control terminal CSD includes a first control terminal CP1 and a second control terminal CP2.

Wherein the first write sub-circuit 311 includes: two twenty-sixth transistors T26', T26″ connected in series between the second power supply terminal and the control electrode of the twenty-fourth transistor T24; the control electrode of one of the twenty-sixth transistors T26', T26 "is connected to the first control terminal CP1, and the control electrode of the other of the two twenty-sixth transistors T26', T26" is connected to the second control terminal CP2.

The second write sub-circuit 312 includes: two twenty-seventh transistors T27', T27″ connected in series between the second power supply terminal and the sixth node N6; the control electrode of one of the twenty-seventh transistors T27', T27 "is connected to the first control terminal CP1, and the control electrode of the other of the two twenty-seventh transistors T27', T27" is connected to the second control terminal CP 2.

FIG. 19 is a schematic diagram of another circuit configuration of the first shift register according to the embodiments of the present disclosure, as shown in FIG. 19, and in some embodiments, the first shift register further includes a twenty-eighth transistor T28; the control electrode of the twenty-eighth transistor T28 is connected to the second node N2, the first electrode of the twenty-eighth transistor T28 is connected to the second power supply terminal, and the second electrode of the twenty-eighth transistor T28 is connected to the sixth node N6.

When the voltage at the second node N2 is in the active level state, the twenty-eighth transistor T28 is turned on, and the low level voltage VGL is written to the sixth node N6 through the twenty-eighth transistor T28, so as to stably maintain the voltage at the sixth node N6 in the inactive level state when the second node N2 is in the active level state.

Based on the same inventive concept, the embodiments of the present disclosure also provide a gate driving circuit, which is a light emission control gate driving circuit, and for convenience of description, will be referred to as a first gate driving circuit. Fig. 20 is a schematic circuit diagram of a gate driving circuit according to an embodiment of the disclosure, and as shown in fig. 20, a first gate driving circuit 200 includes: a plurality of first shift registers SR_1, SR_2, SR_3, SR_4 in cascade; the first shift registers sr_1, sr_2, sr_3, sr_4 are the first shift registers provided in the above embodiments; the light emitting signal INPUT end INPUT of the first shift register SR_1 positioned at the first stage is connected with the light emitting starting signal line STV, and the first shift registers SR_2, SR_3 and SR_4 of other stages except the first stage are connected with the light emitting cascade signal output ends CR of the first shift registers of the respective previous stages; the light emission control driving signal output terminal OUT of each of the first shift registers sr_1, sr_2, sr_3, sr_4 is connected to the corresponding light emission control signal line EM.

In some embodiments, a first clock signal line CK1 and a second clock signal line CK2 are configured for the first gate driving circuit; the first clock signal end CKA of the first shift register located at the odd-numbered stage is connected with the first clock signal line CK1, the second clock signal end CKB of the first shift register located at the odd-numbered stage is connected with the second clock signal line CK2, the first clock signal end CKA of the first shift register located at the even-numbered stage is connected with the second clock signal line CK2, and the second clock signal end CKB of the first shift register located at the even-numbered stage is connected with the first clock signal line CK 1.

When the first shift register in the first gate driving circuit is configured with a light-emitting global Reset circuit, the first gate driving circuit is further configured with a light-emitting global Reset signal line Reset, and the light-emitting global Reset signal terminals TRST configured by the first shift registers of each stage are connected to the same light-emitting global Reset signal line Reset.

Based on the same inventive concept, the embodiment of the disclosure also provides a display device. Fig. 21 is a schematic structural diagram of a display device according to an embodiment of the disclosure, and as shown in fig. 21, the display device 100 includes: the display area 101 and the peripheral area 102 positioned at the periphery of the display area 101, wherein the display area 101 comprises a plurality of pixel units 300 which are arranged in an array, each row of pixel units is provided with a corresponding light-emitting control signal line EM, and the light-emitting control signal line EM is connected with a control electrode of a light-emitting control transistor in the corresponding pixel unit 300; the peripheral region 102 includes a first gate driving circuit 200 for supplying a light emission control signal to the light emission control signal line EM, and the first gate driving circuit 200 employs the first gate driving circuit provided in the above-described embodiment.

In some embodiments, the pixel unit 300 in the embodiments of the disclosure may employ the 4T1C structure shown in fig. 3, and for the second gate line in the display area 100, a corresponding second gate driving circuit 400 may be configured in the peripheral area, where the second gate driving circuit 400 includes a plurality of cascaded second shift registers (not shown in fig. 21), and the second shift registers may provide at least a corresponding driving signal to the corresponding second gate line.

Fig. 22 is a schematic circuit diagram of a second shift register according to an embodiment of the disclosure, as shown in fig. 22, and in some embodiments, the second shift register is configured with a second gate driving signal output terminal OUT2, and the second gate driving signal output terminal OUT2 is connected to a corresponding second gate line.

The second shift register includes a first display precharge reset circuit 41, a sense cascade circuit 42, a first sense precharge reset circuit 43, a first pull-down control circuit 44, a gate cascade output circuit 45, and a second gate drive output circuit 46.

The sensing cascade circuit 42 and the first sensing precharge reset circuit 43 are connected to the sensing cascade node H, the first display precharge reset circuit 41, the first sensing precharge reset circuit 43, the first pull-down control circuit 44, the gate cascade output circuit 45 and the second gate drive output circuit 46 are connected to the first pull-up node PU1, and the first pull-down control circuit 44, the gate cascade output circuit 45 and the second gate drive output circuit 46 are connected to the first pull-down node PD1.

The first display pre-charge reset circuit 41 is connected to the display signal input terminal STU1, the display reset signal terminal STD, and the fifth power supply terminal, and the first display pre-charge reset circuit 41 is configured to write a signal provided by the display signal input terminal STU1 into the first pull-up node PU1 in response to control of a signal provided by the display signal input terminal STU1, and write a fifth operating voltage provided by the fifth power supply terminal into the first pull-down node PD1 in response to control of a signal provided by the display reset signal terminal STD.

The sensing cascade circuit 42 is connected to the sensing signal input terminal STU2 and the random signal terminal OE, and the sensing cascade circuit 42 is configured to write the signal provided by the sensing signal input terminal STU2 into the sensing cascade node H in response to control of the signal provided by the random signal terminal OE.

The first sensing precharge reset circuit 43 is connected to the third clock signal terminal CKC, the sensing reset signal terminal SRST, and the fifth power supply terminal, and the first sensing precharge reset circuit 43 is configured to write a signal provided by the third clock signal terminal CKC to the sensing precharge node N in response to control of a voltage provided by the sensing cascade node H, to write a voltage provided by the sensing precharge node N to the first pull-up node PU1 in response to control of a signal provided by the third clock signal terminal CKC, and to write a fifth operating voltage provided by the fifth power supply terminal to the first pull-up node PU1 in response to control of a signal provided by the sensing reset signal terminal SRST.

The first pull-down control circuit 44 is connected to the fourth power supply terminal and the fifth power supply terminal, and the first pull-down control circuit 44 is configured to write a voltage to the first pull-down node PD1 that is inverted from the voltage at the first pull-up node PU1.

The gate cascade output circuit 45 is connected to the cascade clock signal terminal CLKX, the fifth power supply terminal, and the gate cascade signal output terminal CR1, and the gate cascade output circuit 45 is configured to write a signal provided by the cascade clock signal terminal CLKX to the gate cascade signal output terminal CR1 in response to control of a voltage at the first pull-up node PU1, and to write a fifth operating voltage provided by the fifth power supply terminal to the gate cascade signal output terminal CR1 in response to control of a voltage at the first pull-down node PD 1.

The second gate driving output circuit 46 is connected to the second driving clock signal terminal CLK2 and the sixth power supply terminal, and the second gate driving output circuit 46 is configured to write a signal supplied from the second driving clock signal terminal CLK2 to the second gate driving signal output terminal OUT2 in response to control of the voltage at the first pull-up node PU1, and to write a sixth operating voltage supplied from the sixth power supply terminal to the second gate driving signal output terminal OUT2 in response to control of the voltage at the first pull-down node PD 1.

In some embodiments, when the forced output control terminal is a single control terminal, in the first gate driving circuit 200, the forced output control terminal CSD to which any one of the first shift registers is connected includes: a second gate driving signal output terminal OUT2 or a gate cascade signal output terminal CR1 arranged corresponding to the second shift register of the same row of pixel units as the first shift register.

In some embodiments, when the forced output control terminal CSD includes the first control terminal CP1 and the second control terminal CP2, in the first gate driving circuit 200, the first control terminal CP1 and the second control terminal CP2 to which any one of the first shift registers is connected are respectively: a sensing cascade node H and a preconfigured fourth clock signal terminal inside a second shift register corresponding to the same row of pixel units as the first shift register.

Fig. 23 is a schematic diagram of another circuit structure of the second shift register in the embodiment of the disclosure, and as shown in fig. 23, the first display precharge and reset circuit 41 includes a thirty-first transistor T31 and a thirty-second transistor T32.

The control electrode of the thirty-first transistor T31 is connected to the display signal input terminal STU1, the first electrode of the thirty-first transistor T31 is connected to the control electrode of the thirty-first transistor T31, and the second electrode of the thirty-first transistor T31 is connected to the first pull-up node PU 1.

The control electrode of the thirty-second transistor T32 is connected to the display reset signal terminal STD, the first electrode of the thirty-second transistor T32 is connected to the first pull-up node PU1, and the second electrode of the thirty-second transistor T32 is connected to the fifth power supply terminal.

In some embodiments, the sense cascode circuit 42 includes a thirteenth transistor T33; the control electrode of the third transistor is connected to the random signal terminal OE, the first electrode of the thirty-third transistor T33 is connected to the sensing signal input terminal STU2, and the second electrode of the thirty-third transistor T33 is connected to the sensing cascade node H.

In some embodiments, the first sensing precharge reset circuit 43 includes a thirty-fourth transistor T34, a thirty-fifth transistor T35, and a thirty-sixth transistor T36.

The control electrode of the thirty-fourth transistor T34 is connected to the sensing cascade node H, the first electrode of the thirty-fourth transistor T34 is connected to the third clock signal terminal CKC, and the second electrode of the thirty-fourth transistor T34 is connected to the sensing precharge node N.

The control electrode of the thirty-fifth transistor T35 is connected to the third clock signal terminal CKC, the first electrode of the thirty-fifth transistor T35 is connected to the sensing precharge node N, and the second electrode of the thirty-fifth transistor T35 is connected to the first pull-up node PU 1.

The control electrode of the thirty-sixth transistor T36 is connected to the sensing reset signal terminal SRST, the first electrode of the thirty-sixth transistor T36 is connected to the first pull-up node PU1, and the second electrode of the thirty-sixth transistor T36 is connected to the fifth power supply terminal.

In some embodiments, the first pull-down control circuit 44 includes a thirty-seventh transistor T37, a thirty-eighth transistor T38, a thirty-ninth transistor T39, and a forty-transistor T40.

The control electrode of the thirty-seventh transistor T37 is connected to the fourth power supply terminal, the first electrode of the thirty-seventh transistor T37 is connected to the control electrode of the thirty-seventh transistor T37, and the second electrode of the thirty-seventh transistor T37 is connected to the control electrode of the thirty-eighth transistor T38.

The control electrode of the thirty-eighth transistor T38 is connected to the first electrode of the fortieth transistor T40, the first electrode of the thirty-eighth transistor T38 is connected to the fourth power supply terminal, and the second electrode of the thirty-eighth transistor T38 is connected to the first pull-down node PD 1.

The control electrode of the thirty-ninth transistor T39 is connected to the first pull-up node PU1, the first electrode of the thirty-ninth transistor T39 is connected to the first pull-down node PD1, and the second electrode of the thirty-ninth transistor T39 is connected to the fifth power supply terminal.

The control electrode of the forty transistor T40 is connected to the first pull-up node PU1, and the second electrode of the forty transistor T40 is connected to the fifth power supply terminal.

In some embodiments, the gate cascade output circuit 45 includes a forty-first transistor T41 and a forty-second transistor T42.

The control electrode of the forty-first transistor T41 is connected to the first pull-up node PU1, the first electrode of the forty-first transistor T41 is connected to the cascade clock signal terminal CLKX, and the second electrode of the forty-first transistor T41 is connected to the gate cascade signal output terminal CR 1.

The control electrode of the forty-second transistor T42 is connected to the first pull-down node PD1, the first electrode of the forty-second transistor T42 is connected to the fifth power supply terminal, and the second electrode of the forty-second transistor T42 is connected to the gate cascade signal output terminal CR 1.

In some embodiments, the second gate drive output circuit 46 includes a thirteenth transistor T43 and a forty-fourth transistor T44.

The control electrode of the thirteenth transistor T43 is connected to the first pull-up node PU1, the first electrode of the thirteenth transistor T43 is connected to the second driving clock signal terminal CLK2, and the second electrode of the forty-third transistor T43 is connected to the second gate driving signal output terminal OUT 2.

The control electrode of the forty-fourth transistor T44 is connected to the first pull-down node PD1, the first electrode of the forty-fourth transistor T44 is connected to the sixth power supply terminal, and the second electrode of the forty-fourth transistor T44 is connected to the second gate driving signal output terminal OUT 2.

In some embodiments, the second shift register further includes a twelfth capacitor C12, a first end of the twelfth capacitor C12 is connected to the first pull-up node PU1, and a second end of the twelfth capacitor C12 is connected to the second gate driving signal output terminal OUT 2.

In some embodiments, the second shift register further comprises: a first noise reduction circuit 48; the first noise reduction circuit 48 is connected to the first pull-up node PU1, the first pull-down node PD1, and the fifth power supply terminal, and the first noise reduction circuit 48 is configured to write the fifth operating voltage provided by the fifth power supply terminal to the first pull-up node PU1 in response to the control of the voltage at the first pull-down node PD 1. In the disclosed embodiment, noise reduction from the first pull-up node PU1 may be performed by the first noise reduction circuit 48 to maintain the voltage at the first pull-up node PU1 stable.

Optionally, the first noise reduction circuit 48 includes a forty-seventh transistor T47; the control electrode of the forty-seventh transistor T47 is connected to the first pull-down node PD1, the first electrode of the forty-seventh transistor T47 is connected to the fifth power supply terminal, and the second electrode of the forty-seventh transistor T47 is connected to the first pull-up node PU 1.

In some embodiments, the second shift register further comprises: a second noise reduction circuit 49; the second noise reduction circuit 49 is connected to the first pull-down node PD1, the sensing cascode node H, the third clock signal terminal CKC, and the fifth power supply terminal, and the second noise reduction circuit 49 is configured to write the fifth operating voltage provided by the fifth power supply terminal into the first pull-down node PD1 in response to control of the voltage at the sensing cascode node H and the signal provided by the third clock signal terminal CKC. In the embodiment of the present disclosure, noise reduction from the first pull-down node PD1 may be performed by the second noise reduction circuit 49 to maintain the stability of the voltage at the first pull-down node PD1.

Optionally, the second noise reduction circuit includes a forty-eight transistor T48 and a forty-nine transistor T49. The control electrode of the forty-eight transistor T48 is connected to the third clock signal terminal CKC, the first electrode of the forty-eight transistor T48 is connected to the first pull-down node PD1, and the second electrode of the forty-eight transistor T48 is connected to the first electrode of the forty-nine transistor T49. The control electrode of the forty-nine transistor T49 is connected to the sensing cascade node H, and the second electrode of the forty-nine transistor T49 is connected to the fifth power supply terminal.

In some embodiments, the second shift register further comprises: the third noise reduction circuit 50, the third noise reduction circuit 50 is connected to the display signal input terminal STU1, the first pull-down node PD1 and the fifth power supply terminal, and the third noise reduction circuit 50 is configured to write the fifth operating voltage provided by the fifth power supply terminal into the first pull-down node PD1 in response to control of the signal provided by the display signal input terminal STU 1. In the embodiment of the present disclosure, the noise reduction from the first pull-down node PD1 may be performed by the third noise reduction circuit to maintain the stability of the voltage at the first pull-down node PD1.

Optionally, the third noise reduction circuit 50 includes: a fifty-th transistor T50; the control electrode of the fifty-th transistor T50 is connected to the display signal input terminal STU1, the first electrode of the fifty-th transistor T50 is connected to the fifth power supply terminal, and the second electrode of the fifty-th transistor T50 is connected to the first pull-down node PD1.

The operation of the second shift register shown in fig. 23 will be described in detail with reference to the accompanying drawings. The fourth operating voltage provided by the fourth power supply terminal is a high level voltage VGH, the fifth operating voltage provided by the fifth power supply terminal is a low level operating voltage VGL1, the sixth operating voltage provided by the sixth power supply terminal is a low level operating voltage VGL2, and the fifth operating voltage VGL1 is slightly smaller than the sixth operating voltage VGL2.

Fig. 24 is a timing chart of the operation of the second shift register shown in fig. 23, and as shown in fig. 23 and 24, the operation of the second shift register includes the following 7 stages:

in the sensing cascade stage t0 (in the blank period of the previous frame), the signal provided by the signal input terminal STU1 is in a low level state, the signal provided by the signal input terminal STU2 is in a high level state, the signal provided by the reset signal terminal STD is in a low level state, the signal provided by the third clock signal terminal CKC is in a low level state, the signal provided by the random signal terminal OE is in a high level state, the signal provided by the reset signal terminal SRST is sensed in a high level state, the signal provided by the cascade clock signal terminal CLKX is in a high level state, and the signal provided by the second driving clock signal terminal CLK2 is in a high level state.

At this time, the thirty-third transistor T33 is turned on under the control of the high level signal provided from the random signal terminal OE, the high level signal provided from the sensing signal input terminal STU2 is written into the sensing cascode node H through the thirty-third transistor T33, and the voltage at the sensing cascode node H is in a high level state. Meanwhile, the thirty-fourth transistor T34 is turned on under the control of the voltage at the sensing cascode node H, and the low-level signal provided by the third clock signal terminal CKC is written to the sensing precharge node N (i.e., the first pole of the thirty-fifth transistor T35) through the thirty-fourth transistor T34; meanwhile, the thirty-fifth transistor T35 is turned off by the low signal provided by the third clock signal terminal CKC, so that the sensing precharge node N and the first pull-up node PU1 are disconnected.

The thirty-sixth transistor T36 is turned on under the control of the high level signal provided by the sensing reset signal terminal SRST, so that the fifth operating voltage VGL1 provided by the fifth power terminal is written into the first pull-up node PU1 through the thirty-sixth transistor T36, and the first pull-up node PU1 is in the low level state.

Since the display signal input terminal STU1 and the display reset signal terminal STD both supply low level signals, the thirty-first transistor T31 and the thirty-second transistor T32 are both turned off.

Since the voltage at the first pull-up node PU1 is in a low level state, the thirty-ninth transistor T39, the fortieth transistor T40, and the forty-third transistor T43 are all turned off; meanwhile, in the pull-down control circuit, under the control of the fourth operating voltage VGH supplied from the fourth power supply terminal, the thirty-seventh transistor T37 and the thirty-eighth transistor T38 are turned on, the fourth operating voltage VGH supplied from the fourth power supply terminal is written to the first pull-down node PD1 through the thirty-eighth transistor T38, and the voltage at the first pull-down node PD1 is in a high level state. At this time, the forty-fourth transistor T44 is turned on under the control of the voltage (high level voltage at this time) at the first pull-down node PD1, and the sixth operating voltage VGL2 supplied from the sixth power supply terminal is written to the second gate driving signal output terminal OUT2, i.e., the second gate driving signal output terminal OUT2 outputs the low level signal, through the forty-fourth transistor T44.

In the display pre-charge stage t1, the signal provided by the display signal input terminal STU1 is in a high level state, the signal provided by the sensing signal input terminal STU2 is in a low level state first and is switched to a high level state after a period of time, the signal provided by the display reset signal terminal STD is in a low level state, the signal provided by the third clock signal terminal CKC is in a low level state, the signal provided by the random signal terminal OE is in a low level state, the signal provided by the sensing reset signal terminal SRST is in a low level state, and the signal provided by the second driving clock signal terminal CLK2 is in a low level state.

Meanwhile, since the signal provided from the random signal terminal OE and the signal provided from the sensing reset signal terminal SRST are both in a low level state, the thirteenth transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascode node H is in a Floating (Floating) state, and the voltage of the sensing cascode node H maintains a high level state of the previous stage. Since the thirty-third transistor T33 is turned off, the voltage of the sensing cascode node H is not affected regardless of whether the signal supplied from the sensing signal input terminal STU2 is in the high level state or the low level state.

In some embodiments, an eleventh capacitor C11 is disposed in the second shift register, a first end of the eleventh capacitor C11 is connected to the sensing cascade node H, and a second end of the eleventh capacitor C11 is connected to the fifth power supply terminal. The eleventh capacitor C11 can maintain the voltage at the sensing cascade node H stable after the sensing cascade stage t0 ends and when the sensing cascade node H is in the floating state; since the signal provided by the third clock signal terminal CKC is in a low level state, the thirty-fifth transistor T35 maintains an off state.

Meanwhile, since the signal provided by the display signal input terminal STU1 is in the high level state and the signal provided by the reset signal terminal STD is in the low level state, the thirty-first transistor T31 is turned on and the thirty-first transistor T32 is turned off, the fourth operating voltage VGH provided by the fourth power supply terminal can be written into the first pull-up node PU1 through the thirty-first transistor T31, and the voltage at the first pull-up node PU1 is in the high level state.

Under the control of the voltage at the first pull-up node PU1, the thirty-ninth transistor T39, the fortieth transistor T40, and the forty-third transistor T43 are turned on, the fifth operating voltage VGL1 supplied from the fifth power supply terminal is written to the first pull-down node PD1 through the thirty-ninth transistor T39 and to the control electrode of the thirty-eighth transistor T38 through the fortieth transistor T40, at which time the thirty-eighth transistor T38 is turned off and the thirty-seventh transistor T37 is equivalent to one resistor, the voltage at the first pull-down node PD1 is in a low state, and the fortieth transistor T47 and the fortieth transistor T44 are both turned off. Meanwhile, the low level signal provided from the second driving clock signal terminal CLK2 is written to the corresponding second gate driving signal output terminal OUT2 through the forty-third transistor T43, i.e., the second gate driving signal output terminal OUT2 outputs the low level signal.

In addition, the fifty-th transistor T50 is turned on under the control of the high level signal provided from the display signal input terminal STU1, and the fifth operating voltage VGL1 provided from the fifth power supply terminal is written to the first pull-down node PD1 through the fifty-th transistor T50, so that the first pull-down node PD1 is noise-reduced to maintain the voltage at the first pull-down node PD1 stable.

In the display output stage t2, the signal provided by the display signal input terminal STU1 is in a low level state, the signal provided by the sensing signal input terminal STU2 is in a high level state and is switched to a low level state after a period of time, the signal provided by the display reset signal terminal STD is in a low level state, the signal provided by the third clock signal terminal CKC is in a low level state, the signal provided by the random signal terminal OE is in a low level state, the signal provided by the sensing reset signal terminal SRST is in a low level state, and the signal provided by the second driving clock signal terminal CLK2 is in a high level state and is switched to a low level state after a period of time.

Since the signal provided by the random signal terminal OE and the signal provided by the sensing reset signal terminal SRST are both in a low level state, the thirteenth transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascode node H is in a Floating state, and the voltage at the sensing cascode node H maintains a high level state in the previous stage (the signal provided by the sensing input signal terminal does not affect the voltage of the sensing cascode node H); since the signal provided by the third clock signal terminal CKC is in a low level state, the thirty-fifth transistor T35 maintains an off state.

Since the signal supplied from the display signal input terminal STU1 and the signal supplied from the display reset signal terminal STD are both in a low level state, the thirty-first transistor T31 and the thirty-first transistor T32 are both in an off state, the first pull-up node PU1 is in a floating state, and maintains a high level state of the previous stage, at this time, the thirty-ninth transistor T39, the fortieth transistor T40, and the fortieth transistor T43 maintain an on state, the first pull-down node PD1 maintains a low level state, the fortieth transistor T47 and the fortieth transistor T44 are both turned off, and the signal supplied from the second driving clock signal terminal CLK2 is written to the second gate driving signal output terminal OUT2 through the fortieth transistor T43.

As can be seen from fig. 24, at the initial time of the display driving stage t2, the signal provided by the second driving clock signal terminal CLK2 is switched from the low level state to the high level state, and the second gate driving signal output terminal OUT2 outputs the high level signal. At the same time, the voltage at the first pull-up node PU1 is pulled up to a higher state under the bootstrap action of the twelfth capacitor C12. In the present embodiment, assuming that the voltages corresponding to the signals provided by the second driving clock signal terminal CLK2 and the third clock signal terminal CKC are VGH and VGL (approximately 0V) when the signals are in the high state, the voltage at the first pull-up node PU1 is approximately VGH during the display pre-charge period t1, and the voltage at the first pull-up node PU1 can be pulled up to approximately 2VGH during the initial time of the display driving period t2. After a period of time, the signal provided by the second driving clock signal terminal CLK2 is switched from the high level state to the low level state, and the second gate driving signal output terminal OUT2 outputs the low level signal; at the same time, under the bootstrap action of the twelfth capacitor C12, the voltage at the first pull-up node PU1 drops to the level at the initial time of the display driving stage t2, that is, to VGH, and at this time, the pull-up node PU is still in the high state.

In the display reset phase t3, the signal provided by the display signal input terminal STU1 is in a low level state, the signal provided by the sensing signal input terminal STU2 is in a low level state, the signal provided by the display reset signal terminal STD is in a high level state, the signal provided by the third clock signal terminal CKC is in a low level state, the signal provided by the random signal terminal OE is in a low level state, the signal provided by the sensing reset signal terminal SRST is in a low level state, and the signal provided by the second driving clock signal terminal CLK2 is in a low level state first and is switched to a high level state after a period of time.

At this time, since the signal provided from the random signal terminal OE and the signal provided from the sensing reset signal terminal SRST are both in a low level state, the thirteenth transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascode node H is in a Floating (Floating) state, and the voltage of the sensing cascode node H maintains a high level state of the previous stage; since the signal provided by the third clock signal terminal CKC is still in the low state, the thirty-fifth transistor T35 maintains the off state.

Since the signal provided from the display signal input terminal STU1 is in a low level state, the thirty-first transistor T31 is turned off, and since the signal provided from the display reset signal terminal STD is in a high level state, the thirty-second transistor T32 is turned on, the fifth operating voltage VGL1 provided from the fifth power supply terminal is written to the first pull-up node PU1 through the thirty-first transistor T32, and the voltage at the first pull-up node PU1 is pulled down to a low level state.

Since the voltage of the first pull-up node PU1 is in the low level state, the thirty-ninth transistor T39, the fortieth transistor T40, and the thirteenth transistor T43 are all in the off state. Since the thirteenth transistor T43 is turned off, the signal supplied from the second driving clock signal terminal CLK2 cannot be written to the second gate driving signal output terminal OUT2. In the pull-down control circuit, the thirty-seventh transistor T37 and the thirty-eighth transistor T38 are turned on under the control of the fourth operating voltage VGH provided at the fourth power supply terminal, the fourth operating voltage VGH provided at the fourth power supply terminal is written to the first pull-down node PD1 through the turned-on thirty-eighth transistor T38, the voltage at the first pull-down node PD1 is in a high level state, at this time, both the forty-fourth transistor T44 and the forty-seventh transistor T47 are turned on, and the fifth operating voltage VGL1 provided at the fifth power supply terminal is written to the first pull-up node PU1 through the turned-on forty-seventh transistor T47, thereby noise reduction is performed on the first pull-up node PU 1; meanwhile, the sixth operating voltage VGL2 supplied from the sixth power supply terminal is written to the second gate driving signal output terminal OUT2 through the forty-fourth transistor T44, that is, the second gate driving signal output terminal OUT2 outputs a low level signal.

In the sensing precharge phase t4, the signal provided by the signal input terminal STU1 is shown in a low level state, the signal provided by the sensing signal input terminal STU2 is shown in a low level state, the signal provided by the reset signal terminal STD is shown in a low level state, the signal provided by the third clock signal terminal CKC is shown in a high level state, the signal provided by the random signal terminal OE is shown in a low level state, the signal provided by the sensing reset signal terminal SRST is shown in a low level state, and the signal provided by the second driving clock signal terminal CLK2 is shown in a low level state.

At this time, since the signal provided from the random signal terminal OE and the signal provided from the sensing reset signal terminal SRST are both in a low level state, the thirteenth transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascode node H is in a Floating (Floating) state, and the voltage of the sensing cascode node H maintains a high level state of the previous stage; accordingly, the thirty-fourth transistor T34 maintains an on state. Meanwhile, since the signal provided by the third clock signal terminal CKC is in the high level state, the thirty-fifth transistor T35 is turned on, the high level signal provided by the third clock signal terminal CKC is written to the first pull-up node PU1 sequentially through turning on the thirty-fourth transistor T34, the sensing precharge node N, and the thirty-fifth transistor T35, and the voltage at the first pull-up node PU1 is in the high level state.

Since the signal supplied from the display signal input terminal STU1 and the display reset signal terminal STD are both in a low level state, both the thirty-first transistor T31 and the thirty-second transistor T32 are turned off.

Since the voltage at the first pull-up node PU1 is in the high state, the thirty-ninth transistor T39, the fortieth transistor T40, and the forty-third transistor T43 are all turned on, the fifth operating voltage VGL1 supplied from the fifth power supply terminal is written to the first pull-down node PD1 through the thirty-ninth transistor T39 and to the gate of the thirty-eighth transistor T38 through the fortieth transistor T40, at which time the thirty-eighth transistor T38 is turned off and the thirty-seventh transistor T37 is equivalent to one resistor, the voltage at the first pull-down node PD1 is in the low state, and the fortieth transistor T47 and the fortieth transistor T44 are all turned off. Meanwhile, the low level signal provided from the second driving clock signal terminal CLK2 is written to the corresponding second gate driving signal output terminal OUT2 through the forty-third transistor T43, i.e., the second gate driving signal output terminal OUT2 outputs the low level signal.

In addition, since the signal provided by the third clock signal terminal CKC is in the high state, the voltage at the sensing cascade node H is in the high state, and thus both the forty-eight transistor T48 and the forty-nine transistor T49 are turned on, the fifth operating voltage VGL1 provided by the fifth power terminal is written into the first pull-down node PD1, so that the first pull-down node PD1 is noise-reduced to maintain the voltage at the first pull-down node PD1 stable.

In the sense output stage t5, the signal provided by the signal input terminal STU1 is shown in a low level state, the signal provided by the sense signal input terminal STU2 is shown in a low level state, the signal provided by the reset signal terminal STD is shown in a low level state, the signal provided by the third clock signal terminal CKC is shown in a low level state, the signal provided by the random signal terminal OE is shown in a low level state, the signal provided by the sense reset signal terminal SRST is shown in a low level state, and the signal provided by the second driving clock signal terminal CLK2 is shown in a high level state and is shown in a low level state after a period of time.

At this time, since the signal provided from the random signal terminal OE and the signal provided from the sensing reset signal terminal SRST are both in a low level state, the thirteenth transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascode node H is in a Floating (Floating) state, the voltage of the sensing cascode node H maintains a high level state of the previous stage, and the thirty-fourth transistor T34 maintains a conductive state; since the signal provided by the third clock signal terminal CKC is in a low level state, the thirty-fifth transistor T35 is turned off, and the signal provided by the third clock signal terminal CKC does not affect the voltage at the first pull-up node PU 1.

Since the signal provided from the display signal input terminal STU1 and the signal provided from the display reset signal terminal STD are both in the low level state, the thirty-first transistor T31 and the thirty-first transistor T32 are both turned off, the first pull-up node PU1 is in the floating state, and maintains the high level state of the previous stage, at this time, the thirty-ninth transistor T39, the fortieth transistor T40 and the fortieth transistor T43 remain turned on, the first pull-down node PD1 maintains the low level state, the fortieth transistor T47 and the fortieth transistor T44 remain turned off, and the signal provided from the second driving clock signal terminal CLK2 is written to the corresponding second gate driving signal output terminal OUT2 through the turned-on fortieth transistor T43.

At the initial time of the sensing output stage t5, the signal provided by the second driving clock signal terminal CLK2 is switched from the low level state to the high level state, and the second gate driving signal output terminal OUT2 outputs the high level signal. At the same time, the voltage at the first pull-up node PU1 is pulled up to a higher state under the bootstrap action of the twelfth capacitor C12. In the present embodiment, assuming that the voltages corresponding to the signals provided by the second driving clock signal terminal CLK2 and the third clock signal terminal CKC are VGH and VGL (approximately 0V) when the signals are in the high state, the voltage at the first pull-up node PU1 is approximately VGH when the precharge phase t4 is sensed, and the voltage at the first pull-up node PU1 can be pulled up to approximately 2VGH when the initial time of the driving phase t5 is sensed. After a period of time, the signal provided by the second driving clock signal terminal CLK2 is switched from the high level state to the low level state, and the second gate driving signal output terminal OUT2 outputs the low level signal; meanwhile, under the bootstrap action of the twelfth capacitor C12, the voltage at the first pull-up node PU1 drops to the level at the initial time of the sensing driving stage t5, that is, to VGH, and at this time, the first pull-up node PU1 is still in the high state.

In the sense reset phase t6, the signal provided by the signal input terminal STU1 is shown in a low level state, the signal provided by the sense signal input terminal STU2 is shown in a low level state, the signal provided by the reset signal terminal STD is shown in a low level state, the signal provided by the third clock signal terminal CKC is shown in a low level state, the signal provided by the random signal terminal OE is shown in a high level state, the signal provided by the sense reset signal terminal SRST is shown in a high level state, and the signal provided by the second driving clock signal terminal CLK2 is shown in a low level state.

Since the signal provided by the random signal end OE and the signal provided by the sensing reset signal end SRST are both in the high level state, the thirty-third transistor T33 and the thirty-sixth transistor T36 are both turned on, the low level signal provided by the sensing signal input end STU2 is written into the sensing cascade node H through the thirty-third transistor T33, the voltage at the sensing cascade node H is in the low level state, and the thirty-fourth transistor T34 is turned off, so as to realize the reset of the sensing cascade node H. Since the signal provided from the third clock signal terminal CKC is in a low level state, the thirty-fifth transistor T35 is turned off.

Since the thirty-sixth transistor T36 is turned on, the fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-up node PU1 through the thirty-sixth transistor T32, and the voltage at the first pull-up node PU1 is in a low level state, so as to reset the first pull-up node PU 1.

Since the signal supplied from the display signal input terminal STU1 is in a low level state and the signal supplied from the display reset signal terminal STD is in a low level state, both the thirty-first transistor T31 and the thirty-second transistor T32 are turned off.

Since the voltage at the first pull-up node PU1 is in the low level state, the thirty-ninth transistor T39, the fortieth transistor T40, and the thirteenth transistor T43 are all turned off; in the pull-down control circuit, the first operating voltage VDD supplied from the fourth power supply terminal is written to the first pull-down node PD1 through the thirty-eighth transistor T38, the voltage at the first pull-down node PD1 is in a high level state, at this time, the forty-seventh transistor T47 and the forty-fourth transistor T44 are turned on, the fifth operating voltage VGL1 supplied from the fifth power supply terminal is written to the first pull-up node PU1 through the forty-seventh transistor T47 to noise-reduce the first pull-up node PU1, and the sixth operating voltage VGL2 supplied from the sixth power supply terminal is written to the second gate driving signal output terminal OUT2 through the forty-fourth transistor T44, that is, the second gate driving signal output terminal OUT2 outputs a low level signal.

Therefore, the second shift register can output high-level (effective level) signals in the display driving period and the blank period in one frame respectively so as to meet the driving requirement of the sensing transistors in the pixel units of the corresponding row.

In the present embodiment, the voltage at the first pull-up node PU1 needs to be kept in the low level (inactive level) state during the period between the end of the display reset period t3 and the start of the sensing precharge period t 4. By providing the forty-seventh transistor T47, the pull-down control circuit and the forty-seventh transistor T47 can form a positive feedback loop to strengthen the voltage at the first pull-up node PU 1. Specifically, when the voltage of the first pull-up node PU1 is in the low level state, the pull-down control circuit controls the voltage at the first pull-down node PD1 to be in the high level state, and at this time, the forty-seventh transistor T47 is turned on, and the fifth operating voltage VGL1 is written into the first pull-up node PU1 through the forty-seventh transistor T47, so as to strengthen the voltage at the pull-up node to be in the low level state (the voltage is VGL 1), thereby achieving the purpose of noise reduction.

It should be noted that, at each stage in the driving process, the operating states of the forty-first transistor T41 in the gate cascade output circuit 45 and the operating states of the forty-third transistor T43 in the second gate driving output circuit 46 are the same (both are turned on or off at the same time), and the operating states of the forty-fourth transistor T42 in the gate cascade output circuit 45 and the operating states of the forty-fourth transistor T44 in the second gate driving output circuit 46 are the same (both are turned on or off at the same time). The waveform of the signal provided by the cascade clock signal terminal CLKX may be the same as or different from the waveform of the signal provided by the second driving clock signal terminal CLK 2.

Fig. 25A is a timing chart of one operation of the cascade clock signal terminal, the second driving clock signal terminal, the gate cascade signal output terminal, and the second gate driving signal output terminal in the embodiment of the present disclosure, as shown in fig. 25A, the waveform of the signal provided by the cascade clock signal terminal CLKX may be the same as the waveform of the signal provided by the second driving clock signal terminal CLK2, and at this time, the waveforms of the signals output by the gate cascade signal output terminal CR1 and the second gate driving signal output terminal OUT2 are the same.

Fig. 25B is another operation timing diagram of the cascade clock signal terminal, the second driving clock signal terminal, the gate cascade signal output terminal, and the second gate driving signal output terminal in the embodiment of the present disclosure, as shown in fig. 25B, a portion of the waveform of the signal provided by the cascade clock signal terminal CLKX in the display driving period is the same as a portion of the waveform of the signal provided by the second driving clock signal terminal CLK2 in the display driving period, but a portion of the waveform of the signal provided by the cascade clock signal terminal CLKX in the blanking period is different from a portion of the waveform of the signal provided by the second driving clock signal terminal CLK2 in the blanking period. For example, the start time of the signal provided by the cascade connection clock signal terminal CLKX in the active level state in the blank period is the same as the start time of the signal provided by the second driving clock signal terminal CLK2 in the active level state, and the duration of the signal provided by the cascade connection clock signal terminal CLKX in the active level state in the blank period may be smaller than the duration of the signal provided by the second driving clock signal terminal CLK2 in the active level state in the blank period.

In practical applications, when the start time of the signal provided by the cascade connection clock signal terminal CLKX in the active level state in the blank period is the same as the start time of the signal provided by the second driving clock signal terminal CLK2 in the active level state in the blank period, the period of the signal provided by the cascade connection clock signal terminal CLKX in the active level state in the blank period is overlapped with the period of the signal provided by the random signal terminal OE of the second shift register corresponding to the next pixel unit to be subjected to external compensation sensing in the active level state in the blank period (the start time of the signal provided by the second driving clock signal terminal CLK2 in the active level state in the blank period is the period of the signal provided by the random signal terminal OE of the second shift register corresponding to the next pixel unit to be subjected to external compensation sensing in the active level state in the blank period), so that the sensing cascade signal outputted by the second shift register at the present stage and in the active level state can be written into the sensing cascade connection node in the overlapped second shift register in the above period is ensured.

It should be noted that, as will be appreciated by those skilled in the art, in some embodiments, the second shift register may optionally not include the first noise reduction circuit, the second noise reduction circuit, and/or the third noise reduction circuit.

In the embodiment of the disclosure, taking the pixel unit in the m-th row as an example of the pixel unit needing external compensation sensing, the second gate driving signal output terminal OUT2 of the second shift register corresponding to the pixel unit in the m-th row outputs an effective level signal to the second gate line configured by the pixel unit in the m-th row in a blank period. In order to ensure smooth execution of the external compensation sensing process of the pixel units in the m-th row, the light emission control driving signal output end of the first shift register corresponding to the pixel units in the m-th row needs to output an effective level signal to the light emission control signal line configured by the pixel units in the m-th row. Based on this principle, in the embodiment of the present disclosure, the second gate driving signal output end OUT2 of the second shift register corresponding to the mth row of pixel units may be used as the forced output control end of the first shift register corresponding to the mth row of pixel units, so that the forced output control end of the first shift register corresponding to the mth row of pixel units always receives an effective level signal in the external compensation sensing process of the mth row of pixel units, and the light-emitting control driving signal output end of the first shift register corresponding to the mth row of pixel units always outputs an effective level signal in the external compensation sensing process of the mth row of pixel units, so as to ensure that the external compensation sensing process of the mth row of pixel units is normally performed. That is, in the first gate driving circuit, the forced output control terminal to which any one of the first shift registers is connected is the second gate driving signal output terminal OUT2 arranged in the second shift register corresponding to the same row of pixel units as the first shift register.

Similarly, when the period in which the signal provided by the cascade clock signal terminal CLKX is in the active level state in the blank period completely covers the period in which the signal provided by the second driving clock signal terminal CLK2 is in the active level state in the blank period, the gate cascade signal output terminal CR1 of the second shift register corresponding to the pixel unit in the m-th row may be used as the forced output control terminal CSD of the first shift register corresponding to the pixel unit in the m-th row. That is, in the first gate driving circuit, the forced output control terminal to which any one of the first shift registers is connected is the gate cascade signal output terminal CR1 arranged in the second shift register corresponding to the same row of pixel units as the first shift register.

In addition, when the forced output control terminal includes the first control terminal CP1 and the second control terminal CP2, the first control terminal CP1 configured by the first shift register corresponding to the m-th row of pixel units may be a sensing cascade node H inside the second shift register corresponding to the m-th row of pixel units, and the second control terminal CP2 configured by the first shift register corresponding to the m-th row of pixel units may be a fourth clock signal terminal CP2 configured in advance.

Fig. 25C is a working timing chart of a sensing cascade node, a fourth clock signal terminal, and a second gate driving signal output terminal in the embodiment of the disclosure, as shown in fig. 25C, as an alternative implementation, a signal provided by the fourth clock signal terminal CKD is in an active level state in a blank period and is in an inactive level state in other periods, and a period in which the signal provided by the fourth clock signal terminal CKD is in the active level state and a period in which a sensing cascade node H inside the second shift register corresponding to the mth row of pixel units are in the active level state overlap each other, and the two overlapping periods completely cover each other, so that the second gate driving signal output terminal OUT2 of the second shift register corresponding to the mth row of pixel units outputs the active level signal in the blank period, and the second gate driving signal output terminal OUT2 of the second shift register corresponding to the mth row of pixel units outputs the active level signal in the blank period. That is, in the first gate driving circuit, the first control terminal CP1 and the second control terminal CP2 to which any one of the first shift registers is connected are respectively: a sensing cascade node H inside the second shift register corresponding to the same row of pixel units as the first shift register and a fourth clock signal terminal CKD configured in advance. Of course, the duration of the fourth clock signal terminal in the active level state may be smaller than the duration of the blank period; for example, the period in which the fourth clock signal terminal is in the active level state is only the period corresponding to the sensing output stage t5, or the period in which the fourth clock signal terminal is in the active level state is only the period corresponding to the sensing output stage t5 plus at least part of the period in the sensing precharge stage t 4.

Fig. 26 is a schematic circuit diagram of a second shift register according to an embodiment of the disclosure, where, as shown in fig. 26, the second shift register shown in fig. 26 further includes: a first gate drive output circuit 47; wherein the first gate driving output circuit 47 is connected to the first pull-up node PU1, the first pull-down node PD1, the first gate driving signal output terminal OUT1, the first driving clock signal terminal CLK1, and the sixth power supply terminal, the first gate driving output circuit 47 is configured to write a signal provided by the first driving clock signal terminal CLK1 to the first gate driving signal output terminal OUT1 in response to control of a voltage at the first pull-up node PU1, and to write a sixth operating voltage provided by the sixth power supply terminal to the first gate driving signal output terminal OUT1 in response to control of a voltage at the first pull-down node PD 1.

In the embodiment of the disclosure, the second shift register may not only provide the gate driving signal to the second gate line configured by the corresponding row of pixel units, but also provide the gate driving signal to the first gate line configured by the corresponding row of pixel units at the same time. That is, the second gate driving circuit may be used to simultaneously drive the first gate line and the second gate line.

Wherein in some embodiments the first gate drive output circuit 47 comprises: a forty-fifth transistor T45 and a forty-sixth transistor T46.

The control electrode of the forty-fifth transistor T45 is connected to the first pull-up node PU1, the first electrode of the forty-fifth transistor T45 is connected to the first driving clock signal terminal CLK1, and the second electrode of the forty-fifth transistor T45 is connected to the first gate driving signal output terminal OUT 1.

The control electrode of the forty-sixth transistor T46 is connected to the first pull-down node PD1, the first electrode of the forty-sixth transistor T46 is connected to the sixth power supply terminal, and the second electrode of the forty-sixth transistor T46 is connected to the first gate driving signal output terminal OUT 1.

In some embodiments, the second shift register further includes a thirteenth capacitor C13, a first terminal of the thirteenth capacitor C13 is connected to the first pull-up node PU1, and a second terminal of the thirteenth capacitor C13 is connected to the first gate driving signal output terminal OUT 1.

The driving process of the second shift register shown in fig. 26 is the same as the driving process of the second shift register shown in fig. 23, and the detailed process is not repeated here. It should be noted that, at each stage in the driving process, the operating states of the forty-fifth transistor T45 in the first gate driving output circuit and the operating states of the forty-third transistor T43 in the second gate driving output circuit 46 are the same (both are turned on or off at the same time), and the operating states of the forty-sixth transistor T46 in the first gate driving output circuit and the operating states of the forty-fourth transistor T44 in the second gate driving output circuit 46 are the same (both are turned on or off at the same time).

Fig. 27 is a timing chart of an operation of the first driving clock signal terminal, the second driving clock signal terminal, the first gate driving signal output terminal, and the second gate driving signal output terminal in the embodiment of the disclosure, as shown in fig. 27, since the gate driving signals required for configuring the first gate line and the second gate line of the same row of pixel units are different, the signals provided by the first driving clock signal terminal CLK1 and the second driving clock signal terminal CLK2 are different. Specifically, the waveforms of the signals provided by the first driving clock signal terminal CLK1 and the second driving clock signal terminal CLK2 are the same in the display driving period, but the waveforms of the signals provided by the first driving clock signal terminal CLK1 and the second driving clock signal terminal CLK2 in the active level state in the blank period are different.

Fig. 28 is a schematic circuit diagram of a second shift register according to an embodiment of the disclosure, as shown in fig. 28, in some embodiments, the second shift register is configured with a fourth gate driving signal output terminal OUT4, and the fourth gate driving signal output terminal OUT4 is connected to a corresponding second gate line. That is, one second shift register may supply a gate driving signal to the second gate lines where the two rows of pixel units are arranged.

The second shift register further includes a second display precharge reset circuit 51, a second sensing precharge reset circuit 53, a second pull-down control circuit 54, and a fourth gate drive output circuit 56; the second display precharge reset circuit 51, the second sensing precharge reset circuit 53, the second pull-down control circuit 54, and the fourth gate driving output circuit 56 are connected to the second pull-up node PU2, and the second pull-down control circuit 54 and the fourth gate driving output circuit 56 are connected to the second pull-down node PD2.

The second display pre-charge reset circuit 51 is connected to the display signal input terminal STU1, the display reset signal terminal STD, and the fifth power supply terminal, and the second display pre-charge reset circuit 51 is configured to write a signal provided by the display signal input terminal STU1 into the second pull-up node PU2 in response to control of a signal provided by the display signal input terminal STU1, and write a fifth operating voltage provided by the fifth power supply terminal into the second pull-down node PD2 in response to control of a signal provided by the display reset signal terminal STD.

The second sensing precharge reset circuit 53 is connected to the sensing precharge signal terminal, the third clock signal terminal CKC, the sensing reset signal terminal SRST, and the fifth power supply terminal, and the second sensing precharge reset circuit 53 is configured to write the voltage at the sensing precharge node N to the second pull-up node PU2 in response to the control of the signal provided by the third clock signal terminal CKC, and write the fifth operating voltage provided by the fifth power supply terminal to the second pull-up node PU2 in response to the control of the signal provided by the sensing reset signal terminal SRST.

The second pull-down control circuit 54 is connected to the seventh power supply terminal and the fifth power supply terminal, and the second pull-down control circuit 54 is configured to write a voltage inverted from the voltage at the second pull-up node PU2 to the second pull-down node PD 2.

The fourth gate driving output circuit 56 is connected to the fourth driving clock signal terminal CLK4 and the sixth power supply terminal, and the fourth gate driving output circuit 56 is configured to write a signal provided from the fourth driving clock signal terminal CLK4 to the fourth gate driving signal output terminal OUT4 in response to control of the voltage at the second pull-up node PU2, and to write a sixth operating voltage provided from the sixth power supply terminal to the fourth gate driving signal output terminal OUT4 in response to control of the voltage at the second pull-down node PD 2.

In some embodiments, the second shift register further includes a first gate drive output circuit 47 and a third gate drive output circuit 57. The detailed description of the first gate driving output circuit 47 can be found in the previous embodiment, and the detailed description of the third gate driving circuit 57 will be omitted here.

The third gate driving output circuit 57 is connected to the second pull-up node PU2, the second pull-down node PD2, the third gate driving signal output terminal OUT3, the third driving clock signal terminal CLK3, and the sixth power supply terminal, and the third gate driving output circuit 57 is configured to write a signal supplied from the third driving clock signal terminal CLK3 to the third gate driving signal output terminal OUT3 in response to control of a voltage at the second pull-up node PU2, and to write a sixth operating voltage supplied from the sixth power supply terminal to the third gate driving signal output terminal OUT3 in response to control of a voltage at the second pull-down node PD 2. The first gate driving signal output terminal OUT1 and the third gate driving signal output terminal OUT3 are connected to the corresponding first gate lines, respectively.

In the embodiment of the disclosure, each stage of the second shift register in the second gate driving circuit may correspond to two rows of pixel units, where the second gate driving output circuit 46 and the fourth gate driving output circuit 56 may respectively provide gate driving signals to the second gate lines configured by the corresponding rows of pixel units, and the first gate driving output circuit 47 and the third gate driving output circuit 57 may respectively provide gate driving signals to the first gate lines configured by the corresponding rows of pixel units.

In some embodiments, the second display precharge reset circuit 51 includes a fifty-first transistor T51 and a fifth twelve transistor T52.

The control electrode of the fifty-first transistor T51 is connected to the display signal input STU1, the first electrode of the fifty-first transistor T51 is connected to the control electrode of the fifty-first transistor T51, and the second electrode of the fifty-first transistor T51 is connected to the second pull-up node PU 2.

The control electrode of the fifty-second transistor T52 is connected to the display reset signal terminal STD, the first electrode of the fifty-second transistor T52 is connected to the second pull-up node PU2, and the second electrode of the fifty-second transistor T52 is connected to the fifth power supply terminal.

In some embodiments, the sensing precharge reset circuit includes a fifty-fifth transistor T55 and a fifty-sixth transistor T56.

The control electrode of the fifty-fifth transistor T55 is connected to the third clock signal terminal CKC, the first electrode of the fifty-fifth transistor T55 is connected to the sensing pre-charge node N, and the second electrode of the fifty-fifth transistor T55 is connected to the second pull-up node PU 2.

The control electrode of the fifty-sixth transistor T56 is connected to the sensing reset signal terminal SRST, the first electrode of the fifty-sixth transistor T56 is connected to the second pull-up node PU2, and the second electrode of the fifty-sixth transistor T56 is connected to the fifth power supply terminal.

In some embodiments, the second pull-down control circuit 54 includes a fifty-seventh transistor T57, a fifty-eighth transistor T58, a fifty-ninth transistor T59, and a sixty-transistor T60.

The control electrode of the fifty-seventh transistor T57 is connected to the seventh power supply terminal, the first electrode of the fifty-seventh transistor T57 is connected to the control electrode of the fifty-seventh transistor T57, and the second electrode of the fifty-seventh transistor T57 is connected to the control electrode of the fifty-eighth transistor T58.

The control electrode of the fifty-eighth transistor T58 is connected to the first electrode of the sixty transistor T60, the first electrode of the fifty-eighth transistor T58 is connected to the seventh power supply terminal, and the second electrode of the fifty-eighth transistor T58 is connected to the second pull-down node PD 2.

The control electrode of the fifty-ninth transistor T59 is connected to the second pull-up node PU2, the first electrode of the fifty-ninth transistor T59 is connected to the second pull-down node PD2, and the second electrode of the fifty-ninth transistor T59 is connected to the fifth power supply terminal.

The control electrode of the sixty transistor T60 is connected to the second pull-up node PU2, and the second electrode of the sixty transistor T60 is connected to the fifth power supply terminal.

In some embodiments, the third gate drive output circuit 57 includes: a sixty-fifth transistor T65 and a sixty-sixth transistor T66.

The control electrode of the sixty-fifth transistor T65 is connected to the first pull-up node PU1, the first electrode of the sixty-fifth transistor T65 is connected to the third driving clock signal terminal CLK3, and the second electrode of the sixty-fifth transistor T65 is connected to the third gate driving signal output terminal OUT 3.

The control electrode of the sixty-sixth transistor T66 is connected to the second pull-down node PD2, the first electrode of the sixty-sixth transistor T66 is connected to the sixth power supply terminal, and the second electrode of the sixty-sixth transistor T66 is connected to the third gate driving signal output terminal OUT 3.

In some embodiments, the fourth gate drive output circuit 56 includes a sixty-third transistor T63 and a sixty-fourth transistor T64.

The control electrode of the sixteenth transistor T63 is connected to the second pull-up node PU2, the first electrode of the sixty-third transistor T63 is connected to the fourth driving clock signal terminal CLK4, and the second electrode of the sixty-third transistor T63 is connected to the fourth gate driving signal output terminal OUT 4.

The control electrode of the sixty-fourth transistor T64 is connected to the second pull-down node PD2, the first electrode of the sixty-fourth transistor T64 is connected to the sixth power supply terminal, and the second electrode of the sixty-fourth transistor T64 is connected to the fourth gate driving signal output terminal OUT 4.

In some embodiments, the second shift register further includes a fourteenth capacitor C14, a first terminal of the fourteenth capacitor C14 is connected to the second pull-up node PU2, and a second terminal of the fourteenth capacitor C14 is connected to the fourth gate driving signal output terminal OUT 4.

In some embodiments, the second shift register further includes a fifteenth capacitor C15, a first end of the fifteenth capacitor C15 is connected to the second pull-up node PU2, and a second end of the fifteenth capacitor C15 is connected to the third gate driving signal output terminal OUT 3.

In some embodiments, the second shift register further comprises: a fourth noise reduction circuit 58; the fourth noise reduction circuit 58 is connected to the second pull-up node PU2, the second pull-down node PD2, and the fifth power supply terminal, and the fourth noise reduction circuit 58 is configured to write the fifth operating voltage provided by the fifth power supply terminal to the second pull-up node PU2 in response to the control of the voltage at the second pull-down node PD 2. In the disclosed embodiment, noise reduction from the second pull-up node PU2 may be performed by the fourth noise reduction circuit 58 to maintain the voltage at the second pull-up node PU2 stable.

Optionally, the fourth noise reduction circuit 58 includes a sixty-seventh transistor T67; the control electrode of the sixty-seventh transistor T67 is connected to the second pull-down node PD2, the first electrode of the sixty-seventh transistor T67 is connected to the fifth power supply terminal, and the second electrode of the sixty-seventh transistor T67 is connected to the second pull-up node PU 2.

In some embodiments, the second shift register further comprises: a fifth noise reduction circuit 59; the fifth noise reduction circuit 59 is connected to the second pull-down node PD2, the sensing cascode node H, the third clock signal terminal CKC, and the fifth power supply terminal, and the fifth noise reduction circuit 59 is configured to write a fifth operating voltage provided by the fifth power supply terminal into the second pull-down node PD2 in response to control of the voltage at the sensing cascode node H and the signal provided by the third clock signal terminal CKC. In the embodiment of the present disclosure, noise reduction from the second pull-down node PD2 may be performed by the fifth noise reduction circuit 59 to maintain the stability of the voltage at the second pull-down node PD2.

Optionally, the fifth noise reduction circuit 59 includes a sixty-eighth transistor T68 and a sixty-ninth transistor T69. The control electrode of the sixty-eighth transistor T68 is connected to the third clock signal terminal CKC, the first electrode of the sixty-eighth transistor T68 is connected to the second pull-down node PD2, and the second electrode of the sixty-eighth transistor T68 is connected to the first electrode of the sixty-ninth transistor T69. The control electrode of the sixty-nine transistor T69 is connected to the sensing cascade node H, and the second electrode of the sixty-nine transistor T69 is connected to the fifth power supply terminal.

In some embodiments, the second shift register further comprises: and a sixth noise reduction circuit 60, the sixth noise reduction circuit 60 being connected to the display signal input terminal STU1, the second pull-down node PD2 and the fifth power supply terminal, the sixth noise reduction circuit 60 being configured to write the fifth operating voltage supplied from the fifth power supply terminal into the second pull-down node PD2 in response to control of the signal supplied from the display signal input terminal STU 1. In the embodiment of the present disclosure, noise reduction from the second pull-down node PD2 may be performed by the sixth noise reduction circuit 60 to maintain the stability of the voltage at the second pull-down node PD2.

Optionally, the sixth noise reduction circuit 60 includes: a seventy transistor T70; the control electrode of the seventy transistor T70 is connected to the display signal input terminal STU1, the first electrode of the seventy transistor T70 is connected to the fifth power supply terminal, and the second electrode of the fifty transistor T50 is connected to the second pull-down node PD2.

The driving timing of the second shift register shown in fig. 28 can be seen from fig. 24, and the detailed process is not repeated here. Wherein, the voltage at the first pull-up node PU1 and the voltage at the second pull-up node PU2 are kept consistent in each stage, and the voltage at the first pull-down node PD1 and the voltage at the second pull-down node PD2 are kept consistent.

Fig. 29 is a schematic diagram of still another circuit structure of a second shift register according to an embodiment of the present disclosure, where, as shown in fig. 29, the second shift register further includes: the active output circuit 61 is blank.

The blank valid output circuit 61 is connected to the second pull-up node PU2, the second pull-down node PD2, the blank valid clock signal terminal CLKY, the blank valid signal output terminal CR2, and the sixth power supply terminal, and the blank valid output circuit 61 is configured to write a signal provided by the blank valid clock signal terminal CLKY to the blank valid signal output terminal CR2 in response to control of a voltage at the second pull-up node PU2, and write a sixth operating voltage provided by the sixth power supply terminal to the blank valid signal output terminal CR2 in response to control of a voltage at the second pull-down node PD 2.

In some embodiments, the blank valid output circuit 61 includes a sixty-one transistor T61 and a sixty-two transistor T62.

The control electrode of the sixty-first transistor T61 is connected to the second pull-up node PU2, the first electrode of the sixty-first transistor T61 is connected to the blank valid clock signal terminal CLKY, and the second electrode of the sixty-first transistor T61 is connected to the blank valid signal output terminal CR2.

The control electrode of the sixty transistor T62 is connected to the second pull-down node PD2, the first electrode of the sixty transistor T62 is connected to the fifth power supply terminal, and the second electrode of the sixty transistor T62 is connected to the blank valid signal output terminal CR2.

The driving timing of the second shift register shown in fig. 29 can be seen from fig. 24, and the detailed process is not repeated here. In each stage, the operating states of the sixty-first transistor T61 in the blank effective output circuit 61 and the operating states of the thirteenth transistor T43 in the second gate driving output circuit 46 are the same (both are turned on or off at the same time), and the operating states of the sixty-second transistor T62 in the blank effective output circuit 61 and the forty-fourth transistor T44 in the second gate driving output circuit 46 are the same (both are turned on or off at the same time).

In some embodiments, the blank valid clock signal terminal CLKY clocks inactive level signals during the display drive period and valid level signals during the blank period. In other embodiments, the blank valid clock signal terminal clocks the inactive level signal during the display driving period and provides the same signal waveform as the signal waveform provided by the second driving clock signal terminal CLK2 during the blank period.

In the first gate driving circuit 200, the forced output control terminal CSD connected to any one of the first shift registers includes: and a blank valid signal output end CR2 configured by a second shift register corresponding to the same row of pixel units as the first shift register. The specific principle can be found in the foregoing, and will not be described in detail here.

Since the voltages of the first pull-up node PU1 and the second pull-up node PU2 remain consistent throughout, the voltages of the first pull-down node PD1 and the second pull-down node PD2 remain consistent throughout, the blank valid output circuit 61 may also be configured to be connected to the first pull-up node PU1 and the second pull-up node, where the blank valid output circuit 61 is configured to write the signal provided by the blank valid clock signal terminal to the blank valid signal output terminal in response to the control of the voltage at the first pull-up node PU1, and to write the sixth operating voltage provided by the sixth power supply terminal to the blank valid signal output terminal CR1 in response to the control of the voltage at the first pull-down node PD 1. The corresponding figures are not given here.

Fig. 30 is a schematic diagram of a circuit structure in which two pixel units located in adjacent rows share the same light emission control transistor in the embodiment of the present disclosure, as shown in fig. 30, in the embodiment of the present disclosure, each pixel unit may include an independent light emission control transistor ETFT, and of course, two pixel units located in adjacent rows may share the same light emission control transistor ETFT. By the design of the common light emission control transistor ETFT, the number of transistors in the display area can be effectively reduced, and the number of first shift registers in the first gate driving circuit 200 can be effectively reduced. Specifically, the number of the first shift registers in the first gate driving circuit 200 can be halved by sharing the same light emission control transistor ETFT for two pixel cells of adjacent rows, compared to a scheme in which each pixel cell may include a separate one light emission control transistor ETFT.

Of course, other circuit structures may also be used for the pixel unit in the embodiments of the disclosure. The specific cases are not exemplified here.

The display device provided by the embodiment of the disclosure may be: flexible wearable equipment, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigator and any other products or components with display functions. Other essential components of the display device will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the invention.

It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims

1. A shift register, comprising:

2. The shift register of claim 1, further comprising: the node control circuit is positioned between the sixth node and the first node, and the sixth node is connected with the first node through the node control circuit;

3. The shift register of claim 2, wherein the node control circuit comprises a first write sub-circuit, a second write sub-circuit, a twenty-fourth transistor, and a twenty-fifth transistor;

4. A shift register as claimed in claim 3, in which the first write sub-circuit comprises a twenty-sixth transistor and the second write sub-circuit comprises a twenty-seventh transistor;

5. A shift register according to claim 3, wherein the forced output control terminal comprises a first control terminal and a second control terminal;

6. The shift register according to claim 2, further comprising a twenty-eighth transistor;

7. The shift register according to claim 1, wherein the second light-emitting drive output circuit includes a twenty-third transistor;

8. The shift register of claim 1, wherein the forced output control terminal comprises a first control terminal and a second control terminal;

9. The shift register of claim 1, wherein the voltage regulating circuit comprises:

10. The shift register of claim 9, wherein the first input circuit comprises a first transistor, the second input circuit comprises a second transistor and a third transistor, the first voltage control circuit comprises a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitor, the second voltage control circuit comprises a seventh transistor and an eighth transistor, the light emitting cascode output circuit comprises a ninth transistor and a tenth transistor, the first light emitting driving output circuit comprises a twenty-first transistor and a twenty-second transistor;

11. The shift register of claim 9, wherein the voltage regulating circuit further comprises a first anti-leakage circuit, the first input circuit, the second node control voltage being connected to a fifth node, the first anti-leakage circuit being located between the fifth node and the second node, the first input circuit, the second voltage control circuit being all connected to the second node through the first anti-leakage circuit;

and/or the voltage regulating circuit further comprises a second anti-leakage circuit, the output circuit is connected with a second power supply end through the second anti-leakage circuit, and the luminous cascade output circuit and the second anti-leakage circuit are connected with a second anti-leakage node;

12. The shift register according to claim 11, wherein the first leakage preventing circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

the light-emitting global reset circuit includes a sixteenth transistor;

13. A gate driving circuit, comprising: a plurality of first shift registers in cascade, the first shift registers employing the shift registers of any one of the preceding claims 1 to 12;

14. A display device, comprising: the display area comprises a plurality of pixel units which are arranged in an array, wherein each row of pixel units is provided with a corresponding light-emitting control signal line, and the light-emitting control signal line is connected with a control electrode of a light-emitting control transistor in the corresponding pixel unit;

the peripheral region includes a first gate driving circuit employing the gate driving circuit of claim 13.

15. The display device according to claim 14, wherein each row of pixel cells is further configured with a corresponding second gate line connected to a control electrode of a sense transistor in the corresponding pixel cell;

16. The display device according to claim 15, wherein the forced output control terminal to which any one of the first shift registers is connected in the first gate driving circuit includes: a second gate driving signal output terminal or a gate cascade signal output terminal configured to correspond to a second shift register of the same row of pixel units as the first shift register;

17. The display device according to claim 15, wherein the second shift register is configured with a fourth gate driving signal output terminal connected to the corresponding second gate line;

18. The display device according to claim 17, wherein the second shift register further comprises: a blank valid output circuit;

19. A display device according to claim 17 or 18, wherein each row of pixel cells is further provided with a corresponding first gate line connected to a control electrode of a data writing transistor in the corresponding pixel cell;