CN116645923A

CN116645923A - Display substrate, driving method thereof and display device

Info

Publication number: CN116645923A
Application number: CN202210138912.XA
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-02-15
Filing date: 2022-02-15
Publication date: 2023-08-25

Abstract

The present disclosure provides a display substrate including: the display device comprises a display area and a peripheral area positioned at the periphery of the display area, wherein a plurality of pixel units and a plurality of light-emitting control signal lines are arranged in the display area; the peripheral area is internally provided with a first grid driving circuit and at least two first starting control signal lines, the first grid driving circuit comprises at least two first shift register groups which are in one-to-one correspondence with the first starting control signal lines and are independent of each other, each first shift register group comprises at least two first shift registers which are cascaded, and the signal output end of each first shift register is connected with the corresponding light-emitting control signal line; in the first shift register group, the signal input end of the first shift register positioned at the first stage is connected with a first start control signal line configured by the first shift register group, and the signal input end of any one of the other first shift registers except the first stage is connected with the signal output end of the first shift register of the previous stage.

Description

Display substrate, driving method thereof and display device

Technical Field

The present invention relates to the field of display, and in particular, to a display substrate, a driving method thereof, and a display device.

Background

Active matrix organic light emitting diode panels (Active Matrix Organic Light Emitting Diode, abbreviated as AMOLED) are becoming increasingly popular. The pixel display device of the AMOLED is an Organic Light-Emitting Diode (OLED), and the AMOLED is capable of Emitting Light by driving a thin film transistor to generate a driving current in a saturated state, and the driving current drives the Light-Emitting device to emit Light.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a display substrate, including: the display device comprises a display area and a peripheral area positioned at the periphery of the display area, wherein a plurality of pixel units which are arranged in an array manner are arranged in the display area, and each row of pixel units is provided with a corresponding light-emitting control signal line;

the peripheral area is internally provided with a first grid driving circuit and at least two first start control signal lines configured for the first grid driving circuit, the first grid driving circuit comprises at least two first shift register groups which are in one-to-one correspondence with the first start control signal lines and are independent of each other, the first shift register groups comprise at least two first shift registers which are cascaded, the first shift registers are provided with signal input ends and signal output ends, and the signal output ends of the first shift registers are connected with the corresponding light-emitting control signal lines;

In the first shift register group, the signal input end of the first shift register located at a first stage is connected to the first start control signal line configured by the first shift register group, and the signal input end of any one of the first shift registers other than the first stage is connected to the signal output end of the first shift register of the preceding stage.

In some embodiments, the number of first start control signal lines is 2 to 5.

In some embodiments, the first shift register includes:

a first input circuit connected to a signal input terminal, a first clock signal terminal, and a second node, and configured to write a signal provided by the signal input terminal to the second node in response to control of a signal provided by the first clock signal terminal;

the second input circuit is connected with a first clock signal end, a first power end and a second node and is configured to write a first working voltage provided by the first power end into a third node in response to control of signals provided by the first clock signal end and write signals provided by the first clock signal end into the third node in response to control of voltages at the second node;

A first voltage control circuit connected to a second clock signal terminal, a second power supply terminal, a first node, a second node, and a third node, configured to write a signal provided by the second clock signal terminal to the first node in response to control of a voltage at the third node and a signal provided by the second clock signal terminal, and to write a second operating voltage provided by the second power supply terminal to the first node in response to control of a voltage at the second node;

the second voltage control circuit is connected with a second clock signal end, a second power supply end and a third node and is configured to respond to the voltage at the third node and the signal provided by the second clock signal end to write the second working voltage provided by the second power supply end into the second node;

and the output circuit is connected with the first power supply end, the second power supply end, the signal output end, the first node and the second node and is configured to write a second working voltage provided by the second power supply end into the signal output end in response to the control of the voltage at the first node and write a first working voltage provided by the first power supply end into the signal output end in response to the control of the voltage at the second node.

In some embodiments, the first input circuit includes a first transistor, the second input circuit includes a second transistor and a third transistor, the first voltage control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitance, the second voltage control circuit includes a seventh transistor and an eighth transistor, and the output circuit includes a ninth transistor, a tenth transistor, a first capacitance, and a second capacitance;

the control electrode of the first transistor is connected with a first clock signal end, the first electrode of the first transistor is connected with a signal input end, and the second electrode of the first transistor is connected with the second node;

the control electrode of the second transistor is connected with the first clock signal end, the first electrode of the second transistor is connected with the second power supply end, and the second electrode of the second transistor is connected with the third node;

a control electrode of the third transistor is electrically connected with the second node, a first electrode of the third transistor is connected with the third node, and a second electrode of the third transistor is connected with the first clock signal end;

the control electrode of the fourth transistor is connected with the third node, the first electrode of the fourth transistor is connected with the second clock signal end, and the second electrode of the fourth transistor is connected with the fourth node;

The control electrode of the fifth transistor is connected with the second clock signal end, the first electrode of the fifth transistor is connected with the fourth node, and the second electrode of the fifth transistor is connected with the first node;

the control electrode of the sixth transistor is connected with the second node, the first electrode of the sixth transistor is connected with the first node, and the second electrode of the sixth transistor is connected with the second power supply end;

the first end of the third capacitor is connected with the third node, and the second end of the third capacitor is connected with the fourth node;

a control electrode of the seventh transistor is connected with the third node, a first electrode of the seventh transistor is connected with a second power supply end, and a second electrode of the seventh transistor is connected with a first electrode of the eighth transistor;

the control electrode of the eighth transistor is connected with the second clock signal end, and the second electrode of the eighth transistor is connected with the second node;

a control electrode of the ninth transistor is connected with the first node, a first electrode of the ninth transistor is connected with the second power supply end, and a second electrode of the ninth transistor is connected with the signal output end;

The control electrode of the tenth transistor is connected with the second node, the first electrode of the tenth transistor is connected with the signal output end, and the second electrode of the tenth transistor is connected with the first power supply end.

In some embodiments, the first shift register further comprises: a first anticreep circuit;

the first input circuit, the second input circuit and the second node control voltage are connected to a fifth node, the first anti-leakage circuit is positioned between the fifth node and the second node, and the first input circuit, the second input circuit and the second node control voltage are all connected with the second node through the anti-leakage node;

the first anti-leakage circuit is further connected with the first power end and the third power end, and is configured to write a third working voltage provided by the third power end into a first anti-leakage node under the control of the voltage at the second node, and the first anti-leakage node is located between the second node and the fifth node.

In some embodiments, the first anti-leakage circuit comprises: an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

The control electrode of the eleventh transistor is connected with the first power supply end, the first electrode of the eleventh transistor is connected with a fifth node, and the second electrode of the eleventh transistor is connected with the first anti-leakage node;

the control electrode of the twelfth transistor is connected with the first power supply end, the first electrode of the twelfth transistor is connected with the first anti-leakage node, and the second electrode of the twelfth transistor is connected with the second node;

the control electrode of the thirteenth transistor is connected with the second node, the first electrode of the thirteenth transistor is connected with the third power supply end, and the second electrode of the thirteenth transistor is connected with the first anti-leakage node.

In some embodiments, the first shift register further comprises: the output circuit is connected with a second power end through the second anti-leakage circuit, and the output circuit and the second anti-leakage circuit are connected with a second anti-leakage node;

the second anti-leakage circuit is further connected with the first node, the first power end, the second power end and the signal output end, and is configured to write the first working voltage provided by the first power end into the second anti-leakage node in response to control of the voltage at the signal output end.

In some embodiments, the second anti-leakage circuit includes: a fourteenth transistor and a fifteenth transistor;

a control electrode of the fourteenth transistor is connected with the first node, a first electrode of the fourteenth transistor is connected with the second power supply end, and a second electrode of the fourteenth transistor is connected with the second anti-leakage node;

the control electrode of the fifteenth transistor is connected with the signal output end, the first electrode of the fifteenth transistor is connected with the first power supply end, and the second electrode of the fifteenth transistor is connected with the second anti-leakage node.

In some embodiments, the first shift register further comprises:

and the global reset circuit is connected with the global reset signal end, the first power end and the second node and is configured to respond to the control of signals provided by the global reset signal end to write the first working voltage provided by the first power end into the second node.

In some embodiments, the global reset circuit includes: a sixteenth transistor;

the control electrode of the sixteenth transistor is connected with the global reset signal end, the first electrode of the sixteenth transistor is connected with the second node, and the second electrode of the sixteenth transistor is connected with the first power end.

In some embodiments, the first gate driving circuit is further configured with a first clock signal supply line and a second clock signal supply line arranged along a first direction; the first clock signal supply line and the second clock signal supply line each extend in a second direction;

the first shift registers in the first gate driving circuit are sequentially arranged along the second direction, wherein a first clock signal end configured by a first shift register in an odd number of bits is connected with the first clock signal supply line, a second clock signal end configured by a first shift register in an odd number of bits is connected with the second clock signal supply line, a first clock signal end configured by a first shift register in an even number of bits is connected with the second clock signal supply line, and a second clock signal end configured by a first shift register in an even number of bits is connected with the first clock signal supply line.

In a second aspect, embodiments of the present disclosure further provide a display apparatus, including: the display substrate as provided in the first aspect described above.

In a third aspect, an embodiment of the present disclosure further provides a driving method of a display substrate, where the display substrate provided in the first aspect is used, the first gate driving circuit includes n first shift register groups, n is greater than or equal to 2, one frame includes n-1 black insertion driving stages, and the first gate driving circuit is configured to sequentially provide, in the i-th black insertion driving stage, an i-th black insertion driving signal to each of the light emission control signal lines, where 1 is greater than or equal to i is less than or equal to n-1;

Each black insertion driving stage is divided into a first sub-stage and a second sub-stage by a preset blank period, wherein the first sub-stage is positioned before the blank period, and the second sub-stage is positioned after the blank period;

the driving method includes:

in a first sub-stage in the ith black insertion driving stage, sequentially and respectively providing the ith black insertion driving start signals to first start control signal lines configured by the 1 st to n-i th first shift register groups, so that the first shift registers in the 1 st to n-i th first shift register groups sequentially output the ith black insertion driving signals;

in the blank period, each first shift register does not output a black insertion driving signal;

in a second sub-stage in the ith black insertion driving stage, the ith black insertion driving start signals are sequentially and respectively supplied to the first start control signal lines configured by the (n-i+1) -th to nth first shift register groups, so that the first shift registers in the (n-i+1) -th to nth first shift register groups sequentially output the ith black insertion driving signals.

Drawings

FIG. 1 is a schematic diagram of a circuit structure of a pixel unit in a display substrate according to the related art;

FIG. 2 is a timing diagram illustrating operation of the pixel unit shown in FIG. 1;

FIG. 3 is a schematic diagram of another circuit structure of a pixel unit in a display substrate according to the related art;

FIG. 4A is a timing diagram illustrating operation of the pixel unit shown in FIG. 3;

FIG. 4B is a timing diagram illustrating an operation of the pixel unit of FIG. 3 for performing external compensation sensing during a blank period;

fig. 5 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;

FIG. 6 is a schematic circuit diagram of the first gate driving circuit in FIG. 5;

FIG. 7 is a timing diagram illustrating operation of the first gate driving circuit according to one embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a circuit configuration of a first shift register according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram of another circuit structure of the first shift register according to the embodiment of the disclosure;

FIG. 10 is a timing diagram illustrating operation of the first shift register of FIG. 9;

fig. 11 is a flowchart of a driving method of a display substrate according to an embodiment of the disclosure.

Detailed Description

In order to enable those skilled in the art to better understand the technical scheme of the present invention, a display substrate, a driving method thereof and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not limited to physical or mechanical coupling, but may include electrical connection, whether direct or indirect.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the drain and source of each transistor may be coupled interchangeably, so that the drain and source of each transistor are virtually indistinguishable in the embodiments of the present disclosure. Here, only in order to distinguish between two electrodes of a transistor except a control electrode (i.e., a gate electrode), one of the electrodes is called a drain electrode and the other is called a source electrode. The thin film transistor adopted in the embodiment of the disclosure may be an N-type transistor or a P-type transistor. In the embodiment of the disclosure, when an N-type thin film transistor is used, the first pole may be a source electrode and the second pole may be a drain electrode. In the following embodiments, a thin film transistor is described as an example of an N-type transistor.

In the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on after being input to the control electrode of the transistor, and a "inactive level signal" refers to a signal that can control the transistor to be turned off after being input to the control electrode of the transistor. For an N-type transistor, the high level signal is an active level signal, and the low level signal is an inactive level signal; for a P-type transistor, the low level signal is an active level signal and the high level signal is an inactive level signal.

In the following description, a transistor will be described as an example of an N-type transistor, where an active level signal means a high level signal and an inactive level signal means a low level signal. It is conceivable that when a P-type transistor is employed, the timing variation of the control signal needs to be adjusted accordingly. Specific details are not set forth herein but are intended to be within the scope of the present disclosure.

Fig. 1 is a schematic circuit diagram of a pixel unit in a display substrate according to the related art, and fig. 2 is a timing chart of operation of the pixel unit shown in fig. 1, and as shown in fig. 1 and 2, the pixel circuit has a 3T1C structure, i.e., includes three transistors (a data writing transistor QTFT, a driving transistor DTFT, a sensing transistor STFT) and 1 capacitor (a storage capacitor Cst). The control electrode of the DATA writing transistor QTFT is connected to the first gate line G1, the first electrode of the DATA writing transistor QTFT is connected to the DATA line DATA, the control electrode of the sensing transistor STFT is connected to the second gate line G2, and the first electrode of the sensing transistor STFT is connected to the sensing line SENCE.

For a single pixel cell, it needs to go through a write display data phase and a light emitting phase during one frame; during the stage of writing display Data, the first gate line G1 controls the Data writing transistor QTFT to be turned on, and the Data line Data writes the Data voltage Vdata to the control electrode of the driving transistor DTFT; in the light emitting stage, the driving transistor DTFT outputs a corresponding driving current according to the voltage at its own control electrode to drive the light emitting element OLED to emit light.

In addition, a Blank period (also referred to as Blank period) is also typically configured between two adjacent frames, and the Blank period can be used for externally compensating and sensing a certain pixel unit row at random.

In the pixel unit shown in fig. 1, the display brightness of the light emitting element OLED in one frame can be controlled only by the data voltage Vdata, which is output from the IC, and the problem of low gray scale spread cannot be caused if the IC accuracy is insufficient. For example, the IC accuracy is 0.1V, and the data voltage of 0.1V corresponds to the gray level L20, and at this time, the IC cannot accurately output the gray levels L1 to L19.

In order to solve the above technical problems, the related art improves the circuit structure of the pixel unit. Fig. 3 is a schematic diagram of another circuit structure of a pixel unit in a display substrate according to the related art, fig. 4A is a timing chart of operation of the pixel unit shown in fig. 3, fig. 4B is a timing chart of operation of the pixel unit shown in fig. 3 for performing external compensation sensing in a blank period, and as shown in fig. 3 to fig. 4B, the new pixel unit provided in the related art is a 4T1C structure, which includes not only the data writing transistor QTFT, the driving transistor DTFT, the sensing transistor STFT, but also the light emission control transistor ETFT in fig. 1. As an example, referring to fig. 3, the light emission control transistor ETFT is disposed between the driving transistor DTFT and the power source terminal ELVDD, and a control electrode of the light emission control transistor ETFT is connected to a light emission control signal line. As yet another example, the light emission control transistor may be disposed between the driving transistor DTFT and the light emitting device OLED (the corresponding drawing is not given).

Referring to fig. 4A, for a single pixel unit, the light emission control transistor ETFT is controlled to be turned on or off through the light emission control signal line during the light emission period, so that the lighting time of the light emitting element OLED in the light emission period can be controlled, and thus the equivalent luminance (i.e., the luminance perceived by the human eye, also referred to as the sense luminance) of the light emitting element OLED in one frame can be controlled. Specifically, the lighting stage includes a lighting stage and a black insertion stage, and during the lighting stage, a lighting driving signal (i.e., an effective level signal) is provided through a lighting control signal line to control the lighting control transistor ETFT to be turned on, and at this time, the driving transistor can normally output a driving current, and the light emitting element OLED emits light; the light emission control transistor ETFT is controlled to be turned off by providing a black insertion driving signal (i.e., a non-active level signal) through the light emission control signal line during the black insertion stage, and at this time, the driving transistor DTFT does not have a driving current output, and the light emitting element does not emit light. In general, the longer the total duration of the black insertion stage, the lower the equivalent luminance of the light emitting element.

Fig. 4A exemplarily shows a case where 2 black inserting stages are included in the light emitting stage, but of course, in practical application, the light emitting stage may also include 1 black inserting stage, 3 black inserting stages, or more black inserting stages.

As can be seen from the above, the light emitting element can display the brightness corresponding to the lower gray scale by setting the light emitting control transistor ETFT, so that the problem that the pixel unit cannot display the low gray scale brightness due to insufficient IC precision is effectively solved. However, in practical use, it has been found that since all shift registers inside the existing gate driving circuit for supplying the black insertion driving signal are sequentially cascaded, the existing gate driving circuit for supplying the black insertion driving signal sequentially outputs the black insertion driving signal to each light emission control signal line without interruption. At this time, it inevitably occurs that the time when the light emission control signal lines corresponding to some rows of pixel units receive the black insertion driving signal is within the blank period. As can be seen from the timing sequence shown in fig. 4B, when external compensation sensing is performed on a certain row of pixel units, the signal provided by the light-emitting control signal line connected to the row of pixel units is required to be a light-emitting driving signal (i.e. an active level signal) all the time. Therefore, external compensation sensing cannot be performed for the pixel cell rows that receive the black insertion driving signal in the blank period. That is, the related art cannot support random external compensation sensing in a blank period.

In order to effectively solve the problem that the related art cannot support random external compensation sensing during a blank period, embodiments of the present disclosure provide a display substrate, and inventive principles of the present disclosure will be described in detail with reference to specific embodiments.

Fig. 5 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure, and fig. 6 is a schematic circuit structural diagram of a first gate driving circuit in fig. 5, where, as shown in fig. 5 and fig. 6, the display substrate 100 includes: the display device comprises a display area 101 and a peripheral area 102 positioned at the periphery of the display area 101, wherein a plurality of pixel units 300 are arranged in an array manner in the display area 101, and each row of pixel units 300 is provided with a corresponding light-emitting control signal line EM.

The peripheral region 102 is provided with a first gate driving circuit 200 and at least two first start control signal lines STV1 to STV3 configured for the first gate driving circuit 102, the first gate driving circuit 200 includes at least two first shift register groups SRG1 to SRG3 which are in one-to-one correspondence with the first start control signal lines STV1 to STV3 and are independent of each other, the first shift register groups SRG1 to SRG3 include at least two first shift registers sr_1 to sr_a1, sr_a1+1 to sr_a1+a2, sr_a1+a2+1 to sr_a1+a2+a3 which are cascade-connected, the first shift registers sr_1 to sr_a1+a2+a3 have signal INPUT terminals put and signal output terminals OUT, and the signal output terminals OUT of the respective first shift registers sr_1 to sr_a1+a2+a3 are connected to the corresponding light emission control signal lines EM.

In the first shift register groups SRG1 to SRG3, the signal INPUT terminal INPUT of the first shift registers sr_1, sr_a1+1, sr_a1+a2+1 located at the first stage is connected to the first start control signal lines STV1, STV2, STV3 arranged in the first shift register groups SRG1 to SRG3, and the signal INPUT terminal INPUT of any one of the other first shift registers sr_2 to sr_a1, sr_a1+2 to sr_a1+a2, sr_a1+a2+2 to sr_a1+a2+a3 located at the first stage is connected to the signal output terminal OUT of the first shift register at the preceding stage.

Note that, in the present disclosure, the first start control signal lines STV1 to STV3 are connected to the signal INPUT terminals INPUT of the first shift registers sr_1, sr_a1+1, sr_a1+a2+1 located at the first stage in the corresponding first shift register groups SRG1 to SRG3, and the first start control signal lines STV1 to STV3 sequentially output black-inserting driving signals to the signal INPUT terminals of the first shift registers sr_1, sr_a1+1, sr_a1+a2+a1, sr_a1 to sr_a2+a3 located at the first stage in the corresponding first shift register groups SRG1 to SRG3 after the black-inserting driving start signals are supplied to the signal INPUT terminals of the first shift registers sr_1 to sr_a1, sr_a1+1 to sr_a1+a2, sr_a1+a2+a3 located at the first stage in the corresponding first shift register groups SRG1 to SRG 3.

Furthermore, since the first shift register groups are independent of each other, that is, there is no cascade relationship between the first shift registers located in different first shift register groups; in the first shift register group to which the black insertion driving start signal is input, the black insertion driving signal outputted from the first shift register at the last stage is supplied only to the corresponding light emission control signal line, and is not supplied to the first shift registers in the other first shift register groups.

Based on the above, unlike the case where all the first shift registers in the first gate driving circuit related to the related art are sequentially cascaded, the technical solution of the present disclosure divides all the first shift registers in the first gate driving circuit into at least two first shift register groups that are independent of each other, so that there is no cascade relationship between the first shift registers in different first shift register groups, and then, each first shift register group is configured with a corresponding first start control signal line to independently control the time when each first shift register group outputs the black insertion driving signal, and it is able to realize that there is no black insertion driving signal output by the first shift register in a blank period. Therefore, the technical scheme of the disclosure supports random external compensation sensing of the display substrate in a blank period.

In some embodiments, the number of the first start control signal lines configured by the first gate driving circuit 200 is 2 to 5. That is, the number of the first shift register groups divided by the first gate driving circuit 200 is 2 to 5.

In the embodiment of the present disclosure, the number of the first shift register groups divided by the first gate driving circuit 200 may be determined according to the number of black insertion stages configured in one light emitting stage of the pixel unit 300. Specifically, the number of the first shift register groups divided by the first gate driving circuit 200 is greater than the number of black insertion stages configured by the pixel unit 300 in one light emitting stage.

The greater the number of first shift register groups divided by the first gate driving circuit 200, the greater the number of black insertion stages that the pixel unit 300 can be configured to have in one light emitting stage; under the condition that the total black inserting duration required in one lighting stage is certain, the more the number of black inserting stages are configured, the shorter the duration configured by a single black inserting stage is, and the flicker problem generated by alternate lighting stages and black inserting stages can be effectively reduced. However, the larger the number of the first shift register groups, the larger the number of the first start control signal lines to be configured, and accordingly, the greater the control difficulty and the larger the occupied peripheral area space. In order to effectively balance the flicker problem and the wiring space problem, it is preferable in the present disclosure that the number of the first shift register groups divided by the first gate driving circuit 200 is 2 to 5; further preferably, the number of the first shift register groups SRG1 to SRG3 divided by the first gate driving circuit 200 is 3, and accordingly, the number of the first start control signal lines STV1 to STV3 arranged by the first gate driving circuit is 3.

In some embodiments, the first gate driving circuit 200 includes n first shift register groups, n+.2, and one frame includes n-1 black insertion driving stages, and the gate driving circuit is configured to sequentially supply the ith black insertion driving signal to each light emission control signal line in the ith black insertion driving stage, where 1+.ltoreq.i+.n-1. Each black insertion driving stage is divided into a first sub-stage and a second sub-stage by a preset blank period, wherein the first sub-stage is positioned before the blank period, and the second sub-stage is positioned after the blank period.

In one frame driving process, the first sub-stage of each black inserting driving stage starts in sequence before the blank period. In the first sub-stage in the ith black insertion driving stage, the ith black insertion driving start signals are sequentially and respectively provided for the first start control signal lines configured by the 1 st to n-i th first shift register groups, so that the first shift registers in the 1 st to n-i th first shift register groups sequentially output the ith black insertion driving signals.

In the blank period, each of the first shift registers does not output the black insertion driving signal.

The second sub-phase of each black insertion driving phase after the blanking period may be sequentially started or may be simultaneously started. In the second sub-stage in the ith black inserting driving stage, the ith black inserting driving start signals are sequentially and respectively provided for the first start control signal lines configured by the (n-i+1) th to (n) th first shift register groups, so that the first shift registers in the (n-i+1) th to (n) th first shift register groups sequentially output the ith black inserting driving signals.

The technical solution of the present disclosure will be described in detail with reference to one specific example. Fig. 7 is a timing chart of an operation of the first gate driving circuit in the embodiment of the disclosure, as shown in fig. 7, fig. 7 illustrates a case where the number of black inserting stages of the pixel unit 300 configured in one lighting stage is 2, the first gate driving circuit 200 includes 3 first shift register groups, and the numbers of the first shift registers included in the 3 first shift register groups are a1, a2, and a3, respectively. In FIG. 7, OUT_m represents the signal output terminal of the ith first shift register in the first gate driving circuit 200, and 1.ltoreq.m.ltoreq.a1+a2+a3.

The number of black insertion stages of the pixel unit 300 in one light emitting stage is 2, that is, the signal output terminals of the first shift registers in the first gate driving circuit 200 need to sequentially output 2 black insertion driving signals. At this time, one frame includes 2 black insertion driving stages, the first gate driving circuit 200 sequentially supplies the 1 st black insertion driving signal to each of the light emission control signal lines EM in the 1 st black insertion stage, and the first gate driving circuit 200 sequentially supplies the 2 nd black insertion driving signal to each of the light emission control signal lines EM in the 2 nd black insertion stage. The time interval between the start time of the second black inserting driving stage and the start time of the first black inserting driving stage may be preset according to actual needs. Each black insertion driving stage is divided into a first sub-stage and a second sub-stage by a preset blank period, wherein the first sub-stage is positioned before the blank period, and the second sub-stage is positioned after the blank period.

In the first sub-stage in the 1 st black insertion driving stage, the 1 st black insertion driving start signal is sequentially supplied to the first start control signal lines STV1, STV2 configured by the 1 st and 2 nd first shift register groups SRG1, SRG2, respectively, so that the first shift registers in the 1 st and 2 nd first shift register groups SRG1, SRG2 sequentially output the 1 st black insertion driving signal, that is, the 1 st to 1 st+a2 first shift registers sr_1 to sr_a1+a2 in the first gate driving circuit 200 sequentially output the 1 st black insertion driving signal to the corresponding light emission control signal lines EM.

In the first sub-stage in the 2 nd black insertion driving stage, the 2 nd black insertion driving start signal is supplied to the first start control signal line STV1 configured by the 1 st first shift register group SRG1, so that the first shift registers in the 1 st first shift register group SRG1 sequentially output the 1 st black insertion driving signal, that is, the 1 st to a1 st first shift registers sr_1 to sr_a1 in the first gate driving circuit 200 sequentially output the 2 nd black insertion driving signal to the corresponding light emission control signal lines EM.

In the second sub-stage in the 1 st black insertion driving stage, the 1 st black insertion driving start signal is sequentially supplied to the first start control signal lines STV3 arranged in the 3 rd first shift register group SRG3, respectively, so that the first shift registers in the 3 rd first shift register group SRG3 sequentially output the 1 st black insertion driving signal, that is, the 1 st black insertion driving signal is sequentially output to the corresponding light emission control signal lines EM from the 1 st 1+a2+1 to the 1 st+a2+a3 first shift registers sr_a1+a2+1 to sr_a1+a2+a3 in the first gate driving circuit 200.

In the second sub-stage in the 2 nd black insertion driving stage, the 2 nd black insertion driving start signal is sequentially supplied to the first start control signals STV2 and STV3 lines configured by the 2 nd and 3 rd first shift register groups SRG2 and SRG3, respectively, so that the first shift registers in the 2 nd and 3 rd first shift register groups SRG2 and SRG376 sequentially output the 2 nd black insertion driving signal, that is, the 1 st+1 to the 1 st+a2+a3 first shift registers sr_a1+1 to sr_a2+a3 in the first gate driving circuit 200 sequentially output the 2 nd black insertion driving signal to the corresponding light emission control signal lines EM.

It should be noted that, fig. 7 exemplarily illustrates that the duration of the 1 st black insertion driving start signal is smaller than the duration of the 2 nd black insertion driving start signal (i.e., the duration of the 1 st black insertion driving signal is smaller than the duration of the 2 nd black insertion driving signal), which serves as an example only and does not limit the technical solution of the present disclosure. In practical application, the duration of each black insertion driving start signal can be designed according to practical requirements.

It should be noted that, fig. 7 illustrates a case where the second sub-phase in the 1 st black insertion driving phase and the second sub-phase in the 2 nd black insertion driving phase start at the same time, which serves as an example only and does not limit the technical solution of the present disclosure.

Fig. 8 is a schematic circuit diagram of a first shift register according to an embodiment of the disclosure, as shown in fig. 8, and in some embodiments, the first shift register includes: a first input circuit 21, a second input circuit 22, a first voltage control circuit 23, a second voltage control circuit 24, and an output circuit 25.

The first INPUT circuit 21 is connected to the signal INPUT terminal INPUT, the first clock signal terminal CKA, and the second node N2, and the first INPUT circuit 21 is configured to write the signal provided by the signal INPUT terminal INPUT to the second node N2 in response to the control of the signal provided by the first clock signal terminal CKA.

The second input circuit 22 is connected to the first clock signal terminal CKA, the first power source terminal, and the second node N2, and the second input circuit 22 is configured to write the first operating voltage provided by the first power source terminal to the third node N3 in response to the control of the signal provided by the first clock signal terminal CKA, and write the signal provided by the first clock signal terminal CKA to the third node N3 in response to the control of the voltage at the second node N2.

The first voltage control circuit 23 is connected to the second clock signal terminal CKB, the second power source terminal, the first node N1, the second node N2, and the third node N3, and the first voltage control circuit 23 is configured to write the signal provided by the second clock signal terminal CKB to the first node N1 in response to the control of the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB, and to write the second operating voltage provided by the second power source terminal to the first node N1 in response to the control of the voltage at the second node N2.

The second voltage control circuit 24 is connected to the second clock signal terminal CKB, the second power source terminal, and the third node N3, and the second voltage control circuit 24 is configured to write the second operating voltage provided by the second power source terminal to the second node N2 in response to the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB.

The output circuit 25 is connected to the first power source terminal, the second power source terminal, the signal output terminal OUT, the first node N1, and the second node N2, and the output circuit 25 is configured to write the second operating voltage provided by the second power source terminal to the signal output terminal OUT in response to control of the voltage at the first node N1, and to write the first operating voltage provided by the first power source terminal to the signal output terminal OUT in response to control of the voltage at the second node N2.

In some embodiments, the first shift register further includes a first anti-leakage circuit 26; the first input circuit 21, the second input circuit 22, and the second voltage control circuit 24 are connected to the fifth node N5, the first anti-leakage circuit 26 is located between the fifth node N5 and the second node N2, and the first input circuit 21, the second input circuit, and the second voltage control circuit are all connected to the second node N2 through the first anti-leakage circuit 26; the first anti-leakage circuit 26 is further connected to the first power supply terminal and the third power supply terminal, and the first anti-leakage circuit 26 is configured to write the third operating voltage provided by the third power supply terminal into the first anti-leakage node OFF1 under the control of the voltage at the second node N2, where the first anti-leakage node OFF1 is located between the second node N2 and the fifth node N5.

In some embodiments, the first shift register further includes a second anti-leakage circuit 27, the output circuit 25 is connected to the second power supply terminal through the second anti-leakage circuit 27, and the output circuit 25 and the second anti-leakage circuit 27 are connected to the second anti-leakage node OFF2; the second anti-leakage circuit 27 is further connected to the first node N1, the first power terminal, the second power terminal, and the signal output terminal OUT, and the second anti-leakage circuit 27 is configured to write the first operating voltage provided by the first power terminal to the second anti-leakage node OFF2 in response to control of the voltage at the signal output terminal OUT.

Fig. 9 is a schematic diagram of another circuit structure of the first shift register according to the embodiment of the disclosure, where, as shown in fig. 9, the shift register shown in fig. 9 is an implementation alternative implementation of the first shift register shown in fig. 8.

In some embodiments, the first input circuit 21 includes a first transistor T1, the second input circuit 22 includes a second transistor T2 and a third transistor T3, the first voltage control circuit 23 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a third capacitor C3, the second voltage control circuit 24 includes a seventh transistor T7 and an eighth transistor T8, and the output circuit 25 includes a ninth transistor T9, a tenth transistor T10, a first capacitor C1 and a second capacitor C2.

The control electrode of the first transistor T1 is connected to the first clock signal terminal CKA, the first electrode of the first transistor T1 is connected to the signal INPUT terminal INPUT, and the second electrode of the first transistor T1 is connected to the second node N2.

The control electrode of the second transistor T2 is connected to the first clock signal terminal CKA, the first electrode of the second transistor T2 is connected to the second power supply terminal, and the second electrode of the second transistor T2 is connected to the third node N3.

The control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the first clock signal terminal CKA.

The control electrode of the fourth transistor T4 is connected to the third node N3, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CKB, and the second electrode of the fourth transistor T4 is connected to the fourth node N4.

The control electrode of the fifth transistor T5 is connected to the second clock signal terminal CKB, the first electrode of the fifth transistor T5 is connected to the fourth node N4, and the second electrode of the fifth transistor T5 is connected to the first node N1.

The control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the second power supply terminal.

The first end of the third capacitor C3 is connected to the third node N3, and the second end of the third capacitor C3 is connected to the fourth node N4.

The control electrode of the seventh transistor T7 is connected to the third node N3, the first electrode of the seventh transistor T7 is connected to the second power supply terminal, and the second electrode of the seventh transistor T7 is connected to the first electrode of the eighth transistor T8.

The gate of the eighth transistor T8 is connected to the second clock signal terminal CKB, and the second pole of the eighth transistor T8 is connected to the second node N2.

The control electrode of the ninth transistor T9 is connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the second power supply terminal, and the second electrode of the ninth transistor T9 is connected to the signal output terminal OUT.

The control electrode of the tenth transistor T10 is connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the signal output terminal OUT, and the second electrode of the tenth transistor T10 is connected to the first power supply terminal.

The first end of the first capacitor C1 is connected to the first node N1, and the second end of the first capacitor C1 is connected to the second power supply end.

The first end of the second capacitor C2 is connected to the signal output terminal OUT, and the second end of the second capacitor C2 is connected to the second node N2.

In some embodiments, the first anti-leakage circuit 26 includes: an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.

Wherein the control electrode of the eleventh transistor T11 is connected with the first power supply terminal, the first electrode of the eleventh transistor T11 is connected with the fifth node N5, the second electrode of the eleventh transistor T11 is connected with the first anti-leakage node OFF1,

The control electrode of the twelfth transistor T12 is connected with the first power supply end, the first electrode of the twelfth transistor T12 is connected with the first anti-leakage node OFF1, the second electrode of the twelfth transistor T12 is connected with the second node N2,

The control electrode of the thirteenth transistor T13 is connected to the second node N2, the first electrode of the thirteenth transistor T13 is connected to the third power supply terminal, and the second electrode of the thirteenth transistor T13 is connected to the first anti-leakage node OFF 1.

In some embodiments, the second anti-leakage circuit 27 includes: a fourteenth transistor T14 and a fifteenth transistor T15.

The control electrode of the fourteenth transistor T14 is connected to the first node N1, the first electrode of the fourteenth transistor T14 is connected to the second power supply terminal, and the second electrode of the fourteenth transistor T14 is connected to the second anti-leakage node OFF 2.

The control electrode of the fifteenth transistor T15 is connected to the signal output terminal OUT, the first electrode of the fifteenth transistor T15 is connected to the first power supply terminal, and the second electrode of the fifteenth transistor T15 is connected to the second leakage preventing node OFF 2.

Fig. 10 is a timing chart of an operation of the first shift register shown in fig. 9, as shown in fig. 10, wherein the first operating voltage provided by the first power supply terminal is a high level operating voltage VGH1, the second operating voltage provided by the second power supply terminal is a low level operating voltage VGL, and the third operating voltage provided by the third power supply terminal is a high level operating voltage VGH2, wherein VGH2 is slightly greater than VGH1. The first shift register shown in fig. 9 comprises the following stages of operation:

in the first stage t1, the signal INPUT terminal INPUT provides a low level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 are all turned on; the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the thirteenth transistor T13, and the fourteenth transistor T14 are all turned off.

Specifically, the first clock signal terminal CKA provides a high level signal, the first transistor T1 and the second transistor T2 are both turned on, the low level signal provided by the signal INPUT terminal INPUT is written into the fifth node N5, at this time, the eleventh transistor T11 and the twelfth transistor T12 are both turned on, so that the low level signal is written into the second node N2 through the eleventh transistor T11 and the twelfth transistor T12, the second node N2 is in a low level state, and the sixth transistor T6, the thirteenth transistor T13 and the tenth transistor T10 are all turned off. Meanwhile, the first working voltage VGH1 is written into the third node N3 through the second transistor T2, the voltage at the third node N3 is in a high level state, the fourth transistor T4 is turned on, the low level signal provided by the second clock signal terminal CKB is written into the fourth node N4 through the fourth transistor T4, and the voltage at the fourth node N4 is in a low level state.

Since the second clock signal is in a low level state, the fifth transistor T5 is turned off. At this time, the first node N1 is in a floating state, and the voltage at the first node N1 maintains a low state of the previous stage. Since the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT is in a floating state, and the signal output terminal OUT maintains a high state of the previous stage, i.e., the signal output terminal OUT outputs a high signal. At this time, the fifteenth transistor T15 is turned on, and the first operating voltage VGH1 is written into the second anti-leakage node OFF2 through the fifteenth transistor T15, so that the voltage at the signal output terminal OUT can be effectively prevented from generating leakage through the ninth transistor T9, which is beneficial to maintaining the stability of the voltage at the signal output terminal OUT.

The second phase t2 comprises two sub-phases s1, s2 which alternate.

In the sub-stage s1, the signal INPUT terminal INPUT provides a low level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. The fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are all turned on; the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all turned off.

Specifically, when the first clock signal terminal CKA is in a low level state, the first transistor T1 and the second transistor T2 are turned off, the third node N3 is in a floating state and maintains a high level, the high level signal provided by the second clock signal terminal CKB is written into the fourth node N4 through the fourth transistor T4, the voltage at the fourth node N4 is changed from the low level state to the high level state, and the voltage at the third node N3 is further pulled up to a higher level under the bootstrap action of the third capacitor C3. Meanwhile, since the second clock signal terminal CKB provides the high level signal, the fifth transistor T5 and the eighth transistor T8 are turned on; since the seventh transistor T7 and the eighth transistor T8 are both turned on, the second operating voltage VGL1 is written to the fifth node N5 through the seventh transistor T7 and the eighth transistor T8, the fifth node N5 maintains a low state, and accordingly the eleventh transistor T11 and the twelfth transistor T12 are both turned on, the second node N2 also maintains a low state, and the sixth transistor T6, the tenth transistor T10 and the thirteenth transistor T13 are all maintained turned off.

Since the fifth transistor T5 is turned on, the high level signal at the fourth node N4 can be written to the first node N1 through the fifth transistor T5, the voltage at the first node N1 is in the high level state, at this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned on, the second operating voltage VGL is written to the signal output terminal OUT through the fourteenth transistor T14 and the ninth transistor T9, and the signal output terminal OUT outputs the low level signal. Accordingly, the fifteenth transistor T15 is turned off.

In the sub-stage s2, the signal INPUT terminal INPUT provides a low level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal.

The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are all turned on; the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all turned off.

Specifically, the first clock signal terminal CKA provides a high level signal, and the first transistor T1 and the second transistor T2 are both turned on, the low level signal provided by the signal INPUT terminal INPUT is written into the fifth node N5, the fifth node N5 maintains a low level state, and accordingly the second node N2 maintains a low level state. The sixth transistor T6, the tenth transistor T10, and the thirteenth transistor T13 all remain turned off. Meanwhile, the first operating voltage is written into the third node N3 through the second transistor T2, the voltage at the third node N3 drops to VGH1, the voltage at the third node N3 is in a high level state, and the fourth transistor T4 is turned on. The low level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, the voltage at the fourth node N4 is in a low level state,

Since the second clock signal terminal CKB is in the low state, the fifth transistor T5 and the eighth transistor T8 are turned off, the first node N1 is in the floating state, the first node N1 maintains the high state of the previous node, the ninth transistor T9 and the fourteenth transistor T14 maintain the on state, and the signal output terminal OUT maintains the output of the low signal. Accordingly, the fifteenth transistor T15 remains turned off.

In the third stage t3, the signal INPUT terminal INPUT provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. The fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are all turned on; the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all turned off.

The specific operation of the first shift register in the third stage t3 is the same as that in the sub-stage s1, and will not be described here again.

The fourth phase t4 comprises two sub-phases s3, s4 which alternate.

In the sub-stage s3, the signal INPUT terminal INPUT provides a high level signal, the first clock signal terminal CKA provides a high level signal, and the second clock signal terminal CKB provides a low level signal. The first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10, the thirteenth transistor T13, the sixteenth transistor T16 are all turned on, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the fourteenth transistor T14 are all turned off, and the eleventh transistor T11 and the twelfth transistor T12 are all turned on and then switched to an off state.

Specifically, the first clock signal terminal CKA is in a high level state, the first transistor T1 and the second transistor T2 are both turned on, the high level signal provided by the signal INPUT terminal INPUT is written to the fifth node N5 through the first transistor T1, and the eleventh transistor T11 and the twelfth transistor T12 are both turned on, so that the high level signal is written to the second node N2 through the eleventh transistor T11 and the twelfth transistor T12, and the second node N2 is in a low level state, so that the sixth transistor T6, the thirteenth transistor T13, and the tenth transistor T10 are all turned on. Since the thirteenth transistor T13 is turned on, the third operating voltage VGH2 is written to the first anti-leakage node OFF1 through the thirteenth transistor T13, and the voltages at the fifth node N5 and the second node N2 are pulled up through the eleventh transistor T11 and the twelfth transistor T12, respectively, at which time the gate-source voltages of the eleventh transistor T11 and the twelfth transistor T12 decrease until the gate-source voltage of the eleventh transistor T11 is equal to the threshold voltage of the eleventh transistor T11 and the gate-source voltage of the twelfth transistor T12 is equal to the threshold voltage of the twelfth transistor T12, and both the eleventh transistor T11 and the twelfth transistor T12 are turned OFF, at which time the first anti-leakage node OFF1 is in the floating state. Through the design, the second node N2 can be effectively prevented from generating electric leakage through other transistors, so that the voltage at the second node N2 is kept in a high-level state all the time. It should be noted that, in the process of charging the fifth node N5 and the second node N2 by the eleventh transistor T11 and the twelfth transistor T12 through the first anti-leakage node OFF1, the voltages at the fifth node N5 and the second node N2 are only slightly raised, so that the eleventh transistor T11 and the twelfth transistor T12 are turned OFF.

Meanwhile, the first working voltage VGH1 is written into the third node N3 through the second transistor T2, the voltage at the third node N3 is in a high level state, the fourth transistor T4 is turned on, the low level signal provided by the second clock signal terminal CKB is written into the fourth node N4 through the fourth transistor T4, and the voltage at the fourth node N4 is in a low level state.

Also, since the second clock signal is in a low level state, the fifth transistor T5 is turned off. At this time, since the sixth transistor T6 is turned on, the second operating voltage VGL is written to the first node N1 through the sixth transistor T6, and the voltage at the first node N1 is in a low level state. At this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned off.

In the case where the ninth transistor T9 is turned off and the tenth transistor T10 is turned on, the signal output terminal OUT outputs a high level signal. Accordingly, the fifteenth transistor T15 is turned on.

In the sub-stage s4, the signal INPUT terminal INPUT provides a high level signal, the first clock signal terminal CKA provides a low level signal, and the second clock signal terminal CKB provides a high level signal. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, the sixteenth transistor T16 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the fourteenth transistor T14 are all turned off, and the eleventh transistor T11 and the twelfth transistor T12 are all turned on and then switched to an off state.

Specifically, when the first clock signal terminal CKA is in a low level state, the first transistor T1 and the second transistor T2 are turned off, the fifth node N5 maintains the high level state of the previous stage, the third transistor T3 is turned on, the low level signal provided by the first clock signal terminal CKA is written into the third node N3 through the third transistor T3, the voltage at the third node N3 is in the low level state, and the fourth transistor T4 and the seventh transistor T7 are turned off.

Since the eleventh transistor T11 and the twelfth transistor T12 are turned off, the second node N2 is floated to maintain the high state of the previous stage, and the sixth transistor T6, the tenth transistor T10 and the thirteenth transistor T13 are turned on, the voltage at the first node N1 maintains the low state, and the ninth transistor T9 and the fourteenth transistor T14 maintain the turned-off state.

In the case where the ninth transistor T9 is turned off and the tenth transistor T10 is turned on, the signal output terminal OUT maintains to output a high level signal. Accordingly, the fifteenth transistor T15 is turned on.

Subsequently, when the first clock signal terminal CKA provides a high level signal and the signal INPUT terminal INPUT provides a low level signal, the first stage t1 of the next cycle is entered.

It should be noted that, the scheme of disposing the first anti-leakage circuit 26 and the second anti-leakage circuit 27 in the first shift register is a preferred embodiment in the present disclosure, the first anti-leakage circuit 26 may maintain the voltage at the second node N2 stable in the fourth stage t4, and the second anti-leakage circuit 27 may maintain the voltage at the signal output terminal OUT stable in the first stage t1. It will be appreciated by those skilled in the art that the first shift register may optionally not include the first anti-leakage circuit 26 and/or the second anti-leakage circuit 27 in some embodiments.

In some embodiments, the first shift register further includes a global reset circuit 28, where the global reset circuit 28 is connected to a global reset signal terminal, a first power terminal, and a second node N2, and the global reset circuit 28 is configured to write the first operating voltage provided by the first power terminal to the second node N2 in response to control of a signal provided by the global reset signal terminal.

In some embodiments, global reset circuit 28 includes: a sixteenth transistor T16. The control electrode of the sixteenth transistor T16 is connected to the global reset signal terminal TRST, the first electrode of the sixteenth transistor T16 is connected to the second node N2, and the second electrode of the sixteenth transistor T16 is connected to the first power supply terminal.

As an alternative embodiment, the global reset signal terminal TRST supplies a high level signal (active level signal) during the blank period to turn on the sixteenth transistor T16 in the first shift register, and the first operating voltage VGH1 is written to the fifth node N5 through the sixteenth transistor T16 at this time, so that it is possible to ensure that the second node N2 is always in a high level state, and the tenth transistor T10 remains turned on at this time, and the signal output terminal OUT outputs a high level signal. That is, the first shift register does not output the black insertion driving signal in the blank stage.

With continued reference to fig. 5, in some embodiments, the first gate driving circuit is further configured with a first clock signal supply line CK1 and a second clock signal supply line CK2 arranged in a first direction; the first clock signal supply line and the second clock extend in a second direction; the first shift registers in the first gate driving circuit are sequentially arranged along the second direction, wherein the first clock signal end CKA configured by the first shift registers in the odd number of bits is connected to the first clock signal supply line CK1, the second clock signal end CKB configured by the first shift registers in the odd number of bits is connected to the second clock signal supply line CK2, the first clock signal end CKA configured by the first shift registers in the even number of bits is connected to the second clock signal supply line CK2, and the second clock signal end CKB configured by the first shift registers in the even number of bits is connected to the first clock signal supply line CK 1.

That is, all the first shift registers located within the first gate driving circuit share the first clock signal supply line CK1 and the second clock signal supply line CK2 (the first shift register groups independent of each other share the first clock signal supply line CK1 and the second clock signal supply line CK 2). The design can effectively reduce the arrangement quantity of the signal lines, and is beneficial to the narrow frame design of products.

In some embodiments, the global Reset signal terminal TRST configured by each of the first shift registers is connected to the same global Reset signal supply line Reset. I.e. all first shift registers located within the first gate driving circuit share the same global Reset signal supply line Reset.

In some embodiments, the pixel unit in the embodiments of the disclosure may employ the 4T1C structure shown in fig. 3, and for the first gate line and the second gate line (not shown in fig. 5) in the display area, a corresponding second gate driving circuit 400 may be configured in the peripheral area, where the second gate driving circuit 400 includes a plurality of cascaded second shift registers (not shown in fig. 5), and the second shift registers include at least two signal output terminals, where one signal output terminal is connected to the corresponding first gate line, and the other signal output terminal is connected to the corresponding second gate line. That is, only one second gate driving circuit 400 is required for the plurality of first gate lines and the plurality of second gate lines in the display region. The technical scheme of the present disclosure is not limited to the specific circuit structure of the second shift register.

Based on the same inventive concept, the embodiment of the disclosure also provides a driving method of the display substrate. Fig. 11 is a flowchart of a driving method of a display substrate according to an embodiment of the present disclosure, as shown in fig. 11, where the display substrate in the embodiment of the present disclosure is the display substrate provided in the previous embodiment; the first grid driving circuit in the display substrate comprises n first shift register groups, n is more than or equal to 2, one frame comprises n-1 black inserting driving stages, and the grid driving circuit is configured to sequentially provide an ith black inserting driving signal for each light-emitting control signal line in the ith black inserting driving stage, wherein i is more than or equal to 1 and less than or equal to n-1; each black inserting driving stage is divided into a first sub-stage and a second sub-stage by a preset blank period, wherein the first sub-stage is positioned before the blank period, and the second sub-stage is positioned after the blank period; the driving method of the display substrate comprises the following steps:

S1, respectively performing a first sub-stage of n-1 black insertion driving stages; in the first sub-stage in the ith black insertion driving stage, the ith black insertion driving start signals are sequentially and respectively provided for the first start control signal lines configured by the 1 st to n-i th first shift register groups, so that the first shift registers in the 1 st to n-i th first shift register groups sequentially output the ith black insertion driving signals.

S2, respectively carrying out second sub-stages of n-1 black inserting driving stages; in the second sub-stage in the ith black inserting driving stage, the ith black inserting driving start signals are sequentially and respectively provided for the first start control signal lines configured by the (n-i+1) th to (n) th first shift register groups, so that the first shift registers in the (n-i+1) th to (n) th first shift register groups sequentially output the ith black inserting driving signals.

Between step S1 and step S2 is a blank period in which each of the first shift registers does not output the black insertion driving signal. Therefore, the technical scheme of the disclosure supports random external compensation sensing of the display substrate in a blank period.

For a specific description of step S1 and step S2, reference may be made to the relevant content in the previous embodiments, and the description is omitted here.

Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, where the display device includes a display substrate, and the display substrate provided in the foregoing embodiments is used as the display substrate, and details of the display substrate may be referred to in the foregoing embodiments and will not be described herein.

The display device provided by the embodiment of the disclosure may be: flexible wearable equipment, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigator and any other products or components with display functions. Other essential components of the display device will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the invention.

It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.

Claims

1. A display substrate, comprising: the display device comprises a display area and a peripheral area positioned at the periphery of the display area, wherein a plurality of pixel units which are arranged in an array manner are arranged in the display area, and each row of pixel units is provided with a corresponding light-emitting control signal line;

2. The display substrate according to claim 1, wherein the number of the first start control signal lines is 2 to 5.

3. The display substrate of claim 1, wherein the first shift register comprises:

4. The display substrate according to claim 3, wherein the first input circuit comprises a first transistor, the second input circuit comprises a second transistor and a third transistor, the first voltage control circuit comprises a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitor, the second voltage control circuit comprises a seventh transistor and an eighth transistor, and the output circuit comprises a ninth transistor, a tenth transistor, a first capacitor, and a second capacitor;

the control electrode of the tenth transistor is connected with the second node, the first electrode of the tenth transistor is connected with the signal output end, and the second electrode of the tenth transistor is connected with the first power supply end;

the first end of the first capacitor is connected with the first node, and the second end of the first capacitor is connected with the second power supply end;

the first end of the second capacitor is connected with the signal output end, and the second end of the second capacitor is connected with the second node.

5. The display substrate according to claim 3, wherein the first shift register further comprises: a first anticreep circuit;

the first input circuit, the second input circuit and the second node control voltage are connected to a fifth node, the first anti-leakage circuit is positioned between the fifth node and the second node, and the first input circuit, the second input circuit and the second voltage control circuit are all connected with the second node through the first anti-leakage circuit;

6. The display substrate of claim 5, wherein the first anti-leakage circuit comprises: an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

7. The display substrate according to claim 3, wherein the first shift register further comprises: the output circuit is connected with a second power end through the second anti-leakage circuit, and the output circuit and the second anti-leakage circuit are connected with a second anti-leakage node;

8. The display substrate of claim 7, wherein the second anti-leakage circuit comprises: a fourteenth transistor and a fifteenth transistor;

9. The display substrate of claim 8, wherein the first shift register further comprises:

10. The display substrate of claim 9, wherein the global reset circuit comprises: a sixteenth transistor;

11. The display substrate according to any one of claims 3 to 10, wherein the first gate driving circuit is further configured with a first clock signal supply line and a second clock signal supply line arranged in a first direction; the first clock signal supply line and the second clock signal supply line each extend in a second direction;

12. A display device, comprising: the display substrate according to any of the preceding claims 1 to 11.

13. A driving method of a display substrate, wherein the display substrate adopts the display substrate according to any one of claims 1 to 11, the first gate driving circuit comprises n first shift register groups, n is greater than or equal to 2, one frame comprises n-1 black insertion driving stages, the first gate driving circuit is configured to sequentially provide an ith black insertion driving signal to each light-emitting control signal line in the ith black insertion driving stage, and i is greater than or equal to 1 and less than or equal to n-1;

the driving method includes: