CN116540051A - UIS testing device and using method thereof - Google Patents
UIS testing device and using method thereof Download PDFInfo
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- CN116540051A CN116540051A CN202310383640.4A CN202310383640A CN116540051A CN 116540051 A CN116540051 A CN 116540051A CN 202310383640 A CN202310383640 A CN 202310383640A CN 116540051 A CN116540051 A CN 116540051A
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- 238000012360 testing method Methods 0.000 title claims abstract description 333
- 238000000034 method Methods 0.000 title claims description 20
- 238000012545 processing Methods 0.000 claims abstract description 50
- 239000000523 sample Substances 0.000 claims abstract description 42
- 230000015556 catabolic process Effects 0.000 claims description 30
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 claims description 18
- 239000004973 liquid crystal related substance Substances 0.000 claims description 12
- 230000003068 static effect Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 239000004065 semiconductor Substances 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The invention provides a UIS testing device, which comprises a probe station, a testing processing terminal, a first switch, a second switch, a first testing module, a second testing module and MOS devices positioned on a wafer, wherein the probe station is connected with the testing processing terminal; the probe station is used for loading the wafer and sending the effective information of the MOS device to the test processing terminal; the test processing terminal is connected with the first test module and the second test module through the first switch and the second switch respectively, and is used for: receiving effective information, transmitting the effective information to the first test module and the second test module, and receiving test results of the first test module and the second test module; the first test module is used for non-UIS test, and when the first test module works, the first switch is switched on, and the second switch is switched off; the second test module is used for UIS test, and when the second test module works, the first switch is turned off, and the second switch is turned on. The wafer-level mass production test equipment for the UIS test item meets the total test requirement that various products have the UIS test item at the wafer level.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a UIS testing device and a using method thereof.
Background
More and more MOS devices need to test the ability of the device to withstand the impact of avalanche energy, and avalanche energy breakdown values EAS & EAR (single pulse avalanche breakdown energy & repeated avalanche energy) have become increasingly important indicators of MOS device robustness.
UIS (non-clamp inductive load switching process, unclamped Inductive Switching) test is essentially a test that simulates an MOS device experiencing extreme thermal stresses in a system application, from which we can derive the ability of the MOS device to withstand energy.
Referring to fig. 1 and 2, there is shown a test circuit for UIS test, the test circuit comprising: the MOS device, the inductor, the load resistor and the voltage source form a series test loop, a current probe is arranged on the test loop, voltage probes are arranged on the source end and the drain end of the MOS device, and the grid electrode of the MOS device is connected with the control circuit; when the MOS device is in an off state, the test value of the voltage probe is the voltage of the power supply, and the stored energy of the inductor tends to be zero; applying pulse to the gate electrode of the MOS device by using the control circuit, wherein the MOS device is in an on state, and the voltage source charges the inductor at the moment, so that the current of the test loop reaches the peak current; the voltage of the gate electrode of the MOS device is regulated to be 0 by utilizing the control circuit, the MOS device is turned off, the stored energy is discharged by the inductor through the MOS device, when the voltage at two ends of the MOS device reaches the breakdown voltage, the MOS device is subjected to avalanche breakdown, and the current of the test loop is reduced to be 0 from the peak current; inductance is L, peak current is I AS Breakdown voltage is BV DSS The voltage of the voltage source is V DD Avalanche energy breakdown value E AS ＝LI AS 2 BV DSS /2(BV DSS -V DD )。
In the wafer test stage of the current MOS device, a plurality of technical difficulties still exist for realizing mass production test on the UIS project, and no test equipment is available in the market. The reasons are probably the following:
1. the project test value has large fluctuation, has higher requirement on a test source and has extremely high requirement on the accuracy of the test.
2. The test item relates to an inductance device, and has extremely high requirements on the test precision of an inductance measurement unit.
3. In the test item, the energy release duration of each DUT is slightly different, and the calibration and unification of time sequences are required to be considered in the same test.
4. The test item is a device energy impact endurance test item, and compared with the common test items such as a leakage test, a starting voltage and the like, the test item has higher device damage probability.
For this reason, there is currently no wafer-level mass production test equipment (even single-test or packaged-device-only-oriented test equipment) available on the market for UIS test items. However, as our product types become more and more abundant, more and more products have full test requirements for doing this at the wafer level.
In order to solve the above problems, a new UIS testing device and a method for using the same are needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a UIS test apparatus and a method of using the same, for solving the problem that there is no wafer-level mass production test equipment (even single-test or package-only oriented test equipment) for UIS test items available in the prior art. However, as our product types become more and more abundant, more and more products have the problem of doing the full test requirements of the project at the wafer level.
To achieve the above and other related objects, the present invention provides a UIS test device, comprising:
the test system comprises a probe station, a test processing terminal, a first switch, a second switch, a first test module, a second test module and MOS devices positioned on a wafer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the probe station is used for loading the wafer and sending the effective information of the MOS device to the test processing terminal;
the test processing terminal is connected with the first test module and the second test module through the first switch and the second switch respectively, and the test processing terminal is used for: receiving the effective information, transmitting the effective information to the first test module and the second test module, and receiving test results of the first test module and the second test module;
the first test module is used for non-UIS test, when the first test module works, the first switch is switched on, and the second switch is switched off;
the second test module is used for UIS test, when the second test module works, the first switch is turned off, and the second switch is turned on.
Preferably, the second test module is provided with a test circuit, and the test circuit includes: the MOS device, the inductor, the load resistor and the voltage source form a series test loop, a current probe is arranged on the test loop, voltage probes are arranged on the source end and the drain end of the MOS device, and the grid electrode of the MOS device is connected with a control circuit; when the MOS device is in an off state, the test value of the voltage probe is the voltage of the power supply, and the stored energy of the inductor tends to be zero; applying a pulse to a gate electrode of the MOS device by using the control circuit, wherein the MOS device is in an on state, and the voltage source charges the inductor at the moment so that the current of the test loop reaches a peak current; the control circuit is utilized to adjust the voltage of the gate electrode of the MOS device to be 0, the MOS device is turned off, the inductance discharges the stored energy through the MOS device, when the voltage at two ends of the MOS device reaches the breakdown voltage, avalanche breakdown occurs to the MOS device, and the current of the test loop is reduced to 0 from the peak current; the inductance is L, the peak current is I AS The breakdown voltage is BV DSS The voltage of the voltage source is V DD Avalanche energy breakdown value E AS ＝LI AS 2 BV DSS /2(BV DSS -V DD )。
Preferably, the effective information includes information of the wafer, chip coordinate information on the wafer, and information of whether the MOS device to be tested is effective.
Preferably, the test processing terminal is a computer.
Preferably, the first test module is a static parameter tester.
Preferably, the second test module is a test meter array group.
Preferably, data is transmitted between the probe station and the processing terminal by using a GPIB protocol interface.
Preferably, the test processing terminal communicates data with the first test module using a THIB wiring port.
Preferably, the test processing terminal uses GPIB protocol to transmit data with the second test module.
The invention provides a use method of a UIS testing device, which comprises the following steps:
step one, providing a probe station, a test processing terminal, a first switch, a second switch, a first test module, a second test module and MOS devices positioned on a wafer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the probe station is used for loading the wafer and sending the effective information of the MOS device to the test processing terminal;
the test processing terminal is connected with the first test module and the second test module through the first switch and the second switch respectively, and the test processing terminal is used for: receiving the effective information, transmitting the effective information to the first test module and the second test module, and receiving test results of the first test module and the second test module;
the first test module is used for non-UIS test, when the first test module works, the first switch is switched on, and the second switch is switched off;
the second test module is used for UIS test, when the second test module works, the first switch is turned off, and the second switch is turned on;
step two, the first switch is turned off, the second switch is turned on, and the UIS test is performed by using the second test module;
and thirdly, turning on the first switch, turning off the second switch, and using the first test module to perform the non-UIS test to judge whether the MOS device fails.
Preferably, the second test module in the first step is provided with a test circuit, and the test circuit includes: the MOS device, the inductor, the load resistor and the voltage source form a series test loop, and the test loopA current probe is arranged on the road, a voltage probe is arranged on the source end and the drain end of the MOS device, and the grid electrode of the MOS device is connected with a control circuit; the using method of the test circuit comprises the following steps: turning off the MOS device, wherein the test value of the voltage probe is the voltage of the power supply, and the stored energy of the inductor tends to be zero; applying a pulse to a gate electrode of the MOS device by using the control circuit, starting the MOS device, and charging the inductor by using the voltage source so that the current of the test loop reaches a peak current; the control circuit is utilized to adjust the voltage of the gate electrode of the MOS device to be 0, the MOS device is turned off, the inductance discharges the stored energy through the MOS device, when the voltage at two ends of the MOS device reaches the breakdown voltage, avalanche breakdown occurs to the MOS device, and the current of the test loop is reduced to 0 from the peak current; the inductance is L, the peak current is I AS The breakdown voltage is BVDSS, the voltage of the voltage source is VDD, and the avalanche energy breakdown value E AS ＝LI AS 2 BV DSS /2(BV DSS -V DD )。
Preferably, the effective information in the first step includes information of the wafer, information of chip coordinates on the wafer, and information of whether the MOS device to be tested is effective.
Preferably, the test processing terminal in the first step is a computer.
Preferably, the first test module in the first step is a static parameter tester.
Preferably, the second test module in the first step is a test meter array group.
Preferably, data is transmitted between the probe station and the processing terminal in the first step by using a GPIB protocol interface.
Preferably, the test processing terminal in step one uses a THIB connection port to communicate data with the first test module.
Preferably, the test processing terminal in the first step uses GPIB protocol to transmit data with the second test module.
As described above, the UIS testing device and the using method thereof have the following beneficial effects:
the wafer-level mass production test equipment for the UIS test item meets the total test requirement that various products have the UIS test item at the wafer level.
Drawings
FIG. 1 is a schematic diagram of a prior art UIS test structure;
FIG. 2 is a schematic diagram of a UIS test principle according to the prior art;
FIG. 3 is a schematic diagram of a testing apparatus according to the present invention;
FIG. 4 is a schematic diagram of the test method of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
The invention provides a UIS testing device, comprising:
a probe station 101, a test processing terminal 102, a first switch (S1) and a second switch (S2), a first test module (103) and a second test module (104), and MOS devices positioned on a wafer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the probe station 101 is used for loading a wafer and sending effective information of the MOS device to the test processing terminal 102;
in an alternative embodiment, the valid information includes information about the wafer, die coordinate information on the wafer, and information about whether the MOS device (device under test ) to be tested is valid.
In an alternative embodiment, the second test module 104 is provided with a test circuit, where the test circuit includes: the MOS device, the inductor, the load resistor and the voltage source form a series test loop, the test loop is provided with a current probe, and the source of the MOS deviceThe drain terminal is provided with a voltage probe, and the grid electrode of the MOS device is connected with a control circuit; when the MOS device is in an off state, the test value of the voltage probe is the voltage of the power supply, and the stored energy of the inductor tends to be zero; applying pulse to the gate electrode of the MOS device by using the control circuit, wherein the MOS device is in an on state, and the voltage source charges the inductor at the moment, so that the current of the test loop reaches the peak current; the voltage of the gate electrode of the MOS device is regulated to be 0 by utilizing the control circuit, the MOS device is turned off, the stored energy is discharged by the inductor through the MOS device, when the voltage at two ends of the MOS device reaches the breakdown voltage, the MOS device is subjected to avalanche breakdown, and the current of the test loop is reduced to be 0 from the peak current; inductance is L, peak current is I AS Breakdown voltage is BV DSS The voltage of the voltage source is V DD Avalanche energy breakdown value E AS ＝LI AS 2 BV DSS /2(BV DSS -V DD ). It should be noted that the test circuit herein may be any other circuit for testing UIS, and is not specifically limited herein.
In an alternative embodiment, the test processing terminal 102 is a computer.
In an alternative embodiment, the first test module 103 is a static parametric tester for electrical parametric testing of power semiconductor devices.
In an alternative embodiment, the second test module 104 is a test meter array package. The test instrument array group is a customized instrument array module combination and is used for aligning the time sequence of an automatic calibration instrument after power-on, zeroing parameters and the like. The array meter cluster is an expandable array that can support 1-8 co-tests (which are later expanded up according to specific test requirements and test costs that can be supported) that are consistent with the co-tests of the first test module 103.
In an alternative embodiment, the data is transferred between the probe station 101 and the processing terminal using a GPIB protocol interface. A General-purpose interface bus (GPIB) is a bus to which devices and computers are connected. Most desktop instruments are connected to the computer via GPIB lines and GPIB interfaces.
In an alternative embodiment, test handler terminal 102 communicates data with first test module 103 using a THIB (test head interface bus ) wiring port.
In an alternative embodiment, the test processing terminal 102 communicates data with the second test module 104 using the GPIB protocol.
The test processing terminal 102 is connected with the first test module and the second test module through the first switch and the second switch respectively, and the test processing terminal 102 is used for receiving effective information, transmitting the effective information to the first test module and the second test module and receiving test results of the first test module and the second test module; wherein the first and second switches may be dynamic switching circuits or other types of switches;
the first test module 103 is used for non-UIS test, when the first test module 103 works, the first switch S1 is turned on, and the second switch S2 is turned off;
the second test module 104 is used for UIS test, and when the second test module 104 works, the first switch S1 is turned off, and the second switch S2 is turned on.
The invention provides a use method of a UIS testing device, which comprises the following steps:
step one, providing a probe station 101, a test processing terminal 102, a first switch (S1) and a second switch (S2), a first test module (103) and a second test module (104) and MOS devices positioned on a wafer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the probe station 101 is used for loading a wafer and sending effective information of the MOS device to the test processing terminal 102;
the test processing terminal 102 is connected with the first test module and the second test module through the first switch and the second switch respectively, and the test processing terminal 102 is used for receiving effective information, transmitting the effective information to the first test module and the second test module and receiving test results of the first test module and the second test module; wherein the first and second switches may be dynamic switching circuits or other types of switches;
in an alternative embodiment, the valid information in the first step includes information of a wafer, information of coordinates of chips on the wafer, and information of whether the MOS device (device under test ) to be tested is valid.
In an alternative embodimentIn an embodiment, the second test module 104 in the first step is provided with a test circuit, where the test circuit includes: the MOS device, the inductor, the load resistor and the voltage source form a series test loop, a current probe is arranged on the test loop, voltage probes are arranged on source and drain ends of the MOS device, and a grid electrode of the MOS device is connected with the control circuit; the using method of the test circuit comprises the following steps: turning off the MOS device, wherein the test value of the voltage probe is the voltage of the power supply, and the stored energy of the inductor tends to be zero; applying pulse to the gate electrode of the MOS device by using the control circuit, starting the MOS device, and charging the inductor by using the voltage source to enable the current of the test loop to reach the peak current; the control circuit is used for adjusting the voltage of a gate electrode of the MOS device to be 0, the MOS device is turned off, the inductance discharges stored energy through the MOS device, when the voltage at two ends of the MOS device reaches breakdown voltage, the MOS device is subjected to avalanche breakdown, and the current of the test loop is reduced to 0 from peak current; inductance is L, peak current is I AS Breakdown voltage is BVDSS, voltage of voltage source is VDD, avalanche energy breakdown value E AS ＝LI AS 2 BV DSS /2(BV DSS -V DD )。
In an alternative embodiment, the test processing terminal 102 in step one is a computer.
In an alternative embodiment, the first test module 103 in step one is a static parameter tester.
In an alternative embodiment, the second test module 104 in step one is a test meter array package.
In an alternative embodiment, the data is transferred between the probe station 101 and the processing terminal in step one using a GPIB protocol interface.
In an alternative embodiment, the test handler terminal 102 in step one communicates data with the first test module 103 using a THIB (test head interface bus ) wiring port.
In an alternative embodiment, the test processing terminal 102 in step one uses the GPIB protocol to communicate data with the second test module 104.
Step two, the first switch S1 is turned off, the second switch S2 is turned on, and the UIS test is performed by using the second test module 104;
and thirdly, turning on the first switch S1, turning off the second switch S2, and using the first test module 103 to perform a non-UIS test to determine whether the MOS device fails, for example, by detecting leakage current between source and drain of the MOS device, if the leakage current value is small, the device is good, otherwise, the MOS device is determined to fail.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the wafer-level mass production test equipment for UIS test items of the present invention meets the total test requirements of various products for UIS test items at the wafer level. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (18)
1. An UIS testing device, comprising:
the test system comprises a probe station, a test processing terminal, a first switch, a second switch, a first test module, a second test module and MOS devices positioned on a wafer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the probe station is used for loading the wafer and sending the effective information of the MOS device to the test processing terminal;
the test processing terminal is connected with the first test module and the second test module through the first switch and the second switch respectively, and the test processing terminal is used for: receiving the effective information, transmitting the effective information to the first test module and the second test module, and receiving test results of the first test module and the second test module;
the first test module is used for non-UIS test, when the first test module works, the first switch is switched on, and the second switch is switched off;
the second test module is used for UIS test, when the second test module works, the first switch is turned off, and the second switch is turned on.
2. The UIS testing device according to claim 1, wherein: the second test module is provided with a test circuit, and the test circuit comprises: the MOS device, the inductor, the load resistor and the voltage source form a series test loop, a current probe is arranged on the test loop, voltage probes are arranged on the source end and the drain end of the MOS device, and the grid electrode of the MOS device is connected with a control circuit; when the MOS device is in an off state, the test value of the voltage probe is the voltage of the power supply, and the stored energy of the inductor tends to be zero; applying a pulse to a gate electrode of the MOS device by using the control circuit, wherein the MOS device is in an on state, and the voltage source charges the inductor at the moment so that the current of the test loop reaches a peak current; the control circuit is utilized to adjust the voltage of the gate electrode of the MOS device to be 0, the MOS device is turned off, the inductance discharges the stored energy through the MOS device, when the voltage at two ends of the MOS device reaches the breakdown voltage, avalanche breakdown occurs to the MOS device, and the current of the test loop is reduced to 0 from the peak current; the inductance is L, the peak current is I AS The breakdown voltage is BV DSS The voltage of the voltage source is V DD Avalanche energy breakdown value
E AS ＝LI AS 2 BV DSS /2(BV DSS -V DD )。
3. The UIS testing device according to claim 1, wherein: the effective information comprises information of the wafer, coordinate information of chips on the wafer and information of whether the MOS device to be tested is effective or not.
4. The UIS testing device according to claim 1, wherein: the test processing terminal is a computer.
5. The UIS testing device according to claim 1, wherein: the first test module is a static parameter tester.
6. The UIS testing device according to claim 1, wherein: the second test module is a test instrument array group.
7. The UIS testing device according to claim 1, wherein: and transmitting data between the probe station and the processing terminal by using a GPIB protocol interface.
8. The UIS testing device according to claim 5, wherein: the test processing terminal uses the THIB wiring port to communicate data with the first test module.
9. The UIS testing device according to claim 6, wherein: and the test processing terminal transmits data with the second test module by using a GPIB protocol.
10. Use of a UIS testing device according to any one of claims 1 to 9, characterized in that:
step one, providing a probe station, a test processing terminal, a first switch, a second switch, a first test module, a second test module and MOS devices positioned on a wafer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the probe station is used for loading the wafer and sending the effective information of the MOS device to the test processing terminal;
the test processing terminal is connected with the first test module and the second test module through the first switch and the second switch respectively, and the test processing terminal is used for: receiving the effective information, transmitting the effective information to the first test module and the second test module, and receiving test results of the first test module and the second test module;
the first test module is used for non-UIS test, when the first test module works, the first switch is switched on, and the second switch is switched off;
the second test module is used for UIS test, when the second test module works, the first switch is turned off, and the second switch is turned on;
step two, the first switch is turned off, the second switch is turned on, and the UIS test is performed by using the second test module;
and thirdly, turning on the first switch, turning off the second switch, and using the first test module to perform the non-UIS test to judge whether the MOS device fails.
11. The method of using a UIS test device according to claim 10, wherein: the second test module in the first step is provided with a test circuit, and the test circuit comprises: the MOS device, the inductor, the load resistor and the voltage source form a series test loop, a current probe is arranged on the test loop, voltage probes are arranged on the source end and the drain end of the MOS device, and the grid electrode of the MOS device is connected with a control circuit; the using method of the test circuit comprises the following steps: turning off the MOS device, wherein the test value of the voltage probe is the voltage of the power supply, and the stored energy of the inductor tends to be zero; applying a pulse to a gate electrode of the MOS device by using the control circuit, starting the MOS device, and charging the inductor by using the voltage source so that the current of the test loop reaches a peak current; the control circuit is utilized to adjust the voltage of the gate electrode of the MOS device to 0, the MOS device is turned off, and the inductor discharges the stored energy through the MOS deviceWhen the voltage at two ends of the MOS device reaches the breakdown voltage, the MOS device generates avalanche breakdown, and the current of the test loop is reduced to 0 from the peak current; the inductance is L, the peak current is I AS The breakdown voltage is BVDSS, the voltage of the voltage source is VDD, and the avalanche energy breakdown value E AS ＝LI AS 2 BV DSS /2(BV DSS -V DD )。
12. The method of using a UIS test device according to claim 10, wherein: the effective information in the first step includes information of the wafer, chip coordinate information on the wafer, and information of whether the MOS device to be tested is effective.
13. The method of using a UIS test device according to claim 10, wherein: the test processing terminal in the first step is a computer.
14. The method of using a UIS test device according to claim 10, wherein: the first test module in the first step is a static parameter tester.
15. The method of using a UIS test device according to claim 10, wherein: the second test module in the first step is a test instrument array group.
16. The method of using a UIS test device according to claim 10, wherein: and in the first step, the data are transmitted between the probe station and the processing terminal by using a GPIB protocol interface.
17. The method of using a UIS test device according to claim 14, wherein: and in the first step, the test processing terminal uses the THIB wiring port to transmit data with the first test module.
18. The method of using a UIS test device according to claim 15, wherein: and in the first step, the test processing terminal transmits data with the second test module by using a GPIB protocol.
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| CN202310383640.4A CN116540051A (en) | 2023-04-11 | 2023-04-11 | UIS testing device and using method thereof |
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