CN116539960B - Power supply integrity PDN target impedance acquisition method - Google Patents
Power supply integrity PDN target impedance acquisition method Download PDFInfo
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Abstract
The invention relates to a power supply integrity PDN target impedance acquisition method, which comprises the following steps: the load end of the PDN to be tested of the tested piece is connected with a sampling resistor in series; placing the tested piece in a plurality of preset test scenes, collecting voltage values of sampling resistors corresponding to the tested piece in different test scenes during operation in a preset operation time, and obtaining collected voltage data corresponding to the plurality of test scenes; carrying out frequency domain analysis on the acquired voltage data corresponding to various test scenes, and extracting to obtain the maximum amplitude value of the frequency point corresponding to the alternating current component in the frequency domain; calculating to obtain the impedance of the frequency point according to the maximum amplitude value of the frequency point, the resistance value of the sampling resistor and the allowed floating value of the PDN to be tested; and obtaining a target impedance curve of the PDN to be measured according to the impedance of the frequency point. According to the power supply integrity PDN target impedance obtaining method, the PDN target impedance value of the tested piece in an actual application scene is extracted more accurately through analysis of actual test data and theoretical algorithm.
Description
Technical Field
The invention belongs to the field of electronic system design, and particularly relates to a power supply integrity PDN target impedance acquisition method.
Background
With the development of cloud computing and big data application, the integration density is high, the circuit frequency is higher and higher, and the power integrity becomes necessary to evaluate projects in the project design process. The power supply integrity is mainly divided into DC and AC, DC is an IR-Drop DC voltage Drop simulation test, and AC is PDN (power distribution network) frequency domain impedance simulation optimization.
In a system with a relatively low electrical interface, IR-Drop is a main consideration, but the demands of high-speed and big data application in the market are continuously increasing, the design of an integrated circuit is more and more advanced, the transmission rate of the interface of the whole electronic application system is continuously increased, and in addition, the low-power consumption is driven, the IO voltage is gradually reduced, for example, DDR2-800Mbps to DDR5-6400Mbps, the corresponding IO power is reduced from 1.8V to 1.1V, even the upcoming DDR6-12800Mbps, the Serdes is currently 56Gbps, and the PDN problem of the power integrity is prominent in the application of the interfaces with high-speed and low swing. Therefore, not only the IR-Drop is considered in designing the high-speed data transmission system, but also the PDN impedance is ensured to meet the target impedance, and the PDN simulation result is required to be evaluated based on the known PDN target impedance, so that design guidance is provided for excellent products.
The engineering calculation method of the target impedance of the PDN comprises the following steps:the method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>The impedance which is generated by the power supply network due to the load change and changes along with the frequency when the system works; />The allowable floating value of the power supply distribution network can be calculated through circuit manual information; />Is a constant factor; />In order to ensure that the current values generated by the power supply network at different frequency points due to the load change when the system worksThe manual cannot be found.
Currently, there are mainly 3 methods for obtaining:1. estimating based on project experience; 2. setting a more conservative value according to a manual to ensure the PDN of the product; 3. and modeling and simulating the device to obtain the device. However, the project experience estimation has large error in actual engineering and low reliability, and the problems of under-design risk and over-design resource waste exist in application. Inquiry by manual->Setting a more conservative constant factor beta to obtain a more conservative value to ensure PDN, which can lead to +.>The design difficulty and cost are suddenly reduced, the product development period is prolonged, and the market share is seriously or can be lost. In addition, a->Not explicitly shown in part of the circuit or given in a single scene state, different from the actual application, so that the method resultsWill be more unrealistic. The device modeling simulation is realized based on circuit-level and board-level model simulation, but not product system level, and more application factor pairs are ignored>The conclusion is ideal, and can only be used as a trend reference in engineering application, but cannot be used as a judgment basis.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a power supply integrity PDN target impedance acquisition method. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides a power supply integrity PDN target impedance acquisition method, which comprises the following steps:
the load end of the PDN to be tested of the tested piece is connected with a sampling resistor in series;
the tested piece is placed in a plurality of preset test scenes, the voltage values of sampling resistors corresponding to the tested piece in operation in a preset operation time are collected in different test scenes, and collected voltage data corresponding to the plurality of test scenes are obtained;
carrying out frequency domain analysis on the acquired voltage data corresponding to various test scenes, and extracting to obtain the maximum amplitude value of the frequency point corresponding to the alternating current component in the frequency domain;
calculating to obtain the impedance of the frequency point according to the maximum amplitude value of the frequency point, the resistance value of the sampling resistor and the allowed floating value of the PDN to be tested;
and obtaining a target impedance curve of the PDN to be tested according to the impedance of the frequency point.
In one embodiment of the invention, the plurality of test scenarios include a plurality of operating states formed in combination with a plurality of operating programs under environmental stress conditions of different temperatures and different air pressures.
In one embodiment of the present invention, frequency domain analysis is performed on collected voltage data corresponding to a plurality of test scenarios, and a maximum amplitude value of a frequency point corresponding to an ac component in a frequency domain is extracted, including:
performing fast Fourier transform operation on the acquired voltage data corresponding to each test scene to obtain corresponding frequency domain data;
removing direct current components in the frequency domain data, and extracting amplitude values of frequency points corresponding to alternating current components in the frequency domain data;
and comparing amplitude values of frequency points of alternating current components in frequency domain data corresponding to various test scenes, and reserving the maximum value to obtain the maximum amplitude value of the frequency points corresponding to the alternating current components in the frequency domain.
In one embodiment of the present invention, according to the maximum amplitude value of the frequency point, the resistance value of the sampling resistor, and the allowed floating value of the PDN to be measured, the impedance of the frequency point is calculated, including:
converting the maximum amplitude value of the frequency point to obtain a sampling voltage amplitude value of the frequency point;
according to the sampling voltage amplitude value of the frequency point and the resistance value of the sampling resistor, calculating to obtain the current value of the frequency point;
and calculating the impedance of the frequency point according to the current value of the frequency point and the allowed floating value of the PDN to be detected.
In one embodiment of the present invention, according to the current value of the frequency point and the allowed floating value of the PDN to be measured, calculating the impedance of the frequency point includes:
acquiring an allowed floating value of the PDN to be tested;
according to the current value of the frequency point and the allowed floating value of the PDN to be detected, calculating to obtain the impedance of the frequency point, wherein the impedance of each frequency point is calculated according to the following formula:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the impedance corresponding to the frequency bin, < >>Represents the allowed float value of the PDN under test, +.>Representing a constant factor->The current value corresponding to the frequency point is represented.
In one embodiment of the present invention, obtaining the target impedance curve of the PDN to be measured according to the impedance of the frequency point includes:
and fitting the impedance of the frequency points by a mathematical curve fitting method to obtain a target impedance curve of the PDN to be measured.
The invention provides a power supply integrity PDN target impedance acquisition device, which comprises: the sampling resistor, the data acquisition and storage module and the data processing module, wherein,
the sampling resistor is connected in series with the load end of the PDN to be tested of the tested piece;
the data acquisition and storage module is used for acquiring voltage values of sampling resistors corresponding to the tested piece in running in preset running time in different test scenes and storing acquired voltage data corresponding to various test scenes;
the data processing module is used for carrying out frequency domain analysis on the collected voltage data corresponding to the received various test scenes, extracting to obtain a maximum amplitude value of a frequency point corresponding to the alternating current component in the frequency domain, and calculating to obtain the impedance of the frequency point according to the maximum amplitude value of the frequency point, the resistance value of the sampling resistor and the allowed floating value of the PDN to be tested; and obtaining a target impedance curve of the PDN to be tested according to the impedance of the frequency point.
In one embodiment of the present invention, the data acquisition and storage module is a high-speed ADC acquisition board card, including: the system comprises an FPGA main control platform, a power supply module, a starting program module, a data cache module, a high-speed ADC module and an upper computer communication module, wherein,
the power supply module is used for distributing power to the FPGA main control platform;
the FPGA main control platform is used for configuring the high-speed ADC module and the upper computer communication module after being started according to the received FPGA program loaded by the starting program module;
the high-speed ADC module is used for collecting voltage values of sampling resistors corresponding to the tested piece in different testing scenes in a preset operation time;
the data caching module is used for storing collected voltage data corresponding to various test scenes;
and the upper computer communication module is used for recombining and transmitting the cached acquired voltage data to the data processing module.
In one embodiment of the present invention, the data processing module comprises a PC host.
Compared with the prior art, the invention has the beneficial effects that:
according to the power supply integrity PDN target impedance obtaining method, the PDN target impedance value of the tested piece in an actual application scene is extracted more accurately through the analysis of the actual test data combined with the theoretical algorithm, the method has good guiding value for the design of the electronic product with low cost and high reliability, the problems of power supply PDN undersign risks and over-design resource waste are greatly reduced, and meanwhile the method has universality for extracting PDN target impedance in the design of an electronic product system.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a power supply integrity PDN target impedance obtaining method according to an embodiment of the present invention;
fig. 2 is a block diagram of a power integrity PDN target impedance obtaining apparatus according to an embodiment of the present invention;
FIG. 3 is a block diagram of a high-speed ADC acquisition board according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating operation of a high-speed ADC acquisition board card according to an embodiment of the invention.
Detailed Description
In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the following describes a power integrity PDN target impedance obtaining method according to the invention in detail with reference to the accompanying drawings and the detailed description.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
In a first aspect, the present embodiment provides a method for obtaining power supply integrity PDN target impedance, referring to fig. 1, fig. 1 is a schematic diagram of the method for obtaining power supply integrity PDN target impedance provided in the embodiment of the present invention, as shown in the fig. 1, the method for obtaining power supply integrity PDN target impedance of the present embodiment includes:
step 1: the load end of the PDN to be tested of the tested piece is connected with a sampling resistor in series;
in this embodiment, the power consumption current of the load end of the PDN to be tested in different scenarios flows through the sampling resistor to generate an analog voltage signal, and the voltage values at the two ends of the sampling resistor are collected and analyzed to determine the target impedance of the PDN.
Optionally, the sampling resistor is a precision sampling resistor with small current noise and low temperature drift.
Step 2: placing the tested piece in a plurality of preset test scenes, collecting voltage values of sampling resistors corresponding to the tested piece in different test scenes during operation in a preset operation time, and obtaining collected voltage data corresponding to the plurality of test scenes;
in an alternative embodiment, the plurality of test scenarios includes a plurality of operating states formed in combination with a plurality of operating programs under ambient stress conditions of different temperatures and different air pressures.
It should be noted that, the test scenario is set according to the actual operation scenario of the power supply to be tested, and covers the scenarios of running various application programs, pressure test, setting special limit code patterns manually, and the like, and combining environmental stresses such as three-temperature environment, temperature impact, and the like, and mechanical stress and actual application scenario can be added according to the requirement.
In this embodiment, for a current test scenario, the voltage value of the sampling resistor corresponding to the tested piece in running is collected in a preset running time, and is used as collected voltage data in the test scenario.
Step 3: carrying out frequency domain analysis on the acquired voltage data corresponding to various test scenes, and extracting to obtain the maximum amplitude value of the frequency point corresponding to the alternating current component in the frequency domain;
in an alternative embodiment, step 3 includes:
step 3.1: performing fast Fourier transform operation on the acquired voltage data corresponding to each test scene to obtain corresponding frequency domain data;
optionally, the sample length of the Fast Fourier Transform (FFT) is determined in combination with the frequency resolution required by the target impedance of the PDN.
Step 3.2: removing direct current components in the frequency domain data, and extracting amplitude values of frequency points corresponding to alternating current components in the frequency domain data;
for the frequency domain data after the FFT operation, the first frequency point value is a direct current component, and thus can be removed. In this embodiment, only the alternating current component after the first frequency point in the frequency domain data needs to be analyzed. Specifically, the amplitude information of the second frequency point of the frequency domain data is extracted from the second frequency point, and the amplitude information is taken as an amplitude value at the corresponding frequency.
Step 3.3: and comparing amplitude values of frequency points of alternating current components of frequency domain data corresponding to various test scenes, and reserving the maximum value to obtain the maximum amplitude value of the frequency points corresponding to the alternating current components in the frequency domain.
In this embodiment, different voltage sampling values are acquired along with different actual scenes of the operation of the power supply to be tested, different amplitude values can be obtained for frequency points of the ac component after FFT of the acquired voltage data, the amplitude values are compared, and a large amplitude value of the frequency point of the ac component is reserved until all the involved test scenes are acquired, and finally, the maximum amplitude value of the frequency point corresponding to the ac component in the frequency domain is obtained.
Step 4: calculating to obtain the impedance of the frequency point according to the maximum amplitude value of the frequency point, the resistance value of the sampling resistor and the allowed floating value of the PDN to be tested;
in an alternative embodiment, step 4 includes:
step 4.1: converting the maximum amplitude value of the frequency point to obtain a sampling voltage amplitude value of the frequency point;
illustratively, assume that there are N after FFT conversionFrequency points, the amplitude of each frequency point is A 1 ，A 2 ,A 3 ...A n Then V 1 =A 1 N (in this embodiment, the first frequency point is the DC component removed and no analysis is performed), and the sampling voltage amplitude values of the frequency points of the rest AC components are。
Step 4.2: according to the amplitude value of the sampling voltage of the frequency point and the resistance value of the sampling resistor, calculating to obtain the current value of the frequency point;
in this embodiment, the current value of the frequency point is obtained by dividing the sampled voltage amplitude value of the frequency point by the resistance value of the sampling resistor.
Step 4.3: and calculating the impedance of the frequency point according to the current value of the frequency point and the allowed floating value of the PDN to be detected.
Optionally, step 4.3 includes:
step 4.31: acquiring an allowed floating value of the PDN to be tested;
in this embodiment, the allowable floating value of the PDN to be tested may be obtained by querying according to a circuit manual.
Step 4.32: according to the current value of the frequency point and the allowed floating value of the PDN to be detected, calculating to obtain the impedance of the frequency point, wherein the impedance of each frequency point is calculated according to the following formula:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the impedance corresponding to the frequency bin, < >>Represents the allowed float value of the PDN under test, +.>Representing a constant factor->The current value corresponding to the frequency point is represented.
In this embodiment, the calculated current value of the frequency point in the frequency domain is the frequency point in the frequency domain。
Alternatively, the process may be carried out in a single-stage,the constant factor is determined according to the actual design circuit of the PDN to be tested.
Step 5: and obtaining a target impedance curve of the PDN to be measured according to the impedance of the frequency point.
In an alternative embodiment, step 5 includes: and fitting the impedance of the frequency points by a mathematical curve fitting method to obtain a target impedance curve of the PDN to be measured.
According to the power supply integrity PDN target impedance obtaining method, the PDN target impedance value of the tested piece in an actual application scene is extracted more accurately through analysis of actual test data and theoretical algorithm, the method has good guiding value for the design of low-cost and high-reliability electronic products, the problems of power supply PDN undersign risks and over-design resource waste are greatly reduced, and meanwhile the method has universality for extracting PDN target impedance in the design of an electronic product system.
In a second aspect, the present embodiment provides a power supply integrity PDN target impedance obtaining device, please refer to fig. 2, fig. 2 is a block diagram of a power supply integrity PDN target impedance obtaining device provided in the embodiment of the present invention, and the power supply integrity PDN target impedance obtaining device in the present embodiment is suitable for the power supply integrity PDN target impedance obtaining method described in the above embodiment.
As shown in fig. 2, the power integrity PDN target impedance obtaining apparatus includes: sampling resistor 100, data acquisition and storage module 200 and data processing module 300. The sampling resistor 100 is connected in series with the load end of the PDN to be tested of the tested piece; the data acquisition and storage module 200 is used for acquiring voltage values of sampling resistors corresponding to the tested piece in different test scenes in a preset operation time, and storing acquired voltage data corresponding to various test scenes; the data processing module 300 is configured to perform frequency domain analysis on collected voltage data corresponding to multiple received test scenarios, extract a maximum amplitude value of a frequency point corresponding to an ac component in a frequency domain, and calculate an impedance of the frequency point according to the maximum amplitude value of the frequency point, a resistance value of a sampling resistor, and an allowable floating value of a PDN to be tested; and obtaining a target impedance curve of the PDN to be measured according to the impedance of the frequency point.
In an alternative embodiment, the data acquisition and storage module 200 is a high-speed ADC acquisition board card and the data processing module 300 comprises a PC host.
Referring to fig. 3 and fig. 4 in combination, fig. 3 is a block diagram of a high-speed ADC acquisition board according to an embodiment of the invention; fig. 4 is a flowchart of operation of a high-speed ADC acquisition board provided in an embodiment of the present invention, and specifically illustrates a structure and an operation process of the high-speed ADC acquisition board of the present embodiment.
As shown in fig. 3, in this embodiment, the high-speed ADC acquisition board card includes an FPGA main control platform, a power module, a start program module, a data buffer module, a high-speed ADC module, and an upper computer communication module.
In an alternative embodiment, the power module is used for distributing power to the FPGA master control platform; optionally, the FPGA main control platform needs to support LVDS or J204B high-speed data transmission protocol, power distribution adopts two-level power distribution, the whole power module is input by 220V mains supply of a laboratory through a 12V adapter, and power supply of each module is further realized through DCDC\LDO.
In an optional embodiment, the FPGA master control platform is configured to configure the high-speed ADC module and the upper computer communication module after being started according to the FPGA program loaded by the received starting program module.
Optionally, the starting program module is interconnected with the FPGA master control platform 201 through the SPI FLASH, so as to complete component starting, updating, and the like for the FPGA master control platform.
In an optional embodiment, the high-speed ADC module is configured to collect voltage values of sampling resistors corresponding to the tested piece running in a preset running time in different test scenarios.
Optionally, the high-speed ADC module is selected according to the actually required sampling precision and the highest frequency point of interest, the sampling bit number can be selected from common 12-bit high-speed ADCs, and the sampling frequency is required to meet the Nyquist sampling law, namely. Illustratively, the system PDN needs to pay attention to the impedance of 250MHz at the highest, then 500MSPS up-sampling rate ADC is selected. In this embodiment, a conditioning circuit is provided within the high-speed ADC module.
In an optional embodiment, the data buffer module is configured to store collected voltage data corresponding to multiple test scenarios.
Optionally, the data cache module employs 32-bit DDR3 storage.
In an alternative embodiment, the upper computer communication module is configured to reassemble the buffered acquired voltage data and transmit the reassembled packet to the data processing module.
Optionally, the upper computer communication module is a USB controller, the FPGA main control platform is interconnected with the USB3.0 controller circuit through parallel IO, and realizes data transmission of a USB3.0 standard communication interface with the PC upper computer through parallel-serial conversion, and the data collected by the high-speed ADC module of the lower computer is uploaded to the PC upper computer for processing.
As shown in fig. 4, after the FPGA main control platform is powered on, the configuration register space is emptied, a starting mode is obtained, and the FPGA program is loaded; then, configuring a high-speed ADC module and a USB controller through a preset program; in the process of testing the tested piece in various test scenes, writing the data acquired by the high-speed ADC module into the data cache module; the USB controller reads data from the data cache module and transmits the data to the USB controller in a group through parallel IO; finally, the USB controller is assembled into data conforming to the USB3.0 protocol through parallel-serial conversion and is uploaded to the PC upper computer.
In this embodiment, the specific processing procedure of the collected voltage data corresponding to the received multiple test scenarios by the PC upper computer is consistent with the execution procedure of step 3 and step 4 in the method embodiment, and will not be described herein.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises the element. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (6)
1. A power supply integrity PDN target impedance acquisition method, comprising:
the load end of the PDN to be tested of the tested piece is connected with a sampling resistor in series;
the tested piece is placed in a plurality of preset test scenes, the voltage values of sampling resistors corresponding to the tested piece in operation in a preset operation time are collected in different test scenes, and collected voltage data corresponding to the plurality of test scenes are obtained;
carrying out frequency domain analysis on the acquired voltage data corresponding to various test scenes, and extracting to obtain the maximum amplitude value of the frequency point corresponding to the alternating current component in the frequency domain; comprising the following steps:
performing fast Fourier transform operation on the acquired voltage data corresponding to each test scene to obtain corresponding frequency domain data;
removing direct current components in the frequency domain data, and extracting amplitude values of frequency points corresponding to alternating current components in the frequency domain data;
comparing amplitude values of frequency points of alternating current components in frequency domain data corresponding to various test scenes, and reserving the maximum value to obtain the maximum amplitude value of the frequency points corresponding to the alternating current components in the frequency domain;
calculating to obtain the impedance of the frequency point according to the maximum amplitude value of the frequency point, the resistance value of the sampling resistor and the allowed floating value of the PDN to be tested; comprising the following steps:
converting the maximum amplitude value of the frequency point to obtain a sampling voltage amplitude value of the frequency point;
according to the sampling voltage amplitude value of the frequency point and the resistance value of the sampling resistor, calculating to obtain the current value of the frequency point;
calculating to obtain the impedance of the frequency point according to the current value of the frequency point and the allowed floating value of the PDN to be detected;
comprising the following steps: acquiring an allowed floating value of the PDN to be tested; according to the current value of the frequency point and the allowed floating value of the PDN to be detected, calculating to obtain the impedance of the frequency point, wherein the impedance of each frequency point is calculated according to the following formula:
wherein Z is target Representing the impedance corresponding to the frequency point, V ripple The allowable floating value of the PDN to be tested is represented, alpha represents a constant factor, and delta i represents a current value corresponding to a frequency point;
and obtaining a target impedance curve of the PDN to be tested according to the impedance of the frequency point.
2. The power integrity PDN target impedance obtaining method according to claim 1, wherein the plurality of test scenarios includes a plurality of operating states formed in combination with a plurality of operating procedures under environmental stress conditions of different temperatures and different air pressures.
3. The method of claim 1, wherein obtaining a target impedance curve of the PDN to be tested according to the impedance of the frequency point comprises:
and fitting the impedance of the frequency points by a mathematical curve fitting method to obtain a target impedance curve of the PDN to be measured.
4. A power supply integrity PDN target impedance acquisition device, comprising: the sampling resistor, the data acquisition and storage module and the data processing module, wherein,
the sampling resistor is connected in series with the load end of the PDN to be tested of the tested piece;
the data acquisition and storage module is used for acquiring voltage values of sampling resistors corresponding to the tested piece in running in preset running time in different test scenes and storing acquired voltage data corresponding to various test scenes;
the data processing module is used for carrying out frequency domain analysis on the collected voltage data corresponding to the received various test scenes, extracting to obtain a maximum amplitude value of a frequency point corresponding to the alternating current component in the frequency domain, and calculating to obtain the impedance of the frequency point according to the maximum amplitude value of the frequency point, the resistance value of the sampling resistor and the allowed floating value of the PDN to be tested; obtaining a target impedance curve of the PDN to be tested according to the impedance of the frequency point;
specifically, the data processing module is configured to perform a fast fourier transform operation on the collected voltage data corresponding to each test scenario, so as to obtain corresponding frequency domain data; removing direct current components in the frequency domain data, and extracting amplitude values of frequency points corresponding to alternating current components in the frequency domain data; comparing amplitude values of frequency points of alternating current components in frequency domain data corresponding to various test scenes, and reserving the maximum value to obtain the maximum amplitude value of the frequency points corresponding to the alternating current components in the frequency domain; converting the maximum amplitude value of the frequency point to obtain a sampling voltage amplitude value of the frequency point; according to the sampling voltage amplitude value of the frequency point and the resistance value of the sampling resistor, calculating to obtain the current value of the frequency point; calculating to obtain the impedance of the frequency point according to the current value of the frequency point and the allowed floating value of the PDN to be detected; comprising the following steps: acquiring an allowed floating value of the PDN to be tested; according to the current value of the frequency point and the allowed floating value of the PDN to be detected, calculating to obtain the impedance of the frequency point, wherein the impedance of each frequency point is calculated according to the following formula:
wherein Z is target Representing the impedance corresponding to the frequency point, V ripple And the allowed floating value of the PDN to be tested is represented, alpha represents a constant factor, and delta i represents a current value corresponding to the frequency point.
5. The power integrity PDN target impedance obtaining device according to claim 4, wherein the data acquisition memory module is a high-speed ADC acquisition board card, comprising: the system comprises an FPGA main control platform, a power supply module, a starting program module, a data cache module, a high-speed ADC module and an upper computer communication module, wherein,
the power supply module is used for distributing power to the FPGA main control platform;
the FPGA main control platform is used for starting according to the received FPGA program loaded by the starting program module, and after starting, the high-speed ADC module and the upper computer communication module are configured;
the high-speed ADC module is used for collecting voltage values of sampling resistors corresponding to the tested piece in different testing scenes in a preset operation time;
the data caching module is used for storing collected voltage data corresponding to various test scenes;
and the upper computer communication module is used for recombining and transmitting the cached acquired voltage data to the data processing module.
6. The power integrity PDN target impedance obtaining apparatus of claim 4, wherein the data processing module comprises a PC host computer.
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