CN116528614A - Tiled display panel and tiled display device - Google Patents

Abstract

The disclosure provides a tiled display panel and a tiled display device, wherein the tiled display panel comprises a plurality of tiled light emitting substrates, each light emitting substrate comprises a substrate and a pixel definition layer arranged on the substrate, the pixel definition layer is used for defining a plurality of pixel units and at least two groups of light emitting units positioned in one pixel unit, and one group of light emitting units comprises at least one red sub-pixel, at least one green sub-pixel and at least one blue sub-pixel; and a seam is arranged between the adjacent light-emitting substrates, and at least two pixel units are positioned on two sides of the seam. The luminous substrate can reduce the visual seam of the spliced display device and improve the display effect.

Description

Tiled display panel and tiled display device

Technical Field

The application relates to the technical field of display, in particular to a spliced display panel and spliced display equipment.

Background

The spliced screen is display equipment with a larger display area, which is formed by splicing a plurality of display screen units, and is commonly used for meeting indoor large-size display requirements. The display screen units can be used as a display independently and can be spliced into a large-size spliced screen for use.

Because the spliced screen is formed by splicing a plurality of display screen units, and because the spliced screen is limited by a packaging process, seamless splicing cannot be realized, large macroscopic splice seams exist in the spliced screen generally, and the overall display effect of the spliced screen is reduced due to the existence of the splice seams.

Disclosure of Invention

In view of the above, the present disclosure provides a tiled display panel and a tiled display device, which can reduce the visual seam of the tiled display device and improve the display effect.

In a first aspect, the present disclosure provides, by way of an embodiment, the following technical solutions:

the spliced display panel comprises a plurality of spliced light-emitting substrates, wherein each light-emitting substrate comprises a substrate base plate and a pixel definition layer arranged on the substrate base plate, the pixel definition layer is used for defining a plurality of pixel units and at least two groups of light-emitting units positioned in one pixel unit, and one group of light-emitting units comprises at least one red sub-pixel, at least one green sub-pixel and at least one blue sub-pixel; and a seam is arranged between the adjacent light-emitting substrates, and at least two pixel units are positioned on two sides of the seam.

In some embodiments, the pixel defining layer includes a protrusion portion for defining the plurality of pixel cells and a groove portion for defining the at least two groups of light emitting cells among the pixel cells.

In some embodiments, one of the pixel units includes N therein ² And the group light-emitting units are arranged, wherein N is more than or equal to 2 and is an integer.

In some embodiments, one of the pixel units includes a first pixel circuit, a second pixel circuit, and a third pixel circuit;

the first pixel circuit is configured to drive all red sub-pixels in the pixel unit to emit light, the second pixel circuit is configured to drive all green sub-pixels in the pixel unit to emit light, and the third pixel circuit is configured to drive all blue sub-pixels in the pixel unit to emit light.

In some embodiments, the light emitting unit includes an anode, a cathode, and a light emitting layer disposed between the anode and the cathode;

and in the pixel unit, the anodes of all red sub-pixels are shorted, the anodes of all green sub-pixels are shorted, and the anodes of all blue sub-pixels are shorted.

In some embodiments, the first pixel circuit includes a first transistor, a second transistor, six third transistors, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitance;

the six third transistors are connected in parallel to form a driving transistor group;

a control electrode of the driving transistor group, a negative electrode of the first capacitor, a first electrode of the fourth transistor, and a first electrode of the seventh transistor are coupled to a first node;

a second pole of the first transistor, a first pole of the fifth transistor, and a first pole of the set of drive transistors are coupled to a second node;

a second pole of the set of drive transistors, a first pole of the second transistor, and a second pole of the fourth transistor are coupled to a third node;

the second pole of the second transistor, the first pole of the sixth transistor, and the anodes of all red subpixels are coupled to a fourth node;

the control electrode of the first transistor is connected with a light-emitting control line, and the first electrode of the first transistor is connected with a first power line;

the control electrode of the second transistor is connected with the light-emitting control line;

the control electrode of the fourth transistor is connected with the scanning line;

the control electrode of the fifth transistor is connected with the scanning line, and the second electrode is connected with the data line;

the control electrode of the sixth transistor is connected with a second reset control line, and the second electrode is connected with an initialization signal line;

a second electrode of the seventh transistor is connected with the initialization signal line, and a control electrode of the seventh transistor is connected with a first reset control line;

the positive electrode of the first capacitor is connected with a first power line;

the cathodes of all the red sub-pixels are connected with a second power line.

In some embodiments, a group of the light emitting units includes 2 fourth pixel circuits, 2 fifth pixel circuits, and 2 sixth pixel circuits;

the 2 fourth pixel circuits are configured to drive one red sub-pixel to emit light, the 2 fifth pixel circuits are configured to drive one green sub-pixel to emit light, and the 2 sixth pixel circuits drive one blue sub-pixel to emit light.

In some embodiments, the fourth pixel circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second capacitor;

a negative electrode of the second capacitor, a first electrode of the eleventh transistor, a first electrode of the fourteenth transistor, and a control electrode of the tenth transistor are coupled to a fifth node;

a second pole of the eighth transistor, a first pole of the tenth transistor, and a first pole of the twelfth transistor are coupled to a sixth node;

a first pole of the ninth transistor, a second pole of the tenth transistor, and a second pole of the eleventh transistor are coupled to a seventh node;

a second pole of the ninth transistor, a first pole of the thirteenth transistor, and an anode of the red subpixel are coupled to an eighth node;

the control electrode of the eighth transistor is connected with a light-emitting control line, and the first electrode is connected with a first power line;

a control electrode of the ninth transistor is connected with a light-emitting control line;

a control electrode of the eleventh transistor is connected with the scanning line;

the control electrode of the twelfth transistor is connected with the scanning line, and the second electrode is connected with the data line;

a control electrode of the thirteenth transistor is connected with a second reset control line, and the second electrode is connected with an initialization signal line;

a second pole of the fourteenth transistor is connected with the initialization signal line, and a control pole of the fourteenth transistor is connected with a first reset control line.

In some embodiments, in the pixel unit, the scan line, the first reset control line, the second reset control line, the initialization signal line, and the light emission control line connected to the red subpixel are respectively shorted; and the data line positioned in the pixel unit is short-circuited.

In a second aspect, based on the same inventive concept, the present disclosure provides, through an embodiment, the following technical solutions:

a tiled display device includes a tiled display panel provided by an embodiment of the first aspect.

Through one or more technical schemes of the present disclosure, the present disclosure has the following beneficial effects or advantages:

the disclosure provides a spliced display panel, which comprises a plurality of spliced light-emitting substrates, wherein a plurality of groups of light-emitting units are arranged in one pixel unit in the light-emitting substrates, and red sub-pixels, green sub-pixels and blue sub-pixels in one group of light-emitting units form a light-emitting center, so that a plurality of light-emitting centers are formed in one pixel unit; under the same frame design, compared with the prior scheme of arranging a group of light-emitting units in one pixel unit, the original light-emitting center is decomposed into a plurality of light-emitting centers, on one hand, the light-emitting centers are shifted to the edges of the pixel units, so that the distance between two adjacent light-emitting centers positioned at two sides of the seam can be shortened, the visual seam is reduced, and the seam is narrowed visually; on the other hand, the pixel density is also improved, so that the display image quality is finer, and the display effect of the spliced display device and the viewing experience of audiences are improved.

The foregoing description is merely an overview of the technical solutions of the present disclosure, and may be implemented according to the content of the specification in order to make the technical means of the present disclosure more clearly understood, and in order to make the above and other objects, features and advantages of the present disclosure more clearly understood, the following specific embodiments of the present disclosure are specifically described.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram showing a pixel arrangement of a tiled display panel;

FIG. 2 shows a schematic view of the light emitting center shown in FIG. 1;

FIG. 3 shows a schematic diagram of a pixel arrangement of a tiled display panel according to an embodiment of the present disclosure;

FIG. 4 shows a schematic diagram of a light emitting center arrangement according to an embodiment of the present disclosure;

FIG. 5 illustrates a cross-sectional view of a pixel definition layer according to an embodiment of the disclosure;

FIG. 6A illustrates a circuit layout of a pixel drive scheme 1 of an embodiment of the present disclosure forming a poly layer on a substrate base;

FIG. 6B shows the circuit layout of scenario 1 continuing to form the first scan line layer;

FIG. 6C shows the circuit layout of scenario 1 continuing to form the second scan line layer;

fig. 6D shows a circuit layout in which the interlayer insulating layer continues to be formed in scheme 1;

FIG. 6E shows the circuit layout of scenario 1 continuing to form the first data line layer;

fig. 6F shows the circuit layout of scenario 1 continuing to form the first passivation layer;

FIG. 6G shows the circuit layout of scenario 1 continuing to form the first planarization layer;

FIG. 6H shows the circuit layout of scenario 1 continuing to form the second data line layer;

FIG. 6I shows the circuit layout of scheme 1 continuing to form a second planarizing layer;

FIG. 6J shows the circuit layout of scheme 1 continuing to form the anode layer;

fig. 7 shows an equivalent circuit schematic of a first pixel circuit according to an embodiment of the present disclosure;

FIG. 8A illustrates a multi-layer circuit layout of pixel drive scheme 2 of an embodiment of the present disclosure;

FIG. 8B shows the circuit layout of scheme 2 continuing to form the first scan line layer;

FIG. 8C shows the circuit layout of scheme 2 continuing to form the second scan line layer;

fig. 8D shows a circuit layout in which the interlayer insulating layer continues to be formed in scheme 2;

FIG. 8E shows the circuit layout of scheme 2 continuing to form the first data line layer;

fig. 8F shows the circuit layout of scheme 2 continuing to form the first passivation layer;

FIG. 8G shows the circuit layout of scenario 2 continuing to form the first planarization layer;

FIG. 8H shows the circuit layout of scenario 2 continuing to form the second data line layer;

FIG. 8I shows the circuit layout of scheme 2 continuing to form a second planarizing layer;

FIG. 8J shows the circuit layout of scheme 2 continuing to form the anode layer;

fig. 9 shows an equivalent circuit schematic diagram of a fourth pixel circuit according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.

In the context of the present disclosure, the light-emitting side of the light-emitting substrate is referred to as "top side" or "upper side", and the opposite side is referred to as "bottom side" or "lower side", unless otherwise specified, in order to describe the relative direction. Accordingly, the direction from the bottom side to the top side is the thickness direction of the light emitting substrate, and the direction perpendicular to the thickness direction is the "plane direction" or the "extending direction" of the light emitting substrate. It should be understood that these directions are relative directions rather than absolute directions.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Because the packaging technology is limited and can not be spliced seamlessly, a row of non-luminous areas with the pixel width exist at the splice joint of the spliced screen at present, and the areas are packaging areas, so that a large splice joint visible to naked eyes exists. Meanwhile, since the tiled screen is mainly applied to indoor large-size display, the viewing distance between a person and the tiled screen is farther than that of a computer display in consideration of the fact that the tiled screen is larger, the current design scheme of the tiled screen is usually high current and low pixel density (PPI). The high current is to improve the display brightness of the spliced screen, and the low PPI is because the viewing distance is far, so that the viewing requirement can be met.

Fig. 1 to 2 show a pixel arrangement scheme of a conventional tiled display screen, in which a group of RGB light emitting units are disposed in one pixel unit (RGB unit) and the area of the light emitting units is large due to the low PPI design, so that the light emitting center or white light center of the pixel unit is located in the middle area of the RGB light emitting unit. Therefore, the luminous centers on both sides of the seam have larger gaps, forming a wider visual gap, as shown in fig. 2, and the circles in fig. 2 represent the luminous centers. The wider visual gap leads to the obvious decline of the display effect of concatenation screen in the piece department, has also influenced the whole display effect of concatenation screen simultaneously, has reduced people's use experience.

Based on the above analysis, in order to solve the problem that the viewing of the tiled screen is greatly affected by the visual stitching, in a first aspect, in an alternative embodiment, referring to fig. 3 to 5, a tiled display panel is provided, including a plurality of tiled light emitting substrates, the light emitting substrates including a substrate and a pixel defining layer 20 disposed on the substrate, the pixel defining layer 20 being configured to define a plurality of pixel units 100 and at least two groups of light emitting units 110 located within one pixel unit 100, one group of light emitting units 110 including at least one red subpixel R, at least one green subpixel G and at least one blue subpixel B; a seam is formed between adjacent light emitting substrates, and at least two pixel units 100 are located at two sides of the seam.

In the tiled display panel provided in this embodiment, by arranging multiple groups of light-emitting units 110 in one pixel unit 100 in a light-emitting substrate, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B in one group of light-emitting units 110 form one light-emitting center, so that multiple light-emitting centers are formed in one pixel unit 100; under the same frame design, compared with the prior scheme of arranging a group of light-emitting units 110 in one pixel unit 100, the original light-emitting center is decomposed into a plurality of light-emitting centers, on one hand, the light-emitting centers are shifted to the edge of the pixel unit 100, so that the distance between two adjacent light-emitting centers positioned at two sides of the seam can be shortened, and the visual seam is reduced, even if the seam is narrowed visually, as shown in fig. 4; on the other hand, the pixel density is also improved, so that the display image quality is finer, and the display effect of the spliced display device and the viewing experience of audiences are improved.

It should be noted that, the steps of MASK process of the light emitting substrate are not added to the plurality of groups of light emitting units 110 in one pixel unit 100, so that the cost of the light emitting substrate or the tiled display panel is not increased significantly.

The light emitting element of the sub-pixel in the light emitting unit 110 may be any one of a light emitting diode (LED, light Emitting Diode), an organic light emitting diode (OLED, organic Light Emitting Diode), a quantum dot light emitting diode (QLED, quantum Dot Light Emitting Diodes), a Mini-LED (sub-millimeter light emitting diode), a Micro-LED (Micro light emitting diode), and the like.

In some embodiments, the group of light emitting units 110 may adopt an RGB arrangement, that is, the group of light emitting units 110 includes one red sub-pixel R, one green sub-pixel G, and one blue sub-pixel B, where the three sub-pixels may adopt a horizontal juxtaposition, a vertical juxtaposition, or a delta arrangement. The group of light emitting units 110 may also adopt an RGBW arrangement scheme, that is, include one red subpixel R, one green subpixel G, one blue subpixel B, and one white subpixel W, where the four subpixels may adopt a horizontal parallel, vertical parallel, or square arrangement, which is not limited in this embodiment. However, the description will be made on the basis of the arrangement of the RGB sub-pixels in a character form unless otherwise specified.

The pixel unit 100, the light emitting unit 110, and the sub-pixels may be defined by the pixel definition layer 20 (Pixel Define Layer, PDL). In some alternative embodiments, referring to fig. 5, the pixel defining layer 20 includes a protrusion 21 and a groove 22, the groove 22 is configured to define a plurality of pixel units 100, and the protrusion 21 is configured to define at least two groups of light emitting units 110 in the pixel units 100. The light emitting unit 110 includes an anode 111, a cathode 113, and a light emitting layer 112 disposed between the anode 111 and the cathode 113. The pixel defining layer 20 has a plurality of openings therein, and the light emitting layer 112 is disposed in the openings. By providing the light emitting layer 112, light of different colors can be emitted upon carrier recombination, thereby forming RGB sub-pixels.

Unlike the scheme in which the pixel units 100 and the light emitting units 110 are defined by the convex pixel definition layer 20, the pixel units 100 are divided by the groove portion 22 of the pixel definition layer 20, which can reduce the occupied space of the pixel definition layer 20, and is beneficial to further improving the pixel density PPI on the light emitting substrate, i.e. more pixel units 100 can be provided or more groups of light emitting units 110 can be defined in one pixel unit 100.

In some alternative embodiments, N is included in one pixel cell 100 ² The group light emitting units 110, N is equal to or greater than 2 and is an integer. Fig. 3 to 5 show a case where one pixel unit 100 includes 4 sets of light emitting units 110, i.e., 4 sets of RGB sub-pixels. The value of N can be specifically determined according to the image quality requirement of the spliced display device and the design specification of the MASK, and the value is usually 2-10, i.e. one pixel unit 100 is provided with4 to 100 groups of RGB light emitting units 110 are provided.

Based on the pixel arrangement scheme provided in the foregoing embodiment, the present disclosure provides two corresponding wiring modes of the pixel driving circuit, which are specifically as follows:

scheme 1: one pixel circuit design for the pixel arrangement scheme shown in fig. 3, one pixel unit 100 includes a first pixel circuit, a second pixel circuit, and a third pixel circuit formed on a substrate base plate; the first pixel circuit is configured to drive all red sub-pixels R within the pixel unit 100 to emit light, the second pixel circuit is configured to drive all green sub-pixels G within the pixel unit 100 to emit light, and the third pixel circuit is configured to drive all blue sub-pixels B within the pixel unit 100 to emit light.

Specifically, the pixel circuit may be configured to supply a driving current to drive the light emitting layer 112 or the light emitting element in the sub-pixel to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor, and for example, a common pixel circuit may be a 3T1C structure, a 4T1C structure, a 7T1C structure, or an 8T1C structure, or the like. Where T denotes a transistor, C denotes a capacitance, a number before T denotes the number of transistors in the pixel circuit, and a number before C denotes the number of capacitances in the pixel circuit.

In scheme 1, 3 pixel circuits are provided in one pixel unit 100, the first pixel circuit drives red sub-pixels R1, R2, R3 and R4 simultaneously, the second pixel circuit drives green sub-pixels G1, G2, G3 and G4 simultaneously, and the third pixel circuit drives blue sub-pixels B1, B2, B3 and B4 simultaneously. By driving all the same-color sub-pixels in one pixel unit by one pixel circuit, the number of pixel circuits can be reduced, so that the wiring density of the pixel circuits is not increased while the light emitting unit 110 is increased.

Optionally, within the pixel cell 100, the anodes 111 of all red sub-pixels R are shorted, the anodes 111 of all green sub-pixels G are shorted, and the anodes 111 of all blue sub-pixels B are shorted. By shorting the anodes 111 of the same color sub-pixels, the uniformity of the current signals driving the pixels can be improved.

Fig. 6A to 6I show schematic circuit layouts of pixel driving circuits of scheme 1 formed in one pixel unit 100, including a polycrystalline layer (Poly), a first scan line layer (Gate 1), a second scan line layer (Gate 2), a first data line layer (SD 1), a first passivation layer (PVX 1), a first planarization layer (PLN 1), a second data line layer (SD 2), and a second planarization layer (PLN 2) sequentially formed on a substrate, and then Anode layers (inode) of respective sub-pixels connected to the pixel driving circuits are formed as shown in fig. 6J.

Fig. 7 shows an equivalent circuit schematic diagram of an alternative first pixel circuit for driving red sub-pixels R1, R2, R3 and R4, comprising a first transistor T1, a second transistor T2, six third transistors T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1;

six third transistors T3 are connected in parallel to form a driving transistor group;

the control electrode of the driving transistor group, the negative electrode of the first capacitor C1, the first electrode of the fourth transistor T4 and the first electrode of the seventh transistor T7 are coupled to the first node N1;

the second pole of the first transistor T1, the first pole of the fifth transistor T5 and the first pole of the set of driving transistors are coupled to the second node N2;

the second pole of the driving transistor group, the first pole of the second transistor T2 and the second pole of the fourth transistor T4 are coupled to the third node N3;

the second pole of the second transistor T2, the first pole of the sixth transistor T6 and the anodes of all red sub-pixels R1, R2, R3, R4 are coupled to the fourth node N4;

the control electrode of the first transistor T1 is connected with a light-emitting control line, and the first electrode is connected with a first power line;

the control electrode of the second transistor T2 is connected with a light-emitting control line;

the control electrode of the fourth transistor T4 is connected with the scanning line;

the control electrode of the fifth transistor T5 is connected with the scanning line, and the second electrode is connected with the data line;

a control electrode of the sixth transistor T6 is connected with a second reset control line, and the second electrode is connected with an initialization signal line;

a second electrode of the seventh transistor T7 is connected with an initialization signal line, and a control electrode of the seventh transistor T7 is connected with a first reset control line;

the anode of the first capacitor C1 is connected with a first power line;

the cathodes of all the red sub-pixels R1, R2, R3, R4 are connected to the second power line.

Wherein the first power supply line is configured to supply a constant first voltage signal VDD to the first pixel circuit, the second power supply line is configured to supply a constant second voltage signal VSS to the first pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line is configured to supply a scan signal Gate to the first pixel circuit. The Data line Data is configured to supply a Data signal Vdata to the first pixel circuit. The emission control line is configured to supply an emission control signal EM to the first pixel circuit. The first RESET control line is configured to supply a first RESET control signal RESET1 to the first pixel circuit, and the second RESET control line is configured to supply a second RESET control signal RESET2 to the first pixel circuit. The initialization signal line is configured to supply an initialization signal Vinit to the first pixel circuit.

In the first pixel circuit in this scheme, six third transistors T3 are connected in parallel to form a driving transistor group as a driving sub-circuit for driving the red sub-pixel R, so that stability and consistency of driving current signal output can be ensured, so as to solve the problem that the display area of the tiled display device is not uniform or poor in consistency due to a large-size display area, which is easily generated when a plurality of sub-pixels with the same color are driven by one pixel circuit.

Scheme 2: another pixel circuit design for the pixel arrangement shown in fig. 3, a group of light emitting units 110 includes 2 fourth pixel circuits, 2 fifth pixel circuits, and 2 sixth pixel circuits; the 2 fourth pixel circuits are configured to drive one red sub-pixel R to emit light, the 2 fifth pixel circuits are configured to drive one green sub-pixel G to emit light, and the 2 sixth pixel circuits drive one blue sub-pixel B to emit light.

Specifically, one pixel unit 100 in fig. 3 includes 4 sets of light emitting units 110, and thus four pixel circuit islands each for driving one set of light emitting units 110 are formed in one pixel unit 100, each pixel circuit island including 6 pixel circuits: 2 fourth pixel circuits drive one red sub-pixel R,2 fifth pixel circuits drive one green sub-pixel G, and 2 sixth pixel circuits drive one blue sub-pixel B, so that 24 pixel circuits are provided in total in one pixel unit 100. Alternatively, the fourth pixel circuit, the fifth pixel circuit, and the sixth pixel circuit may adopt the same circuit configuration.

Fig. 8A to 8I show schematic circuit layouts of four pixel circuit islands of scheme 2 formed in one pixel unit 100, including a polycrystalline layer (Poly), a first scan line layer (Gate 1), a second scan line layer (Gate 2), an interlayer Insulating Layer (ILD), a first data line layer (SD 1), a first passivation layer (PVX 1), a first planarization layer (PLN 1), a second data line layer (SD 2), and a second planarization layer (PLN 2) sequentially formed on a substrate, and then an Anode layer (Anode) of each sub-pixel connected to a pixel driving circuit is formed as shown in fig. 8J.

Taking the fourth pixel circuit for driving the red sub-pixel R1 as an example, please refer to the equivalent circuit diagram of fig. 9, a fourth pixel circuit 70 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a second capacitance C2;

the negative electrode of the second capacitor C2, the first electrode of the eleventh transistor T11, the first electrode of the fourteenth transistor T14 and the control electrode of the tenth transistor T10 are coupled to the fifth node N5;

the second pole of the eighth transistor T8, the first pole of the tenth transistor T10 and the first pole of the twelfth transistor T12 are coupled to the sixth node N6;

the first pole of the ninth transistor T9, the second pole of the tenth transistor T10 and the second pole of the eleventh transistor T11 are coupled to the seventh node N7;

the second pole of the ninth transistor T9, the first pole of the thirteenth transistor T13 and the anode of the red subpixel R are coupled to the eighth node N8;

the control electrode of the eighth transistor T8 is connected with the light-emitting control line, and the first electrode is connected with the first power line;

a control electrode of the ninth transistor T9 is connected with a light-emitting control line;

the control electrode of the eleventh transistor T11 is connected with the scanning line;

a control electrode of the twelfth transistor T12 is connected with the scanning line, and a second electrode is connected with the data line;

a control electrode of the thirteenth transistor T13 is connected with a second reset control line, and the second electrode is connected with an initialization signal line;

the fourteenth transistor T14 has a second electrode connected to the initialization signal line and a control electrode connected to the first reset control line.

Wherein the first power line is configured to supply a constant first voltage signal VDD to the fourth pixel circuit, the second power line is configured to supply a constant second voltage signal VSS to the fourth pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line is configured to supply a scan signal Gate to the fourth pixel circuit. The Data line Data is configured to supply a Data signal Vdata to the fourth pixel circuit. The emission control line is configured to supply an emission control signal EM to the fourth pixel circuit. The first RESET control line is configured to supply a first RESET control signal RESET1 to the fourth pixel circuit, and the second RESET control line is configured to supply a second RESET control signal RESET2 to the fourth pixel circuit. The initialization signal line is configured to supply an initialization signal Vinit to the fourth pixel circuit.

The scheme 2 adopts the scheme that two pixel circuits jointly drive one sub-pixel, so that the stability and consistency of driving current output signals can be improved, and the problem that the driving current signals in a display area of the spliced display device are not uniform or poor in consistency due to the large-size display area is solved.

Alternatively, taking the red sub-pixel R as an example, in one pixel unit 100, the anodes 111 of all the red sub-pixels R are shorted, the anodes 111 of all the green sub-pixels G are shorted, and the anodes 111 of all the blue sub-pixels B are shorted.

Optionally, all signal lines connected to the red subpixel R include: the scan line, the first reset control line, the second reset control line, the initialization signal line, and the light emission control line are respectively shorted, and the shorted positions may be two ends of the signal line in the first direction of the pixel unit 100. Alternatively, the data line within the pixel unit 100 is shorted, and the shorted position may be the second end of the data line in the second direction.

In the pixel unit 100, a plurality of gate lines (e.g., a scan line, a reset control line, a light emission control line, and an initialization signal line) are arranged and extended in a first direction, and a plurality of data lines and power lines are arranged and extended in a second direction. The first direction and the second direction may lie in the same plane, and the first direction intersects and is perpendicular to the second direction. For example, the first direction may be a horizontal direction X of the pixel unit 100, and the second direction may be a vertical direction Y of the pixel unit 100. Therefore, as shown in fig. 8, the gate lines of all red sub-pixels R arranged in the lateral direction may be shorted on both left and right sides of the entire pixel unit 100, and the data lines arranged in the longitudinal direction may be shorted directly under the pixel unit 100.

By shorting the anodes 111 of all red sub-pixels R, shorting the anodes 111 of all blue sub-pixels B and all green sub-pixels G, respectively, and shorting the gate lines and the data lines of all red sub-pixels R, the stability and consistency of the driving current signals in the pixel unit 100 when driving one sub-pixel using two pixel circuits can be further improved, thereby further improving the display effect.

Alternatively, the transistors used in the pixel circuits of the schemes 1 and 2 may be the polymer thin film transistors PTFT. For a thin film transistor, the gate electrode of the extremely thin film transistor is controlled, one of the source electrode and the drain electrode of the first extremely thin film transistor is controlled, and the second electrode is the other of the source electrode and the drain electrode. Since the source and drain electrodes of the thin film transistor may be symmetrical in structure, the source and drain electrodes may be indistinguishable in structure. For example, when the thin film transistor is a P-type transistor, the first electrode is a source electrode and the second electrode is a drain electrode; when the thin film transistor is an N-type transistor, the first electrode is a drain electrode and the second electrode is a source electrode.

In a second aspect, based on the same inventive concept, in another alternative embodiment, a tiled display device is provided, including the tiled display panel provided by the embodiment of the first aspect. The spliced display panel is formed by splicing a plurality of display panels. The display panel can be cut into common 46 inch, 55 inch, 65 inch and 75 inch, and can be adjusted according to product requirements, such as 10cm×10cm display panel. A display panel can be used as display equipment alone or can be spliced into an oversized display screen for use. The number and the manner of the tiled display panels may be specifically determined according to the required display area of the tiled display device and the manufacturing size of the tiled display panels, which is not specifically limited herein.

The advantages of the tiled display device provided by the embodiment of the second aspect are the same as those of the tiled display panel provided by the embodiment of the first aspect, and will not be described here again.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (10)

1. The spliced display panel is characterized by comprising a plurality of spliced light-emitting substrates, wherein each light-emitting substrate comprises a substrate and a pixel definition layer arranged on the substrate, the pixel definition layer is used for defining a plurality of pixel units and at least two groups of light-emitting units positioned in one pixel unit, and one group of light-emitting units comprises at least one red sub-pixel, at least one green sub-pixel and at least one blue sub-pixel; and a seam is arranged between the adjacent light-emitting substrates, and at least two pixel units are positioned on two sides of the seam.

2. The tiled display panel according to claim 1, wherein the pixel defining layer includes a raised portion and a recessed portion, the recessed portion for defining the plurality of pixel elements, the raised portion for defining the at least two sets of light emitting elements in the pixel elements.

3. The tiled display panel according to claim 1, wherein one of the pixel elements includes N ² And the group light-emitting units are arranged, wherein N is more than or equal to 2 and is an integer.

4. The tiled display panel according to claim 1, wherein one of the pixel elements includes a first pixel circuit, a second pixel circuit, and a third pixel circuit;

the first pixel circuit is configured to drive all red sub-pixels in the pixel unit to emit light, the second pixel circuit is configured to drive all green sub-pixels in the pixel unit to emit light, and the third pixel circuit is configured to drive all blue sub-pixels in the pixel unit to emit light.

5. The tiled display panel according to claim 4, wherein the light emitting unit includes an anode, a cathode, and a light emitting layer disposed between the anode and the cathode;

and in the pixel unit, the anodes of all red sub-pixels are shorted, the anodes of all green sub-pixels are shorted, and the anodes of all blue sub-pixels are shorted.

6. The tiled display panel according to claim 4, wherein the first pixel circuit includes a first transistor, a second transistor, six third transistors, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor;

the six third transistors are connected in parallel to form a driving transistor group;

a control electrode of the driving transistor group, a negative electrode of the first capacitor, a first electrode of the fourth transistor, and a first electrode of the seventh transistor are coupled to a first node;

a second pole of the first transistor, a first pole of the fifth transistor, and a first pole of the set of drive transistors are coupled to a second node;

a second pole of the set of drive transistors, a first pole of the second transistor, and a second pole of the fourth transistor are coupled to a third node;

the second pole of the second transistor, the first pole of the sixth transistor, and the anodes of all red subpixels are coupled to a fourth node;

the control electrode of the first transistor is connected with a light-emitting control line, and the first electrode of the first transistor is connected with a first power line;

the control electrode of the second transistor is connected with the light-emitting control line;

the control electrode of the fourth transistor is connected with the scanning line;

the control electrode of the fifth transistor is connected with the scanning line, and the second electrode is connected with the data line;

the control electrode of the sixth transistor is connected with a second reset control line, and the second electrode is connected with an initialization signal line;

a second electrode of the seventh transistor is connected with the initialization signal line, and a control electrode of the seventh transistor is connected with a first reset control line;

the positive electrode of the first capacitor is connected with a first power line;

the cathodes of all the red sub-pixels are connected with a second power line.

7. The tiled display panel according to claim 1, wherein a set of said light-emitting cells includes 2 fourth pixel circuits, 2 fifth pixel circuits and 2 sixth pixel circuits;

the 2 fourth pixel circuits are configured to drive one red sub-pixel to emit light, the 2 fifth pixel circuits are configured to drive one green sub-pixel to emit light, and the 2 sixth pixel circuits drive one blue sub-pixel to emit light.

8. The tiled display panel according to claim 7, wherein the fourth pixel circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second capacitor;

a negative electrode of the second capacitor, a first electrode of the eleventh transistor, a first electrode of the fourteenth transistor, and a control electrode of the tenth transistor are coupled to a fifth node;

a second pole of the eighth transistor, a first pole of the tenth transistor, and a first pole of the twelfth transistor are coupled to a sixth node;

a first pole of the ninth transistor, a second pole of the tenth transistor, and a second pole of the eleventh transistor are coupled to a seventh node;

a second pole of the ninth transistor, a first pole of the thirteenth transistor, and an anode of the red subpixel are coupled to an eighth node;

the control electrode of the eighth transistor is connected with a light-emitting control line, and the first electrode is connected with a first power line;

a control electrode of the ninth transistor is connected with a light-emitting control line;

a control electrode of the eleventh transistor is connected with the scanning line;

the control electrode of the twelfth transistor is connected with the scanning line, and the second electrode is connected with the data line;

a control electrode of the thirteenth transistor is connected with a second reset control line, and the second electrode is connected with an initialization signal line;

a second pole of the fourteenth transistor is connected with the initialization signal line, and a control pole of the fourteenth transistor is connected with a first reset control line.

9. The tiled display panel according to claim 8, wherein in the pixel unit, the scan line, the first reset control line, the second reset control line, the initialization signal line, and the light emission control line connected to the red subpixel are shorted, respectively; and the data line positioned in the pixel unit is short-circuited.

10. A tiled display device, characterized in that it comprises a tiled display panel according to any of claims 1-9.