CN116528459A - Multilayer PCB and detection method thereof - Google Patents

Multilayer PCB and detection method thereof Download PDF

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Publication number
CN116528459A
CN116528459A CN202310424301.6A CN202310424301A CN116528459A CN 116528459 A CN116528459 A CN 116528459A CN 202310424301 A CN202310424301 A CN 202310424301A CN 116528459 A CN116528459 A CN 116528459A
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CN
China
Prior art keywords
layers
capacitor
layer
pcb
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310424301.6A
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Chinese (zh)
Inventor
王忠缪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Heshan Zhongfu Xingye Circuit Co ltd
Original Assignee
Heshan Zhongfu Xingye Circuit Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Heshan Zhongfu Xingye Circuit Co ltd filed Critical Heshan Zhongfu Xingye Circuit Co ltd
Priority to CN202310424301.6A priority Critical patent/CN116528459A/en
Publication of CN116528459A publication Critical patent/CN116528459A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits

Abstract

The invention discloses a multilayer PCB and a detection method thereof, wherein the multilayer PCB comprises: the electric layer comprises a base material and two circuit layers, the two circuit layers are symmetrically arranged on two sides of the base material, and the two circuit layers are electrically connected with the electric element; an adhesive layer for adhering two adjacent electrical layers; the electric layers are provided with a plurality of layers, two adjacent electric layers are adhered through the adhesive layer, the adhesive layer and the two adjacent circuit layers are matched to form a capacitor, and the stacking sequence of the electric layers can be detected through the capacitance value of the capacitor. The stacking sequence of the electric layers is detected by measuring the capacitance value of the capacitor, so that the stacking sequence of the multi-layer PCB can be detected in an electric measurement mode by the multi-layer PCB, and then manual visual detection can be replaced, and the detection efficiency of the multi-layer PCB is improved.

Description

Multilayer PCB and detection method thereof
Technical Field
The invention relates to the technical field of PCB manufacturing, in particular to a multilayer PCB and a detection method thereof.
Background
The existing multilayer PCB manufacturing process mainly comprises the steps of manually assembling and superposing the PCB, but the PCB is not easy to distinguish, so that the problems of disordered laminating sequence, multilayer missing and the like of the manually superposed multilayer PCB are caused easily, the conventional multilayer PCB mainly depends on manual visual detection, but the detection mode is high in labor intensity, inaccurate in detection, easy to cause missing detection or wrong detection, and the production efficiency of the multilayer PCB is reduced.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, the invention provides the multilayer PCB, the lamination sequence of the multilayer PCB can be detected by an electrical measurement mode, the multilayer PCB with wrong lamination can be conveniently distinguished, and the production efficiency of the multilayer PCB is improved.
According to a first aspect of an embodiment of the present invention, there is provided a multi-layer PCB board, comprising: the electric layer comprises a base material and two circuit layers, the two circuit layers are symmetrically arranged on two sides of the base material, and the two circuit layers are electrically connected with the electric element; an adhesive layer for adhering two adjacent electrical layers; the electric layers are provided with a plurality of layers, two adjacent electric layers are adhered through the adhesive layer, the adhesive layer and the two adjacent circuit layers are matched to form a capacitor, and the stacking sequence of the electric layers can be detected through the capacitance value of the capacitor.
The multilayer PCB provided by the embodiment of the invention has at least the following beneficial effects: adjacent two electrical layers are adhered through the adhesive layer, so that the electrical layers and the adhesive layers are alternately arranged to form a multilayer PCB, the adhesive layers and the adjacent two circuit layers form a capacitor, the distance between the electrical layers can be detected through measuring the capacitance value of the capacitor, the multilayer PCB can detect the multilayer PCB with wrong lamination through an electrical measurement mode, manual visual detection is replaced, and the production efficiency of the multilayer PCB is improved.
According to some embodiments of the invention, blind holes are connected to two sides of the capacitor, the inner walls of the blind holes are covered with a first metal layer, and the blind holes are respectively communicated with two ends of the capacitor through the first metal layer.
According to some embodiments of the invention, the outer surface of the multilayer PCB board is covered with a second metal layer, which is electrically connected to the first metal layer.
According to some embodiments of the invention, the second metal layer is provided with a plurality of isolation trenches for separating the second metal layer.
According to a second aspect of the embodiment of the present invention, there is provided a method for detecting a multi-layer PCB board, including the steps of:
s100, obtaining the capacitance value of the capacitor of the PCB in the correct lamination, and recording the capacitance value as first data;
s200, acquiring the capacitance value of the capacitor of the tested multilayer PCB, and recording the capacitance value as second data;
s300, obtaining a difference value between the first data and the second data, and recording the difference value as third data;
and S400, comparing the third data with a threshold value to detect the lamination sequence of the electrical layers.
The detection method of the multilayer PCB provided by the embodiment of the invention has at least the following beneficial effects: firstly, measuring the capacitance value of the capacitance of the correctly laminated PCB, recording the capacitance value as first data, then measuring the capacitance value of the capacitance of the tested PCB, recording the capacitance value as second data, obtaining the difference value of the capacitance value and the second data according to the second data and the first data, recording the difference value as third data, and judging the lamination sequence of the multi-layer PCB of the power supply layer by comparing the third data with a threshold value. The lamination sequence of the electric layers can be detected in an electric measurement mode, so that manual visual detection is replaced, and the detection efficiency of the multilayer PCB is improved.
According to some embodiments of the invention, the step S100 includes the steps of:
s110, respectively placing a high-level interface and a low-level interface of the digital bridge on two sides of the capacitor to obtain the capacitance value of the capacitor.
According to some embodiments of the invention, the PCB board is properly stacked when the third data is less than the threshold.
According to some embodiments of the invention, the third data is an error stack PCB when the third data is greater than the threshold.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic view of a multilayer PCB board according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another multi-layer PCB board according to an embodiment of the present invention;
fig. 3 is a schematic block diagram of a method for detecting a multi-layer PCB board according to an embodiment of the present invention;
fig. 4 is a schematic block diagram of step S110 of the method for inspecting a multi-layer PCB according to an embodiment of the present invention.
Reference numerals illustrate:
an electrical layer 100, a substrate 110, a wiring layer 120;
an adhesive layer 200;
a capacitor 300, a first detection layer 310, a second detection layer 320, a blind via 330, a first metal layer 340;
a second metal layer 400, and isolation trenches 410.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
With reference to fig. 1 and fig. 2, it may be understood that the multi-layer PCB board according to the first aspect of the present invention includes: the electric layer 100 comprises a base material 110 and two circuit layers 120, wherein the two circuit layers 120 are symmetrically arranged on two sides of the base material 110, and the two circuit layers 120 are electrically connected with the electric element; an adhesive layer 200, the adhesive layer 200 being used to adhere two adjacent electrical layers 100; wherein, the electrical layers 100 are provided with a plurality of, two adjacent electrical layers 100 are adhered by the adhesive layer 200, the adhesive layer 200 and two adjacent circuit layers 120 are matched to form the capacitor 300, and the stacking sequence of the electrical layers 100 can be detected by the capacitance value of the capacitor 300.
Two adjacent electrical layers 100 are adhered to two sides through the adhesive layer 200, the electrical layers 100 and the adhesive layer 200 are alternately arranged to form a multi-layer PCB, the adhesive layer 200 and two adjacent circuit layers 120 are matched to form a capacitor 300, the capacitance values at two ends of the capacitor 300 can reflect the lamination sequence of the multi-layer PCB, the multi-layer PCB can detect the spacing between the electrical layers 100 by measuring the capacitance value of the capacitor 300, the multi-layer PCB can detect the multi-layer PCB with wrong lamination through an electrical measurement mode, and then the multi-layer PCB can replace manual visual detection, so that the use performance of the PCB is prevented from being influenced by the lamination errors of the multi-layer PCB, and the production efficiency and the yield of the multi-layer PCB are improved.
It should be noted that, two ends of the capacitor 300 are formed on two adjacent circuit layers 120 of the adhesive layer 200, so that the first detection layer 310 and the second detection layer 320 of the capacitor 300 are formed on two adjacent circuit layers 120 of the adhesive layer 200, the first detection layer 310 and the second detection layer 320 are separated by the adhesive layer 200, and the first detection layer 310, the adhesive layer 200 and the second detection layer 320 are sequentially arranged to form the capacitor 300, so that the lamination sequence of the multi-layer PCB board can be detected by measuring the capacitance value of the capacitor 300, and the detection efficiency of the multi-layer PCB board is improved.
When the stacking order of the multi-layered PCB is wrong, the number of the adhesive layer 200 and the electrical layer 100 disposed between the first and second test layers 310 and 320 is changed, so that the interval between the first and second test layers 310 and 320 is changed, thereby changing the capacitance value of the capacitor 300, and further, the stacking order of the multi-layered PCB can be detected by measuring the capacitance value between the first and second test layers 310 and 320.
When the multi-layer PCB has multiple layers or lacks layers, the number of the first detection layer 310 and the second detection layer 320 is abnormal, so that the capacitance of the capacitor 300 cannot be measured, and the multi-layer PCB with wrong lamination can be detected.
In addition, when the PCB boards are stacked upside down, the facing areas of the first detecting layer 310 and the second detecting layer 320 are reduced, so that the capacitance of the capacitor 300 is reduced, and the multilayer PCB boards with incorrect stacking direction can be detected.
Specifically, referring to fig. 1, blind holes 330 are connected to two sides of the capacitor 300, the inner walls of the blind holes 330 are covered with a first metal layer 340, and the blind holes 330 respectively conduct two ends of the capacitor 300 through the first metal layer 340. Blind holes 330 are formed in two symmetrical sides of the multilayer PCB, the side walls of the blind holes 330 are covered with first metal layers 340, and the first detection layers 310 and the second detection layers 320 are respectively conducted through the first metal layers 340, so that the capacitance value of the capacitor 300 is conveniently measured through the first metal layers 340.
It should be noted that, the closed end of the blind hole 330 is connected to the first detection layer 310 or the second detection layer 320, so that the blind hole 330 is prevented from penetrating into the adhesive layer 200 and the electrical layer 100 between the first detection layer 310 and the second detection layer 320, and the first detection layer 310 and the second detection layer 320 are kept electrically isolated, so that the blind hole 330 can be connected to the first detection layer 310 and the second detection layer 320 respectively through the open end of the blind hole 330, so as to measure the capacitance value of the capacitor 300.
Specifically, referring to fig. 1, the outer surface of the multi-layer PCB board is covered with a second metal layer 400, and the second metal layer 400 is electrically connected with the first metal layer 340. The second metal layer 400 covers the outer surface of the multi-layer PCB board and is in communication with the first metal layer 340, so that the first detection layer 310 and the second detection layer 320 can be conducted through the second metal layer 400, so that the capacitance value of the capacitor 300 can be directly measured through the second detection layer 400.
Specifically, referring to fig. 1, the second metal layer 400 is provided with a plurality of isolation trenches 410, and the isolation trenches 410 are used to separate the second metal layer 400. The second metal layer 400 is separated into a plurality of parts electrically isolated from each other by the isolation groove 410, so that one capacitor 300 can correspond to one part of the second metal layer 400, so that the second metal layer 400 is divided into a plurality of detection parts to respectively correspond to a plurality of capacitors 300, mutual interference among the plurality of capacitors 300 is prevented, and the detection precision of the multilayer PCB is improved.
It can be understood that referring to fig. 1 to 3, the method for detecting a multi-layer PCB board according to the second aspect of the embodiment of the present invention includes the following steps:
s100, obtaining the capacitance value of a capacitor 300 of a correctly laminated PCB and recording the capacitance value as first data;
s200, obtaining the capacitance value of the capacitor 300 of the tested multilayer PCB, and recording the capacitance value as second data;
s300, obtaining a difference value between the first data and the second data, and recording the difference value as third data;
and S400, comparing the third data with the threshold value to detect the lamination sequence of the electric layer 100.
Firstly, the capacitance value of the capacitor 300 of the correct laminated PCB is measured and recorded as first data, then the capacitance value of the capacitor 300 of the tested PCB is measured and recorded as second data, the difference value of the second data and the first data is obtained according to the second data and recorded as third data, and the size of the threshold value is set, so that the lamination sequence of the multilayer PCB can be detected by comparing the size of the third data with the size of the threshold value, the lamination sequence of the electric layer 100 can be detected by the third data and the threshold value, manual visual detection is replaced, the multilayer PCB is prevented from being mistakenly detected or missed, and the detection efficiency and the detection precision of the multilayer PCB are improved.
It should be noted that, in order to prevent the multi-layer PCB from being misjudged, the size of the threshold value may be specifically set according to the actual requirement, so as to adapt to the PCBs of different specifications, expand the application range of the detection method of the multi-layer PCB, and improve the detection precision.
Specifically, referring to fig. 1 and 4, in step S110, a high-level interface and a low-level interface of the digital bridge are respectively disposed at two ends of the capacitor 300 to obtain a capacitance value of the capacitor 300. The capacitance values of the two ends of the capacitor 300 are directly measured through the digital bridge, so that the capacitance value of the capacitor 300 can be quickly obtained, and the detection efficiency of the multilayer PCB is improved.
It should be noted that, the capacitance value of the capacitor 300 of the PCB board to be correctly stacked can be obtained through the digital bridge, and the capacitance value of the capacitor 300 of the PCB board to be tested can also be obtained, so as to directly measure the capacitance value of the capacitor 300. The digital bridge in the above embodiment may be replaced by a multimeter, and the capacitance of the capacitor 300 may be measured by the capacitance file of the multimeter, so as to obtain the capacitance of the capacitor 300, and improve the detection efficiency of the multilayer PCB board.
Specifically, referring to fig. 1 and 2, when the third data is smaller than the threshold value, the PCB board is properly stacked. When the stacking sequence of the electrical layers 100 is correct, the capacitance value of the capacitor 300 can be maintained within the tolerance range, so that the difference value between the second data and the first data is kept within the tolerance range, and the third data is smaller than the threshold value, thereby determining that the multi-layer PCB board is a correct stacked PCB board.
It should be noted that, due to the errors in the thickness and density of the electrical layer 100 and the adhesive layer 200, the capacitance value of the capacitor 300 floats slightly within the tolerance range, and the floating error of the capacitance value is filtered by setting a threshold value, so that the multi-layer PCB board can detect the stacking sequence of the electrical layer 100 through the capacitance value of the capacitor 300.
Specifically, referring to fig. 1 and 2, when the third data is smaller than the threshold value, the PCB board is properly stacked. When the stacking sequence of the electrical layers 100 is wrong, the capacitance value of the capacitor 300 is changed, so that the capacitance value of the capacitor 300 is doubled or reduced, the difference between the second data and the first data is increased, the third data is increased, and the third data is further greater than the threshold value, so that the tested multilayer PCB is judged to be the wrong stacked PCB.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention.

Claims (8)

1. Multilayer PCB board, its characterized in that includes:
the electric layer comprises a base material and two circuit layers, the two circuit layers are symmetrically arranged on two sides of the base material, and the two circuit layers are electrically connected with the electric element;
an adhesive layer for adhering two adjacent electrical layers;
the electric layers are provided with a plurality of layers, two adjacent electric layers are adhered through the adhesive layers, the adhesive layers and the two adjacent circuit layers are matched to form a capacitor, and the stacking sequence of the electric layers can be detected through the capacitance value of the capacitor.
2. The multilayer PCB of claim 1, wherein blind holes are connected to both sides of the capacitor, the inner walls of the blind holes are covered with a first metal layer, and the blind holes are respectively connected to both ends of the capacitor through the first metal layer.
3. The multilayer PCB of claim 2, wherein an outer surface of the multilayer PCB is covered with a second metal layer, the second metal layer being electrically connected to the first metal layer.
4. A multi-layer PCB board according to claim 3, wherein the second metal layer is provided with a plurality of isolation trenches for separating the second metal layer.
5. The method for detecting the multilayer PCB board, which comprises any one of the claims 1 to 4, is characterized by comprising the following steps:
s100, obtaining the capacitance value of the capacitor of the PCB in the correct lamination, and recording the capacitance value as first data;
s200, acquiring the capacitance value of the capacitor of the tested multilayer PCB, and recording the capacitance value as second data;
s300, obtaining a difference value between the first data and the second data, and recording the difference value as third data;
and S400, comparing the third data with a threshold value to detect the lamination sequence of the electrical layers.
6. The method for inspecting a multi-layer PCB according to claim 5, wherein the step S100 includes the steps of:
s110, respectively placing a high-level interface and a low-level interface of the digital bridge at two ends of the capacitor to obtain the capacitance value of the capacitor.
7. The method of claim 5, wherein when the third data is less than the threshold, the PCB is properly stacked.
8. The method of claim 5, wherein the third data is an erroneous stacked PCB when the third data is greater than the threshold.
CN202310424301.6A 2023-04-19 2023-04-19 Multilayer PCB and detection method thereof Pending CN116528459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310424301.6A CN116528459A (en) 2023-04-19 2023-04-19 Multilayer PCB and detection method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310424301.6A CN116528459A (en) 2023-04-19 2023-04-19 Multilayer PCB and detection method thereof

Publications (1)

Publication Number Publication Date
CN116528459A true CN116528459A (en) 2023-08-01

Family

ID=87407563

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310424301.6A Pending CN116528459A (en) 2023-04-19 2023-04-19 Multilayer PCB and detection method thereof

Country Status (1)

Country Link
CN (1) CN116528459A (en)

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