CN116525384A - Method for preparing horizontal nano air channel transistor based on sacrificial layer - Google Patents
Method for preparing horizontal nano air channel transistor based on sacrificial layer Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 77
- 238000000151 deposition Methods 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002360 preparation method Methods 0.000 claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 208
- 229910052751 metal Inorganic materials 0.000 claims description 55
- 239000002184 metal Substances 0.000 claims description 55
- 238000005530 etching Methods 0.000 claims description 40
- 238000001039 wet etching Methods 0.000 claims description 40
- 238000001259 photo etching Methods 0.000 claims description 20
- 239000003960 organic solvent Substances 0.000 claims description 13
- 238000005260 corrosion Methods 0.000 claims description 11
- 230000007797 corrosion Effects 0.000 claims description 11
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims description 4
- 229910052752 metalloid Inorganic materials 0.000 claims description 3
- 150000002738 metalloids Chemical class 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 2
- 238000003491 array Methods 0.000 abstract description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 229910052804 chromium Inorganic materials 0.000 description 8
- 239000011651 chromium Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 239000007787 solid Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000002090 nanochannel Substances 0.000 description 2
- 230000036632 reaction speed Effects 0.000 description 2
- -1 TiN Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002120 nanofilm Substances 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000002077 nanosphere Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J31/00—Cathode ray tubes; Electron beam tubes
- H01J31/02—Cathode ray tubes; Electron beam tubes having one or more output electrodes which may be impacted selectively by the ray or beam, and onto, from, or over which the ray or beam may be deflected or de-focused
- H01J31/04—Cathode ray tubes; Electron beam tubes having one or more output electrodes which may be impacted selectively by the ray or beam, and onto, from, or over which the ray or beam may be deflected or de-focused with only one or two output electrodes with only two electrically independant groups or electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J31/00—Cathode ray tubes; Electron beam tubes
- H01J31/02—Cathode ray tubes; Electron beam tubes having one or more output electrodes which may be impacted selectively by the ray or beam, and onto, from, or over which the ray or beam may be deflected or de-focused
- H01J31/06—Cathode ray tubes; Electron beam tubes having one or more output electrodes which may be impacted selectively by the ray or beam, and onto, from, or over which the ray or beam may be deflected or de-focused with more than two output electrodes, e.g. for multiple switching or counting
Abstract
The invention provides a method for preparing a horizontal nano air channel transistor based on a sacrificial layer, and belongs to the technical field of semiconductor transistors. Firstly, depositing a conductive film and a sacrificial layer film on an insulating substrate in sequence; forming a photoresist-sacrificial layer pattern; then removing part of the sacrificial layer film laterally to suspend the edge of the photoresist; depositing a mask film to form a horizontal nanometer air channel; and finally, stripping the redundant part, and leaving the electrode to finish the preparation of the horizontal nano air channel diode. The method can realize the control precision of the horizontal nanometer air channel size reaching the nanometer level by controlling the lateral removal depth of the sacrificial layer; meanwhile, the method has the advantages of low cost, simplicity, easiness in implementation, complete compatibility with a semiconductor process, good repeatability, stability and consistency, suitability for mass production of large-area wafer-level nanometer air channel transistor arrays and real practicability.
Description
Technical Field
The invention belongs to the technical field of semiconductor transistors, and particularly relates to a method for preparing a horizontal nano air channel transistor based on a sacrificial layer.
Background
Vacuum is an ideal medium for high-speed ballistic transport of electrons. Electrons can move in vacuum at almost the speed of light, which is 3 orders of magnitude higher than the transmission speed of a semiconductor medium, so that the limitations of diffusion of a solid gate and carrier transmission speed are solved to a great extent, the reaction speed and the working frequency of a semiconductor transistor are further improved, and certain advantages exist in the aspects of heat dissipation and power consumption. In recent years, a nano air channel transistor combines the advantages of vacuum electrons and semiconductor electrons, and reduces the distances among a cathode, an anode or a source electrode, a drain electrode and a gate electrode on a nano scale, thereby reducing the size of an electron transmission channel to be lower than the average free path in air, and realizing ballistic transmission of electrons in the air. Compared with a semiconductor transistor, the nano air channel transistor has the great advantages of miniaturization, high integration, mass production and the like. Because the channel size is greatly reduced, the semiconductor micro-nano structure can work under low voltage and can be processed and manufactured by the semiconductor micro-nano technology. Unlike conventional semiconductors, solid lattice scattering does not affect the electron transport process of the device. The reaction speed and operating frequency can be much higher than those of semiconductor transistors at the same channel size area as the device. The device can work under the ultra-high frequency band of millimeter waves, terahertz and even beat hertz frequency, and has the advantages of low heat, low power consumption, radiation resistance, high temperature resistance, low temperature resistance and the like. Thus, future nano-air channel transistors are most likely to be the next revolutionary and subversion of the existing vacuum transistors and solid semiconductor transistors.
Currently, most reported nano-air channel transistors are typically fabricated and manufactured by fine nano-processes, such as electron beam lithography and focused ion beam etching. On the one hand, these processes are based on expensive nanofabrication devices, and on the other hand, they have low yields during the process, poor reproducibility and are not suitable for mass production. In recent years, new methods of fabricating nano-air channel transistors have been reported. For example, the invention patent of publication number CN112103158A proposes a method of manufacturing an air nano-channel vertical diode by selectively etching a nano-film. However, this method is only applicable to processing devices with vertical nano-air channel structures, and is not applicable to horizontal nano-air channel transistors with smaller capacitance and larger bandwidth. The invention patent of publication number CN 112951916a proposes a nano-air channel transistor based on a sidewall process and a method for preparing the same, which can be used for processing a transistor with a horizontal nano-air channel structure, however, the Chemical Mechanical Polishing (CMP) process required for the process is greatly affected by wafer warpage, and has limited control precision, so that it is difficult to prepare a uniform device array on a large-area wafer. There are also some documents reporting that the self-assembled micro-nano-sphere mask or metal fracture to produce gap and other semiconductor process incompatible process methods are adopted to prepare the horizontal nano-air channel structure transistor. In general, a large-area wafer-level manufacturing process method truly suitable for a horizontal nano-air channel transistor is still a bottleneck problem, so that a method with the processing precision reaching the nano-level and suitable for mass production on a large-area wafer is urgently needed to reduce the manufacturing cost of the nano-channel transistor and put into practical use in production.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a method for preparing a horizontal nano air channel transistor based on a sacrificial layer, which aims to provide a method for preparing nano air channel transistors on a large-area wafer in batches, wherein the channel processing precision can reach the nano level, the method is completely compatible with a semiconductor process, the repeatability, the stability and the consistency are good, and the method does not depend on high nano processing equipment, and is low in cost and high in yield.
The technical aim of the invention is realized by the following technical scheme:
a method for preparing a horizontal nano-air channel diode based on a sacrificial layer, which is characterized by comprising the following steps:
s1, sequentially depositing a conductive film and a sacrificial layer film on an insulating substrate;
s2, forming a photoresist pattern on the surface of the sacrificial layer film through photoetching, and then corroding or etching the sacrificial layer film through a wet method to obtain the photoresist-sacrificial layer pattern;
s3, removing part of the sacrificial layer film laterally through etching or wet etching to suspend the edge of the photoresist;
s4, depositing a mask film, wherein a horizontal nanometer air channel is formed between the sacrificial layer film and the mask film positioned on the same horizontal plane;
s5, removing the photoresist and the mask film above the photoresist through an organic solvent wet method;
s6, transferring the nano air channel into the conductive film at the lower layer by a wet etching or etching method, and forming a cathode and an anode; and then stripping the rest sacrificial layer film and the mask film to finish the preparation of the horizontal nano air channel diode.
Further, when the materials of the sacrificial layer film and the mask film are conductive materials, the preparation method of the horizontal nano air channel diode comprises the following steps:
s1, depositing a first conductive film on an insulating substrate; the first conductive film is an electrode material and also serves as a sacrificial layer;
s2, forming a photoresist pattern on the first conductive film through photoetching, and then patterning the first conductive film through wet etching to obtain the photoresist-conductive film pattern.
S3, removing part of the first conductive film laterally through etching or wet etching to suspend the edge of the photoresist;
s4, depositing a second conductive film; at the moment, a horizontal nanometer air channel is formed between the first conductive film and the second conductive film which is positioned on the same horizontal plane;
s5, removing the photoresist and the second conductive film above the photoresist through an organic solvent wet method to finish the preparation of the horizontal nano air channel diode.
Further, the conductive film, the first conductive film and the second conductive film are metal conductive films, metalloid conductive films or semiconductor conductive films.
Further, the material of the sacrificial layer film is SiO 2 Or a metal or a semiconductor having different corrosion properties from those of the conductive film; the mask film is made of SiO 2 Or a metal having different corrosion properties from the conductive film.
A method for fabricating a horizontal nano-air channel transistor based on a sacrificial layer, comprising the steps of:
s1, depositing a metal grid film on an insulating substrate;
s2, forming a first photoresist pattern on the metal gate film through photoetching, and then forming a gate through wet etching or etching patterning.
S3, sequentially depositing a first sacrificial layer film, a source drain electrode film and a second sacrificial layer film above the insulating substrate and the grid electrode;
s4, forming a second photoresist pattern on the second sacrificial layer film through photoetching, and forming a photoresist-sacrificial layer pattern through wet etching or dry etching.
S5, removing part of the second sacrificial layer film laterally through etching or wet etching to suspend the edge of the photoresist;
s6, depositing a mask film, wherein a horizontal nano air channel is formed between the second sacrificial layer film and the mask film positioned on the same horizontal plane, and the nano air channel is positioned right above the grid electrode;
s7, removing the photoresist and the mask film above the photoresist through an organic solvent wet method;
s8, transferring the nano air channel into a source drain film at the lower layer through wet etching or etching, and forming a source electrode and a drain electrode; and then stripping the remaining second sacrificial layer film and the mask film to complete the preparation of the horizontal nano air channel transistor. Further, the source-drain electrode film is a metal film or a semiconductor conductive film.
The invention has the following advantages:
1. the preparation method provided by the invention does not depend on expensive nanometer processing equipment, is low in cost, simple, convenient and feasible, is fully compatible with a semiconductor process, has good repeatability, stability and consistency, is suitable for mass production of large-area wafer-level nanometer air channel transistor arrays, and has real practicability.
2. The invention can realize the control precision of the horizontal nanometer air channel size reaching the nanometer level by controlling the lateral removal depth of the sacrificial layer.
3. The preparation method provided by the invention can realize the horizontal nanometer air channel structure with high aspect ratio by adopting the thick sacrificial layer mask, and is not limited by the aspect ratio of the traditional photoetching and etching patterning process.
4. The sacrificial layer mask method provided by the invention has the function of aligning the source, the drain and the grid when forming the channel for the nano air channel triode with the bottom grid structure, and avoids the problem of alignment error when the nano air channel and the grid are generated by traditional photoetching.
Drawings
Fig. 1 and 2 are a side view cross-sectional view and a 3D schematic diagram of a process flow of a sacrificial layer-based horizontal nano air channel diode manufacturing method according to the present invention, respectively. Wherein: 11. an insulating substrate; 12. a conductive film; 13. a sacrificial layer film; 14. a photoresist; 15. a mask film; 16. a nano-air channel.
Fig. 3 and 4 are a side view cross-section and a 3D schematic diagram of a method for manufacturing a horizontal nano-air channel back gate transistor based on a sacrificial layer according to the present invention. Wherein: 31. an insulating substrate; 32. a metal gate film; 33. a first sacrificial layer film; 34. a source/drain thin film; 35. a second sacrificial layer film; 36. a photoresist; 37. SiO (SiO) 2 A dielectric film; 38. horizontal nano-air channels.
Fig. 5 and 6 are a side cross-sectional view and a 3D schematic diagram of a method for manufacturing a horizontal nano-air channel diode based on a cathode as a sacrificial layer according to the present invention. Wherein: 51. an insulating substrate; 52. a first conductive film; 53. a photoresist; 54. a second conductive film; 55. horizontal nano-air channels.
Fig. 7 is a schematic 3D diagram of the basic principle of the sacrificial layer-based anode surrounding type horizontal nano air channel diode manufacturing method. Wherein: 71. an insulating substrate; 72. a metal conductive film; 73. a sacrificial layer film; 74. a photoresist; 75. a mask film; 76. horizontal nano-air channels.
Fig. 8 is a 3D schematic diagram of a method for preparing a single-side gate horizontal nano air channel crystal based on a sacrificial layer according to the present invention. Wherein: 81. an insulating substrate; 82. a metal gate; 83. a photoresist; 84. a metal anode film; 85. metal cathode films, 86, horizontal nano-air channels.
Fig. 9 is a 3D schematic diagram of a method for preparing a double-sided gate horizontal nano air channel crystal based on a sacrificial layer according to the present invention. Wherein: 91. an insulating substrate; 92. a metal gate; 93. a photoresist; 94. a metal anode film; 95. metal cathode thin film, 96, horizontal nano air channel.
Detailed Description
The technical scheme of the invention is further described below with reference to the accompanying drawings and examples.
Example 1
The preparation method of the horizontal nano air channel diode based on the sacrificial layer, the anode and the cathode of which are both metals, has the process flow shown in figures 1 and 2 and comprises the following steps:
s1, sequentially depositing a metal conductive film (such as gold, aluminum, chromium, titanium and the like) and a sacrificial layer film (such as Si O) on an insulating substrate 2 Thin films, etc.).
S2, forming a photoresist pattern on the surface of the sacrificial layer film through photoetching, and then carrying out wet etching or etching on the sacrificial layer film to obtain the photoresist-sacrificial layer pattern.
S3, removing part of the sacrificial layer film laterally through etching or wet etching to suspend one side edge of the photoresist; the nanometer air channel is formed in the lower area of the photoresist suspending part, and the width of the nanometer channel can be accurately controlled by controlling the etching or wet etching time.
S4, depositing a mask film, wherein the mask film is made of SiO 2 Or a metal having a different corrosion property from the conductive film, and a horizontal nano-air channel is formed between the sacrificial layer film and the mask film at the same level.
S5, removing the photoresist and the mask film above the photoresist by using an organic solvent wet method.
S6, transferring the nano air channel into the metal conductive film at the lower layer by a wet etching or etching method, and forming a cathode and an anode; and then stripping the rest sacrificial layer film and the mask film to finish the preparation of the horizontal nano air channel diode.
Example 2
The preparation method of the horizontal nano air channel diode with the anode and the cathode being high temperature resistant metalloids (such as TiN, hfN, zrN, ITO) based on the sacrificial layer comprises the following steps:
s1, sequentially depositing a high-temperature-resistant metal-like conductive film (such as TiN, hfN, zrN, ITO and the like) and a sacrificial layer film (such as SiO) on an insulating substrate 2 Etc.).
S2, forming a photoresist pattern on the surface of the sacrificial layer film through photoetching, and then carrying out wet etching or etching on the sacrificial layer film to obtain the photoresist-sacrificial layer pattern.
S3, removing part of the sacrificial layer film laterally through etching or wet etching to suspend one side edge of the photoresist; the nanometer air channel is formed in the lower area of the photoresist suspending part, and the width of the nanometer channel can be accurately controlled by controlling the etching or wet etching time.
S4, depositing a mask film, wherein the mask film is made of SiO 2 Or a metal having a different corrosion property from the conductive film, and a horizontal nano-air channel is formed between the sacrificial layer film and the mask film at the same level.
S5, removing the photoresist and SiO above the photoresist by using an organic solvent wet method 2 And (3) masking the film.
S6, transferring the nano air channel into the high-temperature-resistant metal-like conductive film on the lower layer by a wet etching or etching method, and forming a cathode and an anode; and then stripping the rest sacrificial layer film and the mask film to finish the preparation of the horizontal nano air channel diode.
This example differs from example 1 in that the electrode material of the prepared diode is different.
Example 3
The preparation method of the horizontal nano air channel back gate transistor based on the sacrificial layer comprises the following steps:
s1, depositing a metal grid film (such as gold, chromium, titanium and the like) on an insulating substrate.
S2, forming a first photoresist pattern on the metal gate film through photoetching, and then forming a gate through wet etching or etching patterning.
S3, sequentially depositing a first sacrificial layer film, a source drain electrode film and a second sacrificial layer film above the insulating substrate and the grid electrode; the source/drain film is a metal film (such as gold, chromium, titanium, etc.) or a semiconductor film (such as P-type Si).
S4, forming a second photoresist pattern on the second sacrificial layer film through photoetching, and forming a photoresist-sacrificial layer pattern through wet etching or dry etching.
S5, removing part of the second sacrificial layer film laterally through etching or wet etching to suspend one side edge of the photoresist. The nanometer air channel is formed in the lower area of the photoresist suspending part and is positioned right above the grid electrode, and the width of the nanometer air channel can be accurately controlled by controlling the etching time length.
S6, depositing SiO 2 Dielectric film, at this time, the second sacrificial layer film is formed on the same level as the SiO 2 Horizontal nano air channels are formed between the dielectric films.
S7, removing the photoresist and SiO above the photoresist by using an organic solvent wet method 2 A dielectric film.
S8, transferring the nano air channel into a source drain film at the lower layer by a wet etching or etching method, and forming a source and a drain; and then stripping the remaining part of the second sacrificial layer filmAnd SiO 2 And (3) preparing the dielectric film to complete the preparation of the horizontal nano air channel back gate transistor.
Example 4
The preparation method of the horizontal nano air channel diode based on the sacrificial layer, wherein the cathode is made of a semiconductor material and the anode is made of a metal material, has the process flow shown in figures 5 and 6 and comprises the following steps:
s1, depositing a first conductive film on an insulating substrate; the first conductive film is a semiconductor film (such as Si, ge, inGaAs, etc.) or a metal film (such as Al, etc.). In this embodiment, the first conductive film is both an electrode material and also serves as a sacrificial layer.
S2, forming a photoresist pattern on the first conductive film through photoetching, and then etching the patterned conductive film through a wet method to obtain the photoresist-conductive film pattern.
S3, removing part of the first conductive film laterally through etching or wet etching to suspend one side edge of the photoresist; an air channel is formed in the lower area of the photoresist suspension part, and the width of the horizontal nanometer air channel can be accurately controlled by controlling the corrosion duration.
S4, depositing a second conductive film, wherein the second conductive film is a semiconductor film (such as Si, ge, inGaAs) or a metal film (such as Al); at this time, a horizontal nano air channel is formed between the first conductive film and the second conductive film at the same horizontal plane.
S5, removing the photoresist and the second conductive film above the photoresist through an organic solvent wet method to finish the preparation of the horizontal nano air channel diode.
Example 5
The preparation method of the anode surrounding type horizontal nano air channel diode based on the sacrificial layer, the anode and the cathode of which are both metals, has the process flow shown in figure 7 and comprises the following steps:
s1, sequentially depositing a metal conductive film (such as gold, aluminum, chromium, titanium and the like) and a sacrificial layer film (such as Si O) on an insulating substrate 2 Etc.).
S2, forming a photoresist pattern on the surface of the sacrificial layer film through photoetching, and then carrying out wet etching or etching on the sacrificial layer film to obtain the photoresist-sacrificial layer pattern.
S3, removing part of the sacrificial layer film laterally through etching or wet etching to suspend the side edges of the photoresist; the nanometer air channel is formed in the lower area of the photoresist suspending part, and the width of the nanometer air channel can be accurately controlled by controlling the corrosion duration.
S4, depositing a mask film, wherein the mask film material can be SiO 2 Or a metal having a different corrosion property from the conductive film, and a horizontal nano-air channel is formed between the sacrificial layer film and the mask film at the same level.
S5, removing the photoresist and the mask film above the photoresist by using an organic solvent wet method.
S6, transferring the nano air channel into the metal conductive film at the lower layer by a wet etching or etching method, and forming a cathode and an anode; and then stripping the rest sacrificial layer film and the mask film to finish the preparation of the horizontal nano air channel diode.
This example differs from example 1 in the electrode structure of the prepared diode.
Example 6
A sacrificial layer-based horizontal nano-air channel single-side gate transistor preparation method comprises the following steps:
s1, depositing a metal grid film (such as gold, chromium, titanium and the like) on an insulating substrate.
S2, forming a first photoresist pattern on the metal gate film through photoetching, and then forming a photoresist-gate pattern through wet etching patterning.
S3, removing part of the metal gate film laterally through etching or wet etching to suspend the edge of the photoresist. The nanometer air channel is formed in the lower area of the photoresist suspending part, and the width of the nanometer air channel can be accurately controlled by controlling the corrosion or etching time length.
S4, depositing a first metal conductive film (such as gold, chromium, titanium and the like) on the insulating substrate and the photoresist.
S5, generating a second photoresist pattern on the first metal conductive film through photoetching, and forming a photoresist-source/drain electrode pattern through wet etching or dry etching. The photolithographic shape of this step affects the source/drain of the final device, so the reticle is designed according to the source/drain shape.
S6, removing part of the first metal conductive film laterally through etching or wet etching.
S7, depositing a second metal conductive film.
S8, removing the first photoresist and the first metal gate film above the first photoresist, the second photoresist and the second metal gate film above the second photoresist through an organic solvent wet method, wherein at the moment, the reserved second metal conductive film is used as a drain/source electrode, and the gate electrode, the source electrode and the drain electrode are positioned on the same plane, so that the preparation of the horizontal nano air channel single-side gate transistor is completed.
Example 7
A sacrificial layer-based horizontal nano-air channel double-side gate transistor preparation method comprises the following steps:
s1, depositing a metal grid film (such as gold, chromium, titanium and the like) on an insulating substrate.
S2, forming two first photoresist patterns on the metal gate film through photoetching, and then forming two photoresist-gate patterns through wet etching patterning.
S3, removing part of the metal gate film laterally through etching or wet etching to suspend the edge of the photoresist. The nanometer air channel is formed in the lower area of the photoresist suspending part, and the width of the nanometer air channel can be accurately controlled by controlling the corrosion or etching time length.
S4, depositing a first metal conductive film (such as gold, chromium, titanium and the like) on the insulating substrate and the photoresist.
S5, generating a second photoresist pattern on the first metal conductive film through photoetching, and forming a photoresist-source/drain electrode pattern through wet etching or dry etching. The photolithographic shape of this step affects the source/drain of the final device, so the reticle is designed according to the source/drain shape.
S6, removing part of the first metal conductive film laterally through etching or wet etching.
S7, depositing a second metal conductive film.
S8, removing the first photoresist and the first metal gate film above the first photoresist, the second photoresist and the second metal gate film above the second photoresist through an organic solvent wet method, wherein at the moment, the reserved second metal conductive film is used as a drain/source electrode, and the double gates, the source electrode and the drain electrode are positioned on the same plane, so that the preparation of the horizontal nano air channel double-side gate transistor is completed.
This embodiment differs from embodiment 6 in that the gate structure of the transistor is different from that of the transistor manufactured.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.
Claims (6)
1. A method for preparing a horizontal nano-air channel diode based on a sacrificial layer, which is characterized by comprising the following steps:
s1, sequentially depositing a conductive film and a sacrificial layer film on an insulating substrate;
s2, forming a photoresist pattern on the surface of the sacrificial layer film through photoetching, and then corroding or etching the sacrificial layer film through a wet method to obtain the photoresist-sacrificial layer pattern;
s3, removing part of the sacrificial layer film laterally through etching or wet etching to suspend the edge of the photoresist;
s4, depositing a mask film, wherein a horizontal nanometer air channel is formed between the sacrificial layer film and the mask film positioned on the same horizontal plane;
s5, removing the photoresist and the mask film above the photoresist through an organic solvent wet method;
s6, transferring the nano air channel into the conductive film at the lower layer by a wet etching or etching method, and forming a cathode and an anode; and then stripping the rest sacrificial layer film and the mask film to finish the preparation of the horizontal nano air channel diode.
2. The method for preparing a horizontal nano-air channel diode based on a sacrificial layer according to claim 1, wherein when the materials of the sacrificial layer film and the mask film are conductive materials, the method for preparing the horizontal nano-air channel diode comprises the following steps:
s1, depositing a first conductive film on an insulating substrate; the first conductive film is an electrode material and also serves as a sacrificial layer;
s2, forming a photoresist pattern on the first conductive film through photoetching, and then patterning the first conductive film through wet etching to obtain the photoresist-conductive film pattern.
S3, removing part of the first conductive film laterally through etching or wet etching to suspend the edge of the photoresist;
s4, depositing a second conductive film; at the moment, a horizontal nanometer air channel is formed between the first conductive film and the second conductive film which is positioned on the same horizontal plane;
s5, removing the photoresist and the second conductive film above the photoresist through an organic solvent wet method to finish the preparation of the horizontal nano air channel diode.
3. The method for manufacturing a horizontal nano-air channel diode based on a sacrificial layer according to claim 1 or 2, wherein the conductive film, the first conductive film, the second conductive film are metal conductive films, metalloid conductive films or semiconductor conductive films.
4. The method for fabricating a horizontal nano-air channel diode based on a sacrificial layer according to claim 3, wherein the material of the sacrificial layer film is SiO 2 Or a metal or a semiconductor having different corrosion properties from those of the conductive film; the mask film is made of SiO 2 Or a metal having different corrosion properties from the conductive film.
5. A method for fabricating a horizontal nano-air channel transistor based on a sacrificial layer, comprising the steps of:
s1, depositing a metal grid film on an insulating substrate;
s2, forming a first photoresist pattern on the metal gate film through photoetching, and then forming a gate through wet etching or etching patterning.
S3, sequentially depositing a first sacrificial layer film, a source drain electrode film and a second sacrificial layer film above the insulating substrate and the grid electrode;
s4, forming a second photoresist pattern on the second sacrificial layer film through photoetching, and forming a photoresist-sacrificial layer pattern through wet etching or dry etching.
S5, removing part of the second sacrificial layer film laterally through etching or wet etching to suspend the edge of the photoresist;
s6, depositing a mask film, wherein a horizontal nano air channel is formed between the second sacrificial layer film and the mask film positioned on the same horizontal plane, and the nano air channel is positioned right above the grid electrode;
s7, removing the photoresist and the mask film above the photoresist through an organic solvent wet method;
s8, transferring the nano air channel into a source drain film at the lower layer through wet etching or etching, and forming a source electrode and a drain electrode; and then stripping the remaining second sacrificial layer film and the mask film to complete the preparation of the horizontal nano air channel transistor.
6. The method for fabricating a horizontal nano-air channel transistor based on a sacrificial layer according to claim 5, wherein the source/drain thin film is a metal thin film or a semiconductor conductive thin film.
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