CN116505957A - Flexible partial parallel pipeline LDPC decoder based on semi-probability calculation - Google Patents

Flexible partial parallel pipeline LDPC decoder based on semi-probability calculation Download PDF

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CN116505957A
CN116505957A CN202310412214.9A CN202310412214A CN116505957A CN 116505957 A CN116505957 A CN 116505957A CN 202310412214 A CN202310412214 A CN 202310412214A CN 116505957 A CN116505957 A CN 116505957A
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module
cyclic shift
data
input end
check node
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刘齐
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Sichuan Innogence Technology Co Ltd
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Sichuan Innogence Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Advance Control (AREA)

Abstract

The invention discloses a flexible parallel flow LDPC decoder based on semi-probability calculation, which comprises: APP RAM module, cyclic shift module one, multistage register beat module, variable node module, check node module, posterior probability update module, cyclic shift module two. The LDPC decoding architecture requires a large amount of information to be transferred between variable nodes and check nodes. After the formula is simplified, the information storage RAM which is mutually transmitted between the variable node and the check node can be removed. In the framework of the invention, only two parallel shifting processes are included, and the barreled shifting process of the intermediate node is not included.

Description

Flexible partial parallel pipeline LDPC decoder based on semi-probability calculation
Technical Field
The invention relates to the field of logic circuits, in particular to a flexible partial parallel pipeline LDPC decoder based on semi-probability calculation.
Background
LDPC (Low Density Parity Check Codes) the low density parity check code belongs to channel coding and is one of the linear block codes. In the LDPC layered decoding structure, generally, as shown in fig. 1. The meaning of the semi-probability calculation is that the check node calculation unit adopts a probability calculation mode based on full correlation to calculate the minimum value, and other addition and subtraction operations still are normal.
Patent CN114553242a describes a partially parallel LDPC decoder based on semi-probability computation, which has the following problems: 1) A large amount of storage resources are needed for storing the mutual transmission information between the variable nodes and the check nodes; 2) Processing time is consumed in the storage process and the reading and storing process, so that the module cannot reach a large processing bandwidth; 3) In the above structure, the parallelism is selected so that only partial parallel processing can be performed basically according to the maximum Zc value. The flexibility is insufficient, and in this case, a large amount of hardware resources are required to be consumed.
Disclosure of Invention
In order to solve the problems of overlarge storage resources and consumed processing time for storage and reading in a conventional LDPC decoding structure, the invention provides a flexible parallel pipeline LDPC decoder based on half-probability calculation, which solves the problems.
A flexible parallel pipelined LDPC decoder based on semi-probability computation, comprising:
the APP RAM module is used for storing LLR values in the LDPC decoding iteration process;
the first cyclic shift module is used for completing cyclic shift of ZC data by reading data corresponding to an address one addr, an address two addr+1 and an address three addr+2 where a cyclic shift value corresponding to a serial number LLR value in the base matrix is located and then performing data splicing of 3 addresses;
the multi-stage register beat module is used for delaying the output data of the first cyclic shift module, and the output data of the first cyclic shift module and the output data of the check node module are aligned by completing the register beat mode;
the variable node module is used for converting LLR values of the variable nodes output by the cyclic shift module I into N full-correlation random bit streams with fixed lengths through comparison with N random sobol sequences, so as to be used for calculation of the subsequent check node module;
the check node module is used for completing the calculation of the minimum absolute value through AND gate operation and bit counting accumulation, completing the operation of multiplying the symbols through exclusive OR operation, and then converting the symbol minimum absolute value into a signed LLR value according to the symbol minimum absolute value;
the posterior probability updating module is used for completing addition of data of the check node module and data information of the variable node module through addition of signed LLR values;
and the second cyclic shift module is used for determining the address written into the APP RAM module according to the cyclic shift value in the base matrix, and writing the address of the appointed APP RAM module after data splicing of front and rear data is carried out.
Preferably, the output end of the APP RAM module is connected with the input end of the first cyclic shift module,
the output end of the first cyclic shift module is respectively connected with the input end of the multi-stage register beat module and the input end of the variable node module,
the output end of the multistage register beat module is connected with the input end of the posterior probability updating module,
the output end of the variable node module is connected with the input end of the check node module,
the output end of the check node module is connected with the input end of the posterior probability updating module,
the output end of the posterior probability updating module is connected with the input end of the cyclic shift module II,
and the output end of the second cyclic shift module is connected with the input end of the APP RAM module.
Preferably, the formula of the variable node module is specifically:
L (l) (q nm )＝L (l-1) (q n )，
wherein L is (l-1) (q n ) Representing LLR values corresponding to variable nodes in APP RAM after the L-1 th iteration, L (l) (q nm ) Representing the information transmitted by the variable node to the check node in the L-th iteration process.
The invention has the beneficial effects that:
(1) The resources are better. Omitting information transmission memory registers between variable nodes and check nodes
(2) The throughput rate is higher, and the operation time is reduced by adopting pipeline operation.
(3) The parallel flexibility is higher, and the parallelism is not limited by Zc.
Drawings
FIG. 1 is a conventional LDPC decoding structure;
FIG. 2 is a flexible parallel pipelined LDPC decoder based on semi-probability computation according to an embodiment of the present invention;
FIG. 3 shows a memory mode of an APP RAM according to an embodiment of the present invention;
FIG. 4a shows LLR alignment in RAM according to an embodiment of the present invention;
FIG. 4b shows a RAM selection 68_to_19 according to an embodiment of the present invention;
FIG. 5a is a LLR-to-bit architecture according to an embodiment of the present invention;
fig. 5b is a detailed structure of single LLR bit conversion according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the operation of a check node module according to an embodiment of the present invention;
FIG. 7a is a flowchart of embodiment 7a of the present invention for writing back LLR to RAM;
FIG. 7b shows a RAM selection 19_to_68 according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a posterior probability update operation according to an embodiment of the present invention.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and examples.
The construction method of the LDPC code mainly comprises two construction methods of pseudo-random construction and algebraic construction;
under the condition that the code length of the LDPC code is longer, the irregular LDPC code constructed by the pseudo-random construction method has good performance, and the performance curve is close to the theoretical limit. In this case, the performance curve of the algebraic LDPC code is poor, so that the performance of the irregular LDPC code is superior to that of the algebraic LDPC code in the case of a long code length. In the case of the LDPC code having a short code length (the code length is several kilobits or less), the situation is changed, and since it is easier to satisfy the minimum distance characteristic between codewords, the regular LDPC code generally has better performance than the irregular LDPC code.
The algebraic construction method mainly comprises two types, wherein one type is constructed based on a limited geometric figure, and the other type is a construction method based on a cyclic shift matrix which is focused on. The LDPC code constructed based on the cyclic shift matrix is called a quasi-cyclic LDPC code, i.e., QC-LDPC code. The check matrix of the QC-LDPC code consists of sparse cyclic submatrices with the same matrix size, and the H matrix of the check matrix can be expressed in the following form:
wherein B is i,j For a sparse cyclic sub-matrix of dimension z×z, n=n×z, m=m×z. Each sub-matrix in the H matrix has a quasi-cyclic characteristic, so the LDPC code of this structure is called a quasi-cyclic LDPC code. A more specific case in QC-LDPC is B i,j Is a unitary circular sub-matrix of dimension Z x Z.
If x is used i,j Representing submatrix B i,j The H matrix of which can be expressed as the number of bits shifted right in the cycle:
wherein H is base Called the basis matrix of the QC-LDPC code. This special QC-LDPC code greatly simplifies the design of the encoder and because of its submatrix B i,j The row weight and the column weight are 1, thereby facilitating the parallel realization of the coding and decoding algorithm. The QC-LDPC code in 802.11n is the special QC-LDPC code.
As shown in fig. 2, the present invention provides a flexible parallel pipelined LDPC decoder based on semi-probability computation, comprising:
the APP RAM module 1 is used for storing LLR values in the LDPC decoding iteration process;
the first cyclic shift module 2 is configured to complete cyclic shift of ZC data by reading data corresponding to an address one addr, an address two addr+1, and an address three addr+2 where a cyclic shift value in the base matrix corresponds to a serial number LLR value, and then performing data splicing of 3 addresses;
the multistage register beat module 3 is used for delaying the output data of the cyclic shift module I2, and is completed in a register beat mode, so that the aim of aligning the shifted LLR data output by the cyclic shift module I2 with the output data of the check node module 5 is fulfilled;
the variable node module 4 is configured to convert the LLR values of the variable nodes output from the cyclic shift module one 2 into N full-correlation random bit streams with fixed lengths by comparing with N random sobol sequences, for calculation by the subsequent check node module 5;
the check node module 5 completes the calculation of the minimum absolute value through AND gate operation and bit counting accumulation, completes the operation of multiplying the symbols through exclusive OR operation, and then converts the symbol LLR value into a signed LLR value according to the minimum absolute value and the symbols;
the posterior probability updating module 6 is used for completing the addition of the data of the check node module 5 and the data information of the variable node module 4 through signed LLR value addition;
and the second cyclic shift module 7 is used for determining the address written into the APP RAM module 1 according to the cyclic shift value in the base matrix, and writing the address of the appointed APP RAM module 1 after data splicing of front and rear data is carried out.
The output end of the APP RAM module 1 is connected with the input end of the cyclic shift module I2,
the output end of the first cyclic shift module 2 is respectively connected with the input end of the multi-stage register beat module 3 and the input end of the variable node module 4,
the output end of the multistage register beat module 3 is connected with the input end of the posterior probability updating module 6,
the output end of the variable node module 4 is connected with the input end of the check node module 5,
the output end of the check node module 5 is connected with the input end of the posterior probability updating module 6,
the output end of the posterior probability updating module 6 is connected with the input end of the cyclic shift module II 7,
the output end of the second cyclic shift module 7 is connected with the input end of the APP RAM module 1.
The formula of the variable node module is specifically as follows:
L (l) (q nm )＝L (l-1) (q n )，
wherein L is (l-1) (q n ) Representing LLR values corresponding to variable nodes in APP RAM after the L-1 th iteration, L (l) (q nm ) Representing the information transmitted by the variable node to the check node in the L-th iteration process.
Taking 5G bg=0 (68 columns), zc=384, and the parallelism P is described as an example (P is the parallelism of processing check nodes simultaneously).
S1, storing LLR data into an APP RAM module 1. The storage mode of the APP RAM is shown in fig. 3, and each RAM stores data of a ZC. There are 68 RAMs in total, corresponding to 68 columns of the base matrix.
S2, selecting not more than 19 RAMs from the RAMs 0 to 67 according to the base matrix of 5G (the degree of check nodes in the base matrix of 5G is not more than 19 at maximum), calculating and selecting specified address data according to the value of the base matrix, and then performing bit spelling output. As shown in fig. 4, the structure will be described by taking zc=384, the base matrix value is 5, and p=12 as an example. Address and start bit calculation mode: addr=5/12=0 start:5% 12=5. After the data is circularly read, the front address data and the rear address data are spliced. This process corresponds to (1-65) without the subtraction process in the previous algorithm.
S3, a multistage register beating module 3 carries out register beating processing on the data output by the cyclic shift module 2, and achieves the aim of alignment with the output of the check node module 5, wherein the beating bit width is 19 x P x M.
S4, a variable node module 4 compares M sobol random sequences with LLRs to generate M bit sequences, wherein the length is M, and the parallelism is 19X P X M, as shown in FIG. 5.
S5, the check node module 5 performs check node calculation to complete the process of multiplying the minimum absolute value by the symbol, and the corresponding formula (0-1) is formed. Similar to the original semi-probability computation architecture, the output is LLR data, as shown in FIG. 6.
S6, a posterior probability updating module 6 completes posterior probability updating. The formula of the variable node module is as follows: l (L) (l) (q nm )＝L (l-1) (q n ) Wherein L is (l-1) (q n ) Representing LLR values corresponding to variable nodes in APP RAM after the L-1 th iteration, L (l) (q nm ) Represents the firstAnd in the L iterative processes, the variable nodes transmit information to the check nodes. The modules directly add signed numbers in parallel as shown in fig. 7.
S7, the cyclic shift module II 7 performs cyclic shift, which is the inverse operation of the step S3, as shown in FIG. 8. Taking zc=384, the base matrix value is 5, and p=12 as an example, the structure will be described. After registering and splicing the data, the data is written into the appointed RAM. The layering iteration is completed so far.
S8, performing loop execution of S1-S7 according to configuration and actual requirements.
The foregoing has shown and described the basic principles and main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (3)

1. A flexible parallel pipelined LDPC decoder based on semi-probability computation, comprising:
the APP RAM module is used for storing LLR values in the LDPC decoding iteration process;
the first cyclic shift module is used for completing cyclic shift of ZC data by reading data corresponding to an address one addr, an address two addr+1 and an address three addr+2 where a cyclic shift value corresponding to a serial number LLR value in the base matrix is located and then performing data splicing of 3 addresses;
the multi-stage register beat module is used for delaying the output data of the first cyclic shift module, and the output data of the first cyclic shift module and the output data of the check node module are aligned by completing the register beat mode;
the variable node module is used for converting LLR values of the variable nodes output by the cyclic shift module I into N full-correlation random bit streams with fixed lengths through comparison with N random sobol sequences, so as to be used for calculation of the subsequent check node module;
the check node module is used for completing the calculation of the minimum absolute value through AND gate operation and bit counting accumulation, completing the operation of multiplying the symbols through exclusive OR operation, and then converting the symbol minimum absolute value into a signed LLR value according to the symbol minimum absolute value;
the posterior probability updating module is used for completing addition of data of the check node module and data information of the variable node module through addition of signed LLR values;
and the second cyclic shift module is used for determining the address written into the APP RAM module according to the cyclic shift value in the base matrix, and writing the address of the appointed APP RAM module after data splicing of front and rear data is carried out.
2. A flexible parallel pipelined LDPC decoder based on semi-probability computation as recited in claim 1 wherein,
the output end of the APP RAM module is connected with the input end of the first cyclic shift module,
the output end of the first cyclic shift module is respectively connected with the input end of the multi-stage register beat module and the input end of the variable node module,
the output end of the multistage register beat module is connected with the input end of the posterior probability updating module,
the output end of the variable node module is connected with the input end of the check node module,
the output end of the check node module is connected with the input end of the posterior probability updating module,
the output end of the posterior probability updating module is connected with the input end of the cyclic shift module II,
and the output end of the second cyclic shift module is connected with the input end of the APP RAM module.
3. The flexible parallel pipeline LDPC decoder based on semi-probability computation of claim 1, wherein the variable node module has a formula:
L (l) (q nm )＝L (l-1) (q n )，
wherein L is (l-1) (q n ) Representing LLR values corresponding to variable nodes in APP RAM after the L-1 th iteration, L (1) (q nm ) Representing the information transmitted by the variable node to the check node in the L-th iteration process.
CN202310412214.9A 2023-04-18 2023-04-18 Flexible partial parallel pipeline LDPC decoder based on semi-probability calculation Pending CN116505957A (en)

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