CN116505759A - Voltage-adjustable charge pump circuit and equipment - Google Patents
Voltage-adjustable charge pump circuit and equipment Download PDFInfo
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- CN116505759A CN116505759A CN202310491074.9A CN202310491074A CN116505759A CN 116505759 A CN116505759 A CN 116505759A CN 202310491074 A CN202310491074 A CN 202310491074A CN 116505759 A CN116505759 A CN 116505759A
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- 238000000034 method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a charge pump circuit and equipment with adjustable voltage, the circuit includes: the voltage doubling module, the pressure boosting module and the voltage output module are connected with the clock module, the voltage doubling module is connected with the pressure boosting module, the voltage doubling module generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the pressure boosting module, the pressure boosting module generates a pressure boosting signal according to the clock signal and the voltage doubling signal and outputs the pressure boosting signal to the voltage output module, and the voltage output module generates an output signal according to the clock signal and the pressure boosting signal. The circuit output signal has the effects that the circuit output signal has a larger voltage range and the adjusting range of the circuit output signal has more flexibility.
Description
The present application is a divisional application of Chinese patent application (application No. 202310254947.4, application day 2023, month 03 and 16, title of invention, charge pump circuit and device capable of regulating voltage).
Technical Field
The invention belongs to the technical field of charge pumps, and particularly relates to a voltage-adjustable charge pump circuit and equipment.
Background
As processes progress, system applications move closer to lower supply voltages and circuit and system designs migrate to deep submicron, typically the supply voltage decreases to 1.5V or less under such processes. Because in many low supply voltage and switched capacitor systems high voltages are required to drive the analog switches. A charge pump loop is required to obtain a DC voltage higher than the supply voltage.
In the related art, a conventional multiplication charge pump is generally used to obtain a DC voltage higher than a power supply voltage, and the conventional multiplication charge pump includes a clock circuit for generating an alternate clock signal, two capacitors for filtering, and two NMOS transistors. Furthermore, since the charge pump circuit is an active circuit, its output is affected by input terminal parameters (e.g., capacitance, resistance, etc.) and input voltage. Since these parameters are fixed, the output voltage regulation range of the charge pump circuit is limited.
Disclosure of Invention
The invention provides a charge pump circuit and a charge pump device with adjustable voltage.
In a first aspect, the present invention provides a voltage-adjustable charge pump circuit comprising a clock module for providing a clock signal, the circuit further comprising: the voltage doubling module, the pressure boosting module and the voltage output module are connected with the clock module, the voltage doubling module is connected with the pressure boosting module, the voltage doubling module generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the pressure boosting module, the pressure boosting module generates a pressure boosting signal according to the clock signal and the voltage doubling signal and outputs the pressure boosting signal to the voltage output module, the voltage output module generates an output signal according to the clock signal and the pressure boosting signal, and the voltage range of the output signal is larger than twice the voltage range of the clock signal.
Optionally, the voltage doubling module includes a first voltage doubling charge pump unit and a voltage doubling auxiliary unit, the first voltage doubling charge pump unit is connected with the voltage doubling auxiliary unit, the voltage doubling auxiliary unit is connected with the pressurizing module, the first voltage doubling charge pump unit and the voltage doubling auxiliary unit generate the voltage doubling signal based on the clock signal, and the voltage doubling auxiliary unit outputs the voltage doubling signal to the pressurizing module.
Optionally, the first voltage-multiplying charge pump unit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, and an NMOS tube M4, one ends of the capacitor C1 and the capacitor C4 are all connected with one end of the clock module, one ends of the capacitor C2 and the capacitor C3 are all connected with the other end of the clock module, the other end of the capacitor C1 is connected with the source of the NMOS tube M1 and the gate of the NMOS tube M2, the other end of the capacitor C2 is connected with the gate of the NMOS tube M1 and the source of the NMOS tube M2, the other end of the capacitor C3 is connected with the source of the NMOS tube M3 and the gate of the NMOS tube M4, the other end of the capacitor C4 is connected with the gate of the NMOS tube M3 and the source of the NMOS tube M4, the drain of the NMOS tube M2 and the drain of the NMOS tube M3 and the drain of the NMOS tube M4 are all connected with the auxiliary voltage-multiplying unit.
Optionally, the voltage doubling auxiliary unit includes a capacitor C5, a capacitor C6, an NMOS tube M5 and an NMOS tube M6, a gate of the NMOS tube M5 is connected with a gate of the NMOS tube M4, a gate of the NMOS tube M6 is connected with a gate of the NMOS tube M2, the NMOS tube M1, the NMOS tube M2, the NMOS tube M3, the NMOS tube M4, the NMOS tube M5 and a drain of the NMOS tube M6 are connected in series, a source of the NMOS tube M5 is connected with one end of the capacitor C5 and the pressurizing module, a source of the NMOS tube M6 is connected with one end of the capacitor C6 and the pressurizing module, another end of the capacitor C5 is connected with one end of the clock module, and another end of the capacitor C6 is connected with another end of the clock module and the pressurizing module.
Optionally, the voltage doubling module includes a second voltage doubling charge pump unit and an inversion unit, the second voltage doubling charge pump unit is connected with the inversion unit, the inversion unit is connected with the pressurizing module, the second voltage doubling charge pump unit generates the voltage doubling signal based on the clock signal, and the inversion unit performs inversion processing on the voltage doubling signal and outputs the voltage doubling signal after the inversion processing to the pressurizing module.
Optionally, the second voltage-multiplying charge pump unit includes a capacitor C1, a capacitor C2, a PMOS tube M1 and a PMOS tube M2, the capacitor C1 is connected with one end of the clock module, the capacitor C2 is connected with the other end of the clock module, the other end of the capacitor C1 is connected with the drain electrode of the PMOS tube M1 and the gate electrode of the PMOS tube M2, the other end of the capacitor C2 is connected with the gate electrode of the PMOS tube M1 and the drain electrode of the PMOS tube M2, the drain electrode and the source electrode of the PMOS tube M2, and the source electrode of the PMOS tube M1 are connected with the inverting unit.
Optionally, the inverting unit includes a PMOS tube M3, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6, a PMOS tube M7, and an NMOS tube M8, sources of the PMOS tube M1, the PMOS tube M2, the PMOS tube M3, the PMOS tube M5, and the PMOS tube M7 are connected in series, a drain of the PMOS tube M2 is connected with the PMOS tube M3 and a gate of the NMOS tube M4, drains of the PMOS tube M3 and the NMOS tube M4 are connected with the gates of the PMOS tube M5 and the NMOS tube M6, drains of the PMOS tube M5 and the NMOS tube M6 are connected with the gates of the PMOS tube M7 and the NMOS tube M8, and sources of the PMOS tube M4, the NMOS tube M6, and the NMOS tube M8 are connected with the pressurizing module.
Optionally, the voltage boosting module includes a PMOS tube M1 and an NMOS tube M2, a first reference voltage is input to a gate of the PMOS tube M1, a second reference voltage is input to a gate of the NMOS tube M2, drains of the PMOS tube M7 and the NMOS tube M8 are all connected with a source of the PMOS tube M1, sources of the NMOS tube M4, the NMOS tube M6 and the NMOS tube M8 are all connected with a source of the NMOS tube M2, a source of the NMOS tube M2 is also connected with one end of the clock module, and drains of the PMOS tube M1 and the NMOS tube M2 are all connected with the voltage output module.
Optionally, the voltage output module includes capacitor c1, capacitor c2, NMOS tube m3 and NMOS tube m4, PMOS tube m1 with NMOS tube m 2's drain electrode all with capacitor c 1's one end is connected, capacitor c 1's the other end with NMOS tube m 3's source and NMOS tube m 4's grid is connected, capacitor c 2's one end with the one end of clock module is connected, capacitor c 2's the other end with NMOS tube m 3's grid and NMOS tube m 4's source is connected, NMOS tube m 3's drain electrode with NMOS tube m 4's drain electrode is connected, NMOS tube m 4's grid is used for exporting output signal.
In a second aspect, the invention also provides an apparatus comprising a voltage-adjustable charge pump circuit as described in the first aspect.
The beneficial effects of the invention are as follows: the circuit comprises a voltage doubling module, a voltage boosting module and a voltage output module, wherein the voltage doubling module, the voltage boosting module and the voltage output module are all connected with the clock module, the voltage doubling module is connected with the voltage boosting module, the voltage doubling module generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the voltage boosting module, the voltage boosting module generates a voltage boosting signal according to the clock signal and the voltage doubling signal and outputs the voltage boosting signal to the voltage output module, the voltage output module generates an output signal according to the clock signal and the voltage boosting signal, the voltage doubling processing of the voltage doubling module and the voltage boosting processing of the voltage boosting module are carried out on the signal, the output signal has a larger voltage range, and the voltage range is larger than twice the voltage range of the clock signal. Because of the increase of the modules in the circuit, the adjustable parameters are increased, so that the adjusting range of the output signal of the circuit is more flexible.
Drawings
Fig. 1 is a schematic circuit diagram of a voltage-adjustable charge pump circuit according to one embodiment of the present application.
Fig. 2 is a signal timing diagram of clock signals provided by the clock module according to one embodiment of the present application.
Fig. 3 is a voltage timing diagram of capacitors C5 and C6 in one embodiment of the present application.
Fig. 4 is a second circuit schematic diagram of a voltage-adjustable charge pump circuit according to one embodiment of the present application.
Reference numerals illustrate:
1. a voltage doubling module; 11. a first voltage-multiplying charge pump unit; 12. a voltage doubling auxiliary unit; 13. a second voltage-multiplying charge pump unit; 14. a reversing unit; 3. a pressurizing module; 4. and a voltage output module.
Detailed Description
The invention discloses a voltage-adjustable charge pump circuit.
In one embodiment, referring to fig. 1, the voltage-adjustable charge pump circuit includes a clock module for providing a clock signal, and in this embodiment, referring to fig. 2, the clock module may provide two-phase non-overlapping clock signals, namely CLKP and CLKN, where the voltage range of the clock signal provided by the clock module is 0-AVDD. The circuit further comprises a voltage doubling module 1, a voltage boosting module 3 and a voltage output module 4, wherein the voltage doubling module 1, the voltage boosting module 3 and the voltage output module 4 are connected with the clock module, the voltage doubling module 1 is connected with the voltage boosting module 3, the voltage doubling module 1 generates voltage doubling signals based on clock signals and outputs the voltage doubling signals to the voltage boosting module 3, the voltage boosting module 3 generates voltage boosting signals according to the clock signals and the voltage doubling signals and outputs the voltage boosting signals to the voltage output module 4, and the voltage output module 4 generates output signals according to the clock signals and the voltage boosting signals.
In this embodiment, referring to fig. 1, the voltage doubling module 1 includes a first voltage doubling charge pump unit 11 and a voltage doubling auxiliary unit 12, where the first voltage doubling charge pump unit 11 includes two groups of multiplication charge pump units, specifically includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an NMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3 and an NMOS transistor M4, one ends of the capacitor C1 and the capacitor C4 are connected to the CLKP end of the clock module, one ends of the capacitor C2 and the capacitor C3 are connected to the CLKN end of the clock module, the other ends of the capacitor C1 are connected to the source of the NMOS transistor M1 and the gate of the NMOS transistor M2, the other ends of the capacitor C2 are connected to the source of the NMOS transistor M3 and the gate of the NMOS transistor M4, the other ends of the capacitor C4 are connected to the gate of the NMOS transistor M3 and the source of the NMOS transistor M4, and the drain of the NMOS transistor M1, the drain of the NMOS transistor M2 and the drain of the NMOS transistor M3 and the auxiliary unit 12 are connected to the drain of the voltage doubling unit M4.
In the first voltage-multiplying charge pump unit 11, when the clock signals CLKP and CLKN pass through the capacitors C1 and C2, respectively, the capacitor C1 is charged and the capacitor C2 is discharged, thereby generating a positive voltage difference; when the clock signals CLKP and CLKN pass through the capacitors C3 and C4, respectively, the capacitor C3 is charged and the capacitor C4 is discharged, thereby generating a negative voltage difference. Accordingly, the first voltage-multiplying charge pump unit 11 can generate an initial voltage-multiplying signal of the voltage VB1 and output to the voltage-multiplying auxiliary unit 12.
In this embodiment, referring to fig. 1, the voltage doubling auxiliary unit 12 specifically includes a capacitor C5, a capacitor C6, an NMOS transistor M5 and an NMOS transistor M6, the gate of the NMOS transistor M5 is connected to the gate of the NMOS transistor M4, the gate of the NMOS transistor M6 is connected to the gate of the NMOS transistor M2, the drains of the NMOS transistor M1, the NMOS transistor M2, the NMOS transistor M3, the NMOS transistor M4, the NMOS transistor M5 and the NMOS transistor M6 are connected in series, the source of the NMOS transistor M5 is connected to one end of the capacitor C5 and the booster module 3, the source of the NMOS transistor M6 is connected to one end of the capacitor C6 and the booster module 3, the other end of the capacitor C5 is connected to the CLKP end of the clock module, and the other end of the capacitor C6 is connected to the CLKN end of the clock module and the booster module 3. Referring to fig. 3, in the voltage doubler auxiliary unit 12, the upper plate voltages of the capacitor C5 and the capacitor C6 can be charged to VB1 to avdd+vb1 by the initial voltage doubler signal and the clock signal outputted from the first voltage doubler charge pump unit 11.
In this embodiment, referring to fig. 1, the boosting module 3 includes a PMOS transistor M1 and an NMOS transistor M2, the first reference voltage is input to the gate of the PMOS transistor M1, the first reference voltage is output by the voltage doubling auxiliary unit 12 in this embodiment, the gate of the PMOS transistor M1 is connected to the source of the NMOS transistor M5, the source of the PMOS transistor M1 is connected to the source of the NMOS transistor M6, and one end of the capacitor C6 connected to the clock module is also connected to the source of the NMOS transistor M2, so the voltage range of the first reference voltage in this embodiment is VB1 to avdd+vb1. The second reference voltage is input to the grid electrode of the NMOS tube M2, in the embodiment, the second reference voltage is input through a power supply, the input voltage is the maximum voltage of signals output by the clock module, the drains of the PMOS tube M7 and the NMOS tube M8 are connected with the source electrode of the PMOS tube M1, the sources of the NMOS tube M4, the NMOS tube M6 and the NMOS tube M8 are connected with the source electrode of the NMOS tube M2, the source electrode of the NMOS tube M2 is further connected with one end of the clock module, and the drains of the PMOS tube M1 and the NMOS tube M2 are connected with the voltage output module 4.
Therefore, in the present embodiment, when the CLKN signal is at the high level in the clock module, the upper plate of the capacitor C5, that is, the gate voltage of the PMOS transistor m1 is avdd+vb1, and the upper plate of the capacitor C6, that is, the source voltage of the PMOS transistor m1 is VB1, the voltage difference between the gate and the source of the PMOS transistor m1 is AVDD, which is greater than the threshold voltage of the PMOS transistor m1, so that the PMOS transistor m1 is turned on, but the voltage difference between the gate and the source of the NMOS transistor m2 is smaller than the threshold voltage of the NMOS transistor m2, so that the NMOS transistor m2 is turned off, and at this time, the voltage avdd+vb1 on the upper plate of the capacitor C6 is outputted as the boost signal to the voltage output module 4 through the PMOS transistor m 1.
Similarly, when the CLKN signal is at a low level, the threshold voltage of the PMOS transistor m1 is greater than the voltage difference between the gate and the source of the PMOS transistor m1, so that the PMOS transistor m1 is not turned on, but the NMOS transistor m2 is turned on, and the threshold voltage of the NMOS transistor m2 is 0, so that the voltage difference in the circuit is counteracted, and the voltage of the boost signal output to the voltage output module 4 is changed to 0. In this case, since the PMOS transistor m1 is not turned on and does not affect the voltage in the circuit, the voltage of the boost signal output to the voltage output module 4 is 0 at this time, and thus the voltage range of the boost signal output by the boost module 3 is 0 to avdd+vb1 in the present embodiment.
In this embodiment, referring to fig. 1, the voltage output module 4 includes a capacitor c1, a capacitor c2, an NMOS transistor m3 and an NMOS transistor m4, drains of the PMOS transistor m1 and the NMOS transistor m2 are connected to one end of the capacitor c1, the other end of the capacitor c1 is connected to a source of the NMOS transistor m3 and a gate of the NMOS transistor m4, one end of the capacitor c2 is connected to a CLKP end of the clock module, the other end of the capacitor c2 is connected to a gate of the NMOS transistor m3 and a source of the NMOS transistor m4, a drain of the NMOS transistor m3 is connected to a drain of the NMOS transistor m4, and a gate of the NMOS transistor m4 is used for outputting an output signal.
As can be seen from the above description, in the present embodiment, the timing of the boost signal received by the capacitor c1 is the same as the timing of the clock signal CLKN, so that the boost signal received by the capacitor c1 and the CLKP terminal at the capacitor c2 form two-phase non-overlapping clocks. Therefore, when the voltage boosting signal, i.e. the voltage of the lower plate of the capacitor c1 is 0, the CLKP signal is AVDD, so that the NMOS transistor m4 is not turned on and the NMOS transistor m3 is turned on. Assuming that the voltage between the drains of NMOS transistor m3 and NMOS transistor m4 is VB, the voltage on capacitor c1 will charge to VB, the voltage on the upper plate of capacitor c2 will become avdd+vb, at which time the output signal OUT at the gate of NMOS transistor m4 will remain at VB.
Similarly, when the boost signal, that is, the voltage of the lower plate of the capacitor c1 is avdd+vb1, the NMOS transistor m3 is not turned on, the NMOS transistor m4 is turned on, the voltage of the upper plate of the capacitor c1 is vb+vb1+avd, and the voltage of the upper plate of the capacitor c2 is VB. At this time, the output signal OUT at the gate of NMOS tube m4 will remain at VB+Vb1+AVD. Therefore, the voltage range of the output signal OUT is VB-VB+Vb1+AVDD, and the voltage range of the upper electrode plate of the capacitor c2 is VB-AVDD+VB. In the circuit structure of the embodiment, since VB and VB1 are adjustable voltages, the final output voltage OUT can be changed in a fixed range from 0 to AVDD, the output signal has a larger voltage range, and the adjustable parameters are increased, so that the adjustment range of the output signal of the circuit is also more flexible.
In another embodiment of the present invention, referring to fig. 4, the voltage doubling module 1 includes a second voltage doubling charge pump unit 13 and an inverting unit, the second voltage doubling charge pump unit 13 is connected with the inverting unit, the inverting unit is connected with the pressurizing module 3, the second voltage doubling charge pump unit 13 generates a voltage doubling signal based on a clock signal, the inverting unit performs an inversion process on the voltage doubling signal, and outputs the voltage doubling signal after the inversion process to the pressurizing module 3.
In this embodiment, referring to fig. 4, the second voltage-multiplying charge pump unit 13 is mainly a multiplying charge pump unit, and specifically includes a capacitor C1, a capacitor C2, a PMOS transistor M1 and a PMOS transistor M2, where the capacitor C1 is connected to the CLKP end of the clock module, the capacitor C2 is connected to the CLKN end of the clock module, the other end of the capacitor C1 is connected to the drain of the PMOS transistor M1 and the gate of the PMOS transistor M2, the other end of the capacitor C2 is connected to the gate of the PMOS transistor M1 and the drain of the PMOS transistor M2, the drain and the source of the PMOS transistor M2, and the source of the PMOS transistor M1 are all connected to the inverting unit.
Referring to fig. 4, the inverting unit in this embodiment specifically includes a PMOS transistor M3, an NMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, and an NMOS transistor M8, where sources of the PMOS transistor M1, the PMOS transistor M2, the PMOS transistor M3, the PMOS transistor M5, and the PMOS transistor M7 are connected in series, drains of the PMOS transistor M2 are connected to gates of the PMOS transistor M3 and the NMOS transistor M4, drains of the PMOS transistor M3 and the NMOS transistor M4 are connected to gates of the PMOS transistor M5 and the NMOS transistor M6, drains of the PMOS transistor M5 and the NMOS transistor M6 are connected to gates of the PMOS transistor M7 and the NMOS transistor M8, and sources of the NMOS transistor M4, the NMOS transistor M6, and the NMOS transistor M8 are connected to the booster module 3.
In this embodiment, referring to fig. 4, the boosting module 3 includes a PMOS transistor M1 and an NMOS transistor M2, a first reference voltage VB1 is input to the gate of the PMOS transistor M1, the source of the PMOS transistor M1 is connected to the drains of the PMOS transistor M7 and the NMOS transistor M8, the sources of the NMOS transistor M4, the NMOS transistor M6 and the NMOS transistor M8 are all connected to the source of the NMOS transistor M2, the source of the NMOS transistor M2 is connected to the CLKP end of the clock module, a second reference voltage is input to the gate of the NMOS transistor M2, in this embodiment, the second reference voltage is input through a power supply, the magnitude of the input voltage is the maximum voltage of the signal output by the clock module, and the drains of the PMOS transistor M1 and the NMOS transistor M2 are all connected to the voltage output module 4.
In this embodiment, referring to fig. 4, the voltage output module 4 includes a capacitor c1, a capacitor c2, an NMOS transistor m3 and an NMOS transistor m4, drains of the PMOS transistor m1 and the NMOS transistor m2 are connected to one end of the capacitor c1, the other end of the capacitor c1 is connected to a source of the NMOS transistor m3 and a gate of the NMOS transistor m4, one end of the capacitor c2 is connected to a CLKP end of the clock module, the other end of the capacitor c2 is connected to a gate of the NMOS transistor m3 and a source of the NMOS transistor m4, a drain of the NMOS transistor m3 is connected to a drain of the NMOS transistor m4, and a gate of the NMOS transistor m4 is used for outputting an output signal.
In this embodiment, it is assumed that the voltage between the drain of the PMOS transistor M1 and the drain of the PMOS transistor M2 is VB0, and the voltage between the drain of the NMOS transistor M3 and the drain of the NMOS transistor M4 is VB2. Since CLKN and CLKP are two-phase non-overlapping clocks, it can be deduced that the voltage range at the upper polar plate of the capacitor C2 is 0 to VB0, the high and low levels in the inverting unit are VB0 and VB1 respectively, when the gate inputs of the PMOS transistor M3 and the NMOS transistor M4 are 0, the voltage difference between the gate and the source of the PMOS transistor M3 is VB0, which is greater than the threshold voltage of the PMOS transistor M3, so that the PMOS transistor M3 is turned on, and the NMOS transistor M4 is turned off. At this time, the drain outputs of the PMOS transistor M3 and the NMOS transistor M4 are VB0.
Similarly, when the gate inputs of the PMOS transistor M3 and the NMOS transistor M4 are VB0, the PMOS transistor M3 is turned off, the voltage difference between the gate and the source of the NMOS transistor M4 is |vb0-vb1|, which is greater than the threshold voltage of the NMOS transistor M4, so that the NMOS transistor M4 is turned on, the drain outputs of the PMOS transistor M3 and the NMOS transistor M4 are VB1, and so on, the voltage range of the source of the PMOS transistor M1 is VB1 to VB0. Further deducing that the voltage range of the lower polar plate of the capacitor c1 is 0 to VB0, and the output voltage range output by the grid electrode of the final NMOS tube m4 is VB2-VB1+VB0. Compared with the traditional multiplication type charge pump circuit, the output signal output by the circuit in the embodiment has a larger voltage range, and the adjustable parameters are increased, so that the adjusting range of the output signal of the circuit is more flexible. The charge pump circuit in this embodiment has a finer adjustment range of the output voltage than the charge pump circuit in the first embodiment, and can be set to a voltage within 1 AVDD, but VB0 must be larger than VB1 when setting the voltage.
The invention also discloses equipment, which comprises the charge pump circuit with adjustable voltage shown in fig. 1 or 4, wherein the circuit comprises a voltage doubling module 1, a voltage boosting module 3 and a voltage output module 4, the voltage doubling module 1, the voltage boosting module 3 and the voltage output module 4 are all connected with a clock module, the voltage doubling module 1 is connected with the voltage boosting module 3, the voltage doubling module 1 generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the voltage boosting module 3, the voltage boosting module 3 generates a voltage boosting signal according to the clock signal and the voltage doubling signal and outputs the voltage boosting signal to the voltage output module 4, the voltage output module 4 generates an output signal according to the clock signal and the voltage boosting signal, the voltage doubling processing of the signal by the voltage doubling module 1 and the voltage boosting processing of the signal by the voltage boosting module 3 are carried out, the output signal has a larger voltage range, and the voltage range is larger than twice the voltage range of the clock signal. Because of the increase of the modules in the circuit, the adjustable parameters are increased, so that the adjusting range of the output signal of the circuit is more flexible.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to imply that the scope of the present application is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the spirit of the application, steps may be implemented in any order, and there are many other variations of the different aspects of one or more embodiments described above which are not provided in detail for the sake of brevity.
One or more embodiments herein are intended to embrace all such alternatives, modifications and variations that fall within the broad scope of the present application. Any omissions, modifications, equivalents, improvements, and the like, which are within the spirit and principles of the one or more embodiments in the present application, are therefore intended to be included within the scope of the present application.
Claims (7)
1. A voltage-adjustable charge pump circuit, the circuit comprising a clock module for providing a clock signal, the circuit further comprising: the voltage doubling module, the pressure boosting module and the voltage output module are connected with the clock module, the voltage doubling module is connected with the pressure boosting module, the voltage doubling module generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the pressure boosting module, the pressure boosting module generates a pressure boosting signal according to the clock signal and the voltage doubling signal and outputs the pressure boosting signal to the voltage output module, the voltage output module generates an output signal according to the clock signal and the pressure boosting signal, and the voltage range of the output signal is larger than twice the voltage range of the clock signal.
2. The voltage-adjustable charge pump circuit according to claim 1, wherein the voltage-multiplying module includes a second voltage-multiplying charge pump unit and an inverting unit, the second voltage-multiplying charge pump unit is connected with the inverting unit, the inverting unit is connected with the boosting module, the second voltage-multiplying charge pump unit generates the voltage-multiplying signal based on the clock signal, the inverting unit performs an inverting process on the voltage-multiplying signal, and outputs the voltage-multiplying signal after the inverting process to the boosting module.
3. The voltage-adjustable charge pump circuit according to claim 2, wherein the second voltage-doubling charge pump unit comprises a capacitor C1, a capacitor C2, a PMOS transistor M1 and a PMOS transistor M2, wherein the capacitor C1 is connected to one end of the clock module, the capacitor C2 is connected to the other end of the clock module, the other end of the capacitor C1 is connected to the drain of the PMOS transistor M1 and the gate of the PMOS transistor M2, the other end of the capacitor C2 is connected to the gate of the PMOS transistor M1 and the drain of the PMOS transistor M2, the drain and the source of the PMOS transistor M2, and the source of the PMOS transistor M1 are connected to the inverting unit.
4. The voltage-adjustable charge pump circuit of claim 3, wherein the inverting unit comprises a PMOS transistor M3, an NMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, and an NMOS transistor M8, sources of the PMOS transistor M1, the PMOS transistor M2, the PMOS transistor M3, the PMOS transistor M5, and the PMOS transistor M7 are connected in series, a drain of the PMOS transistor M2 is connected to gates of the PMOS transistor M3 and the NMOS transistor M4, drains of the PMOS transistor M3 and the NMOS transistor M4 are connected to gates of the PMOS transistor M5 and the NMOS transistor M6, drains of the PMOS transistor M5 and the NMOS transistor M6 are connected to gates of the PMOS transistor M7 and the NMOS transistor M8, drains of the PMOS transistor M7 and the NMOS transistor M8, and sources of the NMOS transistor M4, the NMOS transistor M6, and the NMOS transistor M8 are connected to the module.
5. The voltage-adjustable charge pump circuit of claim 4, wherein the voltage boosting module comprises a PMOS transistor M1 and an NMOS transistor M2, a first reference voltage is input to a gate of the PMOS transistor M1, a second reference voltage is input to a gate of the NMOS transistor M2, drains of the PMOS transistor M7 and the NMOS transistor M8 are connected to a source of the PMOS transistor M1, sources of the NMOS transistor M4, the NMOS transistor M6 and the NMOS transistor M8 are connected to a source of the NMOS transistor M2, a source of the NMOS transistor M2 is further connected to one end of the clock module, and drains of the PMOS transistor M1 and the NMOS transistor M2 are connected to the voltage output module.
6. The voltage-adjustable charge pump circuit according to claim 5, wherein the voltage output module comprises a capacitor c1, a capacitor c2, an NMOS transistor m3 and an NMOS transistor m4, wherein drains of the PMOS transistor m1 and the NMOS transistor m2 are connected to one end of the capacitor c1, the other end of the capacitor c1 is connected to a source of the NMOS transistor m3 and a gate of the NMOS transistor m4, one end of the capacitor c2 is connected to one end of the clock module, the other end of the capacitor c2 is connected to the gate of the NMOS transistor m3 and a source of the NMOS transistor m4, a drain of the NMOS transistor m3 is connected to a drain of the NMOS transistor m4, and the gate of the NMOS transistor m4 is used for outputting the output signal.
7. An apparatus comprising a voltage-adjustable charge pump circuit as claimed in any one of claims 1 to 6.
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| CN202310491074.9A CN116505759A (en) | 2023-03-16 | 2023-03-16 | Voltage-adjustable charge pump circuit and equipment |
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| CN202310491074.9A CN116505759A (en) | 2023-03-16 | 2023-03-16 | Voltage-adjustable charge pump circuit and equipment |
| CN202310254947.4A CN115967271B (en) | 2023-03-16 | 2023-03-16 | Voltage-adjustable charge pump circuit and equipment |
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| JP2002026254A (en) * | 2000-07-03 | 2002-01-25 | Hitachi Ltd | Semiconductor integrated circuit and nonvolatile memory |
| US6385065B1 (en) * | 2000-09-14 | 2002-05-07 | Fairchild Semiconductor Corporation | Low voltage charge pump employing distributed charge boosting |
| TW550589B (en) * | 2002-02-18 | 2003-09-01 | Winbond Electronics Corp | Charge pump circuit having clock voltage doubling and the method |
| CN1310410C (en) * | 2002-11-28 | 2007-04-11 | 华邦电子股份有限公司 | Electric charge pumping circuit having time pulse multiplication and process thereof |
| US7760010B2 (en) * | 2007-10-30 | 2010-07-20 | International Business Machines Corporation | Switched-capacitor charge pumps |
| US7602233B2 (en) * | 2008-02-29 | 2009-10-13 | Freescale Semiconductor, Inc. | Voltage multiplier with improved efficiency |
| JP5109187B2 (en) * | 2008-05-13 | 2012-12-26 | ルネサスエレクトロニクス株式会社 | Charge pump |
| US8339183B2 (en) * | 2009-07-24 | 2012-12-25 | Sandisk Technologies Inc. | Charge pump with reduced energy consumption through charge sharing and clock boosting suitable for high voltage word line in flash memories |
| CN101694961A (en) * | 2009-09-18 | 2010-04-14 | 和芯微电子(四川)有限公司 | Low ripple wave boosting type charge pump |
| US8836412B2 (en) * | 2013-02-11 | 2014-09-16 | Sandisk 3D Llc | Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple |
| US8981835B2 (en) * | 2013-06-18 | 2015-03-17 | Sandisk Technologies Inc. | Efficient voltage doubler |
| CN204361895U (en) * | 2014-12-02 | 2015-05-27 | 无锡市南长区科技创业服务中心 | Drive pressurizer |
| US9602921B2 (en) * | 2015-06-24 | 2017-03-21 | Robert Bosch Gmbh | Independently charge pumps for differential microphone |
| CN108075654A (en) * | 2016-11-15 | 2018-05-25 | 合肥科盛微电子科技有限公司 | The supply voltage amplifier of New Charge pump configuration |
| CN108696118B (en) * | 2017-04-07 | 2020-12-08 | 原相科技(槟城)有限公司 | Boosting circuit and method for biasing substrate therein |
| CN109842290A (en) * | 2017-11-24 | 2019-06-04 | 北京兆易创新科技股份有限公司 | A kind of high pressure bleeder circuit, charge pump circuit and NOR FLASH |
| CN108646841A (en) * | 2018-07-12 | 2018-10-12 | 上海艾为电子技术股份有限公司 | A kind of linear voltage-stabilizing circuit |
| CN111313568B (en) * | 2020-03-13 | 2022-03-25 | 华中科技大学 | Energy acquisition circuit for wearable equipment and power management circuit thereof |
| CN215498731U (en) * | 2021-02-07 | 2022-01-11 | 南京威派视半导体技术有限公司 | Voltage-stabilizing charge pump circuit for outputting negative voltage |
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| CN115967271B (en) | 2023-05-30 |
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