CN116501261A - Combined coding method of content addressable memory - Google Patents

Combined coding method of content addressable memory Download PDF

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CN116501261A
CN116501261A CN202310574759.XA CN202310574759A CN116501261A CN 116501261 A CN116501261 A CN 116501261A CN 202310574759 A CN202310574759 A CN 202310574759A CN 116501261 A CN116501261 A CN 116501261A
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entry
memory
cam
feature
memory cells
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黄如
徐伟凯
黄芊芊
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Peking University
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Peking University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)

Abstract

The invention provides a combined coding method of a content addressable memory, belonging to the technical field of novel storage and calculation. The invention discloses a combined coding method for realizing a configurable multi-feature content addressable memory based on a nonvolatile memory, which is characterized in that a plurality of nonvolatile memory devices are used as a group for combined coding, and compared with the traditional implementation mode of using two nonvolatile memory devices to store complementary information to represent 1-bit entry information, the combined coding method improves coding efficiency, namely, more entry states are coded by the same number of memory devices. The invention can not only improve the coding efficiency of the CAM based on the nonvolatile memory, but also configure the feature number of the CAM according to the actual requirement, so that the CAM can be more flexibly used for different search systems, and correspondingly, higher search speed and energy efficiency can be brought.

Description

Combined coding method of content addressable memory
Technical Field
The invention relates to the technical field of novel storage and computation, in particular to a combined coding mode for realizing a configurable multi-feature content addressable memory based on a nonvolatile memory.
Background
Content Addressable Memory (CAM) can perform search operations efficiently and in parallel, and is widely used in applications such as table look-up operations, data caching, database searching, etc. associated with packet forwarding and classification in network routers. CAM is a special type of memory for parallel searching that can perform unique search operations in addition to read and write operations with conventional memory. CAM can complete a search operation of the entire memory array in one clock cycle, making it significantly more efficient than other hardware or software based search systems, and has been successfully used in modern routers and the like. With the advent of the smart internet of everything age, the number of Internet Protocol (IP) addresses has been exponentially increasing, and has transitioned from internet protocol version 4 (IPv 4) with a 32-bit address length to internet version 6 (IPv 6) with a 128-bit address length, and an increase in the amount of data has put higher demands on the storage density, speed and energy efficiency of CAM. In the big data age, since CAM enables high-speed parallel search operations, applications in the fields of machine learning, image, DNA sequencing and biomedical are widely studied and explored. The main difference between the method and the traditional routing table lookup application is that the characteristics of each dimension are not only in 0 and 1 states, for example, 4 base types in DNA sequencing and 20 amino acid types in protein detection, and new requirements are put on the characteristic expansion of the CAM dimension.
CAM designs based on conventional Static Random Access Memories (SRAM) occupy a large cell area, and as moore's law evolves, it is difficult to increase density by continuing to shrink device dimensions, and the resulting larger parasitic capacitance further increases search latency and power consumption. CAM is designed with reduced cell area and search latency and power consumption based on various nonvolatile memories, such as Resistive Random Access Memory (RRAM), phase Change Memory (PCM), and ferroelectric field effect transistor (FeFET) and Flash memory (Flash), among others. However, the CAM design of the present nonvolatile memory mainly uses a traditional SRAM-based implementation manner, that is, two nonvolatile memory cells for storing complementary information replace an SRAM cell with two complementary memory nodes to represent an entry, and a linear inseparable comparison operation of a 1-bit binary input query and the memory entry is implemented in combination with complementary inputs. However, this coding scheme is wasteful for the nonvolatile memory, which inevitably limits further improvement of the density and energy efficiency of CAM, and can only expand bit by bit in binary pattern form when dimension feature expansion is performed for applications requiring multi-feature CAM such as DNA sequencing, protein detection, and the like, which further brings about waste of hardware overhead. Therefore, in combination with the characteristics of the nonvolatile memory, more effective and configurable coding design is performed according to different application requirements, and the method has important significance for further improving the performance of the configurable multi-feature CAM search system based on the nonvolatile memory.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a combined coding method for realizing the configurable multi-feature content addressable memory based on the nonvolatile memory, which breaks through the coding mode for realizing the CAM based on the traditional SRAM, adopts an optimized configurable combined coding mode, not only can improve the coding efficiency of the CAM based on the nonvolatile memory, but also can configure the feature number of the CAM according to the actual requirement, so that the CAM can be more flexibly used for different search systems, and correspondingly can bring higher search speed and energy efficiency.
The technical scheme of the invention is as follows:
a method for combined coding of content addressable memory is characterized by that,
1) The configurable multi-feature CAM array based on the nonvolatile memory device adopts a conventional NOR type memory array, and each memory cell can be a 1T1R structure formed by connecting an RRAM or PCM in series through a field effect transistor, or a 1F structure formed by FeFET or Flash. The gate of the field effect transistor 1T1R or 1F is a Search Line (SL), one SL is shared by each column of the CAM array; the drain of the field effect transistor 1T1R or 1F is a Match Line (ML), one ML is shared by each row of the CAM array; one end of RRAM or PCM in 1T1R is connected with the source electrode of the field effect transistor, the other end is grounded, and the source electrode of 1F is grounded.
2) Each nonvolatile memory device may store data "0" or "1", where "0" corresponds to a low resistance state of RRAM, PCM, or FeFET, flash, a "1" represents a high configuration of RRAM, PCM, or a high threshold state of FeFET, flash. When the entry information is stored, according to the characteristic number K required by the CAM, N storage devices are used as a group for combined coding, if N is even, N/2 of the N storage devices are optionally programmed into data 0, and the rest N/2 devices are programmed into data 1; if N is odd, N-1/2 of N devices are optionally programmed to be data "0", and the remaining (n+1)/2 devices are programmed to be data "1", each programming mode represents an entry state, and the number of entry states that N memory devices can represent is(N is even) or->(N is an odd number). N is chosen such that->(N is even) or->(N is an odd number) is greater than K. The coding scheme of the search query corresponds to the coding scheme of the memory entry, that is, N inputs are "0" and "1", respectively, "0" represents an input low voltage, "1" represents an input high voltage, and the same search query is identical to the positions of "0" and "1" in the memory entry. In addition, when all of the N memory devices are stored as "1", it means that the multi-feature CAM matches any input feature, denoted by entry "X"; similarly, when all N inputs are "0", this indicates that the input feature matches for any stored feature, denoted by query "X".
3) During search operation, the voltage of ML is pre-charged to a high level, then a voltage signal consistent with a search query is applied to SL, for an array based on RRAM or PCM, a field effect transistor with low voltage SL is in an off state, a field effect transistor with high voltage SL is in an on state, only when the memory entry is the same as the search query, RRAM or PCM connected with the on field effect transistor is in a high resistance state, the high level of ML can be maintained, otherwise, at least one on field effect transistor is connected to a low resistance state, so that ML is discharged to the low level very quickly; for FeFET or Flash based 1F arrays, only when the memory entry is consistent with the search query, the low voltage SL acts on the low threshold state 1F, the high voltage SL acts on the high threshold state 1F, i.e., all 1F are off, so that ML remains high, otherwise there would be at least one high voltage SL acting on the low threshold state 1F, so that ML discharges to a low level through this on 1F. Therefore, the precharged ML can be kept high only when the search query is consistent with the memory entry, indicating a match; otherwise ML would go low, indicating a mismatch.
4) The configurable combined coding mode provided by the invention not only can expand the feature number of the CAM, but also can further expand the dimension number for combined coding, if the dimension of the entry to be stored is W and the feature of each dimension is K, the minimum N which enables the formula (1) to be established can be taken, namely W/N K feature entries are realized by taking N storage devices as a group, the entry storage with the dimension W is further realized by N groups in a bit expansion mode, and when n=1, the maximum N is corresponded to max I.e. in N max The K characteristic entry storage with the dimension W can be realized by a group of storage devices.
In summary, the present invention provides a combined encoding method for implementing a configurable multi-feature content addressable memory based on a nonvolatile memory, wherein the nonvolatile memory can be various nonvolatile two-end resistance variable memories such as RRAM or PCM, feFET and Flash, and the ferroelectric material can be HfO 2 Zr (HZO) and HfO doped 2 Al (HfAlO) doped with various HfO 2 The doped ferroelectric material can also be perovskite type ferroelectric (such as PZT, BFO, SBT, etc.), ferroelectric polymer (such as P (VDF-TrFE), etc.), etcThe ferroelectric material and the device gate stack may be based on a variety of structures such as MFMIS, MFIS, MFS.
The invention has the following technical effects:
1. the combination coding mode for realizing the configurable multi-feature content addressable memory based on the nonvolatile memory uses a plurality of nonvolatile memory devices as a group for combination coding, and compared with the traditional implementation mode for storing complementary information to represent 1-bit entry information by using two nonvolatile memory devices, the combination coding mode improves coding efficiency, namely, codes more entry states by using the same number of memory devices, and can further improve the storage density of CAM based on the emerging nonvolatile memory.
2. The combination coding mode for realizing the configurable multi-feature content addressable memory based on the nonvolatile memory provided by the invention reduces the number of memory devices required when realizing the entry memory with the same dimension and feature, reduces the total capacitance of ML, and obviously reduces both search delay and search power consumption.
3. The combination coding mode for realizing the configurable multi-feature content addressable memory based on the nonvolatile memory can flexibly configure the number of combination codes N according to application requirements, can carry out combination coding on feature numbers required by the CAM, can further carry out combination coding on the multidimensional CAM, and is flexible in application.
Drawings
FIG. 1 is a schematic diagram of an array structure and a memory cell structure of a combined coding scheme for implementing a configurable multi-feature content addressable memory based on a non-volatile memory according to the present invention;
FIG. 2 is a schematic diagram of a specific implementation of a combination encoding method for implementing a configurable multi-feature content addressable memory based on a non-volatile memory according to the present invention, where the combination encoding is performed by taking a group of 3 and 4 memory devices as an example;
Detailed Description
The present invention will be further clarified and fully explained by the following detailed description of embodiments, which are to be taken in connection with the accompanying drawings.
The schematic diagram of the array structure and the memory cell structure of the combination coding mode for realizing the configurable multi-feature content addressable memory based on the nonvolatile memory is shown in fig. 1, the CAM array based on the nonvolatile memory device adopts a conventional NOR type memory array, each memory cell can be a 1T1R structure formed by connecting a field effect transistor in series with an RRAM or PCM, and can also be a 1F structure formed by a FeFET or Flash, each row of the CAM array shares an ML, and each column shares an SL. During search operation, firstly charging ML of each row to a high level through a precharge circuit, then applying corresponding search voltage to SL of each column according to a search query, and completing search operation of the whole CAM array in parallel, wherein only ML corresponding to entry consistent with the search query is stored to maintain the high level in the search process, so that matching is indicated; the ML corresponding to the row for which the search query does not match will go low during the search.
Fig. 2 is a schematic diagram of a specific implementation of the present embodiment when the combination coding mode of the configurable multi-feature content addressable memory is implemented based on a nonvolatile memory, and the combination coding mode is implemented by taking a group of 3 and 4 memory devices as an example. Taking 3 memory devices as a group, arbitrarily selecting 1 memory device from the group to program as '1', corresponding to the low resistance state of RRAM and PCM or the high threshold state of FeFET and Flash; the other two memory devices are programmed to be "0", corresponding to the high resistance state of RRAM, PCM or the low threshold state of FeFET, flash, there are three different combined encoding modes, representing memory entries "0" to "2", respectively, so that CAM with three features can be realized. The encoding scheme of the search query is identical to that of the memory entry, i.e., two inputs are "0" indicating that the SL is applied low during search, and the other input is "1" indicating that the SL is applied high during search. If all three memory devices are programmed to "1" memory entry "X", this indicates that all inputs match; if all three inputs are "0", meaning that the input is "X", then all match for any memory entry. If 4 memory devices are grouped, any two memory devices are selected to be programmed as '1', and the other two memory devices are programmed as '0', then entry '0' to '5' can be stored, and CAM with feature numbers of 4, 5 or 6 can be used. As can be seen from fig. 2, only when the search query is consistent with the memory entry, the high SL acts on the memory state "1" of the memory device at the same time, and for the 1T1R structure, the memory device connected to the on transistor is in the high resistance state, and for the 1F structure, the 1F in the high threshold state is in the off state; while two low-level SLs act on the memory state "0" of the memory device at the same time, so that the field effect transistor or 1F in the 1T1R structure is turned off, and therefore ML will remain high during the search process, indicating that the search results are matched. If the search query is inconsistent with the memory entry, at least one high-level SL acts on the memory state "0" of the memory device, so that the on-state field effect transistor in the 1T1R structure is connected with the memory device in a low-resistance state or the 1F in a low-threshold state is on, and ML can be discharged to a low level through the RRAM or the PCM in the low-resistance state or the on 1F in the searching process to indicate mismatching. For the combination coding of dimension expansion, the expansion can be performed by increasing the number of a group of memory cells for combination coding and connecting a plurality of memory cell combinations for combination coding in parallel, and only when all the memory cell combinations for combination coding in one row are matched, the ML can keep high level in the searching process, and if any combination has any mismatch, the ML can be reduced to low level in the searching process, which indicates that the coding mode can lead the CAM based on the nonvolatile memory to work correctly.
The embodiment fully and specifically explains a combined coding mode for realizing the configurable multi-feature content addressable memory based on the nonvolatile memory, and compared with the coding mode adopting the traditional CAM based on the SRAM at present, the coding mode provided by the invention improves the coding efficiency and the coding flexibility of the multi-feature CAM, thereby improving the searching speed and the energy efficiency of the CAM array under the same scale.
Finally, it should be noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.

Claims (3)

1. A method for combinatorial coding of a content addressable memory, comprising the steps of:
1) The CAM array adopts a conventional NOR type memory array, each memory cell is a 1T1R structure formed by serially connecting a field effect transistor with an RRAM or PCM, or a 1F structure formed by a FeFET or Flash, each column of the CAM array shares a search line SL, and each row of the CAM array shares a matching line ML;
2) Each memory cell stores data of 0 or 1, wherein 0 corresponds to a low resistance state of RRAM and PCM or a low threshold state of FeFET and Flash, 1 represents a high configuration of RRAM and PCM or a high threshold state of FeFET and Flash, when the entry information is stored, N memory cells are combined and encoded as a group according to a characteristic number K required by CAM, if N is even, N/2 memory cells are optionally programmed into data of 0, and the rest N/2 memory cells are programmed into data of 1; if N is odd, optionally (N-1)/2 of the N memory cells are programmed to be data "0", the rest of the (N+1)/2 memory cells are programmed to be data "1", each programming mode represents an entry state, and when N is even, the number of entry states represented by the N memory cells isWhen N is odd, N memory cells represent entry states of +.>Said->Or->A minimum N greater than K;
3) The coding mode of the search query corresponds to the coding mode of the storage entry, namely N inputs are respectively 0 and 1, 0 represents input low voltage, 1 represents input high voltage, the same search query is consistent with the positions of 0 and 1 in the storage entry, and when all N storage units are stored as 1, the multi-feature CAM is matched with any input feature and is represented by entry X; similarly, when all N inputs are "0", it means that the input features match for any storage feature, denoted by query "X";
4) During searching operation, the voltage of the ML is pre-charged to a high level, then a voltage signal consistent with a search query is applied to the SL, and the pre-charged ML can keep the high level only when the search query is consistent with a storage entry, so that matching is indicated; otherwise ML would go low, indicating a mismatch.
2. The method of claim 1, wherein if the dimension of the entry to be stored is W, the feature of each dimension is K, and N groups of entries with dimension W are implemented, the minimum N is calculated by equation (1), i.e. W/N K features are implemented by using N storage units as a group
3. The method of claim 1, wherein the gate of the field effect transistor 1T1R or 1F is a search line SL, the drain of the field effect transistor 1T1R or 1F is a match line ML, the RRAM or PCM in 1T1R has one end connected to the source of the field effect transistor, the other end grounded, and the source of 1F is grounded.
CN202310574759.XA 2023-05-22 2023-05-22 Combined coding method of content addressable memory Pending CN116501261A (en)

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