CN116489526A - Driving method and driving device of image sensor and image sensor - Google Patents
Driving method and driving device of image sensor and image sensor Download PDFInfo
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- CN116489526A CN116489526A CN202210034265.8A CN202210034265A CN116489526A CN 116489526 A CN116489526 A CN 116489526A CN 202210034265 A CN202210034265 A CN 202210034265A CN 116489526 A CN116489526 A CN 116489526A
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Abstract
The invention describes a driving method of an image sensor, comprising the following steps: acquiring a pre-exposure row address digital signal, a sampling row address digital signal, a pre-exposure row transmission digital signal and a sampling row transmission digital signal, outputting a pre-exposure row address analog signal, a sampling row address analog signal, a pre-exposure row transmission analog signal and a sampling row transmission analog signal through a voltage level converter, and outputting a latch address analog signal based on the analog signals; the gate transfer control signal is output based on the pre-exposure line address analog signal, the sampling line address analog signal, the pre-exposure line transfer analog signal, the sampling line transfer analog signal, and the latch address analog signal. The invention also provides a driving device of the image sensor and the image sensor comprising the driving device. The invention can realize smaller design area and power consumption, save the number of voltage level converters and reduce hardware cost.
Description
Technical Field
The present invention relates to the field of image sensors, and more particularly, to a driving method and device for an image sensor, and an image sensor including the driving device.
Background
With the day-to-day age of intellectualization, cameras are well-known to consumers, and the photographing performance has a direct relationship with CMOS Image Sensor (CIS) chips.
Currently, exposure modes of image sensors can be classified into a rolling exposure mode (rolling shutter) and a global exposure mode (global shutter).
For the rolling exposure mode, the exposure time or the time period of each row of the pixel array is different, only one row is in a reading state at the same time, in order to ensure that the time sequence is correct, a part of rows of pixels are in a state of not exposing and not reading, and for the global exposure mode, each row of the pixel array is simultaneously exposed and is read in different time periods, so that in the reading state of one pixel row, other pixel rows are equivalent to being in an idle state.
Therefore, controlling each row of pixel rows requires a plurality of control signals, which are input by an external control unit, which means that each row of pixel rows requires a plurality of voltage level shifters, which further increases the hardware overhead for a pixel array made up of a plurality of rows and columns.
Disclosure of Invention
In view of the above, the present invention provides a driving method of an image sensor, and an image sensor including the driving method of the image sensor.
The invention provides a driving method of an image sensor, comprising the following steps: acquiring a pre-exposure line address digital signal (d_sp_add), a sampling line address digital signal (d_rp_add), a pre-exposure line transmission digital signal (d_sp_tx) and a sampling line transmission digital signal (d_rp_tx), and outputting a pre-exposure line address analog signal (a_sp_add), a sampling line address analog signal (a_rp_add), a pre-exposure line transmission analog signal (a_sp_tx) and a sampling line transmission analog signal (a_rp_tx) through a voltage level shifter (level shift);
outputting a latch address analog signal (a_lat_addb) based on the pre-exposure line address analog signal (a_sp_add), the sampling line address analog signal (a_rp_add), the pre-exposure line transfer analog signal (a_sp_tx), and the sampling line transfer analog signal (a_rp_tx);
outputting a gate transmission control signal based on the pre-exposure line address analog signal, the sampling line address analog signal, the pre-exposure line transmission analog signal, the sampling line transmission analog signal and the latch address analog signal;
the gate transmission control signal is used for controlling the on and off of a transmission transistor in a pixel circuit of the image sensor.
The present invention also provides a driving apparatus of an image sensor, comprising: the control module is coupled with the driving module, wherein the control module at least comprises an inversion adjusting module, and the driving module at least comprises a grid driving module;
the driving device further comprises a voltage level converter, wherein the voltage level converter is used for outputting a pre-exposure line address analog signal, a sampling line address analog signal, a pre-exposure line transmission analog signal and a sampling line transmission analog signal according to the pre-exposure line address digital signal, the sampling line address digital signal, the pre-exposure line transmission digital signal and the sampling line transmission digital signal;
the reverse phase adjusting module is used for outputting a latch address analog signal according to the exposure row address analog signal, the sampling row address analog signal, the exposure row transmission analog signal and the sampling row transmission analog signal;
the grid driving module is used for outputting a grid transmission control signal according to the exposure row address analog signal, the sampling row address analog signal, the exposure row transmission analog signal, the sampling row transmission analog signal and the latch address analog signal; the gate transmission control signal is used for controlling the on and off of the transmission transistor of the pixel unit.
The invention also provides an image sensor including the driving method of the image sensor, comprising: the pixel array includes a plurality of pixel units arranged in rows and columns, and each pixel unit includes: a photodiode for accumulating image charges in response to incident light, and a transfer transistor coupled between the photodiode and the floating diffusion node to selectively transfer the image charges accumulated in the photodiode to the floating diffusion node; and the control module is used for determining the state of the pixel rows of the pixel array.
Compared with the prior art, the invention has at least one of the following outstanding advantages:
the pixel circuit driving method avoids the generation of latch address analog signals by latch mode control, directly realizes a transmission transistor driving circuit through analog level logic, and further generates a transmission transistor control signal with a latch function to optimize pixel bloom.
Drawings
FIG. 1 is a schematic diagram of a pixel circuit of an image sensor in the prior art;
FIG. 2 is a prior art method of driving an image sensor;
FIG. 3 is a flow chart of a driving method of an image sensor according to the present invention;
FIG. 4 is a block diagram of a portion of an image sensor according to the present invention;
FIG. 5 is a block diagram illustrating a portion of another image sensor according to the present invention;
FIG. 6 is a schematic diagram of a partial structure of an image sensor according to the present invention;
FIG. 7 is a timing control diagram of an image sensor driving method according to the present invention;
FIG. 8 is a timing control diagram of an example of an image sensor driving method according to the present invention;
FIG. 9 is a schematic diagram of a pixel circuit of an image sensor according to the present invention;
fig. 10 is a flowchart of another driving method of an image sensor according to the present invention.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a further description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
It is noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than those herein described, and those skilled in the art may readily devise numerous other arrangements that do not depart from the spirit of the invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.
As shown in fig. 1, fig. 1 is a schematic structural diagram of an image sensor in the prior art. The image sensor includes a pixel array 10, a control module 20, and a driving module 30, wherein the control module 20 is coupled to the driving module 30 for determining a state of a pixel row of the pixel array 10, the pixel array 10 includes a plurality of pixel units arranged in rows and columns, in which all pixels (pixel units) of each column are simultaneously gated through a column selection line, and all pixels of each row are selectively output through a row selection line, respectively. Each pixel has a row address and a column address. The column address of the pixel corresponds to the column selection signal line driven by the column driving unit, and the row address of the pixel corresponds to the row selection signal line driven by the row driving unit. The control module controls the row driving unit and the column driving unit to selectively read pixels corresponding to appropriate rows and columns in the pixel array to output image signals.
Fig. 2 is a driving method of an image sensor in the prior art, and referring to fig. 1-2, the control module 20 acquires a pre-exposure row address digital signal (d_sp_add), a sampling row address digital signal (d_rp_add), a pre-exposure row transmission digital signal (d_sp_tx), and a sampling row transmission digital signal (d_rp_tx), and acquires a latch address digital signal (d_lat_add) through the latch unit 40 and the latch enable signal (lat_en), the latch address digital signal (d_lat_add) is converted into a corresponding latch address analog signal (a_lat_add) through the voltage level converter level shift, and the pre-exposure row address digital signal (d_sp_add), the sampling row address digital signal (d_rp_add), the pre-exposure row transmission digital signal (d_sp_tx), and the sampling row transmission digital signal (d_tx) are also converted into a corresponding latch address analog signal (a_lat_add), and the sampling row transmission analog signal (sp_add) through the voltage level converter level shift, and the sampling row transmission analog signal (sp_add) are further controlled by the control transistor. Whereas controlling each row of pixel rows requires a plurality of control signals, which are input by an external control unit, which means that each row of pixel rows requires a plurality of voltage level shifters, which further increases the hardware overhead for a pixel array consisting of a plurality of rows and columns.
In view of the above, the technical scheme of the invention provides a driving method and a driving device for an image sensor and the image sensor comprising the driving device, so as to realize smaller design area and power consumption, save the number of voltage level converters and further reduce hardware cost.
As shown in fig. 3-4, fig. 3 is a flow chart of a driving method of an image sensor provided by the present invention, and fig. 4 is a partial block diagram of an image sensor provided by the present invention, where the driving method of an image sensor provided by the present invention includes the steps of:
s10: the method comprises the steps of obtaining a pre-exposure row address digital signal, a sampling row address digital signal, a pre-exposure row transmission digital signal and a sampling row transmission digital signal, and outputting a pre-exposure row address analog signal, a sampling row address analog signal, a pre-exposure row transmission analog signal and a sampling row transmission analog signal through a voltage level converter.
It will be appreciated that the voltage level shifter enables devices with different I/O voltages to establish communication, and in an electronic design, the voltage level shifter is used to shift the digital level of the row address circuit in the image sensor control circuit to a higher analog level or the digital level of the column address circuit in the image sensor control circuit to a higher analog level, for example, the digital level is 0-1.8V, and the analog level corresponding to the output after passing through the voltage level shifter is 0-2.8V, and of course, the analog level to be output can be set according to the circuit design requirement, which is not limited herein.
S20: outputting a latch address analog signal based on the pre-exposure line address analog signal, the sampling line address analog signal, the pre-exposure line transmission analog signal, and the sampling line transmission analog signal;
s30: outputting a gate transfer control signal tx based on the pre-exposure line address analog signal, the sampling line address analog signal, the pre-exposure line transfer analog signal, the sampling line transfer analog signal, and the latch address analog signal;
the gate transmission control signal TX is used for controlling the on and off of the transmission transistor TX in the pixel circuit of the image sensor.
Fig. 5 is a partial block diagram of another image sensor according to the present invention, as shown in fig. 5. The pre-exposure row address analog signals include a pre-exposure row address forward signal (sp_add) and a pre-exposure row address reverse signal (sp_addb), the sampling row address analog signals include a sampling row address forward signal (rp_add) and a sampling row address reverse signal (rp_addb), the pre-exposure row transmission analog signals include a pre-exposure row transmission forward signal (sp_tx) and a pre-exposure row transmission reverse signal (sp_txb), and the sampling row transmission analog signals include a sampling row transmission forward signal (rp_tx) and a sampling row transmission reverse signal (rp_txb). It should be noted that, the forward signal and the reverse signal are analog signals, and are not described in detail later.
Thus, the method of outputting the gate transfer control signal tx may include: the gate transfer control signal tx is output to the transfer transistor of the pixel unit within the pixel array based on the pre-exposure row address forward signal (sp_add), the pre-exposure row address reverse signal (sp_addb), the sampling row address forward signal (rp_add), the sampling row address reverse signal (rp_addb), the pre-exposure row transfer forward signal (sp_tx), the pre-exposure row transfer reverse signal (sp_txb), the sampling row transfer forward signal (rp_tx), the sampling row transfer reverse signal (rp_txb), and the latch address analog signal.
In the embodiment of the invention, the digital signals output by the row address circuit in the control module are converted into the analog signals through the voltage level converter, and the analog signals correspondingly output by the row address circuit are utilized to output the latch address analog signals, so that the number of the voltage level converters is reduced, and the hardware cost is further reduced.
Next, a driving method of the corresponding image sensor will be described in specific embodiments. Fig. 6 is a schematic diagram of a partial structure of an image sensor according to the present invention, as shown in fig. 6. Wherein the control module 20 is coupled to the driving module 30, and is used for determining the state of the pixel rows of the pixel array; the control module 20 at least includes an inversion adjustment module 50 to output a latch address analog signal (lat_addb), specifically, the inversion adjustment module 50 outputs the latch address analog signal (lat_addb) based on the exposure line address analog signal, the sampling line address analog signal, the exposure line transmission analog signal, and the sampling line transmission analog signal;
the driving module 30 at least includes a gate driving module 60 for controlling on and off of the transmission transistor of the pixel unit, and specifically, the gate driving module 60 outputs a gate transmission control signal TX based on the exposure row address analog signal, the sampling row address analog signal, the exposure row transmission analog signal, the sampling row transmission analog signal, and the latch address analog signal, wherein the gate transmission control signal TX is used for controlling on and off of the transmission transistor TX of the pixel unit.
The image sensor further includes a voltage level shifter (not shown in the figure) that outputs a pre-exposure line address analog signal, a sampling line address analog signal, a pre-exposure line transmission analog signal, and a sampling line transmission analog signal based on the pre-exposure line address digital signal, the sampling line address digital signal, the pre-exposure line transmission digital signal, and the sampling line transmission digital signal;
alternatively, in some embodiments, as shown in fig. 6, the inverting adjustment module 50 includes a first inverter I1, a second inverter I2, and a third inverter I3; the input end of the first inverter I1 receives an exposure row address analog signal, a sampling row address analog signal, an exposure row transmission analog signal and a sampling row transmission analog signal, the output end of the first inverter I1 is coupled with the input end of the second inverter I2, and the output end of the second inverter I2 outputs a latch address analog signal; the input end of the third inverter I3 is coupled to the output end of the first inverter I1 and the input end of the second inverter I2, and the output end of the third inverter I3 is coupled to the input end of the first inverter I1.
Alternatively, referring to fig. 6 and fig. 7 in combination, fig. 7 is a timing control diagram of an image sensor driving method according to the present invention. The control module 20 further includes a first control path 221 and a second control path 222; the first control path 221 is used for controlling the inverting adjustment module 50 to output a latch address analog signal (lat_addb) to a second latch level; the second control path 222 is configured to control the inverting adjustment module 50 to output the latch address analog signal (lat_addb) as a first latch level, wherein the first latch level is a low level, and the second latch level is a high level; further alternatively, the first control path 221 includes two PMOS transistors, and gates of the two PMOS transistors are respectively connected to the pre-exposure row address inversion signal (sp_addb) and the pre-exposure row transmission inversion signal (sp_txb); the second control path 222 includes two NMOS transistors, and the two NMOS transistors are connected to the sample row address forward signal (rp_add) and the sample row transfer forward signal (rp_tx), respectively.
I.e., a method of correspondingly outputting a latch address analog signal, comprising: the latch address analog signal (lat_addb) is output based on the pre-exposure row address inversion signal (sp_addb), the pre-exposure row transmission inversion signal (sp_txb), the sampling row address forward signal (rp_add), and the sampling row transmission forward signal (rp_tx).
Specifically, when the pre-exposure row address reverse signal (sp_addb) and the pre-exposure row transmission reverse signal (sp_tx) are at a low level, the voltage at the point a is pulled up to AVDD, the inverter I1 and the inverter I2 are adopted to drive the point a, and the positive feedback inverter I3 is added to avoid the point a from becoming a floating point, so that even if the pre-exposure row address reverse signal (sp_addb) and the pre-exposure row transmission reverse signal (sp_tx) are restored to a high level, the level a remains high until both the sampling row address forward signal (rp_add) and the sampling row transmission forward signal (rp_tx) are at a high level, the voltage at the point a is pulled down to AGND, and the latch address analog signal (lat_addb) obtained by driving the point a cooperates with the pre-exposure row address signals (sp_add, sp_addb), the pre-exposure row transmission signals (sp_tx ), the sampling row address signal (rp_add), the sampling row address signal (rp_addb) and the sampling row transmission forward signal (rp_tx) are turned on and off, and the gate transmission control transistor is turned on.
In the embodiment of the invention, under the control of the plurality of analog signals and the action of the inversion adjusting module, the latch address analog signal is low level when the pixel row is in the idle state, and is high level in other states, or can be high level in the idle state, and is low level in other states, and the latch address analog signal in the idle state and the latch address analog signal in other states are only needed to be inverted signals. And then outputting the latch address analog signal to the driving module, and matching the exposure row address signal, the pre-exposure row transmission signal, the sampling row address signal and the sampling row transmission signal to enable the driving module to output the grid transmission control signal tx to the transmission transistor of the pixel row in an idle state.
Fig. 9 is a schematic diagram of a pixel circuit of an image sensor according to the present invention. Each pixel unit in the pixel array includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor RS. During operation of the image sensor, the photodiode PD generates photoelectric charges in response to incident light, and the transfer transistor TX receives a transfer signal TX such that the transfer transistor TX transfers charges accumulated in the photodiode PD to the floating diffusion FD. The reset transistor RST is coupled between the power supply VDD and the floating diffusion FD to reset the pixel cell in response to a reset signal RST. The floating diffusion FD is coupled to control the gate of the source follower transistor SF. The source follower transistor SF is also coupled between the power supply VDD and the row select transistor RS to amplify a signal generated by the charge on the floating diffusion FD. The row selection transistor RS outputs a corresponding pixel signal in response to the row selection signal RS.
It will be appreciated that the exposure period begins when the transfer transistor TX is turned off, during which time the photodiode PD receives incident light to accumulate photo-generated electrons, and the voltage at the photodiode PD decreases as electrons are negative charge carriers. After the exposure period is ended, the transfer transistor TX is turned on, coupling the charge in the photodiode PD to the floating diffusion FD, thereby dropping the voltage of the floating diffusion FD.
Meanwhile, states of the pixel rows of the pixel array include an idle state, a precharge state, an exposure (exposure) state, and a sampling (sample) state; wherein, the row address between the exposure row address analog signal and the read row address analog signal is determined as the pixel row in the exposure state, the row address receiving the pre-exposure row address analog signal is determined as the pixel row in the pre-charge state, the row address receiving the sampling row address analog signal is determined as the pixel row in the sampling state, and the pixel rows not in the pre-charge state, the exposure state and the sampling state are determined as the pixel row in the idle state.
Because each row of pixels has the above-mentioned various states, the time sequence characteristic of rolling exposure and the long and short exposure characteristic in the HDR mode, the pixels of the pixel row in the idle state can continuously receive the incident light to generate charges, and the overexposure phenomenon occurs, so that the charges overflow to the pixels of the adjacent row to affect the charge accumulation of the pixels of the adjacent pixel row in the normal exposure state.
Therefore, the technical scheme of the invention can also solve the influence of the pixels of the pixel row in the idle state on the pixels of the adjacent pixel row, and plays a role in anti-blooming.
In the embodiment of the invention, the digital signals output by the row address circuit are converted into analog signals through the voltage level converter, and the analog signals correspondingly output by the row address circuit are utilized to output the latch address analog signals, so that the number of the voltage level converters is reduced, the hardware cost is further reduced, meanwhile, the transmission control signals of the grid are output in a matched mode based on the analog signals correspondingly output by the row address circuit and the latch address analog signals, the on and off of the transmission transistors in the exposure process of the pixel units are further controlled, the overexposure phenomenon generated by the pixel units is reduced, and the halation phenomenon caused when the pixel units in an idle state are irradiated by strong light is solved.
In some embodiments, with continued reference to fig. 6, the optional gate drive module 60 includes: a first path 301 for controlling on and off of transfer transistors of a pixel row in a precharge state in the pixel array; a second path 302 for controlling on and off of the transfer transistors of the pixel rows in the pixel array in the sampling state; and a third path 303 for controlling the on and off of the pass transistors of the pixel rows in the pixel array in the idle state. The first path 301, the second path 302 and the third path 303 respectively comprise two PMOS transistors and three NMOS transistors;
the two PMOS transistors of the first path 301 are used for controlling the output gate transmission control signal to be an on voltage so as to turn on the transmission transistor, and the gates of the two PMOS transistors of the first path 301 are respectively connected with the pre-exposure row transmission reverse signal and the pre-exposure row address reverse signal; the three NMOS transistors of the first path 301 are used for controlling the output gate transmission control signal to be a turn-off voltage, so as to turn off the transmission transistor, and the gates of the three NMOS transistors of the first path 301 are respectively connected with the pre-exposure row address forward signal, the latch address analog signal and the pre-exposure row transmission reverse signal;
the two PMOS transistors of the second path 302 are used for controlling the output gate transmission control signal to be an on voltage so as to turn on the transmission transistor, and the gates of the two PMOS transistors of the second path 302 are respectively connected with the sampling row transmission reverse signal and the sampling row address reverse signal; the three NMOS transistors of the second path 302 are used for controlling the output gate transmission control signal to be a turn-off voltage to turn off the transmission transistor, and the gates of the three NMOS transistors of the second path 302 are respectively connected with the sampling row address forward signal, the sampling row address forward signal and the sampling row transmission reverse signal;
the two PMOS transistors of the third path 303 are used for controlling the output gate transmission control signal to be an on voltage so as to turn on the transmission transistor, and the gates of the two PMOS transistors of the third path 303 are respectively connected with the latch address analog signal and the sampling row address forward signal; the three NMOS transistors of the third path 303 are used for controlling the output gate transmission control signal to be a turn-off voltage to turn off the transmission transistor, and the gates of the three NMOS transistors of the third path 303 are respectively connected to the pre-exposure row address inversion signal, the sampling row address inversion signal, and the latch address analog signal.
Referring to fig. 6-8 and 10 in combination, fig. 8 is a timing control diagram of an example of an image sensor driving method according to the present invention; fig. 10 is a flowchart of another driving method of an image sensor according to the present invention. The states of the gate transfer control signals and the corresponding transfer transistor switch states in the pixel rows in different states are described in detail below.
S100: for the pixel row in the idle state in the pixel array of the image sensor, the grid transmission control signal is output as the starting voltage so as to conduct the transmission transistor.
It is understood that the turn-on voltage may be the analog supply voltage AVDD.
Optionally, the method for outputting the gate transmission control signal tx to the turn-on voltage AVDD includes: the latch address analog signal (a_lat_addb) is at a first latch level, i.e., the latch address analog signal (a_lat_addb) is at a low level, the sampling row address forward signal (a_rp_add) is at a third level, i.e., the sampling row address forward signal (a_rp_add) is also at a low level, and the transfer transistor TX is turned on to output the gate transfer control signal TX as the on voltage AVDD in an idle state.
In the prior art, the pixel rows in the idle state can generate overexposure phenomenon under strong light irradiation, so that the adjacent pixel rows in other states are affected, and halation phenomenon is generated. In the embodiment of the application, the transmission transistor of the pixel row in the idle state is controlled to be conducted, so that charges accumulated by the photodiode in the pixel row in the idle state are conducted away through the VDD, and then the influence of the pixels of the pixel row in the idle state on the pixels of the adjacent pixel row is solved, and the anti-halation effect is achieved.
S200: a row of pixels in a precharge state in an image sensor pixel array includes a first precharge state and a second precharge state located after the first precharge state; in the first precharge state, outputting a gate transfer control signal as an on voltage to turn on the transfer transistor; in the second precharge state, the output gate transfer control signal is an off voltage to turn off the transfer transistor.
Alternatively, the on voltage may be the analog power supply voltage AVDD, and the off voltage may be the ground voltage AGND.
Specifically, in the first precharge state, the pre-exposure row transmission reverse signal (a_sp_txb) is at a first transmission level, that is, the pre-exposure row transmission reverse signal (a_sp_txb) is at a low level, and the pre-exposure row address reverse signal (a_sp_addb) is at a first level, that is, the pre-exposure row address reverse signal (a_sp_addb) is also at a low level, so that the gate transmission control signal TX is output as the on voltage AVDD in the first precharge state, so that the transmission transistor TX is turned on; in the second precharge state, the pre-exposure row transmission reverse signal (a_sp_db) is at the second transmission level, the pre-exposure row address forward signal (a_sp_add) is at the second level, the latch address analog signal (a_lat_addb) is at the second latch level, that is, the pre-exposure row transmission reverse signal (a_sp_txb), the pre-exposure row address forward signal (a_sp_add) and the latch address analog signal (a_lat_addb) are all at the high level, so that the gate transmission control signal TX is output as the off voltage AGND in the second precharge state, so that the transmission transistor TX is turned off.
S300: the pixel row in the sampling state in the pixel array of the image sensor comprises a first sampling state and a second sampling state positioned after the first sampling state; in a first sampling state, outputting a grid transmission control signal as an opening voltage so as to conduct a transmission transistor; in the second sampling state, the output gate transmission control signal is an off voltage to turn off the transmission transistor.
In the first sampling state, the sampling row transmission inversion signal (a_rp_txb) is at a third transmission level, the sampling row address inversion signal (a_rp_addb) is at a third level, that is, the sampling row transmission inversion signal (a_rp_txb) and the sampling row address inversion signal (a_rp_addb) are both at low levels, so that the gate transmission control signal TX is output as the on voltage AVDD in the first sampling state, so that the transmission transistor TX is turned on;
in the second sampling state, the sampling row transmission reverse signal (a_rp_txb) is at a fourth transmission level, the sampling row address forward signal (a_rp_add) is at a fourth level, that is, both the sampling row transmission reverse signal (a_rp_txb) and the sampling row address forward signal (a_rp_add) are at high levels, so that the gate transmission control signal TX is output as the off voltage AGND in the first sampling state, so that the transmission transistor TX is turned off.
Alternatively, as shown in fig. 7, the first level=0, and the second level=1; third level=0, fourth level=1; first transmission level=0, second transmission level=1; third transmission level=0, fourth transmission level=1; first latch level=0, second latch level.
In some embodiments, referring to fig. 7-8 in combination, a reset control signal RST is output to the reset transistor RST of the pixel cell in the pixel row in the idle state to continuously turn on the reset transistor RST so that the pixel cell in the pixel row in the idle state conducts charge accumulated in the photodiode away through VDD.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (21)
1. A driving method of an image sensor, comprising:
acquiring a pre-exposure line address digital signal, a sampling line address digital signal, a pre-exposure line transmission digital signal and a sampling line transmission digital signal, and outputting a pre-exposure line address analog signal, a sampling line address analog signal, a pre-exposure line transmission analog signal and a sampling line transmission analog signal through a voltage level converter;
outputting a latch address analog signal based on the pre-exposure line address analog signal, the sampling line address analog signal, the pre-exposure line transmission analog signal, and the sampling line transmission analog signal;
outputting a gate transmission control signal based on the pre-exposure line address analog signal, the sampling line address analog signal, the pre-exposure line transmission analog signal, the sampling line transmission analog signal, and the latch address analog signal;
the grid transmission control signal is used for controlling the on and off of a transmission transistor in a pixel circuit of the image sensor.
2. The method of driving an image sensor according to claim 1, wherein the method of outputting the gate transfer control signal comprises:
the pre-exposure line address analog signals comprise pre-exposure line address forward signals and pre-exposure line address reverse signals, the sampling line address analog signals comprise sampling line address forward signals and sampling line address reverse signals, the pre-exposure line transmission analog signals comprise pre-exposure line transmission forward signals and pre-exposure line transmission reverse signals, and the sampling line transmission analog signals comprise sampling line transmission forward signals and sampling line transmission reverse signals;
and outputting a gate transmission control signal based on the pre-exposure row address forward signal, the pre-exposure row address reverse signal, the sampling row address forward signal, the sampling row address reverse signal, the pre-exposure row transmission forward signal, the pre-exposure row transmission reverse signal, the sampling row transmission forward signal, the sampling row transmission reverse signal, and the latch address analog signal.
3. The driving method of an image sensor according to claim 2, wherein the method of outputting the latch address analog signal includes:
outputting the latch address analog signal based on the pre-exposure row address reverse signal, the pre-exposure row transmission reverse signal, the sampling row address forward signal, and the sampling row transmission forward signal.
4. The method of driving an image sensor according to claim 2, wherein the gate transfer control signal is outputted as an on voltage for turning on the transfer transistor for a pixel row in an idle state in the pixel array of the image sensor.
5. The method of driving an image sensor according to claim 4, wherein the method of determining the pixel row in the idle state in the image sensor pixel array comprises:
determining a pixel row in the idle state in the image sensor pixel array based on the pre-exposure row address analog signal and the sampling row address analog signal;
the pre-exposure row address analog signal is used for indicating a row of pixels in the pixel array, which are in a pre-charge state and are ready to start exposure, and the sampling row address analog signal is used for indicating a row of pixels in the pixel array, which are in a sampling state.
6. The method of driving an image sensor according to claim 5, wherein the method of determining a pixel row in the idle state in the image sensor pixel array based on the pre-exposure row address analog signal and the sampling row address analog signal comprises:
determining a row address between the pre-exposure row address analog signal and the sampling row address analog signal as a pixel row in an exposure state;
pixel rows that are not in the precharge state, the exposure state, and the sampling state are determined as pixel rows in the idle state.
7. The method of driving an image sensor according to claim 4, wherein the method of outputting the gate transfer control signal as an on voltage comprises:
the latch address analog signal is a first latch level, and the sampling row address forward signal is a third level, so as to output the gate transmission control signal as an opening voltage in the idle state.
8. The driving method of an image sensor according to claim 2, wherein a pixel row in a precharge state in the image sensor pixel array includes a first precharge state and a second precharge state located after the first precharge state;
outputting the grid transmission control signal as an opening voltage in the first precharge state so as to conduct the transmission transistor;
in the second precharge state, the gate transfer control signal is outputted as a turn-off voltage (GND) to turn off the transfer transistor.
9. The method for driving an image sensor according to claim 8, wherein,
in the first precharge state, the pre-exposure row transmission reverse signal is a first transmission level, and the pre-exposure row address reverse signal is a first level, so as to output the gate transmission control signal as an opening voltage in the first precharge state;
in the second precharge state, the pre-exposure row transmission reverse signal is a second transmission level, the pre-exposure row address forward signal is a second level, and the latch address analog signal is a second latch level, so as to output the gate transmission control signal as a closing voltage in the second precharge state.
10. The driving method of an image sensor according to claim 2, wherein a pixel row in a sampling state in the image sensor pixel array includes a first sampling state and a second sampling state located after the first sampling state;
outputting the grid transmission control signal as an opening voltage in the first sampling state so as to conduct the transmission transistor;
and in the second sampling state, outputting the grid transmission control signal as a closing voltage so as to close the transmission transistor.
11. The method for driving an image sensor according to claim 10, wherein,
in the first sampling state, the sampling line transmission reverse signal is a third transmission level, and the sampling line address reverse signal is a third level, so that the gate transmission control signal is output as an opening voltage in the first sampling state;
in the second sampling state, the sampling line transmission reverse signal is a fourth transmission level, and the sampling line address forward signal is a fourth level, so that the gate transmission control signal is output as a closing voltage in the first sampling state.
12. The driving method of an image sensor according to claim 1, wherein the driving method further comprises: and outputting a reset control signal to the reset transistor of the pixel unit in the pixel row in the idle state so as to continuously conduct the reset transistor.
13. A driving device of an image sensor, comprising: the control module is coupled with the driving module, wherein the control module at least comprises an inversion adjusting module, and the driving module at least comprises a grid driving module;
the driving device further comprises a voltage level converter, wherein the voltage level converter is used for outputting a pre-exposure line address analog signal, a sampling line address analog signal, a pre-exposure line transmission analog signal and a sampling line transmission analog signal according to the pre-exposure line address digital signal, the sampling line address digital signal, the pre-exposure line transmission digital signal and the sampling line transmission digital signal;
the inversion adjustment module is used for outputting a latch address analog signal according to the exposure row address analog signal, the sampling row address analog signal, the exposure row transmission analog signal and the sampling row transmission analog signal;
the grid driving module is used for outputting a grid transmission control signal according to the exposure row address analog signal, the sampling row address analog signal, the exposure row transmission analog signal, the sampling row transmission analog signal and the latch address analog signal; the grid transmission control signal is used for controlling the on and off of the transmission transistor of the pixel unit.
14. The driving device as recited in claim 13, wherein,
the pre-exposure line address analog signals comprise pre-exposure line address forward signals and pre-exposure line address reverse signals, the sampling line address analog signals comprise sampling line address forward signals and sampling line address reverse signals, the pre-exposure line transmission analog signals comprise pre-exposure line transmission forward signals and pre-exposure line transmission reverse signals, and the sampling line transmission analog signals comprise sampling line transmission forward signals and sampling line transmission reverse signals;
and outputting the gate transmission control signal based on the pre-exposure row address forward signal, the pre-exposure row address reverse signal, the sampling row address forward signal, the sampling row address reverse signal, the pre-exposure row transmission forward signal, the pre-exposure row transmission reverse signal, the sampling row transmission forward signal, the sampling row transmission reverse signal, and the latch address analog signal.
15. The drive of claim 14, wherein the control module further comprises a first control path and a second control path;
the first control path is used for controlling the reverse phase adjusting module to output the latch address analog signal to be a second latch level; the second control path is used for controlling the reverse phase adjusting module to output the latch address analog signal to be a first latch level.
16. The driving device as claimed in claim 15, wherein the first control path comprises two PMOS transistors, and gates of the two PMOS transistors are respectively connected to the pre-exposure row address inversion signal and the pre-exposure row transmission inversion signal; the second control path comprises two NMOS (N-channel metal oxide semiconductor) tubes, and the two NMOS tubes are respectively connected with the sampling row address forward signal and the sampling row transmission forward signal.
17. The driving device according to claim 14, wherein the states of the pixel rows of the pixel array include an idle state, a precharge state, an exposure state, and a sampling state;
wherein a row address between the exposure row address analog signal and the read row address analog signal is determined as a pixel row in the exposure state, a row address receiving the pre-exposure row address analog signal is determined as a pixel row in the precharge state, a row address receiving the sample row address analog signal is determined as a pixel row in the sample state, and a pixel row not in the precharge state, the exposure state, and the sample state is determined as a pixel row in the idle state.
18. The drive of claim 17, wherein the gate drive module comprises:
a first path for controlling on and off of a transfer transistor of a pixel row in the precharge state in the pixel array;
a second path for controlling on and off of a transfer transistor of a pixel row in the sampling state in the pixel array;
and a third path for controlling the on and off of the transmission transistor of the pixel row in the idle state in the pixel array.
19. The driving device as recited in claim 18 wherein,
the first channel, the second channel and the third channel respectively comprise two PMOS (P-channel metal oxide semiconductor) tubes and three NMOS (N-channel metal oxide semiconductor) tubes;
the two PMOS tubes of the first passage are used for controlling and outputting the gate transmission control signal to be an opening voltage, the gates of the two PMOS tubes of the first passage are respectively connected with the pre-exposure row transmission reverse signal and the pre-exposure row address reverse signal, the three NMOS tubes of the first passage are used for controlling and outputting the gate transmission control signal to be a closing voltage, and the gates of the three NMOS tubes of the first passage are respectively connected with the pre-exposure row address forward signal, the latch address analog signal and the pre-exposure row transmission reverse signal;
the two PMOS tubes of the second path are used for controlling and outputting the gate transmission control signal to be an on voltage, the gates of the two PMOS tubes of the second path are respectively connected with the sampling row transmission reverse signal and the sampling row address reverse signal, the three NMOS tubes of the second path are used for controlling and outputting the gate transmission control signal to be an off voltage, and the gates of the three NMOS tubes of the first path are respectively connected with the sampling row address forward signal, the sampling row address forward signal and the sampling row transmission reverse signal;
the two PMOS tubes of the third passage are used for controlling and outputting the gate transmission control signal to be an opening voltage, the grid electrodes of the two PMOS tubes of the third passage are respectively connected with the latch address analog signal and the sampling row address forward signal, the three NMOS tubes of the third passage are used for controlling and outputting the gate transmission control signal to be a closing voltage, and the grid electrodes of the three NMOS tubes of the third passage are respectively connected with the pre-exposure row address reverse signal, the sampling row address reverse signal and the latch address analog signal.
20. The drive of claim 13, wherein the inverting adjustment module comprises a first inverter, a second inverter, and a third inverter;
the input end of the first inverter receives the exposure row address analog signal, the sampling row address analog signal, the exposure row transmission analog signal and the sampling row transmission analog signal, the output end of the first inverter is coupled with the input end of the second inverter, and the output end of the second inverter outputs the latch address analog signal; the input end of the third inverter is coupled to the output end of the first inverter and the input end of the second inverter, and the output end of the third inverter is coupled to the input end of the first inverter.
21. An image sensor, comprising: a pixel array comprising a plurality of pixel cells arranged in rows and columns, and a driving apparatus according to any one of claims 13 to 20, each pixel cell comprising: a photodiode for accumulating image charge in response to incident light, and a transfer transistor coupled between the photodiode and a floating diffusion node to selectively transfer the image charge accumulated in the photodiode to the floating diffusion node;
the control module is used for determining the state of the pixel row of the pixel array.
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