CN116488763A - Encoder communication delay compensation device and method - Google Patents
Encoder communication delay compensation device and method Download PDFInfo
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Abstract
The invention provides a communication delay compensation device and a method for an encoder, wherein the communication delay compensation device for the encoder comprises the following components: the programmable logic unit controls the microcontroller to send data to the encoder and receive data fed back by the encoder; the interval time timing unit starts timing when the output end of the microcontroller finishes data transmission, stops timing when the receiving end of the microcontroller receives data, and obtains the time interval from the completion of the data transmission of the microcontroller to the receipt of the first data; the programmable unit obtains communication delay to be compensated by the encoder according to the time interval from the completion of the data transmission by the microcontroller to the receipt of the first data, the time length of the data received by the encoder and the time length of the data received by the encoder. The communication delay compensation device and the method for the encoder can accurately acquire the communication delay required to be compensated by the encoder.
Description
Technical Field
The invention belongs to the technical field of digital signal processing, and particularly relates to a communication delay compensation device and method for an encoder.
Background
For communication between a microprocessor (MicroconTroller UniT, MCU) and a communication encoder, a universal asynchronous receiver/transmitter (Universal Asynchronous Receiver-TransmiTTer, UART) may be used directly. However, when the distance between the microprocessor and the encoder is long, the transmission delay of the electric signal can affect the real-time performance of the position signal collected by the encoder, and further affect the accuracy of high-precision servo control.
Disclosure of Invention
The invention aims to provide a communication delay compensation device and a communication delay compensation method for an encoder, which can accurately compensate delay between a microprocessor and the encoder.
In order to achieve the above object, the present invention provides an encoder communication delay compensation device, comprising:
the programmable logic unit controls the microcontroller to send data to the encoder and receive data fed back by the encoder; and
the interval time timing unit starts timing when the output end of the microcontroller finishes data transmission, stops timing when the receiving end of the microcontroller receives data, and acquires the time interval from the completion of the data transmission of the microcontroller to the receipt of the first data;
the programmable unit obtains communication delay to be compensated by the encoder according to the time interval from the completion of the data transmission by the microcontroller to the receipt of the first data, the time length of the data received by the encoder and the time length of the data received by the encoder.
In one embodiment of the present invention, the communication delay to be compensated by the encoder is obtained by the following formula:
T＝Td+Rx21+T3；
wherein, T is the communication delay to be compensated by the encoder, td is the delay time of the signal when the signal is transmitted between the microcontroller and the encoder, rx21 is the time length of the encoder to receive the data, and T3 is the time length of the encoder to process the received data.
In one embodiment of the invention, the delay time of the signal when the signal is transmitted between the microcontroller and the encoder is obtained by the following formula:
Td＝(T1-T3)/2；
wherein T1 is the time interval from completion of the microcontroller transmitting data to receipt of the first data, and T3 is the time length for the encoder to process the received data.
In an embodiment of the present invention, the length of time for the encoder to receive data is equal to the length of time for the microcontroller to send data, and the length of time for the microcontroller to send data is obtained by the following formula:
Tx11＝A×1/B。
where Tx11 is the length of time the microcontroller transmits data, a is the number of bits of the transmitted data, and B is the baud rate during data transmission.
In one embodiment of the present invention, the programmable logic units are programmable logic whole columns.
In an embodiment of the invention, the programmable logic unit is a hall sensor interface.
In an embodiment of the present invention, the encoder communication delay compensation device further includes a data pulse number timing unit, and the pulse number timing unit stores a time length of transmitting data and a time length of receiving data.
In one embodiment of the present invention, the data pulse number timing unit is an orthogonal encoder interface.
In an embodiment of the present invention, the programmable logic unit includes a JK flip-flop, a J input terminal of the JK flip-flop inputs a start signal, a clock input terminal of the JK flip-flop inputs a clock signal of the programmable logic unit, and a K input terminal of the JK flip-flop inputs a pulse capture signal.
In one embodiment of the present invention, the programmable logic unit includes:
a one-bit full adder, wherein one input end of the one-bit full adder inputs a low-level signal, and the other input end of the one-bit full adder inputs a pulse capturing signal; and
the data input end of the D latch is input with a high level, the clock input end of the D latch is electrically connected with the output end of the one-bit full adder, and the zero clearing end of the D latch is electrically connected with the data receiving pin of the serial peripheral interface.
In an embodiment of the present invention, the programmable logic unit includes an or gate, and an input end of the or gate is electrically connected to the output ends of the JK flip-flop and the D latch.
In an embodiment of the present invention, the signal output from the output end of the or gate is inverted and then input to the interval time timing unit.
In an embodiment of the invention, the or gate output end is further electrically connected to a synchronization trigger signal of the PWM module.
In an embodiment of the present invention, the programmable logic unit includes an and gate, an input end of the and gate is electrically connected to an output end of the or gate, and another input end of the and gate inputs a PWM clock signal.
In an embodiment of the present invention, the encoder communication delay compensation device further includes another one-bit full adder, where an input end of the another one-bit full adder inputs a low level signal, and another input end of the another one-bit full adder is electrically connected to an output end of a previous one of the one-bit full adders, and an output end of the another one-bit full adder outputs a direct memory access trigger signal.
The invention also provides a communication delay compensation method of the encoder, which comprises the following steps:
the microcontroller is controlled to send data to the encoder and receive the data fed back by the encoder;
starting timing when the output end of the microcontroller finishes data transmission, stopping timing when the receiving end of the microcontroller receives data, and acquiring a time interval from the completion of the data transmission of the microcontroller to the receipt of the first data;
and acquiring communication delay to be compensated by the encoder according to the time interval from the completion of the data transmission by the microcontroller to the reception of the first data, the time length of the data reception by the encoder and the time length of the data processing received by the encoder.
In summary, according to the encoder communication delay compensation device and method provided by the invention, the output and input of the serial peripheral interface data are controlled by the peripheral of the microcontroller, so that the duration of encoder communication delay compensation is accurately obtained, and the accuracy of obtaining signal transmission delay between the microprocessor and the encoder is improved. The peripheral equipment of the microcontroller is used for capturing the time between sending data and receiving data, and the direct memory access handling of the time data does not need the participation of a kernel processor, so that the cost is not increased while the communication delay compensation of the encoder is acquired.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a microcontroller, communication delay compensation device and encoder of the present invention.
Fig. 2 is a communication timing diagram of a microcontroller with a high level state when the communication bus is idle.
Fig. 3 is a communication timing diagram of a microcontroller with a low level state when the communication bus is idle.
Fig. 4 is a timing diagram of the encoder side.
Fig. 5 is a diagram of the internal logic of the programmable logic unit.
Fig. 6 is a timing diagram of logic circuitry within a programmable logic unit.
Reference numerals illustrate:
101. a microcontroller; 102. direct memory access; 103. a serial peripheral interface; 104. a programmable logic unit; 105. a data pulse number timing unit; 106 interval time timing units; 107. a protocol conversion module; 108. an encoder; 1041. a JK flip-flop; 1042. a D register; 1043. a one-bit full adder; 1044. a one-bit full adder; 1045. or gate; 1046. and an AND gate.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or component to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, the present invention provides a microcontroller 101, where the microcontroller 101 includes a core processor, an internal memory, a power management module, a clock, a reset module, a start module, an external memory, a PWM module, a timer, a communication peripheral, an analog peripheral, an input/output module, an information security system, and a system debug module. Different combination control is performed for different application occasions. Also specifically included among peripherals of microcontroller 101 are programmable logic arrays (Programmable logic arrays, PLA), serial peripheral InTerface 103 (Serial Peripheral in InTerface, SPI), direct memory access 102 (DirecT Memory Access, DMA), quadrature encoder InTerface (QuadraTure Encoder in InTerface, QEI), and HALL sensor InTerface (HALL). Encoder 108 may compile and convert signals or data output by microprocessor 101 into a signal form that may be used for communication, transmission and storage. However, when the distance between the microcontroller 101 and the encoder 108 is large, a delay occurs in the signal output from the microcontroller 101 to the encoder 108. In some embodiments, the delay time may be calculated by the length of the wire between microcontroller 101 and encoder 108 and compensated for. But when the application scenarios of the microcontroller 101 and the encoder 108 are different, a recalculation is required. The delay time error obtained by calculating the delay time according to the length of the wire is larger, and the delay time is also influenced by factors such as conductive materials and the like when calculating the delay time. In calculating the delay time based on the length of the wire, the delay time in the circuit board and the inside of the microcontroller 101 cannot be calculated. Therefore, in the application, a communication delay compensation device is arranged, so that the communication transmission delay can be accurately acquired and the delay time can be compensated.
Referring to fig. 1, in an embodiment of the present invention, a protocol conversion module 107 is further disposed between the microcontroller 101 and the encoder 108. In this application, the protocol conversion module 107 can perform conversion between 485 communication and TTL communication.
Referring to fig. 1, in the present application, the communication delay compensation device may be implemented by using a plurality of peripherals of the microcontroller 101. Specifically, the communication delay compensation device includes a programmable logic unit 104, a data pulse number timing unit 105, and an interval time timing unit 106. In one embodiment of the present invention, the programmable logic unit 104 is, for example, a programmable logic array (Programmable logic arrays, PLA). The programmable logic unit 104 is electrically connected to the serial peripheral interface 103 in the microcontroller 101, and when the serial peripheral interface 103 is configured in the slave mode, the programmable logic unit 104 generates a clock signal and controls the start, end, transmission and reception of the serial peripheral interface 103 according to the clock signal. The data pulse number timing unit 105 and the interval time timing unit 106 are electrically connected to the programmable logic unit 104. Wherein the data pulse number timing unit 105 stores the time length of transmitting data and the time length of receiving data, and the interval time timing unit 106 stores the time interval from the completion of transmitting data to the receipt of the first data. Specifically, the data pulse number timing unit 105 may store the number of pulses of the clock signal occupied by the transmission data and the number of pulses of the clock signal occupied by the reception completion data. In the present embodiment, the data pulse number timing unit 105 is, for example, a quadrature encoder interface, and the interval time timing unit 106 is, for example, a hall sensor interface.
Referring to fig. 1, in an embodiment of the present invention, when a communication delay to be compensated is required to be obtained, the microcontroller 101 sends a set of data to the encoder 108 through the transmitting end, and then receives the set of data through the receiving end. Referring to fig. 2 and 3, fig. 2 is a communication timing diagram of the microcontroller 101 with a high level state when the communication bus is idle, and fig. 3 is a communication timing diagram of the microcontroller 101 with a low level state when the communication bus is idle. Wherein, the time length Tx11 of the microcontroller 101 for transmitting data is equal to the first time length T0, the time length Rx11 of the microcontroller 101 for receiving data is equal to the third time length T2, and the time interval from when the microcontroller 101 transmits data to when the first data is received is equal to the second time length T1.
Referring to fig. 2 and 3, in an embodiment of the present invention, the communication bus is set to be in a high level state when idle. When the communication bus is at a low level, the transmitting end and the receiving end are triggered by the falling edge. In other embodiments, when the communication bus is idle, the level state is low, and both the transmitting end and the receiving end are triggered by rising edges, and when the communication bus is high, data is transmitted.
Referring to fig. 4, fig. 4 is a timing diagram of the encoder, and after the encoder 108 receives the data sent by the microcontroller 101, the level of the receiving end is inverted, for example, from high level to low level. After the encoder 108 receives the data, it processes the data for a period of time and sends the processed data to the microcontroller 101. In this application, the length of time Rx21 for which the encoder 108 receives data is equal to the first time period T0, the length of time Tx21 for which the encoder 108 transmits data is equal to the third time period T2, and the length of time for which the encoder 108 processes the received data is equal to the fourth time period T3.
Referring to fig. 1, 2 and 4, in one embodiment of the present invention, the time interval between the completion of transmitting data and the receipt of the first data is equal to twice the sum of the time delay of the signal when the signal is transmitted between the microcontroller 101 and the encoder 108 and the time period during which the encoder 108 processes the received data. Namely:
T1＝2Td+T3；
td= (T1-T3)/2.
Where T1 is the time interval from completion of the transmission of data by the microcontroller 101 to receipt of the first data, td is the time delay of the signal when the signal is transmitted between the microcontroller 101 and the encoder 108, and T3 is the time length for the encoder 108 to process the received data.
And the communication delay T that the encoder 108 needs to compensate is obtained by the following formula:
T＝Td+Rx21+T3＝Td+T0+T3＝(T1-T3)/2+T0+T3＝(T1+T3)/2+T0。
as can be seen from the above formula, the communication delay T required to be compensated by the encoder 108 is equal to the sum of the delay time Td of the signal when the signal is transmitted between the microcontroller 101 and the encoder 108, the time length Rx21 of the encoder 108 receiving the data, and the time length T3 of the encoder 108 processing the received data.
In the above formula, the delay time Td of the signal when the signal is transmitted between the microcontroller 101 and the encoder 108 is equal to one half of the difference between the time interval T1 from when the microcontroller 101 transmits the data to when the first data is received and the time interval T3 from when the encoder 108 processes the received data, the time interval T1 from when the microcontroller 101 transmits the data to when the first data is received being measured by the interval time counting unit 106, and the time interval T3 from when the encoder 108 processes the received data being obtained by depending on the specific model of the encoder 108. The length of time Rx21 for which the encoder 108 receives data is equal to the length of time Tx11 for which the microcontroller 101 transmits data, i.e. equal to the first time length T0. The first duration T0 is obtained by the following formula:
T0＝A×1/B。
wherein A is the number of bits of the transmitted data, and B is the baud rate during data transmission.
When the encoder communication delay compensation device provided by the application is used to obtain the communication delay T to be compensated by the encoder 108, the programmable logic unit 104 is used to control the transmission of the output data. When it is detected that the data transmission is completed, the reception end is detected while the time counting is started using the interval time counting unit 106. When detecting that the level of the receiving end changes, the counting is stopped, and the time interval T1 from the completion of the data transmission of the microcontroller 101 to the receipt of the first data can be obtained.
Referring to fig. 5, in an embodiment of the present invention, a plurality of logic circuits are disposed in the programmable logic unit 104, including a JK flip-flop 1041, two one-bit full adders, a D latch 1042, an or gate 1045 and an and gate 1046.
Specifically, referring to fig. 5, IN an embodiment of the present invention, the J input of the JK flip-flop 1041 is inputted with a start signal moto_trig_in, and the start signal moto_trig_in controls the start etching of the whole communication, and the start signal moto_trig_in can be generated by configuring a start register. One of the etching processes IN the PWM period may be selected to generate a pulse signal, which is the start signal motor_trig_in. The clock input of the JK flip-flop 1041 inputs the programmable logic unit 104 clock signal spi_clk to provide the programmable logic unit 104 with the clock signal. In the present application, the frequency of the clock signal SPI_CLK of the programmable logic unit 104 is, for example, 200M. The K input terminal of the JK flip-flop 1041 receives the pulse capture signal qei_in, and the pulse capture signal qei_in can be generated by configuring a pulse capture module. The pulse capturing module is configured to capture the clock signal spi_clk of the programmable logic unit 104, and when the number of pulses of the clock signal spi_clk of the programmable logic unit 104 captured reaches a specified number, the pulse capturing module generates a pulse capturing signal qei_in.
Referring to fig. 5, in an embodiment of the present invention, the data input (D input) of the D latch 1042 inputs high. The clock input of the D latch 1042 is electrically connected to the output of a one-bit full adder 1043, and one input of the one-bit full adder 1043 inputs a low signal, and the other input inputs a pulse capturing signal qei_in. The clear terminal (| CLR terminal) of the D latch 1042 is electrically connected to the data receiving pin MOSI of the serial peripheral interface 103.
Referring to fig. 1 and 5, in an embodiment of the invention, Q outputs of the JK flip-flop 1041 and the D latch 1042 are electrically connected to an input of the or gate 1045. The output end of the or gate 1045 is electrically connected to an input end of the and gate 1046, the PWM clock signal pwm_clk_in is input to the other input end of the and gate 1046, the PWM clock signal pwm_clk_in is a PWM clock signal generated by the PWM module, the period of the PWM clock signal pwm_clk_in is a period of a clock signal communicated by the serial peripheral interface 103, and the duty ratio of the PWM clock signal pwm_clk_in is, for example, 50%. The output signal of the or gate 1045 also takes the inverse input interval time counting unit 106 to calculate the time. The signal output from the output end of the or gate 1045 is further electrically connected to a synchronization trigger signal of the PWM module, for synchronizing the phase of the PWM clock signal pwm_clk_in. I.e., low level resets the PWM counter, ensuring that the PWM clock signal pwm_clk_in initiates etching and alignment of the data edges received by the data receiving pin MOSI of the serial peripheral interface 103.
Referring to fig. 5, in an embodiment of the present invention, one input terminal of the other one bit full adder 1044 of the programmable logic unit 104 inputs a low signal, and the other input terminal is electrically connected to the output terminal of the previous one bit full adder 1043. The output terminal of the other one-bit full adder 1044 outputs a dma_link trigger signal for triggering the hardware to automatically update the DMA 102 configuration and start the next transmission.
As described above, referring to fig. 1 to 6, when the communication delay compensation device for an encoder provided in the present application is used to implement the communication delay compensation method for an encoder, a time interval T1 from when the microcontroller 101 sends data to when the first data is received is acquired. The serial peripheral interface 103 of the microcontroller 101 may be configured in a slave mode and the programmable logic unit 104 clock signal spi_clk may be generated by the programmable logic unit 104, with or without the programmable logic unit 104 clock signal spi_clk being controlled to start, end, transmit and receive data from the serial peripheral interface 103. For example, first controls the output of microcontroller 101 to send data to encoder 108. Thereafter, the interval time counting unit 106 is used to start counting when the data transmission is completed at the output end of the microcontroller 101, stop counting when the data is received at the receiving end of the microcontroller 101, and acquire the time interval T1 from the completion of the data transmission of the microcontroller 101 to the reception of the first data. The communication delay to be compensated is then determined by the time interval T1 from the completion of the transmission of the data by the microcontroller 101 to the receipt of the first data, the time period Rx21 for the encoder 108 to process the received data, and the time period T3 for the encoder 108 to process the received data.
Specifically, as shown in fig. 1 to 6, during a cycle from when the microcontroller 101 completes transmitting data to when the first data is received, the programmable logic unit 104 is first used to pull down the chip select signal to select the serial peripheral interface 103, and the serial peripheral interface 103 is configured in the slave mode. Then, waiting for an input start signal MOTOR_TRIG_IN from a programmable logic unit 104, when the input start signal MOTOR_TRIG_IN is enabled, the programmable logic unit 104 controls the output terminal of the serial peripheral interface 103 to start outputting data to the encoder 108. Since the number of pulses of the clock signal occupied by the output data is fixed, the number of pulses of the clock signal occupied by the output data is, for example, the first number. Thus when the number of pulses of the clock signal captured by the programmable logic unit 104 by the data pulse number timing unit 105 reaches the first number, the programmable logic unit 104 stops transmitting the programmable logic unit 104 clock signal spi_clk. When the number of pulses of the clock signal captured by the programmable logic unit 104 through the data pulse number timing unit 105 reaches the first number, the signal state of the input terminal of the serial peripheral interface 103 is simultaneously monitored, and the interval time timing unit 106 is used to start timing, and when the signal of the input terminal of the serial peripheral interface 103 changes, the timing is stopped. The time interval T1 from completion of the transmission of data by the microcontroller 101 to receipt of the first data can be acquired. When the interval timing unit 106 stops timing, the programmable logic unit 104 starts to transmit the clock signal spi_clk of the programmable logic unit 104, controls the input terminal of the serial peripheral interface 103 to start receiving data, and uses the clock signal captured by the data pulse number timing unit 105, and since the number of pulses of the clock signal occupied by the input data is constant, the number of pulses of the clock signal occupied by the output data is, for example, the second number. Thus when the number of pulses of the clock signal captured by the programmable logic unit 104 by the data pulse number timing unit 105 reaches the second number, the programmable logic unit 104 stops transmitting the programmable logic unit 104 clock signal spi_clk. The programmable logic unit 104 ends the cycle, and uses the programmable logic unit 104 to pull up the chip select signal to select the serial peripheral interface 103, and triggers the direct memory access 102 to update the parameters of the next cycle, and the pull up low select signal selects the serial peripheral interface 103 to wait for the next cycle.
Referring to fig. 1, in an embodiment of the present invention, after a time interval T1 from when the microcontroller 101 finishes transmitting data to when the first data is received is obtained, a time length Rx21 of the data received by the encoder 108 and a time length T3 of the data received by the encoder 108 are known data, and the programmable logic unit 104 can obtain the communication delay to be compensated by the encoder according to the formula of the communication delay T to be compensated by the encoder. After the communication delay T which is required to be compensated by the encoder is obtained, the time can be carried through direct memory access, and the kernel processor only needs to correct the triggering time of the triggering signal after the signal delay event is obtained.
In summary, the encoder communication delay compensation device provided by the invention comprises a programmable logic unit, a data pulse number timing unit and an interval time timing unit, wherein the programmable logic unit is used for controlling data transmission between the micro-control microcontroller and the decoder, the interval time timing unit is used for acquiring a time interval from the completion of the data transmission of the microcontroller to the receipt of the first data, and the communication delay required to be compensated by the encoder is acquired according to the time interval from the completion of the data transmission of the microcontroller to the receipt of the first data, the time length of the data receipt of the encoder and the time length of the data processing of the encoder.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (16)
1. An encoder communication delay compensation device, comprising:
the programmable logic unit controls the microcontroller to send data to the encoder and receive data fed back by the encoder; and
the interval time timing unit starts timing when the output end of the microcontroller finishes data transmission, stops timing when the receiving end of the microcontroller receives data, and acquires the time interval from the completion of the data transmission of the microcontroller to the receipt of the first data;
the programmable unit obtains communication delay to be compensated by the encoder according to the time interval from the completion of the data transmission by the microcontroller to the receipt of the first data, the time length of the data received by the encoder and the time length of the data received by the encoder.
2. The encoder communication delay compensation device according to claim 1, wherein the communication delay to be compensated by the encoder is obtained by the following formula:
T＝Td+Rx21+T3；
wherein, T is the communication delay to be compensated by the encoder, td is the delay time of the signal when the signal is transmitted between the microcontroller and the encoder, rx21 is the time length of the encoder to receive the data, and T3 is the time length of the encoder to process the received data.
3. An encoder communication delay compensation apparatus according to claim 3 wherein the delay time of the signal as it is transmitted between the microcontroller and the encoder is obtained by the following equation:
Td＝(T1-T3)/2；
wherein T1 is the time interval from completion of the microcontroller transmitting data to receipt of the first data, and T3 is the time length for the encoder to process the received data.
4. The encoder communication delay compensation apparatus of claim 2, wherein the length of time the encoder receives data is equal to the length of time the microcontroller transmits data, and the length of time the microcontroller transmits data is obtained by the following formula:
Tx11＝A×1/B。
where Tx11 is the length of time the microcontroller transmits data, a is the number of bits of the transmitted data, and B is the baud rate during data transmission.
5. The encoder communication delay compensation apparatus of claim 1, wherein the programmable logic unit is a programmable logic array.
6. The encoder communication delay compensation device of claim 1, wherein the programmable logic unit is a hall sensor interface.
7. The encoder communication delay compensation apparatus of claim 1, further comprising a data pulse number timing unit that stores a time length of transmitting data and a time length of receiving data.
8. The encoder communication delay compensation apparatus of claim 7 wherein the data pulse number timing unit is a quadrature encoder interface.
9. The encoder communication delay compensation apparatus of claim 1, wherein the programmable logic unit comprises a JK flip-flop, wherein a J input of the JK flip-flop inputs a start signal, wherein a clock input of the JK flip-flop inputs a programmable logic unit clock signal, and wherein a K input of the JK flip-flop inputs a pulse capture signal.
10. The encoder communication delay compensation apparatus of claim 9, wherein the programmable logic unit comprises:
a one-bit full adder, wherein one input end of the one-bit full adder inputs a low-level signal, and the other input end of the one-bit full adder inputs a pulse capturing signal; and
the data input end of the D latch is input with a high level, the clock input end of the D latch is electrically connected with the output end of the one-bit full adder, and the zero clearing end of the D latch is electrically connected with the data receiving pin of the serial peripheral interface.
11. The encoder communication delay compensation apparatus of claim 10, wherein the programmable logic unit comprises an or gate, wherein an input of the or gate is electrically connected to the JK flip-flop and an output of the D latch.
12. The encoder communication delay compensation apparatus of claim 11, wherein the signal output from the output terminal of the or gate is inverted and input to the interval time timing unit.
13. The encoder communication delay compensation apparatus of claim 11, wherein the or gate output is further electrically coupled to a synchronization trigger signal of the PWM module.
14. The encoder communication delay compensation apparatus of claim 11, wherein the programmable logic unit comprises an and gate, an input terminal of the and gate is electrically connected to the output terminal of the or gate, and another input terminal of the and gate inputs the PWM clock signal.
15. The encoder communication delay compensation apparatus of claim 10, further comprising another one-bit full adder, wherein one input of the another one-bit full adder inputs a low level signal, and wherein the other input of the another one-bit full adder is electrically connected to the output of the previous one of the one-bit full adders, and wherein the output of the another one-bit full adder outputs a direct memory access trigger signal.
16. The encoder communication delay compensation method is characterized by comprising the following steps:
the microcontroller is controlled to send data to the encoder and receive the data fed back by the encoder;
starting timing when the output end of the microcontroller finishes data transmission, stopping timing when the receiving end of the microcontroller receives data, and acquiring a time interval from the completion of the data transmission of the microcontroller to the receipt of the first data;
and acquiring communication delay to be compensated by the encoder according to the time interval from the completion of the data transmission by the microcontroller to the reception of the first data, the time length of the data reception by the encoder and the time length of the data processing received by the encoder.
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| US20180097568A1 (en) * | 2016-10-04 | 2018-04-05 | United States Of America As Represented By The Secretary Of The Navy | System and Method for a Differential Pulse Position Modulation Encoder and Decoder |
| CN109612502A (en) * | 2018-12-05 | 2019-04-12 | 麦歌恩电子(上海)有限公司 | The test method and system of magnetic coder chip interior signal transmission delay |
| CN113726258A (en) * | 2021-09-07 | 2021-11-30 | 成都卡诺普机器人技术股份有限公司 | Measurement and compensation method for internal signal transmission delay of magnetic encoder |
| CN114584116A (en) * | 2022-03-09 | 2022-06-03 | 北京奕斯伟计算技术有限公司 | On-chip differential OCV compensation electronics, methods, and systems |
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| US20180097568A1 (en) * | 2016-10-04 | 2018-04-05 | United States Of America As Represented By The Secretary Of The Navy | System and Method for a Differential Pulse Position Modulation Encoder and Decoder |
| CN109612502A (en) * | 2018-12-05 | 2019-04-12 | 麦歌恩电子(上海)有限公司 | The test method and system of magnetic coder chip interior signal transmission delay |
| CN113726258A (en) * | 2021-09-07 | 2021-11-30 | 成都卡诺普机器人技术股份有限公司 | Measurement and compensation method for internal signal transmission delay of magnetic encoder |
| CN114584116A (en) * | 2022-03-09 | 2022-06-03 | 北京奕斯伟计算技术有限公司 | On-chip differential OCV compensation electronics, methods, and systems |
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