CN116488640A - Double-edge triggered asynchronous Gray code counter - Google Patents
Double-edge triggered asynchronous Gray code counter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/002—Pulse counters comprising counting chains; Frequency dividers comprising counting chains using semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model discloses a double-edge triggered asynchronous Gray code counter, which takes a first-stage trigger Rise1 as a rising edge triggered D trigger and takes other stages of triggers Fall1, fall2 and Fall3 as falling edge triggered D triggers. The utility model solves the problem that the utilization of the clock frequency is not maximized due to the generation of the first-stage mark signal in the prior Gray code counter.
Description
Technical Field
The utility model belongs to the technical field of Gray code counting, and relates to a double-edge triggered asynchronous Gray code counter.
Background
In integrated circuit designs, a counter is often used as one of the most basic circuit blocks. Compared with a binary counter, the gray code counter has the advantages that the difference between two adjacent digital values of the gray code is only one bit, namely, the output level of only one bit is inverted in each counting, so that the error rate of the gray code counter is lower, the anti-interference capability of the system is improved, and the gray code counter can work at a faster speed with fewer errors. Meanwhile, when the Gray code counter works in a counting state, the turnover times of the gate circuits of all the outputs are far less than those of the binary counter, so that the power consumption of the system can be reduced by using the Gray code counter to replace the binary counter.
Chinese patent No. CN108055034a discloses an asynchronous gray code counter circuit, as shown in fig. 1, comprising a flag signal generating circuit and a flip-flop cascade circuit, wherein the D flip-flops used in the circuit are the same kind of D flip-flops, and DFF1, DFF2, DFF3, DFF4, and DFF5 are all falling edge triggered D flip-flops. The D trigger of the first stage trigger circuit is DFF1, the D end of the DFF1 is connected with the self inverting output end QB, the Clock signal Clock is connected to the input end CLK, the signal output by the inverting output end QB of the DFF1 is a sign signal, meanwhile, the signal is input to the CLK end of the second stage trigger DFF2, and the cascade modes of the stages of the DFF2, the DFF3, the DFF4 and the DFF5 are the same, namely the inverting output end QB of the D trigger is connected to the D end of the D trigger of the stage, and the output end XB of the D trigger of the stage is connected to the CLK input end of the D trigger of the next stage. The D trigger of each stage is connected with R by a reset signal RST N The normal phase output ends of the D flip-flops of each stage of the DFF2, the DFF3, the DFF4 and the DFF5 are respectively used as each bit number Y (0), Y (1), Y (2) and Y (3) of the Gray code counter at the reset end. However, in the existing asynchronous gray code counter circuit of fig. 1, the first stage D flip-flop is required to generate the flag signal, so that the positive output end of the first stage D flip-flop cannot be used as the bit number of the gray code counter, and therefore the first stage D flip-flop is wasted to a certain extent, and the utilization of the clock frequency is not maximized just due to the generation of the first stage flag signal.
Disclosure of Invention
The utility model aims to provide an asynchronous Gray code counter triggered by double edges, which solves the problem that the utilization of clock frequency is not maximized due to the generation of a first-stage mark signal in the conventional Gray code counter.
The technical scheme adopted by the utility model is that the asynchronous Gray code counter triggered by double edges takes a first-stage trigger Rise1 as a D trigger triggered by rising edges, and takes the rest of all stages of triggers Fall1, fall2 and Fall3 as D triggers triggered by falling edges.
The utility model is also characterized in that:
the first stage flip-flop Rise1 is used as a rising edge triggered D flip-flop, and the rest stages of flip-flops Fall1, fall2 and Fall3 are used as falling edge triggered D flip-flops.
The D trigger of each stage is connected with R by a reset signal RST N And the reset end, the positive phase output end of each stage of D trigger is respectively used as each bit number Q (0), Q (1), Q (2) and Q (3) of the Gray code counter.
For the first stage D flip-flop Rise1, the positive phase output Q (0) is triggered at the rising edge of the Clock signal Clock, and the XB terminal is triggered at the falling edge of the Clock signal Clock, i.e., the flip-flop trigger point of the XB terminal is advanced by half Clock cycle of Clock than the positive phase output Q (0), and the frequency of the XB signal is the same as the signal Q (0).
For the second stage D flip-flop Fall1, the XB signal output by Rise1 is input to the CLK terminal of the second stage D flip-flop Fall1, the positive phase output Q (1) is triggered at the falling edge of the CLK signal at the input terminal of flip-flop Fall1, the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of flip-flop Fall1, i.e., the flip-flop trigger point of the XB terminal of flip-flop Fall1 is one Clock cycle earlier than the positive phase output Q (1) by one Clock cycle, and the frequency of the XB signal is the same as the signal Q (1), so that the flip-flop trigger point of the positive phase output Q (1) of flip-flop Fall1 lags by one half Clock cycle of Q (0), and the frequency of the Q (0) signal is twice the frequency of the signal Q (1).
For the third stage D flip-flop Fall2, the XB signal output by Fall1 is input to the CLK terminal of the third stage D flip-flop Fall2, the positive phase output Q (2) is triggered at the falling edge of the CLK signal at the input of flip-flop Fall2, the XB terminal is triggered at the rising edge of the CLK signal at the input of flip-flop Fall2, i.e., the flip-flop trigger point of the XB terminal of flip-flop Fall2 is 2 Clock cycles earlier than the positive phase output Q (2) and the frequency of the XB signal is the same as the signal Q (2), so that the flip-flop trigger point of the positive phase output Q (2) of flip-flop Fall2 lags the Clock cycle of Q (1) by one Clock cycle and the frequency of the Q (1) signal is twice the frequency of the signal Q (2).
For the fourth stage D flip-flop Fall3, the XB signal output by Fall2 is input to the CLK terminal of the fourth stage D flip-flop Fall3, and since the fourth stage D flip-flop Fall3 is triggered by a falling edge, the positive phase output Q (3) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall3, the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall3, that is, the flip-flop trigger point of the XB terminal of the flip-flop Fall3 is 4 Clock cycles earlier than the positive phase output Q (3) and the frequency of the XB signal is the same as the frequency of the signal Q (3), so that the flip-flop trigger point of the positive phase output Q (3) of the flip-flop lags the Clock cycle of the Q (2) signal by two Clock cycles, and the frequency of the Q (2) signal is twice the frequency of the signal Q (3).
The beneficial effects of the utility model are as follows:
1. compared with the prior art asynchronous Gray code counter circuit shown in FIG. 1, the dual edge triggered asynchronous Gray code counter circuit provided by the utility model, wherein Rise1 is a rising edge triggered D flip-flop, and Fall1, fall2 and Fall3 are falling edge triggered D flip-flops.
2. Compared with the prior art asynchronous Gray code counter circuit shown in fig. 1, the double-edge triggered asynchronous Gray code counter circuit provided by the utility model does not need a separate circuit to generate a marking signal. And because the normal phase output end Q (0) of the first stage D trigger can be normally used as the first bit of the Gray code counter, the waste of the first stage trigger is avoided. Since the flag signal generating circuit is not present in the whole circuit construction, the use of one D flip-flop is reduced, and the power consumption and area can be further reduced.
3. Compared with the prior art asynchronous Gray code counter circuit shown in fig. 1, the dual edge triggered asynchronous Gray code counter circuit provided by the utility model can maximally utilize the clock frequency in terms of overall function, namely, can complete Gray code counting only by half the time of the prior art asynchronous Gray code counter under the condition of reaching the same bit number Gray code counter.
Drawings
FIG. 1 is a circuit diagram of an asynchronous Gray code counter in the prior art;
FIG. 2 is a circuit diagram of a dual edge triggered asynchronous Gray code counter in accordance with the present utility model;
FIG. 3 is a circuit diagram of the basic structure of the D flip-flop;
FIG. 4 is a timing diagram illustrating an asynchronous Gray code counter according to the prior art;
FIG. 5 is a timing diagram illustrating the operation of the dual-edge triggered asynchronous Gray code counter according to the present utility model.
Detailed Description
The utility model will be described in detail below with reference to the drawings and the detailed description.
For the existing asynchronous gray code counter circuit shown in fig. 1, the positive output end of the first stage D flip-flop cannot be used as the bit number of the gray code counter because the first stage D flip-flop is required to generate the flag signal, so that the first stage D flip-flop causes a certain waste, and the problem that the utilization of the clock frequency is not maximized due to the generation of the first stage flag signal is solved. In view of this, the present utility model proposes a dual edge triggered asynchronous gray code counter structure as shown in fig. 2 to solve the above-mentioned problems.
The utility model relates to a double-edge triggered asynchronous Gray code counter, wherein Rise1 is a rising-edge triggered D trigger, and Fall1, fall2 and Fall3 are falling-edge triggered D triggers. The first stage uses a rising edge D trigger, the working Clock signal Clock is connected to the CLK input end of the rising edge D trigger, the rest stages use falling edge D triggers, and each stage has the same cascading mode, namely the inverting output end QB of the D trigger is connected to the D end of the D trigger of the stage, and the output end XB of the D trigger of the stage is connected to the CLK input end of the D trigger of the next stage. The D trigger of each stage is connected with R by a reset signal RST N And the reset end, the positive phase output end of each stage of D trigger is respectively used as each bit number Q (0), Q (1), Q (2) and Q (3) of the Gray code counter.
The basic structure of the D flip-flop circuit used therein, as shown in fig. 3, mainly comprises two latches connected in series, which are composed of tri-state gates and whose controlled conditions are different. Wherein T1, T4 are tri-state gates controlled by the inverse of the input signal Clock, T2, T3 are tri-state gates controlled by the input signal Clock, and H1, H2 are NOR gates. D-terminalAs the input end of the tri-state gate T1, the output ends of the tri-state gates T1 and T2 are connected and used as one input of the NOR gate H1, the reset end R N After passing through an inverter, the output signal of H1 is XB, XB is respectively used as the input of tri-state gates T2 and T3, the output ends of tri-state gates T3 and T4 are connected and used as one input of NOR gate H2, and the reset end R N After passing through one inverter, the output signal of H2 is used as the input of a tri-state gate T4, the output signal of H2 is used as a normal phase output end Q after passing through two stages of inverters, and the reverse phase output end QB is obtained after passing through one stage of inverter. Fig. 3 shows a rising edge triggered D flip-flop, which may be further changed to a falling edge triggered D flip-flop if tri-state gates T1, T4 are shifted with respect to tri-state gates T2, T3.
The two-edge triggered asynchronous Gray code counter circuit provided by the utility model has the advantages that the cascade mode of the second stage and the D trigger and the corresponding stages thereof are identical to the cascade mode in the prior asynchronous Gray code counter circuit shown in figure 1, except that a mark signal generating circuit is not required to be specially added in the first aspect; in a second aspect, the first stage D flip-flop employs a D flip-flop that toggles in an opposite manner than the other D flip-flops.
In a first aspect, the dual edge triggered asynchronous gray code counter circuit of fig. 2 does not require a separate circuit to generate the flag signal. And because the normal phase output end Q (0) of the first stage D trigger can be normally used as the first bit of the Gray code counter, the waste of the first stage trigger is avoided. Since the flag signal generating circuit is not present in the whole circuit construction, the use of one D flip-flop is reduced, and the power consumption and area can be further reduced.
In the second aspect, in the asynchronous gray code counter circuit triggered by two edges shown in fig. 2, the flip-flop of the first stage D flip-flop adopts a D flip-flop opposite to other D flip-flops, so that the flip-flop point of the XB terminal of the D flip-flop Rise1 is advanced by half a Clock cycle of Clock compared with the positive output signal Q (0), and the frequency of the XB signal is the same as that of the signal Q (0), and the output signal of the XB terminal of the flip-flop Rise1 is used as the input of the CLK terminal of the next stage D flip-flop, so that the output becomes the gray code. In terms of overall function, the introduction of double edge triggering can maximally utilize the clock frequency, namely, the Gray code counting can be completed only by half of the time of the existing asynchronous Gray code counter under the condition that the same bit number Gray code counter is reached.
It should be noted that the output XB is an output derived from the circuit of the D flip-flop, the D terminal is used as the input terminal of the tri-state gate T1, the outputs of the tri-state gates T1, T2 are connected and used as an input of the NOR gate H1, the reset terminal R N After passing through an inverter, the output signal of the nor gate H1 is the output XB.
The working principle of the double-edge triggered asynchronous Gray code counter of the utility model is as follows: for the first stage D flip-flop Rise1, the positive phase output Q (0) is triggered at the rising edge of the Clock signal Clock, and its XB terminal is triggered at the falling edge of the Clock signal Clock, i.e. the flip-flop trigger point of the XB terminal is advanced by half Clock cycle of Clock than the positive phase output Q (0), and the frequency of the XB signal is the same as the signal Q (0). For the second stage D flip-flop Fall1, the XB signal output by Rise1 is input to the CLK terminal of the second stage D flip-flop Fall1, and since the second stage D flip-flop Fall1 is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall1, the positive phase output Q (1) is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall1, i.e., the flip-flop trigger point of the XB terminal of the flip-flop Fall1 is one Clock cycle earlier than the positive phase output Q (1) by one Clock cycle, and the frequency of the XB signal is the same as the frequency of the signal Q (1), so that the flip-flop trigger point of the positive phase output Q (1) of the flip-flop Fall1 lags by Q (0) half the Clock cycle of the Clock cycle, and the frequency of the Q (0) signal is 2 times the frequency of the signal Q (1). For the third stage D flip-flop Fall2, the XB signal output by Fall1 is input to the CLK terminal of the third stage D flip-flop Fall2, and since the third stage D flip-flop Fall2 is triggered by a falling edge, the positive phase output Q (2) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall2, and the XB terminal thereof is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall2, that is, the flip-flop trigger point of the XB terminal of the flip-flop Fall2 is earlier than the positive phase output signal Q (2) by 2 Clock cycles, and the frequency of the XB signal is the same as the frequency of the signal Q (2), so that the flip-flop trigger point of the positive phase output Q (2) of the flip-flop lags the Clock cycle of Q (1) by one Clock cycle of Q (1), and the frequency of the Q (1) signal is 2 times the frequency of the signal Q (2). For the fourth stage D flip-flop Fall3, the XB signal output by Fall2 is input to the CLK terminal of the fourth stage D flip-flop Fall3, and since the fourth stage D flip-flop Fall3 is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall3, the positive phase output Q (3) is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall3, that is, the flip-flop trigger point of the XB terminal of the flip-flop Fall3 is 4 Clock cycles earlier than the positive phase output Q (3) and the frequency of the XB signal is the same as the signal Q (3), so that the flip-flop trigger point of the positive phase output Q (3) of the flip-flop Fall3 lags the Clock cycle of the Q (2) signal by 2 Clock cycles, and the frequency of the Q (2) signal is 2 times the frequency of the signal Q (3). To sum up, Q (0), Q (1), Q (2) and Q (3) constitute a 4-bit gray code counter.
Fig. 4 is a timing diagram of an asynchronous gray code counter according to the prior art shown in fig. 1, and fig. 5 is a timing diagram of an asynchronous gray code counter triggered by double edges according to the present utility model. As can be seen from fig. 4 and 5, both can implement the gray code counting function, except that the time consumed in fig. 5 is only half of that in fig. 4 when implementing the 4-bit gray code counter function, so that the clock frequency is maximally utilized.
The double-edge triggered asynchronous Gray code counter has the advantages that: 1. in terms of the whole circuit construction, because a sign signal generating circuit is not arranged, the use of a D trigger is reduced, and the power consumption and the area can be further reduced; 2. in terms of overall function, the introduction of double edge triggering can maximally utilize the clock frequency, namely, the Gray code counting can be completed only by half of the time of the existing asynchronous Gray code counter under the condition that the same bit number Gray code counter is reached.
Claims (7)
1. The double-edge triggered asynchronous Gray code counter is characterized in that: the first stage flip-flop Rise1 is used as a rising edge triggered D flip-flop, and the rest stages of flip-flops Fall1, fall2 and Fall3 are used as falling edge triggered D flip-flops.
2. The double edge triggered asynchronous gray code counter of claim 1, wherein: the first stage flip-flop Rise1 uses a rising edge D flip-flop, the working Clock signal Clock is connected to the CLK input end of the rising edge D flip-flop, the rest stages all use falling edge D flip-flops, and each stage has the same cascading mode, namely the inverting output end QB of the D flip-flop is connected to the D end of the D flip-flop of the stage, and the output end XB of the D flip-flop of the stage is connected to the CLK input end of the D flip-flop of the next stage.
3. The double edge triggered asynchronous gray code counter of claim 2, wherein: the D trigger of each stage is connected with R by a reset signal RST N And the reset end, the positive phase output end of each stage of D trigger is respectively used as each bit number Q (0), Q (1), Q (2) and Q (3) of the Gray code counter.
4. The double edge triggered asynchronous gray code counter of claim 1, wherein: for the first stage D flip-flop Rise1, the positive phase output Q (0) is triggered at the rising edge of the Clock signal Clock, and the XB terminal is triggered at the falling edge of the Clock signal Clock, i.e., the flip-flop trigger point of the XB terminal is advanced by half Clock cycle of Clock than the positive phase output Q (0), and the frequency of the XB signal is the same as the signal Q (0).
5. The double edge triggered asynchronous gray code counter of claim 4, wherein: for the second stage D flip-flop Fall1, the XB signal output by Rise1 is input to the CLK terminal of the second stage D flip-flop Fall1, the positive phase output Q (1) is triggered at the falling edge of the CLK signal at the input terminal of flip-flop Fall1, the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of flip-flop Fall1, i.e., the flip-flop trigger point of the XB terminal of flip-flop Fall1 is one Clock cycle earlier than the positive phase output Q (1) by one Clock cycle, and the frequency of the XB signal is the same as the signal Q (1), so that the flip-flop trigger point of the positive phase output Q (1) of flip-flop Fall1 lags by one half Clock cycle of Q (0), and the frequency of the Q (0) signal is twice the frequency of the signal Q (1).
6. The double edge triggered asynchronous gray code counter of claim 5, wherein: for the third stage D flip-flop Fall2, the XB signal output by Fall1 is input to the CLK terminal of the third stage D flip-flop Fall2, the positive phase output Q (2) is triggered at the falling edge of the CLK signal at the input of flip-flop Fall2, the XB terminal is triggered at the rising edge of the CLK signal at the input of flip-flop Fall2, i.e., the flip-flop trigger point of the XB terminal of flip-flop Fall2 is 2 Clock cycles earlier than the positive phase output Q (2) and the frequency of the XB signal is the same as the signal Q (2), so that the flip-flop trigger point of the positive phase output Q (2) of flip-flop Fall2 lags the Clock cycle of Q (1) by one Clock cycle and the frequency of the Q (1) signal is twice the frequency of the signal Q (2).
7. The double edge triggered asynchronous gray code counter of claim 6, wherein: for the fourth stage D flip-flop Fall3, the XB signal output by Fall2 is input to the CLK terminal of the fourth stage D flip-flop Fall3, and since the fourth stage D flip-flop Fall3 is a falling edge trigger, the positive phase output Q (3) is triggered at the falling edge of the CLK signal at the input terminal of the flip-flop Fall3, the XB terminal is triggered at the rising edge of the CLK signal at the input terminal of the flip-flop Fall3, that is, the flip-flop trigger point of the XB terminal of the flip-flop Fall3 is 4 Clock cycles earlier than the positive phase output Q (3) and the frequency of the XB signal is the same as the frequency of the signal Q (3), so that the flip-flop trigger point of the positive phase output Q (3) of the flip-flop Fall3 lags the Clock cycle of the Q (2) signal by two Clock cycles, and the frequency of the Q (2) signal is twice the frequency of the signal Q (3).
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