CN116488462A

CN116488462A - Control circuit and method suitable for stackable multiphase power converter

Info

Publication number: CN116488462A
Application number: CN202211507470.8A
Authority: CN
Inventors: 杨大勇; 吴纬权; 杨智皓; 黄柄境; 方立文
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2022-01-24
Filing date: 2022-11-29
Publication date: 2023-07-25

Abstract

A control circuit and method for a stackable multiphase power converter. A control circuit for controlling a stackable multiphase power converter includes: a synchronous terminal; a synchronization signal connected in parallel with a plurality of synchronization terminals of the plurality of control circuits, wherein the synchronization signal includes a plurality of pulses to be continuously counted as a count value; and a reset signal for resetting and starting the count of the count value; the control circuit also comprises a phase sequence number, wherein when the count value is related to the phase sequence number, the control circuit enables the corresponding power stage circuit to generate the output power supply.

Description

Control circuit and method suitable for stackable multiphase power converter

Technical Field

The present invention relates to a control circuit, and more particularly, to a control circuit for a stackable multi-phase power converter. The invention also relates to a method adapted to control a stackable multiphase power converter.

Background

Stackable multiphase power converters provide high performance dc/dc power conversion for high load currents and fast transient response requirements. Accordingly, stackable multiphase power converters are widely used in central processing units, CPUs, graphics processing units, GPUs, and artificial intelligence, AI, for high performance computing applications. As the load current increases, the number of phases of the stackable multi-phase power converter increases. The number of phases is reduced during light load to save power.

Fig. 1 shows a prior art stackable multiphase power converter: US11,081,954"Phase shedding control method used in multiphase switching converters with daisy chain configuration". This prior art uses a daisy chain configuration (Daisy chain configuration) in a stackable multiphase power converter.

The disadvantage of the daisy chain configuration shown in the prior art of fig. 1 is the poor fault tolerance. Failure of any one control circuit in the daisy chain can cause the entire power converter to cease functioning.

The invention provides a control circuit for controlling a stackable multiphase power converter, which has fewer control signals, and is simpler and more reliable. The control signal of the present invention is connected in parallel with the stackable control circuit of the stackable multiphase power converter without adopting a daisy chain configuration.

Disclosure of Invention

In one aspect, the present invention provides a control circuit for controlling a stackable multiphase power converter, wherein the stackable multiphase power converter comprises a plurality of power stage circuits and a corresponding number of control circuits, wherein the power stage circuits are coupled in parallel with each other to generate an output power to a load, wherein each of the power stage circuits comprises at least one switch for controlling a corresponding one of the inductors, wherein each of the control circuits is coupled to a corresponding one of the power stage circuits, the control circuit comprising: a synchronous terminal; a synchronization signal for connecting to the synchronization terminal in parallel, and related to the control circuits, wherein the synchronization signal comprises a plurality of pulses for being continuously counted as a count value; and a reset signal for resetting and starting the count of the count value; the control circuit also comprises a phase sequence number, wherein when the count value is related to the phase sequence number, the control circuit enables the corresponding power stage circuit to generate the output power supply.

In a preferred embodiment, the control circuit further comprises a setting terminal for setting the phase sequence number, wherein the phase sequence number is determined according to an electrical reference number of the setting terminal.

In a preferred embodiment, the control circuit further determines whether to operate as a master circuit or a slave circuit according to the phase sequence number; the main circuit generates the synchronous signal through the synchronous terminal, and the slave circuit is used for receiving the synchronous signal through the synchronous terminal; the master circuit generates the reset signal, and the slave circuit is used for receiving the reset signal.

In a preferred embodiment, the control circuit further comprises a counter for continuously counting the pulses of the synchronization signal to generate the count value; wherein the reset signal is generated when the count value reaches a maximum value.

In a preferred embodiment, the reset signal is generated when the count value reaches a phase-cut number, wherein the phase-cut number increases as the current of the load increases.

In a preferred embodiment, the control circuit further comprises: and a synchronization circuit for generating the synchronization signal through the synchronization terminal when the control circuit is used as the master circuit, and receiving the synchronization signal through the synchronization terminal when the control circuit is used as the slave circuit.

In a preferred embodiment, the control circuit further comprises: a reset terminal, wherein the reset signal is connected with the reset terminals corresponding to the control circuits, and the reset terminals are coupled in parallel; and a reset circuit for generating the reset signal through the reset terminal when the control circuit is used as the master circuit and receiving the reset signal when the control circuit is used as the slave circuit.

In a preferred embodiment, the pulse width of the reset signal is shorter than the pulse width of the synchronization signal.

In a preferred embodiment, a pulse with a higher voltage level in the synchronization signal is used as the reset signal.

In a preferred embodiment, the power stage circuit is a fixed on-time power converter; the fixed on-time power converter is triggered in response to a pulse of the synchronization signal.

In a preferred embodiment, the control circuit further comprises a current source coupled to a resistor through the set terminal, wherein the phase number is determined according to the voltage level of the set terminal.

In a preferred embodiment, the control circuit is configured as an integrated circuit and the synchronization terminal corresponds to a synchronization pin of the integrated circuit.

In another aspect, the present invention provides a method for controlling a stackable multiphase power converter, wherein the stackable multiphase power converter comprises a plurality of power stage circuits and a corresponding number of controllers, wherein the power stage circuits are coupled in parallel with each other to generate an output power to a load, wherein each of the power stage circuits comprises at least one switch for controlling a corresponding one of the inductors, wherein each of the controllers is coupled to a corresponding one of the power stage circuits, the method comprising: generating a synchronization signal connected in parallel with the controllers of the stackable multiphase power converter without adopting a daisy chain configuration; generating a reset signal according to the synchronous signal; each controller comprises a phase sequence number, wherein the synchronous signal comprises a plurality of pulses, the plurality of pulses are used for being continuously counted into a count value, when the count value is related to the phase sequence number, the controller enables the corresponding stackable multiphase power converter to generate the output power supply to the load, and the reset signal is used for resetting and starting the counting of the count value.

The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of specific embodiments.

Drawings

Fig. 1 shows a prior art stackable multiphase power converter.

FIG. 2A is a schematic diagram of a stackable multi-phase power converter according to a preferred embodiment of the present invention.

FIG. 2B is a schematic diagram of a stackable multi-phase power converter according to another preferred embodiment of the present invention.

Fig. 2C shows a more detailed schematic of a subconverter of the stackable multiphase power converter.

FIG. 3 is a block diagram of a control circuit according to a preferred embodiment of the present invention (FIG. 2A).

FIG. 4 shows waveforms corresponding to the stackable 4-phase power converter shown in FIG. 2A in a preferred embodiment according to the present invention.

Fig. 5 shows a switching waveform of an 8-phase power converter employing a stackable control circuit according to a preferred embodiment of the present invention.

FIG. 6 is a schematic diagram of a subconverter and PWM timing circuit of a stackable multi-phase power converter according to one embodiment of the present invention.

Fig. 7 is a schematic diagram of a synchronization circuit for generating a synchronization signal according to a preferred embodiment of the invention.

FIG. 8 is a schematic diagram of a phase enable circuit for generating a ready signal according to a preferred embodiment of the present invention.

FIG. 9 is a schematic diagram of a reset circuit for generating a reset signal according to a preferred embodiment of the present invention.

FIG. 10 is a schematic diagram of a stackable multi-phase power converter according to another preferred embodiment of the present invention.

Fig. 11 shows a schematic diagram of a 4-phase switching waveform corresponding to the control circuit shown in fig. 10 in accordance with a preferred embodiment of the present invention.

Fig. 12 is a schematic diagram of a synchronization circuit for generating a synchronization signal mixed with a reset signal according to a preferred embodiment of the present invention corresponding to fig. 10 and 11.

FIG. 13 shows a reset circuit for generating a reset control signal according to a preferred embodiment of the present invention, corresponding to FIGS. 10, 11 and 12.

Fig. 14 is a schematic diagram of a pulse mixer of the synchronization circuit according to a preferred embodiment of the present invention corresponding to fig. 10, 11 and 12.

Description of the symbols in the drawings

10. 20, 30, 40: power stage circuit

101: stackable multiphase power converter

102A: stackable multiphase power converter

102B: stackable multiphase power converter

102C1, 102C2: integrated circuit

106: sub-converter

110: stackable multiphase power converter

130: error amplifier

141. 142: resistor

15. 25, 35, 45: control circuit

150: comparator with a comparator circuit

16. 26, 36, 46: driver(s)

160: buffer device

17. 27, 37, 47: resistor

170: multiplexer

175: inverter with a high-speed circuit

1N: driver(s)

210: constant current source

220: analog-to-digital converter

230: counter

235: inverter with a high-speed circuit

240: delay unit

250: digital comparator

260: flip-flop

320: analog-to-digital converter

335: flip-flop

360: buffer device

370: multiplexer

503: control circuit

51: driver(s)

55. 65, 75, 85: control circuit

56: master-slave decision circuit

560: pulse mixer

57: synchronous circuit

57': synchronous circuit

58: phase enable circuit

59: reset circuit

59': reset circuit

60: pulse width modulation timing circuit

5N: control circuit

710. 720: buffer device

715. 725: diode

750: transistor with a high-voltage power supply

90: conduction time timing circuit

91: single-shot pulse generator

92: latch circuit

93: AND gate

95: minimum off-time timing circuit

99: load(s)

CLK: clock signal

CMP: comparing signals

ISUM: load current

IX: number of tangential phases

L: inductor(s)

L1-LN: inductor(s)

MS: main signal

MST: main circuit

N_max: maximum phase number value

N0: power stage circuit

NX: count value

QH: high side switch

QL: low side switch

R#: reset terminal

RAMP: ramp signal

RDY: ready signal

RMC: combined ramp signal

RSRn: inverted reset control signal

RST: reset signal

Rst_c: reset control signal

RST_C': reset control signal

S#: set terminal

S1-SN: slave circuit

Set_n: phase number

SPWM: pulse width modulation control signal

SW: switching node signals

SW0-SWN: switching node signals

SX: synchronous generation of signals

SYNC: synchronization signal

Sync_c: synchronous control signal

t0'-t1': time point

t0-t7: time point

Ton: conduction period

VA: amplifying a signal

VFB: feedback voltage

VH: high voltage level

VIN: input voltage

VL: low voltage level

VO: output voltage

VREF: reference voltage

Vst1-VstN: voltage (V)

VT1: critical voltage

VTH: threshold value

Y#: synchronous terminal

Detailed Description

The drawings in the present invention are schematic and are mainly intended to represent coupling relationships between circuits and relationships between signal waveforms, which are not drawn to scale.

FIG. 2A is a schematic diagram of a stackable multi-phase power converter according to a preferred embodiment of the present invention. The stackable multiphase power converter 102A includes power stage circuits 10, 20, 30, 40 connected in parallel with one another to generate an output power source (e.g., corresponding to output voltage VO) to a load 99. In one embodiment, the power stage circuits 10, 20, 30, 40 operate in an interleaved phase fashion. More specifically, the power stage circuits 10, 20, 30, 40 are configured to switch the inductors L1, L2, L3, LN for interleaved switching power conversion, where N is an integer greater than 1.

In one embodiment, the power stage circuit is a buck converter. However, this is not intended to limit the scope of the invention. The power stage circuit may also be other switching power converters, such as boost, buck-boost, flyback power converters.

The stackable multiphase power converter further comprises stackable control circuits 15, 25, 35, 45 for controlling the switching of the corresponding power stage circuits 10, 20, 30, 40, respectively. In an embodiment, the stackable multiphase power converter also includes a corresponding number of drivers 16, 26, 36, 46, where each driver is connected between a corresponding control circuit and power stage circuit and is configured to drive the switch.

In one embodiment, each of the control circuits 15, 25, 35, 45 is programmable to act as a master or a slave, and the interleaved phase sequence numbers are also programmable. With continued reference to fig. 2A, in one embodiment, each of the control circuits 15, 25, 35, 45 includes a SET terminal s# for setting the phase sequence number set_n. In one embodiment, a resistor cooperating with the constant current source of the control circuit is used to determine the phase sequence number SET_N of the control circuit. The resistors 17, 27, 37, 47 are connected to the control circuits 15, 25, 35, 45, respectively, to SET the phase sequence number set_n of the corresponding control circuit. The phase number SET_N is determined according to the voltage level of the SET terminal S#. In one embodiment, the corresponding phase number set_n is determined by detecting the voltages (e.g., vst1, vst3, vst 4) on the SET terminal s# of the control circuit.

In one embodiment, the setting terminal s# of the control circuit 15 is coupled to the ground potential to SET its phase sequence number set_n to 0 (i.e., the resistor 17 may be omitted as a short circuit). In one embodiment, the phase sequence number SET_N further determines whether the control circuit operates as a master or slave. In one embodiment, the SET terminal s# of the control circuit 15 is grounded to SET its phase sequence number set_n to 0 to program the control circuit 15 to operate as a main circuit. In one embodiment, the resistance values R27, R37, R47 of the resistors 27, 37, 47 are related to R27< R34< R47, in which case the phase sequence set_n of the control circuit 25, 35, 45 is SET to 1, 2, 3, respectively. In one embodiment, the phase number SET_N other than 0 also determines the control circuits 25, 35, 45 as slave circuits (labeled S1, S2, SN, respectively, in FIG. 2A).

With continued reference to fig. 2A, in one embodiment, each of the control circuits 15, 25, 35, 45 includes a synchronization terminal y#, for transmitting and receiving a synchronization signal SYNC.

In one embodiment, all of the synchronization terminals (i.e., Y# in the control circuits 15, 25, 35, 45) are connected together or, from another perspective, in parallel. In one embodiment, the master circuit (e.g., control circuit 15) generates and transmits the synchronization signal SYNC through the corresponding synchronization terminal y#. On the other hand, the slave circuit (e.g., control circuits 25, 35, 45) is configured to receive the synchronization signal SYNC through the corresponding synchronization terminal y#.

With continued reference to fig. 2A, in one embodiment, each of the control circuits 15, 25, 35, 45 includes a reset terminal r#, for transmitting and receiving a reset signal RST.

In one embodiment, all reset terminals (i.e., R# in control circuits 15, 25, 35, 45) are connected together or, from another perspective, in parallel. In one embodiment, the master circuit (e.g., control circuit 15) generates and transmits the reset signal RST through the corresponding reset terminal r#. On the other hand, the slave circuit (e.g., control circuits 25, 35, 45) is configured to receive the reset signal RST through the corresponding reset terminal r#.

FIG. 2B is a schematic diagram of a stackable multi-phase power converter according to another preferred embodiment of the present invention. The stackable multiphase power converter 102B is similar to the stackable multiphase power converter 102A, except that the set terminal s# in the control circuit of the stackable multiphase power converter 102B is omitted. In this embodiment, the phase sequence number set_n may be SET by other means, such as a preprogrammed one or more programmable memory circuits, or a digital communication interface (e.g., I2C).

Fig. 2C shows a more detailed schematic of a subconverter of the stackable multiphase power converter. The subconverter is responsible for supplying power to one of the phases of the stackable multi-phase power converter. As shown in fig. 2A, the plurality of subconverters are coupled to form a stackable multiphase power converter.

In one embodiment, the control circuit (e.g., 5N) is integrated in an integrated circuit. In one embodiment, the control circuit 5N and the driver (e.g., 1N) may be integrated into an integrated circuit 102C 1. In one embodiment, the control circuit 5N, the driver 1N, and the power stage circuit (e.g., N0) may be integrated into an integrated circuit 102C2. In an embodiment, the synchronization terminal y# of the control circuit 5N corresponds to a synchronization pin of the integrated circuit.

FIG. 3 is a block diagram of a control circuit according to a preferred embodiment of the present invention (FIG. 2A). In the present embodiment, the control circuit 503 includes a master-slave determination circuit 56, a synchronization circuit 57, a phase enable circuit 58, a reset circuit 59, and a pulse width modulation timing circuit 60.

The master-slave determining circuit 56 generates a master signal MS according to the voltage VstN at the setting terminal s# of the control circuit 503, wherein the master signal MS is used to indicate the control circuit 503 as a master circuit or a slave circuit. In one embodiment, the control circuit 503 corresponding to the master signal MS for enabling state indication is set as the master circuit. The reset circuit 59 generates a reset control signal rst_c according to the reset signal RST, wherein the reset circuit 59 generates the reset signal RST through the reset terminal r# when the control circuit 503 is used as a master circuit (e.g., indicated by an enable state of the master signal MS, and the same applies hereinafter). When the control circuit 503 is used as a slave circuit (for example, indicated by the prohibition state of the master signal MS, the same applies hereinafter), the reset circuit 59 receives the reset signal RST through the reset terminal r#.

The synchronization circuit 57 generates a synchronization control signal sync_c according to the synchronization signal SYNC. When the control circuit 503 is used as a main circuit, the synchronization circuit 57 generates a synchronization signal SYNC through a synchronization terminal y#. When the control circuit 503 is used as a slave circuit, the synchronization circuit 57 receives the synchronization signal SYNC through the synchronization terminal y#.

The phase enable circuit 58 generates a ready signal RDY according to the reset control signal rst_c, the voltage VstN on the set terminal s#, the synchronization control signal sync_c, and the master signal MS. The pwm timing circuit 60 generates a pwm control signal SPWM according to the synchronization control signal sync_c and the master signal MS. The controller 1N drives the high-side switch QH and the low-side switch QL according to the pulse width modulation control signal SPWM.

FIG. 4 shows waveforms corresponding to the stackable 4-phase power converter shown in FIG. 2A in a preferred embodiment according to the present invention. In one embodiment, the synchronization signal SYNC includes a plurality of pulses that are continuously counted as a count value NX in the control circuit. In one embodiment, when the count value NX is related to the phase sequence number set_n, each control circuit enables the corresponding power stage circuit to generate the output power to the load 99. For example, in a preferred embodiment, when the count value NX is equal to the phase sequence number set_n, each control circuit enables the corresponding power stage circuit to generate the output power to the load 99.

In the present embodiment, the reset signal RST is used to reset and start counting of the count value NX in each multiphase period, which ensures that the stackable multiphase power converter according to the present invention has a stable configuration and operation.

With continued reference to fig. 4, in one embodiment, when the count value NX is related to (e.g., equal to) the phase sequence number set_n, the ready signal RDY is enabled, and when the ready signal RDY is enabled, the control circuit enables the corresponding power stage circuit to generate the output power to the load 99.

In the present embodiment, the phase numbers set_n of the control circuits 15, 25, 35, 45 are SET to 0, 1, 2, 3, respectively. With continued reference to fig. 4, the operational flow of the stackable multiphase power converter 102A will be explained.

Time t0: the synchronization signal SYNC and the reset signal RST are generated (e.g., by the control circuit 15), and the count value NX of each of the control circuits 15, 25, 35, 45 is reset to 0.

Time t1: since the count value NX is 0 and is equal to the phase sequence number set_n of the control circuit 15, the falling edge of the synchronization signal SYNC triggers the control circuit 15 to enable the power stage circuit 10 to generate the output power to the load 99, for example, by controlling the high-side switch of the power stage circuit 10 to be conductive, so that the switching node signal SW0 is controlled to be the input voltage VIN for a conductive period Ton. At the same time, the falling edge of the synchronization signal SYNC increases the count value NX to 1. It should be noted that the on period Ton is determined by the pwm timer circuit 60.

Time t2: the rising edge of the synchronization signal SYNC latches the state of the ready signal RDY. Since the phase sequence number set_n of the control circuit 25 is SET to 1, the ready signal RDY of the control circuit 25 is enabled.

Time t3: the falling edge of the synchronization signal SYNC triggers the control circuit 25 (the count value NX is 1) to enable the power stage circuit 20 to generate the output power to the load 99, for example, by controlling the high side switch of the power stage circuit 20 to be turned on, so that the switching node signal SW1 is controlled to the input voltage VIN for an on period Ton. At the same time, the falling edge of the synchronization signal SYNC increases the count value NX to 2.

Time t4: the rising edge of the synchronization signal SYNC latches the state of the ready signal RDY. Since the phase sequence number set_n of the control circuit 35 is SET to 2, the ready signal RDY of the control circuit 35 is enabled.

Time t5: the falling edge of the synchronization signal SYNC triggers the control circuit 35 (the count value NX is 2) to enable the power stage circuit 30 to generate the output power to the load 99, for example, by controlling the high side switch of the power stage circuit 30 to be turned on, so that the switching node signal SW2 is controlled to the input voltage VIN for an on period Ton. At the same time, the falling edge of the synchronization signal SYNC increases the count value NX to 3.

Time t6: the rising edge of the synchronization signal SYNC latches the state of the ready signal RDY. Since the phase sequence number set_n of the control circuit 45 is SET to 3, the ready signal RDY of the control circuit 45 is enabled.

Time t7: the falling edge of the synchronization signal SYNC triggers the control circuit 45 (the count value NX is 3) to enable the power stage circuit 40 to generate the output power to the load 99, for example, by controlling the high-side switch of the power stage circuit 40 to be turned on, so that the switching node signal SW3 is controlled to the input voltage VIN for an on period Ton. At the same time, the falling edge of the synchronization signal SYNC increases the count value NX to 4.

The reset signal RST is generated when the count value NX is equal to or higher than a maximum value. In this embodiment, the maximum value is 4. Therefore, when the count value NX is 4 (e.g. at time t 0'), the reset signal RST is triggered at the rising edge of the synchronization signal SYNC to reset the counter.

Although the synchronization signal SYNC and the reset signal RST are generated simultaneously, in one embodiment, the pulse width of the reset signal RST is shorter than the pulse width of the synchronization signal SYNC.

In one embodiment, the reset signal RST is also generated when the count value NX reaches a phase tangent number IX. The phase-cut number IX increases as the load current ISUM of the load 99 increases. Taking the 4-phase power converter shown in fig. 4 as an example, when the load current ISUM decreases to a certain extent, the phase-cut number IX decreases from 4 (this is the maximum phase number of the 4-phase power converter) to 3. In this case, the fourth phase sub-converter (i.e., the control circuit 45 and the power stage circuit 40) is masked (shed) and stops switching, and the first phase sub-converter (i.e., the control circuit 15 and the power stage circuit 10), the second phase sub-converter (i.e., the control circuit 25 and the power stage circuit 20), and the third phase sub-converter (i.e., the control circuit 35 and the power stage circuit 30) remain active and switch to generate the output power to the load. The phase-cut number IX can be further reduced to 2 or 1 depending on the level of the load current ISUM.

The total phase value (maximum phase number) in a stackable multi-phase power converter coupled using the stackable control circuit according to the present invention may be any positive integer. Fig. 5 shows a switching waveform of an 8-phase power converter formed by the stackable control circuit according to the present invention in accordance with a preferred embodiment of the present invention. The 8-phase power converter employs 8 control circuits configured similarly to the case of n=8 in fig. 2 to control a corresponding number of power stage circuits to generate output power to a load. It should be noted that the on periods of the switches of the different phases may not overlap (e.g., the switch node signals SW0 to SW3 shown in fig. 4) or overlap (e.g., the switch node signals SW0 to SW7 shown in fig. 5), which is determined according to the feedback control loop of the output power supply and the corresponding control circuit and power stage circuit.

In one embodiment, the stackable multi-phase power converter (e.g., 102A, 102B of fig. 2A, 2B) is a Constant on-time (COT) power converter. A multiphase fixed on-time power converter (e.g., 102A in fig. 2A) triggers a fixed on-time in the fixed on-time power converter in response to a pulse of a synchronization signal SYNC. More specifically, in one embodiment, each corresponding sub-converter (i.e., the control circuit and the corresponding power stage circuit cooperate) is a fixed on-time power converter and is triggered in response to a pulse associated with the phase sequence number set_n in the synchronization signal SYNC (e.g., the high-side switch of the corresponding power stage circuit causes it to turn on for a fixed on-time).

Fig. 6 shows a schematic diagram of a subconverter 106 and a pwm timing circuit 60 of a stackable multiphase power converter according to a preferred embodiment of the present invention. The pulse width modulation clocking circuit 60 of the control circuit is used to control the power stage circuit 50. In one embodiment, the pwm timing circuit 60 comprises an on-time timing circuit 90, a single pulse generator 91, a latch circuit 92, an and gate 93, and a minimum off-time timing circuit 95.

When the pwm control signal SPWM is triggered (e.g., for controlling the high-side switch QH to be turned on and the low-side switch QL to be turned off), the on-time timing circuit 90 controls the on-period Ton of the switching node signal SW (e.g., the switching node signal SW0 shown in fig. 4). In one embodiment, the on period Ton decreases as the input voltage VIN of the stackable multiphase power converter increases. In one embodiment, the on period Ton increases as the output current of the load 99 increases to further improve the load transient response. The minimum off-time timer 95 provides a minimum off-time for the pwm control signal SPWM (i.e., the switching node signal SW). When the ready signal RDY is enabled, the synchronization control signal sync_c turns on the high-side switch QH through the one-shot pulse generator 91. The synchronization control signal sync_c is generated according to the falling edge of the pulse corresponding to the synchronization signal SYNC.

Fig. 7 is a schematic diagram of a synchronization circuit for generating a synchronization signal SYNC according to a preferred embodiment of the invention. The resistors 141, 142 are configured as a voltage divider for generating a feedback voltage VFB according to an output power source (e.g., the output voltage VO). The error amplifier 130 (e.g., a transconductance amplifier) amplifies a difference between a reference voltage VREF and the feedback voltage VFB to generate an amplified signal VA. The feedback voltage VFB is added to a RAMP signal RAMP to generate a combined RAMP signal RMC. A comparator 150 is used to compare the combined ramp signal RMC with the amplified signal VA to generate a comparison signal CMP. In one embodiment, the RAMP signal RAMP is generated based on a load current ISUM, where the load current ISUM is the sum of inductor currents of all phases in the stackable multi-phase power converter.

The comparison signal CMP triggers the one-shot pulse generator 155 to generate a synchronization-generating signal SX. The synchronization-generating signal SX is buffered by the buffer 160.

The master-slave determination circuit 56 includes a comparator 180 for generating the master signal MS when the voltage at the set terminal S# is lower than a threshold voltage VT1 (e.g., 0.5 volts). When the control circuit is used as a master circuit, the master signal MS enables the buffer 160 to generate the synchronization signal SYNC through the synchronization terminal y#. The pulse width of the synchronization-generating signal SX determines the pulse width of the synchronization signal SYNC.

The multiplexer 170 is used for selecting the synchronization signal SYNC or the synchronization generating signal SX according to the control of the master signal MS to generate the synchronization control signal sync_c and the clock signal CLK. When the control circuit is used as a slave circuit, the multiplexer 170 selects the synchronization signal SYNC through the synchronization terminal y# to generate the synchronization control signal sync_c and the clock signal CLK. The clock signal CLK is related to the rising edge of the synchronization signal SYNC. In one aspect, the clock signal CLK is the same as the synchronization signal SYNC. In one embodiment, when the control circuit is used as a main circuit, the multiplexer 170 selects the synchronization generating signal SX to generate the synchronization control signal sync_c and the clock signal CLK on the synchronization terminal y#.

FIG. 8 shows a schematic diagram of a phase enable circuit 58 for generating the ready signal RDY according to a preferred embodiment of the present invention. In one embodiment, constant current source 210 outputs a certain current (e.g., 50 microamps) to set terminal S#. The constant current flows through a resistor (e.g., 10 kiloohms to 80 kiloohms) through a SET terminal s# to generate a voltage VstN (e.g., 0.5 volts to 4 volts) for setting the phase sequence number set_n. The adc 220 is connected to the SET terminal s#, and is used for converting the voltage VstN to generate the phase numbers set_n (e.g., 0 to 7, as shown in the embodiment of fig. 5). The counter 230 generates a count value NX according to, for example, a synchronization control signal sync_c (e.g., a rising edge). The counter 230 is reset by a reset control signal rst_c. The reset control signal rst_c is generated according to the reset signal RST. In one embodiment, an inverter 235 is also configured to generate an inverted reset control signal RSTn to reset the counter 230. The count value NX is compared with the phase sequence number set_n by a digital comparator 250 (e.g. an anti-exclusive or gate) to determine whether the count value NX reaches the phase sequence number set_n. The flip-flop 260 is configured to generate the ready signal RDY when the count value NX reaches the phase sequence number set_n according to the comparison result of the digital comparator 250. The state of flip-flop 260 is triggered and latched by clock signal CLK. In one embodiment, the clock signal CLK is delayed by a delay unit 240 to trigger the flip-flop 260. In one aspect, the ready signal RDY enables the corresponding power stage circuit to generate the output power.

Fig. 9 shows a schematic diagram of a reset circuit 59 for generating a reset signal RST according to a preferred embodiment of the invention. The analog-to-digital converter 320 is configured to convert the load current ISUM into the phase-cut number IX. The count value NX is compared with the tangent phase number IX by a digital comparator 330 (e.g., an anti-exclusive or gate) to determine whether the count value NX reaches the tangent phase number IX. In the present embodiment, the output of the digital comparator 330 is connected to the flip-flop 335, and generates the reset signal RST when the count value NX reaches the phase-cut number IX.

With continued reference to fig. 9, when the count value NX reaches a maximum phase value n_max of the count value NX, the comparing circuit 310 is further configured to set the flip-flop 335 to generate the reset signal RST. For example, in a 4-phase power converter, the maximum phase number n_max is 4 and the phase-cut number IX may be 4, 3, 2, or 1. In an 8-phase power converter, the maximum phase number n_max is 8 and the phase-tangent number IX may be any integer from 1 to 8.

The output of the flip-flop 335 is synchronized by the clock signal CLK to trigger the one-shot pulse generator 350 to generate the reset generation signal RX. The master signal MS is configured to output a reset signal RST according to the reset generation signal RX to enable the buffer 360. The multiplexer 370 selects the reset signal RST or the reset generation signal RX according to the control of the main signal MS to generate the reset control signal rst_c. When the control circuit is used as a slave circuit, the multiplexer 370 selects the reset signal RST received through the reset terminal r# to generate the reset control signal rst_c. On the other hand, when the control circuit is used as a main circuit, the multiplexer 370 selects the reset generation signal RX to generate the reset control signal rst_c on the reset terminal r#.

FIG. 10 is a schematic diagram of a stackable multi-phase power converter according to another preferred embodiment of the present invention. The stackable multi-phase power converter 110 in fig. 10 is similar to the stackable multi-phase power converter 102B in fig. 2B, except that the control circuitry 55, 65, 75, 85 of the stackable multi-phase power converter 110 does not include dedicated reset terminals. In the present embodiment, the reset control signal rst_c' is generated according to the synchronization signal SYNC. The reset control signal rst_c' is used to reset and start counting of the count value in each multiphase period, and the same operation as the reset signal RST and the corresponding reset control signal rst_c in the foregoing embodiments is achieved (e.g., fig. 3, 8).

Fig. 11 shows a schematic diagram of a 4-phase switching waveform corresponding to the control circuit shown in fig. 10 in accordance with a preferred embodiment of the present invention. In this embodiment, the synchronization signal SYNC includes a plurality of pulses to sequentially generate the count value NX in the control circuit. When the count value NX is associated with the phase sequence number set_n (e.g., equal to each other, i.e., the ready signal RDY is enabled), the corresponding stackable power stage circuit is enabled to generate the output power to the load 99. In the present embodiment, the reset control signal rst_c' (which may also be regarded as a reset signal in the present embodiment) is used to reset and start counting of the count value NX. As shown in fig. 11, in the present embodiment, a high voltage level pulse (e.g., having a high voltage level VH) of the synchronization signal SYNC is used as the reset signal. The other pulses of the synchronization signal SYNC are at the low voltage level VL. In one aspect, the reset signal in this embodiment is modulated or mixed in the pulses of the synchronization signal SYNC. When the voltage level of the synchronization signal SYNC is higher than a threshold VTH, a reset control signal rst_c' is generated.

Fig. 12 is a schematic diagram of a synchronization circuit 57' for generating a synchronization signal SYNC mixed with a reset signal according to a preferred embodiment of the present invention, corresponding to fig. 10 and 11. The operation of the synchronization circuit 57' is similar to that of the synchronization circuit 57 shown in fig. 7. In this embodiment, the synchronization circuit 57' further includes a pulse mixer 560 for generating the synchronization signal SYNC by adding the synchronization generating signal SX and the reset generating signal RX, so that the reset signal in this embodiment is modulated or mixed in the pulse of the synchronization signal SYNC.

Fig. 13 shows a reset circuit 59 'for generating a reset control signal rst_c' according to a preferred embodiment of the present invention corresponding to fig. 10, 11 and 12. The operation of the reset circuit 59' is similar to that of the reset circuit 59 shown in fig. 9. In this embodiment, the reset circuit 59 'further includes a comparator 680 for receiving the synchronization signal SYNC to generate the reset control signal rst_c' when the control circuit is used as the slave circuit. When the voltage level of the synchronization signal SYNC is higher than the threshold VTH, the reset control signal rst_c' is generated.

Fig. 14 shows a schematic diagram of a pulse mixer 560 corresponding to the preferred embodiment of fig. 10, 11 and 12 of the present invention, of the synchronization circuit 57'.

In one embodiment, when the control circuit is used as the main circuit, the main signal MS enables the buffers 710, 720 and the transistor 750 is turned on to provide a resistive load to bias the multiplexer composed of the diodes 715, 725, wherein the on-resistance of the transistor 750 can be set high enough to maintain high accuracy of the pulse voltage level of the synchronization signal SYNC. The buffer 710 receives the reset generation signal RX to generate a high level pulse of the synchronization signal SYNC. The buffer 720 receives the synchronization generating signal SX to generate a low level pulse of the synchronization signal SYNC. The diodes 715, 725 are used as a multiplexer that automatically selects the one of the buffer outputs of the buffers 710, 720 having the higher voltage to generate the synchronization signal SYNC. In one embodiment, the power supply of buffer 710 (corresponding to high voltage level VH) is higher than the power supply of buffer 720 (corresponding to low voltage level VL).

On the other hand, when the control circuit is used as a slave circuit, the master signal MS disables the buffers 710, 720 and the transistor 750 is turned off, so that the terminal of the pulse mixer 560 for generating the synchronization signal SYNC is in a high impedance state.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of making the person skilled in the art easily understand the present invention, and is not intended to limit the scope of the claims of the present invention. The embodiments described are not limited to single applications but may be combined, for example, two or more embodiments may be combined, and portions of one embodiment may be substituted for corresponding components of another embodiment. In addition, various equivalent changes and various combinations will be apparent to those skilled in the art, and for example, the term "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the processing or calculating based on the signal itself, but includes performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling conversion of the signal, if necessary, and then processing or calculating based on the converted signal to generate an output result. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described herein, embody the principles of the invention and are thus equally well suited to the particular use contemplated. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations.

Claims

1. A control circuit for controlling a stackable multiphase power converter, wherein the stackable multiphase power converter comprises a plurality of power stage circuits and a corresponding number of control circuits, wherein the power stage circuits are coupled in parallel with each other to generate an output power to a load, wherein each of the power stage circuits comprises at least one switch for controlling a corresponding one of the inductors, wherein each of the control circuits is coupled to a corresponding one of the power stage circuits, the control circuit comprising:

a synchronous terminal;

a synchronization signal connected to the synchronization terminals corresponding to the control circuits, the synchronization terminals being coupled in parallel, wherein the synchronization signal comprises a plurality of pulses, and the plurality of pulses are used for being continuously counted into a count value; and

a reset signal for resetting and starting the count of the count value;

the control circuit also comprises a phase sequence number, wherein when the count value is related to the phase sequence number, the control circuit enables the corresponding power stage circuit to generate the output power supply.

2. The control circuit of claim 1, further comprising a set terminal for setting the phase number, wherein the phase number is determined based on an electrical reference number of the set terminal.

3. The control circuit of claim 1, wherein the control circuit further determines to operate as a master circuit or a slave circuit based on the phase sequence number;

the main circuit generates the synchronous signal through the synchronous terminal, and the slave circuit is used for receiving the synchronous signal through the synchronous terminal;

the master circuit generates the reset signal, and the slave circuit is used for receiving the reset signal.

4. The control circuit of claim 1, further comprising a counter for continuously counting the pulses of the synchronization signal to generate the count value; wherein the reset signal is generated when the count value reaches a maximum value.

5. The control circuit of claim 1, wherein the reset signal is generated when the count value reaches a phase-cut number, wherein the phase-cut number increases as the current of the load increases.

6. The control circuit of claim 3, wherein the control circuit further comprises:

and a synchronization circuit for generating the synchronization signal through the synchronization terminal when the control circuit is used as the master circuit, and receiving the synchronization signal through the synchronization terminal when the control circuit is used as the slave circuit.

7. The control circuit of claim 3, wherein the control circuit further comprises:

a reset terminal, wherein the reset signal is connected with the reset terminals corresponding to the control circuits, and the reset terminals are coupled in parallel; and

and the reset circuit is used for generating the reset signal through the reset terminal when the control circuit is used as the master circuit and receiving the reset signal when the control circuit is used as the slave circuit.

8. The control circuit of claim 7, wherein the pulse width of the reset signal is shorter than the pulse width of the synchronization signal.

9. The control circuit of claim 1, wherein a pulse having a higher voltage level in the synchronization signal is used as the reset signal.

10. The control circuit of claim 1, wherein the power stage circuit is a fixed on-time power converter; the fixed on-time power converter is triggered in response to a pulse of the synchronization signal.

11. The control circuit of claim 1, further comprising a current source coupled to a resistor through the set terminal, wherein the phase sequence number is determined based on a voltage level of the set terminal.

12. The control circuit of claim 1, wherein the control circuit is configured as an integrated circuit and the synchronization terminal corresponds to a synchronization pin of the integrated circuit.

13. A method for controlling a stackable multiphase power converter, wherein the stackable multiphase power converter comprises a plurality of power stage circuits and a corresponding number of controllers, wherein the power stage circuits are coupled in parallel with each other to generate an output power to a load, wherein each of the power stage circuits comprises at least one switch for controlling a corresponding one of the inductors, wherein each of the controllers is coupled to a corresponding one of the power stage circuits, the method comprising:

generating a synchronization signal which is connected in parallel with the controllers of the stackable multiphase power converter on the premise of not adopting a daisy chain configuration; and

generating a reset signal according to the synchronous signal;

each controller comprises a phase sequence number, wherein the synchronous signal comprises a plurality of pulses, the plurality of pulses are used for being continuously counted into a count value, when the count value is related to the phase sequence number, the controller enables the corresponding stackable multiphase power converter to generate the output power supply to the load, and the reset signal is used for resetting and starting the counting of the count value.

14. The method of claim 13, wherein a pulse having a higher voltage level in the synchronization signal is used as the reset signal.

15. The method of claim 13, further comprising: the phase sequence number is generated through a set terminal, wherein the phase sequence number is determined according to the voltage level of the set terminal.

16. The method of claim 13, wherein the phase sequence number is further used to determine whether the controller is a master controller or a slave controller, wherein the master controller is used to generate the synchronization signal, and wherein the slave controller is used to receive the synchronization signal.

17. The method of claim 13, wherein the reset signal is enabled when the count value reaches a maximum value.

18. The method of claim 13, wherein the reset signal is enabled when the count value reaches a phase-cut number, wherein the phase-cut number is determined according to the current of the load and increases as the current of the load increases.

19. The method of claim 13, wherein the stackable multiphase power converter is a fixed on-time power converter, wherein the fixed on-time power converter is triggered in response to pulses of the synchronization signal.