CN116488123A - Surge protection circuit for preventing latch-up - Google Patents
Surge protection circuit for preventing latch-up Download PDFInfo
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- CN116488123A CN116488123A CN202310481659.2A CN202310481659A CN116488123A CN 116488123 A CN116488123 A CN 116488123A CN 202310481659 A CN202310481659 A CN 202310481659A CN 116488123 A CN116488123 A CN 116488123A
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- 230000002265 prevention Effects 0.000 claims abstract description 50
- 230000005540 biological transmission Effects 0.000 claims abstract description 36
- 238000007599 discharging Methods 0.000 claims abstract description 7
- 230000003111 delayed effect Effects 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 60
- 230000005669 field effect Effects 0.000 claims description 43
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 208000025274 Lightning injury Diseases 0.000 abstract 2
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 230000001960 triggered effect Effects 0.000 description 5
- 230000009024 positive feedback mechanism Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- NUHSROFQTUXZQQ-UHFFFAOYSA-N isopentenyl diphosphate Chemical compound CC(=C)CCO[P@](O)(=O)OP(O)(O)=O NUHSROFQTUXZQQ-UHFFFAOYSA-N 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/048—Anti-latching or quenching devices, i.e. bringing the protection device back to its normal state after a protection action
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
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Abstract
The invention provides an anti-latch surge protection circuit, which relates to the technical field of semiconductors and comprises: the surge protection unit is connected in series between a power supply end and a ground end of the electronic product; the latch-up prevention unit is connected with the surge protection unit through two current transmission paths; the delay control unit is connected in series between the power supply end and the ground end and is connected with the latch-up prevention unit through a voltage transmission path; the surge protection unit is used for discharging surge current in a large-return state when lightning surge occurs at the power supply end; the delay control unit controls the latch-up prevention unit to be in an off state before the lightning stroke surge is ended, and controls the latch-up prevention unit to be in delayed conduction when the lightning stroke surge is ended, so that current of the surge protection unit flows from the latch-up prevention unit to the ground through the current transmission path, and the surge protection unit is caused to exit from a large-back state, thereby realizing latch-up prevention. The anti-latch unit is controlled to be conducted when the surge is finished, so that the surge protection unit is out of a large snapback state, anti-latch is realized, and the surge protection capability is reserved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an anti-latch surge protection circuit.
Background
In recent years, consumer electronic products are rapidly popularized, and in order to ensure the reliability and quality of the electronic products in the use process, protection capability of lightning surge with a certain level is required in a charging interface and a battery power supply circuit of the electronic products. The silicon controlled rectifier is widely applied to various products as a protection device with strong robustness in unit area, low surge residual voltage and strong limit surge current. A conventional Silicon Controlled Rectifier (SCR) is formed by a N, P type doped region in an N-well and a P-well, respectively, and the device structure is shown in fig. 1. The equivalent circuit is shown in fig. 2, and two back-to-back triodes are connected in series, and the characteristic of large voltage snapback is formed by mutual positive feedback between the triodes, so that the equivalent circuit is conducted under lower residual voltage to release surge current, and the subsequent-stage circuit is protected from being damaged by surge. The resistors Rnw and Rpw are parasitic resistances of an N well and a P well in the device, and the parasitic resistances generate a voltage difference through current flowing through the resistors to drive the triode to conduct.
The voltage across the conventional SCR circuit is maintained at a low level after triggering due to its large snapback characteristic, and the minimum voltage across the SCR circuit can be as low as the holding voltage VH. As shown in fig. 3, if the SCR is used to perform surge protection on a power supply port with a continuous voltage, such as the VBUS end in the USB interface, the VBAT end of the battery power supply line, etc., when the surge is triggered, the voltage at both ends drops below the power supply voltage VDD, after that, although the surge on the port disappears, the SCR cannot be restored to the original off state due to the power supply voltage VDD being greater than the SCR maintaining voltage VH, but maintains its on state, and the port current flows from the SCR in the on state to the ground port, which causes the protected circuit at the later stage to continuously lose power, and the application is abnormal. At present, the common practice in the industry is to increase the maintaining voltage VH of the SCR by reducing the amplifying capability of the triode in the SCR equivalent circuit by lengthening the distance between two ends in the SCR device or increasing the concentration of the doped well. As shown in fig. 3, the high VHSCR prevents latch-up by increasing the sustain voltage VH to be greater than the supply port voltage VDD.
However, the latch-up prevention method increases the residual voltage of the SCR as well as the sustain voltage VH. As can be seen from fig. 3, the residual voltage VC2 of the high VHSCR is significantly greater than the conventional SCR residual voltage VC1 at the same bleed current IPP. The larger residual voltage VC is more likely to damage the fragile protected circuit of the later stage, so the method is equivalent to greatly sacrificing the surge protection capability of SCR.
Disclosure of Invention
The invention provides an anti-latch surge protection circuit, which aims at the problems existing in the prior art and comprises:
the surge protection unit is connected in series between a power supply end and a ground end of the electronic product;
the anti-latch unit is connected with the surge protection unit through two current transmission paths;
the delay control unit is connected in series between the power supply end and the ground end and is connected with the latch-proof unit through a voltage transmission path;
the surge protection unit is used for discharging surge current in a large-return state when lightning surge occurs at the power supply end;
the delay control unit is used for transmitting a first voltage signal through the voltage transmission path before the lightning surge is ended, controlling the latch-up prevention unit to be in an off state, and transmitting a second voltage signal through the voltage transmission path when the lightning surge is ended, controlling the latch-up prevention unit to be in delayed conduction, so that current of the surge protection unit flows from the latch-up prevention unit to the ground through the current transmission path, and the surge protection unit is led to be out of the large-return state, thereby realizing latch-up prevention.
Preferably, the surge protection unit includes:
the emitter of the first triode is connected with one end of the first resistor, the collector of the first triode is connected with one end of the second resistor, and the base of the first triode is respectively connected with the other end of the first resistor and the cathode of the first diode;
the emitter of the second triode is connected with the other end of the second resistor, the collector of the second triode is respectively connected with the other end of the first resistor and the cathode of the first diode, and the base of the second triode is respectively connected with the anode of the first diode, one end of the second resistor and the collector of the first triode;
the emitter of the first triode is connected with the power supply end, and the other end of the second resistor is connected with the ground end.
Preferably, the delay control unit includes:
one end of the third resistor is connected with the latch-up prevention unit through the voltage transmission path, one end of the third resistor is also connected with one end of the first capacitor and one end of the fourth resistor, and the other ends of the first capacitor and the fourth resistor are connected with the ground terminal;
the drain electrode of the first field effect tube is connected with the other end of the third resistor, the grid electrode of the first field effect tube is connected with the power supply end, the drain electrode of the first field effect tube is connected with one end of the second capacitor, and the other end of the second capacitor is connected with the ground end;
and one end of the fifth resistor is connected with the drain electrode of the first field effect transistor, the other end of the fifth resistor is connected with the cathode of the second diode, and the anode of the second diode is connected with the power supply end.
Preferably, the latch-up prevention unit is a second field effect transistor, and a source electrode and a drain electrode of the second field effect transistor are respectively connected with two ends of the second resistor through one current transmission path;
and the grid electrode of the second field effect transistor is connected with one end of the third resistor through the voltage transmission path.
Preferably, the second field effect transistor is an enhanced insulated gate type N-channel field effect transistor.
Preferably, the delay control unit includes:
one end of the sixth resistor is connected with the power supply end, and the other end of the sixth resistor is connected with the latch-up prevention unit through the voltage transmission path;
and one end of the third capacitor is connected with the other end of the sixth resistor, and the other end of the third capacitor is connected with the ground end.
Preferably, the latch-up prevention unit is a third field effect transistor, and a source electrode and a drain electrode of the third field effect transistor are respectively connected with two ends of the second resistor through one current transmission path;
and the grid electrode of the third field effect transistor is connected with one end of the third resistor through the voltage transmission path.
Preferably, the third field effect transistor is a junction type P-channel field effect transistor.
Preferably, the first field effect transistor is an enhanced insulated gate type P-channel field effect transistor.
The technical scheme has the following advantages or beneficial effects: the delay control unit controls the latch-proof unit to be converted into an on state from an original off state after the lightning surge occurs, and current flowing through the second resistor is changed into a current flowing from the latch-proof unit to the ground end, so that triodes in the surge protection unit are converted into the off state from an original on state, a positive feedback mechanism between the two triodes is broken, the surge protection unit is enabled to exit from a large snapback state, the potential of a power supply end is recovered from a maintaining voltage to a power supply voltage, the latch-proof function is realized, and the surge protection capability is reserved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional thyristor device;
FIG. 2 is an equivalent circuit diagram of a conventional SCR circuit;
FIG. 3 is a graph showing voltage variation using a conventional thyristor circuit;
FIG. 4 is a schematic diagram of a surge protection circuit for preventing latch-up according to the preferred embodiment of the present invention;
FIG. 5 is an electrical schematic diagram of a first embodiment;
FIG. 6 is a surge test waveform of a conventional SCR circuit;
FIG. 7 is a surge test waveform of the first embodiment;
fig. 8 is an electrical schematic diagram of the second embodiment.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.
In accordance with the foregoing problems with the prior art, the present invention provides an anti-latch-up surge protection circuit, as shown in fig. 4, comprising:
the surge protection unit 1 is connected in series between a power supply end Vin and a ground end GND of the electronic product;
an anti-latch unit 2, the anti-latch unit 2 being connected to the surge protection unit 1 through two current transmission paths;
the delay control unit 3, the delay control unit 3 is connected in series between the power supply end Vin and the ground end GND, and is connected with the latch-up prevention unit 2 through a voltage transmission path;
the surge protection unit 1 is used for discharging surge current when a lightning surge occurs at the power supply end Vin;
the delay control unit 3 is configured to transmit a first voltage signal through a voltage transmission path before the end of the surge, control the latch-up prevention unit 2 to be in an off state, and transmit a second voltage signal through the voltage transmission path when the surge is over, control the latch-up prevention unit 2 to be turned on in a delayed manner, and enable the current of the surge protection circuit 1 to flow from the latch-up prevention unit 2 to the ground GND through the current transmission path so that the surge protection unit 1 exits from the large-loop state, thereby realizing latch-up prevention.
In a preferred embodiment of the present invention, the surge protection unit 1 includes:
the first triode Q1, the emitter of the first triode Q1 is connected with one end of a first resistor R1, the collector of the first triode Q1 is connected with one end of a second resistor R2, and the base of the first triode Q1 is respectively connected with the other end of the first resistor R1 and the cathode of a first diode D1;
the emitter of the second triode Q2 is connected with the other end of the second resistor R2, the collector of the second triode Q2 is respectively connected with the other end of the first resistor R1 and the cathode of the first diode D1, and the base of the second triode Q2 is respectively connected with the anode of the first diode D1, one end of the second resistor R2 and the collector of the first triode Q1;
an emitter of the first triode Q1 is connected with a power supply end Vin, and the other end of the second resistor R2 is connected with a ground end GND.
Specifically, in this embodiment, as shown in fig. 4, the surge protection circuit of the present invention is applied to a charging interface of an electronic product, and the structure of the surge protection unit is the same as that of a conventional SCR unit.
Normally, no lightning surge occurs on the power supply end Vin, and the potential of the power supply end Vin is the power supply voltage VDD. Since the trigger voltage of the surge protection unit 1 is larger than the supply voltage VDD, the surge protection unit 1 does not trigger conduction at this time. The latch-up preventing unit 2 controlled by the delay control unit 3 is in an off state.
When a lightning surge occurs, the potential of the power supply end Vin rises rapidly. The latch-up prevention unit 2 controlled by the delay control unit 3 is still in the off state at this time. The surge protection unit 1 is triggered by the high potential of the power supply terminal Vin to enter a large snapback state, discharges surge current, and pulls down the power supply terminal Vin potential. The delay control unit 3 always controls the latch-up prevention unit 2 to be in an off state during the whole surge current discharging process.
After the lightning surge occurs, the supply terminal Vin potential tends to return to the supply voltage VDD. At this time, the delay control unit 3 controls the latch-up preventing unit 2 to be switched from the original off state to the on state, so that the latch-up preventing unit 2 is switched from high resistance to low resistance. Because the anti-latch-up unit 2 is connected in parallel with the second resistor R2 in the surge protection unit 3, the current originally flowing through the second resistor R2 flows from the anti-latch-up unit 2 to the ground end GND instead, so that the voltage at two ends of the second resistor R2 is obviously reduced to be lower than 0.7V, the triode in the surge protection unit 1 is converted from the original on state to the off state, the positive feedback mechanism between the two triodes is broken, the surge protection unit 1 is enabled to exit from the large snap-back state, and the potential of the power supply end Vin is recovered from the maintaining voltage VH to the power supply voltage VDD, so that the anti-latch-up function is realized.
Example 1
As shown in fig. 3, the present embodiment is a preferred embodiment of the present invention, wherein the delay control unit 3 includes:
one end of the third resistor R3 is connected with the latch-up prevention unit 2 through a voltage transmission path, one end of the third resistor R3 is also connected with one end of the first capacitor C1 and one end of the fourth resistor R4, and the other ends of the first capacitor C1 and the fourth resistor R4 are connected with the ground end GND;
the drain electrode of the first field effect transistor PMOS is connected with the other end of the third resistor R3, the grid electrode of the first field effect transistor POMS is connected with the power supply end Vin, the drain electrode of the first field effect transistor PMOS is connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is connected with the ground end GND;
and one end of the fifth resistor R5 is connected with the drain electrode of the first field effect transistor PMOS, the other end of the fifth resistor R5 is connected with the cathode of the second diode D2, and the anode of the second diode D2 is connected with the power supply end Vin.
In this embodiment, the latch-up prevention unit 2 is a second field effect transistor NMOS, and the source and the drain of the second field effect transistor NMOS are respectively connected to two ends of the second resistor R2 through a current transmission path;
the grid electrode of the second field effect transistor NMOS is connected with one end of the third resistor R3 through a voltage transmission path.
In this embodiment, the second field effect transistor NMOS is an enhanced insulated gate type N-channel field effect transistor.
In this embodiment, the first fet is an enhancement-mode insulated gate P-channel fet.
Specifically, in this embodiment, in a normal state, the voltage of the power supply terminal Vin is the power supply voltage VDD.
With the delay control unit 3, since the voltage at one end of the second capacitor C2 is charged from the power supply terminal Vin through the second diode D2 and the fifth resistor R5 at this time, the voltage at one end is also the power supply voltage VDD. The source of the first field effect transistor PMOS is connected to the high potential end of the second capacitor C2, so the source voltage of the PMOS is also the supply voltage VDD. The grid electrode of the PMOS is directly connected to the power supply end Vin, so that the grid electrode potential is the power supply voltage VDD, and the point positions between the grid electrode and the source electrode of the PMOS are equal, so that the PMOS is in an off state. At this time, no current can flow to the first capacitor C1 through the PMOS, so the voltages at both ends of the first capacitor C1 are equal to the ground potential.
For the latch-up prevention unit 2, the gate of the second field effect transistor NMOS is grounded through the fourth resistor R4 of the delay control unit 3, and the potential between the gate and the source of the NMOS is equal, so that the NMOS is in an off state.
For the surge protection unit 1, the structure of the surge protection unit 1 is the same as that of a traditional SCR unit, and at the moment, the voltage of the power supply end Vin does not reach the trigger voltage yet, so that the surge protection unit is in an off state.
When a lightning surge occurs, the potential of the power supply end Vin rises rapidly.
For the surge protection unit 1, after the voltage of the power supply end Vin reaches the trigger voltage, the surge protection unit 1 is triggered to enter a large snapback state, and is converted into a conduction and discharge surge current, and the voltage of the power supply end Vin is pulled down.
For the delay control unit 3, the voltage at one end of the second capacitor C2 is charged to the supply voltage VDD in a normal state, and although the voltage at the supply end Vin is pulled down by the surge protection unit 1 at this time, the charge of the second capacitor C2 cannot be released due to the blocking of the second diode D2, so the end voltage of the second capacitor C2 is maintained at the supply voltage VDD in the surge relief stage. The source of the PMOS is connected to one end of the second capacitor C2, so the source potential of the PMOS is also the supply voltage VDD. The grid electrode of the PMOS is connected with the power supply end Vin, at the moment, under the influence of low potential of the power supply end pulled by the surge protection unit 1, the grid voltage of the PMOS is lower than the source voltage, the grid-source voltage difference reaches the PMOS threshold voltage, at the moment, the PMOS is changed from an off state to an on state, a loop is formed by the second capacitor C2, the third resistor R3 and the first capacitor C1, and the second capacitor C2 charges the first capacitor C1 through the third resistor R3. Although the second capacitor C2 and the third resistor R3 and the fourth resistor R4 also form a loop, the resistance of the fourth resistor R4 is set to be large, so that most of the discharge current of the second capacitor C2 flows to the first capacitor C1.
In the circuit design, the capacitor Rong Zhidi has two capacitors C2 larger than the first capacitor C1. During the process of charging the second capacitor C2 to the first capacitor C1, the voltage at one end of the first capacitor C1 slowly rises. Through the reasonable resistance-capacitance value collocation of the third resistor R3 and the first capacitor C1 and the set time constant, the terminal voltage of the first capacitor C1 can be ensured to be always lower than the threshold voltage of the NMOS of the latch-up prevention unit 2 in the whole surge relief stage. Thus, the latch-up prevention unit 2 controlled by the delay control unit 3 is still in the off state during the whole surge relief process. The latch-up prevention unit 2 in the off state does not affect the circuit structure of the surge protection unit 1, and thus the surge protection unit 1 can realize surge current discharge with a low residual voltage.
After the lightning surge disappears, the power supply terminal Vin potential is temporarily in a latch state by the surge protection unit 1, and the potential is still maintained at the maintenance voltage VH. At this time, the terminal voltage of the second capacitor C2 is still greater than the PMOS gate voltage (i.e. the voltage of the power supply terminal Vin), so the PMOS is still in the on state, and the second capacitor C2 continues to charge the first capacitor C1. As the terminal voltage of the first capacitor C1 is charged above the threshold voltage of the NMOS of the latch-up prevention unit 2, the gate-source voltage difference of the NMOS is greater than the threshold voltage thereof, and thus the NMOS is transitioned from the off state to the on state. The opened NMOS has low resistance, bypasses the current on the second resistor in the surge protection unit 1, and accordingly the voltage at two ends of the second resistor R2 is quickly pulled down to be lower than 0.7V, and the second triode Q2 in the surge protection unit 1 is an NPN triode and is converted into an off state. This breaks the triode positive feedback mechanism within the surge protection unit 1, thereby causing the surge protection unit 1 to exit the latched state. Since the surge protection unit 1 is no longer pulled low, the supply terminal Vin voltage is restored from the sustain voltage VH to the supply voltage VDD, i.e., an "latch-up prevention" characteristic is realized.
The voltage difference between the gate and the source of the PMOS does not meet the threshold voltage due to the restoration of the voltage of the power supply terminal Vin, and thus the PMOS is turned back to the off state from the on state. The second capacitor C2 is no longer charged to the first capacitor C1, but is charged to the supply voltage VDD again by the supply terminal Vin through the second diode D2 and the fifth resistor R5. The first capacitor C1 is slowly discharged through the fourth resistor R4, and the terminal voltage of the first capacitor C1 is slowly reduced to the ground potential. The gate potential of the NMOS of the latch-up preventing unit 2 is affected by the drop of the terminal voltage of the first capacitor C1, the voltage difference between the gate and the source voltage drops below the threshold voltage, and the NMOS is switched from the on state to the off state, so that the circuit structure of the surge protecting unit 1 is not affected. So far, the whole circuit is restored to the initial state.
When the lightning surge occurs again, the surge protection circuit repeats the above process to perform the process of surge current discharging and latch-up prevention.
The surge protection circuit and the traditional SCR circuit are tested and compared under the same surge test environment, so that the characteristics of the surge protection circuit are described.
The test environment is carried out at the power supply port with the voltage of VDD. In the t0 period, the power supply voltage of the Vin port of the power supply terminal is VDD. In the t1 time period, the port is connected with a lightning surge. In the t2 period, the lightning surge disappears, and the port power supply voltage is restored to VDD.
Fig. 6 is a surge test waveform of a conventional SCR circuit. In the t0 period, the conventional SCR has not yet triggered, and the voltage across it is equal to the supply voltage VDD. In the t1 period, as the lightning surge triggers the SCR, the voltage at two ends of the SCR is greatly reduced due to the large snapback characteristic, and the surge current is discharged. In the t2 period, the lightning surge disappears, and the power supply voltage VDD is greater than the maintaining voltage VH, so that the conventional SCR is maintained in the latch state, and the power supply terminal Vin is continuously powered down, and the voltage cannot be recovered to the power supply voltage VDD.
Fig. 7 is a surge test waveform of the present embodiment. In the time periods t0 and t1, the surge protection circuit of the invention behaves the same as a conventional SCR. In the period t2, after the lightning surge disappears, the voltage at the two ends of the surge protection unit 1 automatically exits from the latch state after the voltage is subjected to short latch, and the voltage at the power supply end Vin is recovered to the power supply voltage VDD. Therefore, the improved surge protection circuit can effectively prevent the latch-up problem at the power supply end of the electronic product.
Example two
As shown in fig. 8, this embodiment is another preferred embodiment of the present invention, and unlike the first embodiment, the delay control unit 3 in this embodiment includes:
a sixth resistor R6, one end of the sixth resistor R6 is connected to the power supply end Vin, and the other end of the sixth resistor R6 is connected to the latch-up prevention unit 2 through a voltage transmission path;
and one end of the third capacitor C3 is connected with the other end of the sixth resistor R6, and the other end of the third capacitor C3 is connected with the ground end GND.
The latch-up prevention unit 2 is a third field effect transistor Q3, and a source electrode and a drain electrode of the third field effect transistor Q3 are respectively connected with two ends of the second resistor R2 through a current transmission path;
the gate of the third fet Q3 is connected to one end of the third resistor R3 through a voltage transmission path.
The third field effect transistor Q3 is a junction type P-channel field effect transistor, and the first field effect transistor is an enhanced insulated gate type P-channel field effect transistor.
Specifically, in this embodiment, in a normal state, the input terminal Vin is the supply voltage VDD.
For the delay control unit 3, the third capacitor C3 is charged to VDD by the input terminal Vin through the sixth resistor R6.
For the latch-up prevention unit 2, the third fet PJFET is a junction type P-channel fet, and the gate of PJFET is connected to the input terminal Vin through the sixth resistor, and thus is also VDD. The drain and source of the PJFET are connected to ground through a second resistor R2 in the surge protection unit 1. Since the PJFET pinch-off voltage is designed to be less than VDD, the PJFET is in the off state.
When a lightning surge occurs, the potential of the input end Vin rises rapidly.
For the surge protection unit 1, the surge protection unit 1 is the same as a traditional SCR circuit, and when the voltage of the input end Vin reaches the trigger voltage, the surge protection unit 1 is triggered to enter a large snapback state, is turned into conduction, discharges the surge current and pulls down the potential of the input end Vin.
For the delay control unit 3, the input terminal Vin is at this time smaller than the terminal voltage of the third capacitor C3, so that the third capacitor C3 discharges to the input terminal Vin through the sixth resistor R6, and the terminal voltage of the third capacitor C3 slowly decreases. The capacitance value of the third capacitor C3 and the resistance value of the sixth resistor R6 with reasonable design can make the terminal voltage of the third capacitor C3 always greater than the pinch-off voltage of the PJFET in the latch-up prevention unit 2 in the whole surge relief period.
With the latch-up prevention unit 2, since the gate voltage of the PJFET (i.e., the terminal voltage of the third capacitor C3 of the delay control unit 3) is always greater than the pinch-off voltage, the latch-up prevention unit 2 maintains the off state throughout the surge relief period. The latch-up prevention unit 2 in the off state does not affect the circuit structure of the surge protection unit 1, and thus the surge protection unit can realize surge current discharge with a low residual voltage.
After the lightning surge disappears, the input terminal Vin potential is temporarily latched by the surge protection unit 1, and the potential is still maintained at the holding voltage VH. At this time, the third capacitor C3 of the delay control unit is still discharged through the sixth resistor R6, and the terminal voltage of the third capacitor C3 is slowly reduced to be less than the pinch-off voltage of the PJFET. At this time, the delay control unit 3 can no longer maintain the off state of the latch-up prevention unit 2, and the PJFET of the latch-up prevention unit 2 is changed from the off state to the on state. The turned-on PJFET has a low resistance characteristic, and bypasses the current on the second resistor R2 in the surge protection unit 1, so that the voltage across the second resistor R2 is quickly pulled down to be less than 0.7V, and the second triode Q2 in the surge protection unit 1 is turned into an off state. This breaks the triode positive feedback mechanism within the surge protection unit 1, thereby causing the surge protection unit 1 to exit the latched state. Since the surge protection unit 1 is no longer pulled low, the voltage at the input terminal Vin is restored from the sustain voltage VH to the supply voltage VDD, i.e., an "latch-up prevention" characteristic is realized.
Due to the restoration of the voltage of the input terminal Vin, the terminal voltage of the third capacitor C3 is charged to VDD again through the sixth resistor R6 by the input terminal Vin. The gate voltage of the PJFET is also restored to the supply voltage VDD due to the restoration of the voltage of the input terminal Vin, and the PJFET is restored to the off state due to the VDD being greater than the pinch-off voltage thereof, so that the circuit structure of the surge protection unit 1 is not affected. So far, the whole circuit is restored to the initial state.
When the lightning surge occurs again, the surge protection circuit repeats the above process to perform the process of surge current discharging and latch-up prevention.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.
Claims (9)
1. An anti-latch-up surge protection circuit comprising:
the surge protection unit is connected in series between a power supply end and a ground end of the electronic product;
the anti-latch unit is connected with the surge protection unit through two current transmission paths;
the delay control unit is connected in series between the power supply end and the ground end and is connected with the latch-proof unit through a voltage transmission path;
the surge protection unit is used for discharging surge current in a large-return state when lightning surge occurs at the power supply end;
the delay control unit is used for transmitting a first voltage signal through the voltage transmission path before the lightning surge is ended, controlling the latch-up prevention unit to be in an off state, and transmitting a second voltage signal through the voltage transmission path when the lightning surge is ended, controlling the latch-up prevention unit to be in delayed conduction, so that current of the surge protection unit flows from the latch-up prevention unit to the ground through the current transmission path, and the surge protection unit is led to be out of the large-return state, thereby realizing latch-up prevention.
2. The surge protection circuit of claim 1, wherein the surge protection unit comprises:
the emitter of the first triode is connected with one end of the first resistor, the collector of the first triode is connected with one end of the second resistor, and the base of the first triode is respectively connected with the other end of the first resistor and the cathode of the first diode;
the emitter of the second triode is connected with the other end of the second resistor, the collector of the second triode is respectively connected with the other end of the first resistor and the cathode of the first diode, and the base of the second triode is respectively connected with the anode of the first diode, one end of the second resistor and the collector of the first triode;
the emitter of the first triode is connected with the power supply end, and the other end of the second resistor is connected with the ground end.
3. The surge protection circuit of claim 2 wherein the delay control unit comprises:
one end of the third resistor is connected with the latch-up prevention unit through the voltage transmission path, one end of the third resistor is also connected with one end of the first capacitor and one end of the fourth resistor, and the other ends of the first capacitor and the fourth resistor are connected with the ground terminal;
the drain electrode of the first field effect tube is connected with the other end of the third resistor, the grid electrode of the first field effect tube is connected with the power supply end, the drain electrode of the first field effect tube is connected with one end of the second capacitor, and the other end of the second capacitor is connected with the ground end;
and one end of the fifth resistor is connected with the drain electrode of the first field effect transistor, the other end of the fifth resistor is connected with the cathode of the second diode, and the anode of the second diode is connected with the power supply end.
4. The surge protection circuit of claim 3 wherein the latch-up prevention unit is a second field effect transistor, the source and drain of the second field effect transistor being connected to two ends of the second resistor through one of the current transmission paths, respectively;
and the grid electrode of the second field effect transistor is connected with one end of the third resistor through the voltage transmission path.
5. The surge protection circuit of claim 4 wherein the second fet is an enhanced insulated gate N-channel fet.
6. The surge protection circuit of claim 2 wherein the delay control unit comprises:
one end of the sixth resistor is connected with the power supply end, and the other end of the sixth resistor is connected with the latch-up prevention unit through the voltage transmission path;
and one end of the third capacitor is connected with the other end of the sixth resistor, and the other end of the third capacitor is connected with the ground end.
7. The surge protection circuit of claim 6 wherein the latch-up prevention unit is a third field effect transistor, the source and drain of the third field effect transistor being connected to two ends of the second resistor through one of the current transmission paths, respectively;
and the grid electrode of the third field effect transistor is connected with one end of the third resistor through the voltage transmission path.
8. The surge protection circuit of claim 7 wherein the third fet is a junction P-channel fet.
9. The surge protection circuit of claim 3 wherein the first fet is an enhanced insulated gate type P-channel fet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310481659.2A CN116488123A (en) | 2023-04-28 | 2023-04-28 | Surge protection circuit for preventing latch-up |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310481659.2A CN116488123A (en) | 2023-04-28 | 2023-04-28 | Surge protection circuit for preventing latch-up |
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| Publication Number | Publication Date |
|---|---|
| CN116488123A true CN116488123A (en) | 2023-07-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310481659.2A Pending CN116488123A (en) | 2023-04-28 | 2023-04-28 | Surge protection circuit for preventing latch-up |
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| Country | Link |
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| CN (1) | CN116488123A (en) |
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2023
- 2023-04-28 CN CN202310481659.2A patent/CN116488123A/en active Pending
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