CN116487392A

CN116487392A - Display device, method of manufacturing the same, and tiled display device

Info

Publication number: CN116487392A
Application number: CN202310107030.1A
Authority: CN
Inventors: 朴钟范
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-01-24
Filing date: 2023-01-19
Publication date: 2023-07-25

Abstract

A display device, a method of manufacturing the display device, and a tiled display device are provided. The display device includes: a substrate including a first surface, a second surface opposite the first surface, a first chamfer surface extending from one side of the first surface, a second chamfer surface extending from one side of the second surface, and a first side surface between the first chamfer surface and the second chamfer surface; a first pad on a first surface of the substrate; and an upper connection wiring electrically connected to the first pad between the substrate and the first pad on the first surface of the substrate, and including a first contact portion electrically connected to the first pad and a first peeling portion extending from the first contact portion in a direction toward the first chamfer surface and having a width smaller than a width of the first contact portion.

Description

Display device, method of manufacturing the same, and tiled display device

The present application claims priority and rights of korean patent application No. 10-2022-0031694 filed on the korean intellectual property office at 3 months 14 of 2022 and korean patent application No. 10-2022-0009871 filed on the korean intellectual property office at 24 of 2022, the disclosures of which are fully incorporated herein by reference.

Technical Field

The disclosure relates to a display device and a method of manufacturing the display device.

Background

Electronic devices that provide images to users, such as smart phones, tablet personal computers (tablet PCs), digital cameras, laptop computers, navigation devices, and smart televisions, include display devices for displaying images.

The display device includes a display region capable of expressing various colors while operating in units of pixels or sub-pixels, and a frame region in which wirings for driving the pixels or sub-pixels are positioned.

Recently, there is an increasing demand for a borderless technique for removing or reducing a bezel area to thereby increase or maximize a display area of a display device, and in response thereto, research and development of a side wiring forming technique for forming wiring on a side surface of a substrate are steadily underway.

Disclosure of Invention

Aspects of the disclosure provide a display device having improved device reliability.

Aspects of the disclosure also provide a method of manufacturing a display device having improved device reliability.

It should be noted that the aspects of the disclosure are not limited to the above aspects, and other aspects of the disclosure will be apparent to those skilled in the art from the following description.

According to one or more embodiments disclosed, a display apparatus includes: a substrate including a first surface, a second surface opposite the first surface, a first chamfer surface extending from one side of the first surface, a second chamfer surface extending from one side of the second surface, and a first side surface between the first chamfer surface and the second chamfer surface; a first pad on a first surface of the substrate; and an upper connection wiring electrically connected to the first pad between the substrate and the first pad on the first surface of the substrate, and including a first contact portion electrically connected to the first pad and a first peeling portion extending from the first contact portion in a direction toward the first chamfer surface and having a width smaller than a width of the first contact portion.

The first peeling portion may extend toward a boundary between the first surface and the first chamfer surface.

The display device may further include: a flip-chip type micro Light Emitting Diode (LED) element is on a first surface of the substrate.

The first surface may include a display region in which the pixels are positioned and a pad region located at one side of the display region, the first pad being positioned in the pad region and the pad region being more adjacent to the first chamfer surface than the display region, wherein the upper connection wiring further includes a first wiring portion extending from the first contact portion in a direction toward the display region and electrically connected to the pixels.

The display device may further include first peeling portions spaced apart from each other.

The display device may further include: and a bottom connection wiring including a second stripped portion extending in a direction along which the first stripped portion extends.

The display device may further include: a second pad on the second surface; and a side wiring on the first surface, the first chamfer surface, the first side surface, the second chamfer surface, and the second surface, and configured to electrically connect the first pad and the second pad.

The second pad may include a first portion overlapping the side wiring and a second portion spaced apart from the first portion and not overlapping the side wiring, wherein the first portion of the second pad includes: a second contact portion in contact with the side wiring; and a second peeling portion extending from the second contact portion in a direction toward the second chamfer surface and having a width smaller than a width of the second contact portion.

The display device may further include: and a bottom connection wiring between the second pad and the second surface of the substrate and electrically connecting the first portion and the second portion of the second pad.

According to one or more embodiments disclosed, a tiled display device includes: a plurality of display devices and a joint portion between the plurality of display devices, wherein a first display device among the plurality of display devices includes: a substrate including a first surface, a second surface opposite to the first surface, a first chamfer surface extending from one side of the first surface, a second chamfer surface extending from one side of the second surface, and a first side surface connecting the first chamfer surface and the second chamfer surface; a light emitting element on the first surface; a first pad on the first surface and spaced apart from the light emitting element; and an upper connection wiring, on the first surface, between the substrate and the first pad, configured to electrically connect the first pad and the light emitting element, and including a first contact portion electrically connected to the first pad and a first peeling portion extending from the first contact portion in a direction toward the first chamfer surface and having a width smaller than a width of the first contact portion.

The light emitting element may comprise a flip-chip type micro Light Emitting Diode (LED) element.

The substrate may comprise glass.

The first display device may further include: and a side wiring on the first surface, the second surface, and the first side surface of the substrate and connected to the first pad.

The first display device may further include: a bottom connection wiring on the second surface of the substrate; and a flexible film connected to the bottom connection wiring through the conductive adhesive member, and wherein the side wiring is connected to the bottom connection wiring.

The plurality of display devices may be arranged in a matrix form.

According to one or more embodiments disclosed, a method of manufacturing a display device includes: preparing a mother substrate in which scribe lines defining a plurality of cell regions are defined; forming upper connection wiring patterns on upper surfaces of the plurality of unit regions; forming a first pad on the upper connection wiring pattern, and the first pad being electrically connected to the upper connection wiring pattern; scribing one of the plurality of cell regions from the mother substrate to obtain a cell substrate; and forming a chamfer surface by processing an edge of the unit substrate, wherein the upper connection wiring pattern includes a first contact portion electrically connected to the first pad and a first peeling portion pattern extending from the first contact portion in a direction toward the scribe line and having a width smaller than a width of the first contact portion.

The step of forming the chamfer surface may comprise: the first lift-off pattern is formed at an end of the first lift-off portion pattern by processing the end of the first lift-off portion pattern.

The step of forming the first lift-off pattern at the end of the first lift-off portion pattern may be performed simultaneously with the step of processing the edge of the unit substrate.

The step of forming the upper connection wiring pattern and the step of forming the first pad may include: a second pad pattern is formed on a bottom surface of the unit region of the mother substrate, wherein the second pad pattern includes a second peeling portion pattern extending in a direction toward the scribe line.

The step of forming the chamfer surface may further comprise: the second lift-off pattern is formed at an end of the second lift-off portion pattern by processing the end of the second lift-off portion pattern.

Drawings

The above and other aspects and features of the disclosure will become more apparent by describing in detail the disclosed embodiments with reference to the accompanying drawings in which:

FIG. 1 is a perspective view illustrating a front surface of a display device in accordance with one or more embodiments;

fig. 2 is a perspective view illustrating a rear surface of a display device in accordance with one or more embodiments;

Fig. 3 is a view schematically showing the structure of a pixel of a display device according to one or more embodiments;

fig. 4 is a view schematically showing the structure of a pixel of a display device according to one or more other embodiments;

fig. 5 is a block diagram schematically illustrating a cross-sectional structure of a pixel in accordance with one or more embodiments;

fig. 6 is a perspective view illustrating an arrangement relationship between pixels and side wirings of a display device according to one or more embodiments;

fig. 7 is a plan view illustrating an arrangement relationship between pixels and side wirings of a display device according to one or more embodiments;

fig. 8 is a rear view illustrating an arrangement relationship between side wirings and drivers of a display device according to one or more embodiments;

FIG. 9 is a cross-sectional view showing a cross-section taken along the line X1-X1' of FIGS. 7 and 8;

fig. 10 is a layout diagram showing the structure of the first pad and the upper connection wiring;

FIG. 11 is a cross-sectional view showing a cross-section taken along the line X2-X2' of FIG. 10;

FIG. 12 is a cross-sectional view showing a cross-section taken along the line X3-X3' of FIG. 10;

FIG. 13 is a cross-sectional view showing a cross-section taken along line X4-X4' of FIG. 10;

fig. 14 is a layout diagram showing the structure of the second pad and the bottom connection wiring;

FIG. 15 is a cross-sectional view showing a cross-section taken along line X5-X5' of FIG. 14;

FIG. 16 is a cross-sectional view showing a cross-section taken along line X6-X6' of FIG. 14;

FIG. 17 is a cross-sectional view showing a cross-section taken along line X7-X7' of FIG. 14;

fig. 18-28 are flowcharts and views for describing a method of manufacturing a display device in accordance with one or more embodiments;

FIG. 29 is a diagram schematically illustrating a tiled display using a display device in accordance with one or more embodiments;

fig. 30 is an enlarged view showing a region a of fig. 29;

FIG. 31 is a cross-sectional view showing a cross section taken along line XA-XA' of FIG. 30;

FIG. 32 is a block diagram illustrating the structure of a tiled display in accordance with one or more embodiments;

fig. 33 is a diagram illustrating a state in which a tiled display using a display device according to one or more embodiments is driven;

fig. 34 is a layout diagram showing the structure of a first pad and upper connection wirings of a display device according to one or more other embodiments;

fig. 35 is a layout diagram showing the structure of a first pad and upper connection wirings of a display device according to still another embodiment or embodiments; and

fig. 36 is a layout diagram showing the structure of a first pad and upper connection wirings of a display device according to still another embodiment or embodiments.

Detailed Description

Aspects of some embodiments of the disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments may, however, be subject to various modifications and may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of the disclosure to those skilled in the art, and it should be understood that the present disclosure encompasses all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present disclosure. Thus, processes, elements, and techniques not necessary for a person of ordinary skill in the art to fully understand aspects of the present disclosure may not be described.

Throughout the drawings and the written description, like reference numerals, characters or combinations thereof denote like elements unless otherwise indicated, and thus the description thereof will not be repeated. Furthermore, portions that are not related or relevant to the description of the embodiments may not be shown to make the description clear.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity. Furthermore, the use of cross-hatching and/or shading is often provided in the drawings to clarify the boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading, unless otherwise indicated, does not convey or indicate any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other characteristic, attribute, property, or the like of an element.

Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations in the illustrated shapes, such as due to manufacturing techniques and/or tolerances, are to be expected. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative of the embodiments that are consistent with the principles of the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing.

For example, an implanted region shown as a rectangle will typically have rounded (rounded) or curved features and/or gradients of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may cause some implantation in the region between the buried region and the surface through which implantation occurs.

Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It may be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

Spatially relative terms, such as "under … …," "under … …," "lower (lower)", "under … …," "over … …," "upper (upper)", and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below … …" and "below … …" may encompass both an orientation of above and below. The device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this indicates that the first portion is disposed at an upper or lower side of the second portion, and is not limited to the upper side of the second portion based on the direction of gravity.

Further, in this specification, the phrase "on a plane" or "plan view" means that the target portion is viewed from the top, and the phrase "on a section" means that a section formed by vertically cutting the target portion is viewed from the side.

It will be understood that when an element, layer, region or component is referred to as being "formed on," "connected to" or "coupled to" another element, layer, region or component, it can be directly formed on, connected to or coupled to the other element, layer, region or component or be indirectly formed on, connected to or coupled to the other element, layer, region or component, with one or more intervening elements, layers, regions or components being present. Further, this may be collectively referred to as direct bonding or indirect bonding or direct connection or indirect connection, as well as integral bonding or non-integral bonding or integral connection or non-integral connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, and/or component, or intervening layers, regions, or components may be present. However, "directly connected/directly coupled" or "directly on … …" means that one component is directly connected or coupled to another component, or directly on another component, without intervening components. Also, other expressions describing the relationship between components, such as "between … …," immediately adjacent to "between … …," or "adjacent to … …," and "directly adjacent to … …," may be similarly interpreted. Furthermore, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

For purposes of this disclosure, an expression such as "at least one (seed/person) in … …" modifies a column of elements when followed by a column of elements without modifying individual elements listed. For example, "at least one (seed/person) of X, Y and Z" and "at least one (seed/person) selected from the group consisting of X, Y and Z" may be interpreted as any combination of two or more of X only, Y only, Z, X, Y only and Z (such as XYZ, XYY, YZ and ZZ for example) or any variation thereof. Similarly, an expression such as "at least one (seed/each) of a and B" may include A, B or a and B. As used herein, "or" generally means "and/or (and/or)", and the term "and/or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "a and/or B" may include A, B or a and B.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, a first element, first component, first region, first layer, or first section discussed below could be termed a second element, second component, second region, second layer, or second section without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply that a second element or other element is present. The terms "first," "second," and the like, herein also may be used to distinguish between different classes or groups (sets) of elements. For brevity, the terms "first," "second," etc. may represent a "first category (or first group)", "second category (or second group)", etc., respectively.

In an example, the x-axis, y-axis, and/or z-axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and/or the third direction.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," comprising, "" includes, "" including, "" having, "" has been stated, and/or variations thereof, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

While one or more embodiments may be implemented differently, the particular process (processing) sequence may be performed differently than as described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described.

As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms and not as degree terms, and are intended to take into account the inherent deviations of measured or calculated values that will be appreciated by one of ordinary skill in the art. As used herein, "about" or "approximately" includes the stated values and means: within an acceptable deviation of the particular values as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the particular amount of measurements (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of "may" in describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure.

Furthermore, any numerical range disclosed and/or recited herein is intended to include all sub-ranges subsumed with the same numerical precision within the recited range. For example, a range of "1.0 to 10.0" is intended to include all subranges between the recited minimum value of 1.0 (including 1.0) and the recited maximum value of 10.0 (including 10.0), i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in the present specification is intended to include all higher numerical limitations subsumed therein. Accordingly, applicants reserve the right to modify this specification (including the claims) to expressly state any sub-ranges subsumed within the range explicitly recited herein. All such ranges are intended to be inherently described in this specification such that modifications to the explicitly recited any such sub-ranges would be acceptable.

Some embodiments are depicted in the drawings, in terms of functional blocks, units, and/or modules. Those skilled in the art will appreciate that such blocks, units, and/or modules are physically implemented by logic circuits, individual components, microprocessors, hardwired circuits, memory elements, line connections, and other electronic circuits. This may be formed using semiconductor-based fabrication techniques or other fabrication techniques. Blocks, units, and/or modules implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform the various functions discussed herein, and may alternatively be driven by firmware and/or software. Furthermore, each block, unit, and/or module may be implemented by dedicated hardware or a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs functions other than the functions of the dedicated hardware. Furthermore, in some embodiments, a block, unit, and/or module may be physically divided into two or more interacting separate blocks, units, and/or modules without departing from the scope of the present disclosure. Furthermore, in some embodiments, blocks, units, and/or modules may be physically combined into more complex blocks, units, and/or modules without departing from the scope of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or this specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a perspective view illustrating a front surface of a display device in accordance with one or more embodiments. Fig. 2 is a perspective view illustrating a rear surface of a display device in accordance with one or more embodiments.

In fig. 1, a first direction DR1, a second direction DR2, and a third direction DR3 are defined. The first direction DR1 and the second direction DR2 may be perpendicular to each other, the first direction DR1 and the third direction DR3 may be perpendicular to each other, and the second direction DR2 and the third direction DR3 may be perpendicular to each other. The first direction DR1 may be understood as representing a width direction of the display apparatus 10 in the drawing, the second direction DR2 may be understood as representing a length direction of the display apparatus 10 in the drawing, and the third direction DR3 may be understood as representing a thickness direction of the display apparatus 10 in the drawing. In the following description, unless otherwise indicated, the term "direction" may refer to two opposite (opposite) directions toward both sides (edges) extending along the direction. Further, when it is appropriate to distinguish between two directions extending to both sides, the two directions are divided into one side and the other side, and will be referred to as one side and the other side of the direction, respectively. Referring to fig. 1, the direction pointed by the arrow is referred to as one side, and the direction opposite to the one side is referred to as the other side.

Hereinafter, for convenience of description, in describing the surface of the display device 10 or each member constituting the display device 10, one surface facing the side of the direction in which an image is displayed (i.e., the side of the third direction DR 3) is referred to as an upper surface, and the other surface opposite to the one surface is referred to as a bottom surface. However, the present disclosure is not limited thereto, and one surface and the other surface of the member may also be referred to as a front surface and a rear surface, respectively, or may be referred to as a first surface or a second surface, respectively. Further, in describing the relative position of each member of the display device 10, one side in the third direction DR3 may be referred to as an upper portion, and the other side in the third direction DR3 may be referred to as a lower portion.

Referring to fig. 1 and 2, a display device 10 according to one or more embodiments may be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (tablet PC), a mobile communication terminal, an electronic organizer, an electronic book, a Portable Multimedia Player (PMP), a navigation device, or a Ultra Mobile PC (UMPC). Optionally, the display device 10 according to one or more embodiments may be used as a display of a television, a laptop, a monitor, a billboard, or an internet of things (IoT) device.

The display device 10 may be formed in a planar shape similar to a quadrangle. For example, as shown in fig. 1, the display device 10 may have a planar shape similar to a quadrangular shape having a short side in the first direction DR1 and a long side in the second direction DR 2. The corners (corners) where the short sides in the first direction DR1 meet the long sides in the second direction DR2 may be rounded to have a certain curvature or formed at right angles. The planar shape of the display device 10 is not limited to a quadrangle, but may be formed similarly to other polygonal shapes, circular shapes, or elliptical shapes.

The display device 10 may include a display area DA in which a screen is located on one side surface (hereinafter, referred to as an upper surface) in the third direction DR3, and a non-display area NDA which is an area other than the display area DA and in which an image is not displayed. For example, the non-display area NDA may be positioned on an upper surface of the display device 10, two side surfaces (hereinafter, referred to as side surfaces) of the display device 10 in the second direction DR2, two side surfaces of the display device 10 in the first direction DR1, and a portion of the other side surface (hereinafter, referred to as bottom surface) of the display device 10 in the third direction DR3, but the disclosure is not limited thereto. In some embodiments, the non-display area NDA may be positioned around an edge of the display area DA, but the disclosure is not limited thereto. Meanwhile, the display area DA and the non-display area NDA of the display device 10 may also be applied to the substrate 100 to be described below.

According to one or more embodiments, the display device 10 may include a substrate 100, a plurality of pixels PX, a plurality of side wirings 200, and drivers, wherein each of the drivers may include a circuit board CB and a display driving circuit DC.

The substrate 100 may serve as a base of the display device 10. In some embodiments, the substrate 100 may be a rigid substrate having rigidity and may include glass, but the disclosure is not limited thereto. For example, the substrate 100 may also be a flexible substrate having flexibility and may include polyimide. Hereinafter, for convenience of description, the substrate 100 will be mainly described as a rigid substrate and includes glass.

The substrate 100 may have a three-dimensional shape similar to a rectangular parallelepiped, and may have a shape such that: wherein the corners formed by the upper and side surfaces of the cuboid are curved and the corners formed by the bottom and side surfaces of the cuboid are curved. In other words, the substrate 100 may have a three-dimensional shape similar to a rectangular parallelepiped, and have a shape in which edges of upper and lower surfaces are curved. In fig. 1 and 2, a case in which a chamfer surface (chamfered surface) is formed on each of both sides of the upper and bottom surfaces of the substrate 100 in the first and second directions DR1 and DR2 is illustrated. In some embodiments, in the substrate 100, corner-curved surfaces (e.g., chamfer surfaces) thereof may be formed on both sides of the upper and bottom surfaces in the first and second directions DR1 and DR2, but the disclosure is not limited thereto. For example, the chamfer surface may be formed on only one side of each of the upper and bottom surfaces of the substrate 100 in the first direction DR 1. Hereinafter, for convenience of description, the chamfer surfaces formed on each of both sides of the upper and bottom surfaces of the substrate 100 in the first and second directions DR1 and DR2 will be mainly described.

The substrate 100 may include a first surface 100a, a second surface 100b, a plurality of chamfer surfaces, and a plurality of side surfaces.

The first surface 100a may be an upper surface of the substrate 100. The first surface 100a may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR 2.

The second surface 100b may be a surface opposite to the first surface 100a in the third direction DR 3. The second surface 100b may be a bottom surface of the substrate 100. The second surface 100b may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR 2.

The plurality of side surfaces may be surfaces positioned between the first surface 100a and the second surface 100b, and may be two side surfaces of the substrate 100 in the first direction DR1 and two side surfaces in the second direction DR 2. For convenience of description, among the plurality of side surfaces, a side surface positioned on one side of the first direction DR1 is referred to as a first side surface 100c, a side surface positioned on one side of the second direction DR2 is referred to as a second side surface, a side surface positioned on the other side of the first direction DR1 is referred to as a third side surface, and a side surface positioned on the other side of the second direction DR2 is referred to as a fourth side surface.

The plurality of chamfer surfaces refers to surfaces that: the surfaces are positioned between the first surface 100a and the plurality of side surfaces and between the second surface 100b and the plurality of side surfaces and are obliquely cut to reduce or prevent the possibility of occurrence of chipping defects (chipping defects) in the plurality of side wires 200. The bending angle of each of the plurality of side wirings 200 may be gentle (e.g., relatively inclined) due to the plurality of chamfer surfaces, so that the possibility of chipping and cracking occurring in the plurality of side wirings 200 may be reduced or prevented. For convenience of description, among the plurality of chamfer surfaces, the chamfer surface positioned between the first surface 100a and the first side surface 100c is referred to as a first chamfer surface 100d1, the chamfer surface positioned between the second surface 100b and the first side surface 100c is referred to as a second chamfer surface 100d2, the chamfer surface positioned between the first surface 100a and the second side surface is referred to as a third chamfer surface, the chamfer surface positioned between the second surface 100b and the second side surface is referred to as a fourth chamfer surface, the chamfer surface positioned between the first surface 100a and the third side surface is referred to as a fifth chamfer surface, the chamfer surface positioned between the second surface 100b and the third side surface is referred to as a sixth chamfer surface, the chamfer surface positioned between the first surface 100a and the fourth side surface is referred to as a seventh chamfer surface, and the chamfer surface positioned between the second surface 100b and the fourth side surface is referred to as an eighth chamfer surface.

For example, the first chamfer surface 100d1 may extend from one side of the first surface 100a in the first direction DR1, the second chamfer surface 100d2 may extend from one side of the second surface 100b in the first direction DR1, and the first side surface 100c may connect the first chamfer surface 100d1 and the second chamfer surface 100d 2. The third chamfer surface may extend from one side of the first surface 100a in the second direction DR2, the fourth chamfer surface may extend from one side of the second surface 100b in the second direction DR2, and the second side surface may connect the third chamfer surface and the fourth chamfer surface. The fifth chamfer surface may extend from the other side of the first surface 100a in the first direction DR1, the sixth chamfer surface may extend from the other side of the second surface 100b in the first direction DR1, and the third side surface may connect the fifth chamfer surface and the sixth chamfer surface. The seventh chamfer surface may extend from the other side of the first surface 100a in the second direction DR2, the eighth chamfer surface may extend from the other side of the second surface 100b in the second direction DR2, and the fourth side surface may connect the seventh chamfer surface and the eighth chamfer surface.

The plurality of pixels PX may be positioned on the first surface 100a of the substrate 100, and may display an image. The plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR 2. The structure of the plurality of pixels PX will be described in detail below.

Each of the plurality of side wirings 200 serves to connect a first PAD (also referred to as a "PAD") PAD1 (see fig. 7) positioned on the first surface 100a and a second PAD2 (see fig. 8) positioned on the second surface 100 b. The first PAD1 may be connected to a data wire connected to a plurality of pixels PX positioned on the first surface 100a of the substrate 100. The plurality of side wirings 200 may be arranged to be spaced apart from each other in the second direction DR 2.

The plurality of side wires 200 may be positioned on the first surface 100a (e.g., on a portion of the first surface 100 a), the second surface 100b (e.g., on a portion of the second surface 100 b), at least two of the plurality of chamfered surfaces, and at least one of the plurality of side surfaces. For example, as shown in fig. 1 and 2, the plurality of side wirings 200 may be positioned on the first surface 100a, the second surface 100b, the first chamfer surface 100d1, the second chamfer surface 100d2, and the first side surface 100c to connect the first PAD1 positioned on one side of the first surface 100a of the substrate 100 in the first direction DR1 to the second PAD2 positioned on one side of the second surface 100b in the first direction DR 1. The shape of each of the plurality of side wirings 200 will be described in detail below.

In some embodiments, the plurality of side wirings 200 may be positioned only on one side of the substrate 100 in the first direction DR1, but the disclosure is not limited thereto. For example, the plurality of side wirings 200 may also be positioned on the other side of the substrate 100 in the first direction DR1 and on one or the other side of the substrate 100 in the second direction DR 2. In this case, the first PAD1 positioned on the first surface 100a of the substrate 100 may be additionally positioned on the other side of the substrate 100 in the first direction DR1 and positioned on one side or the other side of the substrate 100 in the second direction DR 2. In addition, the second PAD2 positioned on the second surface 100b of the substrate 100 may be additionally positioned on the other side of the substrate 100 in the first direction DR1 and positioned on one side or the other side of the substrate 100 in the second direction DR 2. Hereinafter, for convenience of description, it will be mainly described that the plurality of side wirings 200 are positioned only on one side of the substrate 100 in the first direction DR 1.

The circuit board CB may be positioned on the second surface 100b of the substrate 100. Each of the circuit boards CB may be connected to a third PAD3 (see fig. 8) positioned on the second surface 100b of the substrate 100 using a conductive adhesive member such as an anisotropic conductive film. As described below, since the third PADs PAD3 are electrically connected to the second PADs PAD2, respectively, the circuit board CB may be electrically connected to the first PADs PAD1 through the side wirings 200. Each of the circuit boards CB may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

The display driving circuit DC may generate a data voltage, and may supply the data voltage to the data wiring extending from the pixel PX through the circuit board CB, the third PAD3, the second PAD2, the plurality of side wirings 200, and the first PAD 1. The display driving circuit DC may be formed as an Integrated Circuit (IC) and may be attached on the circuit board CB. Alternatively, the display driving circuit DC may be directly attached to the second surface 100b of the substrate 100 by a Chip On Glass (COG) method.

As described above, since the flexible film bent along the side surface of the substrate 100 can be omitted by connecting the first PAD1 positioned on the first surface 100a to the second PAD2 positioned on the second surface 100b using the plurality of side wirings 200, the bezel-less display device 10 in which the non-display area NDA is reduced or minimized can be realized.

Hereinafter, a structure of the pixel PX of the display device 10 according to one or more embodiments will be described.

Fig. 3 is a view schematically illustrating a structure of a pixel of a display device according to one or more embodiments. Fig. 4 is a view schematically showing the structure of a pixel of a display device according to one or more other embodiments. Fig. 5 is a block diagram schematically illustrating a cross-sectional structure of a pixel in accordance with one or more embodiments.

Referring to fig. 3 and 4, each of the pixels PX may include a plurality of sub-pixels. In fig. 3 and 4, each of the pixels PX is illustrated as including three sub-pixels SPX1, SPX2, and SPX3 (i.e., a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX 3), but the number of sub-pixels is not limited thereto. Each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may be connected to at least one scan wiring among one data wiring and a scan wiring among the data wirings.

Each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may have a rectangular, square, or diamond-shaped planar shape. For example, as shown in fig. 3, each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR 2. Alternatively, as shown in fig. 4, each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may have a square or diamond-shaped planar shape including sides having the same length in the first and second directions DR1 and DR 2.

The first, second, and third sub-pixels SPX1, SPX2, and SPX3 may be arranged along the second direction DR 2. Any one of the second and third sub-pixels SPX2 and SPX3 and the first sub-pixel SPX1 may be arranged along the second direction DR2, and the other one of the second and third sub-pixels SPX2 and SPX3 and the first sub-pixel SPX1 may be arranged along the first direction DR 1. For example, as shown in fig. 4, the first and second sub-pixels SPX1 and SPX2 may be arranged along the second direction DR2, and the first and third sub-pixels SPX1 and SPX3 may be arranged along the first direction DR 1.

The first subpixel SPX1 may emit first light, the second subpixel SPX2 may emit second light, and the third subpixel SPX3 may emit third light. In this case, the first light may be light of a red wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a blue wavelength band. The red wavelength band may be a wavelength band of about 600nm to about 750nm, the green wavelength band may be a wavelength band of about 480nm to about 560nm, and the blue wavelength band may be a wavelength band of about 370nm to about 460nm, but embodiments of the present specification are not limited thereto.

Each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may include an inorganic light emitting element LE (see fig. 5) having an inorganic semiconductor as a light emitting element emitting light. For example, the inorganic light emitting element may be a flip chip type micro Light Emitting Diode (LED), but the disclosure is not limited thereto.

As shown in fig. 3 and 4, the area of the first subpixel SPX1, the area of the second subpixel SPX2, and the area of the third subpixel SPX3 may be substantially the same, but the disclosure is not limited thereto. For example, the area of the first subpixel SPX1, the area of the second subpixel SPX2, and the area of the third subpixel SPX3 may be different from one another.

Referring to fig. 5, each of the plurality of sub-pixels SPX1, SPX2, and SPX3 forming the pixel PX may include a plurality of conductive layers, a plurality of insulating layers, and a plurality of light emitting elements LE. The plurality of conductive layers and the plurality of insulating layers may form a transistor layer that transmits an electric signal to the light emitting element LE.

The plurality of subpixels positioned on the substrate 100 include an active layer ACT as a plurality of conductive layers, a first gate metal layer GTL1, a second gate metal layer GTL2, a first data metal layer DTL1, a second data metal layer DTL2, a third data metal layer DTL3, a fourth data metal layer DTL4, and a fifth data metal layer DTL5. In addition, the plurality of pixels PX include a buffer layer BF, a gate insulating layer 110, a first interlayer insulating layer 130, a second interlayer insulating layer 150, and an upper via layer including a first via layer 160, a second via layer 170, a third via layer 180, and a fourth via layer 190, as a plurality of insulating layers.

The substrate 100 serves as a base of the display device 10, and may be a base substrate or a base member for supporting a plurality of pixels PX. As described above, the substrate 100 may be a rigid substrate made of a glass material.

The buffer layer BF may be positioned on the upper surface of the substrate 100 (i.e., on the first surface 100 a). The buffer layer BF may serve to reduce or prevent air or moisture from penetrating into the element layers constituting the pixels PX. The buffer layer BF may be formed of a plurality of inorganic films alternately stacked. For example, the buffer layer BF may be formed as a plurality of films in which one or more inorganic films among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. According to one or more embodiments, the buffer layer BF may be omitted.

The active layer ACT may be positioned on the buffer layer BF. The active layer ACT may include a silicon semiconductor (such as polysilicon, monocrystalline silicon, low-temperature polysilicon, and amorphous silicon), or may include an oxide semiconductor.

The active layer ACT may include a channel region, a first region positioned at one side of the channel region, and a second region positioned at the other side of the channel region. The channel region of the active layer ACT may be a region overlapping with a gate electrode GE to be described below in the third direction DR 3. The first and second regions of the active layer ACT may be regions not overlapping the gate electrode GE. The first region and the second region may be regions having conductivity by doping a silicon semiconductor or an oxide semiconductor with ions.

The gate insulating layer 110 may be positioned on the active layer ACT. The gate insulating layer 110 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

A first gate metal layer GTL1 may be positioned on the gate insulating layer 110. The first gate metal layer GTL1 may include a gate electrode GE and a first capacitor electrode CAE1 of each subpixel. The gate electrode GE may form a thin film transistor together with the active layer ACT, and the thin film transistor is configured to drive the pixel PX. The first gate metal layer GTL1 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The first interlayer insulating layer 130 may be positioned on the first gate metal layer GTL 1. The first interlayer insulating layer 130 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

A second gate metal layer GTL2 may be positioned on the first interlayer insulating layer 130. The second gate metal layer GTL2 may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in the third direction DR3, and the second capacitor electrode CAE2 and the first capacitor electrode CAE1 form a capacitor Cst. The second gate metal layer GTL2 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The second interlayer insulating layer 150 may be positioned on the second gate metal layer GTL 2. The second interlayer insulating layer 150 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

A first data metal layer DTL1 including a first connection electrode CE1 and a data wire may be positioned on the second interlayer insulating layer 150. The first data metal layer DTL1 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The first connection electrode CE1 may be connected to the first region or the second region of the active layer ACT through a first contact hole CT1 passing through the first and second interlayer insulating layers 130 and 150.

The first via layer 160 may be positioned on the first data metal layer DTL1, and the first via layer 160 is configured to planarize steps due to the active layer ACT, the first gate metal layer GTL1, the second gate metal layer GTL2, and the first data metal layer DTL 1. The first via layer 160 may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

The second data metal layer DTL2 may be positioned on the first via layer 160. The second data metal layer DTL2 may include a second connection electrode CE2. The second connection electrode CE2 may be connected to the first connection electrode CE1 through a second contact hole CT2 passing through the first insulating layer (not shown) and the first via layer 160. The second data metal layer DTL2 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The second via layer 170 may be positioned on the second data metal layer DTL 2. The second via layer 170 may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, and the like.

A third data metal layer DTL3 may be positioned on the second via layer 170. The third data metal layer DTL3 may include a third connection electrode CE3. The third connection electrode CE3 may be connected to the second connection electrode CE2 through a third contact hole CT3 passing through the second insulating layer (not shown) and the second via layer 170. The third data metal layer DTL3 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The third via layer 180 may be positioned on the third data metal layer DTL 3. The third via layer 180 may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, and the like.

A fourth data metal layer DTL4 may be positioned on the third via layer 180. The fourth data metal layer DTL4 may include an anode pad electrode APD and a cathode pad electrode CPD. The anode pad electrode APD may be connected to the third connection electrode CE3 through a fourth contact hole CT4 passing through the third insulating layer (not shown) and the third via layer 180. The cathode pad electrode CPD may receive a first power voltage, which may be a low potential voltage. The fourth data metal layer DTL4 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

A fifth data metal layer DTL5 may be positioned on each of the anode pad electrode APD and the cathode pad electrode CPD. The fifth data metal layer DTL5 may include a transparent conductive layer TCO for increasing adhesion between the fourth data metal layer DTL4 and the first contact electrode CTE1 and the second contact electrode CTE2 of the light emitting element LE. The fifth data metal layer DTL5 may be formed of transparent conductive oxide, for example, indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO).

The fourth via layer 190 may also be positioned on the third via layer 180. The fourth via layer 190 may be positioned in each separation space between the plurality of sub-pixels. In other words, the fourth via layer 190 may be positioned partially on the third via layer 180, rather than being positioned entirely on the third via layer 180. That is, the fourth via layer 190 may serve as a pixel defining film defining the sub-pixels. The fourth via layer 190 may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

The upper protective layer PVX may be positioned on the third via layer 180, the fifth data metal layer DTL5, and the fourth via layer 190. The upper protective layer PVX may cover a portion of the transparent conductive layer TCO positioned on the anode pad electrode APD and an edge of the transparent conductive layer TCO positioned on the cathode pad electrode CPD, and may cover upper and side surfaces of the fourth via layer 190 and an upper surface of the third via layer 180 exposed through the fourth via layer 190. The upper protective layer PVX may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

The first and second element contact holes CTL1 and CTL2 may be formed in the upper protective layer PVX, the first and second element contact holes CTL1 and CTL2 exposing a portion of the transparent conductive layer TCO positioned on the anode pad electrode APD and a portion of the transparent conductive layer TCO positioned on the cathode pad electrode CPD, respectively. The first element contact hole CTL1 may expose a portion of the transparent conductive layer TCO positioned on the anode pad electrode APD, and the second element contact hole CTL2 may expose a portion of the transparent conductive layer TCO positioned on the cathode pad electrode CPD.

Each of the plurality of sub-pixels SPX1, SPX2, and SPX3 may include one light emitting element LE. Each of the light emitting elements LE may be positioned on a portion of the transparent conductive layer TCO positioned on the anode pad electrode APD and a portion of the transparent conductive layer TCO positioned on the cathode pad electrode CPD, which are exposed through the first element contact hole CTL1 and the second element contact hole CTL2, respectively, formed in the upper protective layer PVX. In fig. 5, the light emitting element LE is shown as a flip chip type micro LED in which the first contact electrode CTE1 and the second contact electrode CTE2 are positioned to face the anode pad electrode APD and the cathode pad electrode CPD, respectively.

The light emitting element LE may be an inorganic light emitting element made of an inorganic material such as GaN. The length of the light emitting element LE in each of the first, second, and third directions DR1, DR2, and DR3 may be several micrometers to several hundred micrometers. For example, the length of the light emitting element LE in each of the first, second, and third directions DR1, DR2, and DR3 may be about 100 μm or less.

The light emitting element LE may be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the light emitting elements LE may be directly transferred from the silicon wafer onto the anode pad electrode APD and the cathode pad electrode CPD of the substrate 100. Alternatively, each of the light emitting elements LE may be transferred onto the anode pad electrode APD and the cathode pad electrode CPD of the substrate 100 by an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material such as Polydimethylsiloxane (PDMS) or silicone as a transfer substrate.

Each of the light emitting elements LE may be a light emitting structure including a base substrate PSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE 2.

The base substrate PSUB of the light emitting element LE may be a sapphire substrate, but the disclosure is not limited thereto.

The n-type semiconductor NSEM of the light emitting element LE may be positioned on one surface of the base substrate PSUB. For example, the n-type semiconductor NSEM may be positioned on the lower surface of the base substrate PSUB. The n-type semiconductor NSEM may be made of GaN doped with an n-type conductive dopant such as Si, ge, se, sn and the like.

The active layer MQW of the light-emitting element LE may be positioned on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the disclosure is not limited thereto.

Alternatively, the active layer MQW may have a structure in which semiconductor materials having a large energy band gap and semiconductor materials having a small energy band gap are alternately stacked, and may include group III to group V semiconductor materials according to the wavelength band of the emitted light.

The p-type semiconductor PSEM may be positioned on one surface of the active layer MQW. The p-type semiconductor PSEM may be formed of GaN doped with a p-type conductive dopant such as Mg, zn, ca, ba and the like.

The first contact electrode CTE1 may be positioned on the p-type semiconductor PSEM and the second contact electrode CTE2 may be positioned on another portion of one surface of the n-type semiconductor NSEM. Another portion of one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is positioned may be positioned to be spaced apart from a portion of one surface of the n-type semiconductor NSEM on which the active layer MQW is positioned.

The first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other by a conductive adhesive member such as an Anisotropic Conductive Film (ACF) or an Anisotropic Conductive Paste (ACP). Alternatively, the first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other by a soldering process.

Hereinafter, an arrangement relationship between the pixels PX and the side wiring 200 and an arrangement relationship between the side wiring 200 and the driver will be described.

Fig. 6 is a perspective view illustrating an arrangement relationship between pixels and side wirings of a display device according to one or more embodiments. Fig. 7 is a plan view illustrating an arrangement relationship between pixels and side wirings of a display device according to one or more embodiments. Fig. 8 is a rear view illustrating an arrangement relationship between side wirings and drivers of a display device according to one or more embodiments.

Referring to fig. 6 to 8, the display device 10 further includes a plurality of first PADs PAD1, a plurality of second PADs PAD2, a plurality of third PADs PAD3, and a plurality of bottom connection wirings BCL.

The plurality of first PADs PAD1 may be used to transmit an electric signal of a driver to each of the plurality of pixels PX. The first PAD1 may be positioned on the first surface 100a of the substrate 100. The first PAD1 may be positioned at an edge of one side of the first surface 100a of the substrate 100 in the first direction DR1 (in other words, in the PAD area PDA). The pad area PDA may be a part of the non-display area NDA, and may designate the non-display area NDA located at an edge of one side of the display area DA in the first direction DR 1. The first PAD1 may be disposed along the second direction DR 2.

The plurality of second PADs PAD2 may be used to transmit an electric signal of the driver to the first PAD1 through the side wiring 200. The second PAD2 may be positioned on the second surface 100b of the substrate 100. The second PAD2 may be positioned at an edge of one side of the second surface 100b of the substrate 100 in the first direction DR 1. The second PAD2 may be arranged along the second direction DR 2.

Each of the plurality of first PADs PAD1 and the plurality of second PADs PAD2 may have a shape extending in the second direction DR 2. Accordingly, as described below, the side wiring 200 may expose a portion of each of the plurality of first PADs PAD1 and a portion of each of the plurality of second PADs PAD 2. In other words, the width of the side wiring 200 in the second direction DR2 may be smaller than the width of each of the plurality of first PADs PAD1 in the second direction DR2 and/or smaller than the width of each of the plurality of second PADs PAD2 in the second direction DR 2. In other words, each of the plurality of first PADs PAD1 and each of the plurality of second PADs PAD2 may protrude from the side wiring 200 in the second direction DR2 (e.g., in a plan view).

The plurality of third PADs PAD3 may be used to transmit an electrical signal generated from the driver to the second PAD2 through the bottom connection wiring BCL. The third PAD3 may be positioned on the second surface 100b of the substrate 100. The third PAD3 may be generally more adjacent to a central portion of the second surface 100b of the substrate 100 than the second PAD2. The third PAD3 may be disposed along the second direction DR 2. The third PAD3 may be arranged to correspond to a terminal formed in the driver. In other words, the third PAD3 may be arranged to correspond to a terminal formed on the circuit board CB of the driver. In order to connect more second PADs PAD2 to the circuit board CB, a gap between third PADs PAD3 adjacent to each other in the second direction DR2 may be smaller than a gap between second PADs PAD2 adjacent to each other in the second direction DR 2.

The plurality of bottom connection wirings BCL may be used to respectively connect the second PAD2 to the third PAD3. Since the gap between the second PADs PAD2 adjacent to each other in the second direction DR2 and the gap between the third PADs PAD3 adjacent to each other in the second direction DR2 are different from each other, the bottom connection wiring BCL may be bent at least once. The bottom connection wiring BCL may be integrally formed with the second PAD2 and the third PAD3. The second PAD2, the third PAD3, and the bottom connection wiring BCL may each be formed as a single layer or a plurality of layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The side wiring 200 may include a first flat portion 210, a first inclined portion 240a, a connection portion 230, a second inclined portion 240b, and a second flat portion 220.

The first flat portion 210 of the side wiring 200 may be a portion positioned on the first surface 100a of the substrate 100 (e.g., in a pad area PDA of the first surface 100 a). The first flat portion 210 may be positioned on the first PAD1 to partially cover the first PAD1. The first flat portion 210 may be electrically connected to the first PAD1. As described above, the first PAD1 may protrude from the first flat portion 210 of the side wiring 200 in the second direction DR2 (e.g., in a plan view). A description thereof will be provided below.

The first inclined portion 240a of the side wiring 200 may be a portion positioned on the first chamfer surface 100d1 of the substrate 100. The first inclined portion 240a may form an inclination angle (slope) along a direction in which the first chamfer surface 100d1 is inclined. The first inclined portion 240a may be positioned between the first flat portion 210 and the connection portion 230.

The connection portion 230 of the side wiring 200 may be a portion positioned on the first side surface 100c of the substrate 100. The connection portion 230 may be positioned between the first inclined portion 240a and the second inclined portion 240 b.

The second inclined portion 240b of the side wiring 200 may be a portion positioned on the second chamfer surface 100d2 of the substrate 100. The second inclined portion 240b may form an inclination angle along a direction in which the second chamfer surface 100d2 is inclined. The second inclined portion 240b may be positioned between the second flat portion 220 and the connection portion 230.

The second flat portion 220 of the side wiring 200 may be a portion positioned on the second surface 100b of the substrate 100. The second flat portion 220 may be positioned on the second PAD2 to partially cover the second PAD2. The second flat portion 220 may be electrically connected to the second PAD2. As described above, the second PAD2 may protrude from the second flat portion 220 of the side wiring 200 in the second direction DR2 (e.g., in a plan view). A description thereof will be provided below.

The side wiring 200 may include metal powder (such as silver (Ag) and copper (Cu)) including metal particles and polymer (such as acrylic resin or epoxy resin). The metal powder imparts conductivity to the side wiring 200 and the polymer may act as an adhesive to the metal particles.

The side wiring 200 may be formed by printing a metal paste including metal particles, a monomer, and a solution onto the substrate 100 using a silicon pad and then sintering the metal paste using a laser. In the sintering process, since the monomer is converted into a polymer by the heat of the laser, the metal particles may be closely adhered to each other and aggregated to reduce the resistivity of the side wiring 200.

Hereinafter, a structure in which an edge of one side of the display device 10 in the first direction DR1 (in other words, an arrangement structure of the first PAD1, the second PAD2, the third PAD3, and the pixels PX) is formed at a boundary between the display area DA and the PAD area PDA will be described.

Fig. 9 is a sectional view showing a section taken along the line X1-X1' of fig. 7 and 8.

Referring to fig. 9, the first PAD1 may be positioned adjacent to but spaced apart from the pixel PX positioned at the outermost portion, and the second PAD2 may be positioned on the second surface 100b of the substrate 100.

For convenience of description, among the plurality of sub-pixels positioned in the display area DA, a sub-pixel positioned closest to the pad area PDA is referred to as an outermost pixel. The outermost pixel is a sub-pixel positioned at an edge of one side of the display area DA in the first direction DR 1. The sub-pixels adjacent to the outermost pixels are positioned only on the other side of the outermost pixels in the first direction DR1 (e.g., away from the one side of the display area DA). Accordingly, the fourth via layer 190 may not be positioned on one side of the outermost pixel in the first direction DR1, and may be positioned on the other side of the outermost pixel in the first direction DR 1.

Since the structure of the outermost pixel is the same as that of the sub-pixel described above with reference to fig. 5, a description thereof will be omitted.

In the pad area PDA, the first data metal layer DTL1 may further include a first upper pad electrode PD1, the second data metal layer DTL2 may further include a second upper pad electrode PD2, the third data metal layer DTL3 may further include a third upper pad electrode PD3, the fourth data metal layer DTL4 may further include a fourth upper pad electrode PD4, the fifth data metal layer DTL5 may further include a fifth upper pad electrode PD5, and the second gate metal layer GTL2 may further include an upper connection wiring CNE (or an upper connection wiring pattern CNE').

The first PAD1 may include a first upper PAD electrode PD1, a second upper PAD electrode PD2, a third upper PAD electrode PD3, a fourth upper PAD electrode PD4, and a fifth upper PAD electrode PD5. The second upper pad electrode PD2 may be positioned on the first upper pad electrode PD1, the third upper pad electrode PD3 may be positioned on the second upper pad electrode PD2, the fourth upper pad electrode PD4 may be positioned on the third upper pad electrode PD3, and the fifth upper pad electrode PD5 may be positioned on the fourth upper pad electrode PD 4. The upper surface of the first upper pad electrode PD1 may be in direct contact with the bottom surface of the second upper pad electrode PD2, the upper surface of the second upper pad electrode PD2 may be in direct contact with the bottom surface of the third upper pad electrode PD3, the upper surface of the third upper pad electrode PD3 may be in direct contact with the bottom surface of the fourth upper pad electrode PD4, and the upper surface of the fourth upper pad electrode PD4 may be in direct contact with the bottom surface of the fifth upper pad electrode PD5.

The second upper pad electrode PD2 may be positioned on the first upper pad electrode PD1 to entirely cover the upper surface and the side surface of the first upper pad electrode PD1, the third upper pad electrode PD3 may be positioned on the second upper pad electrode PD2 to entirely cover the upper surface and the side surface of the second upper pad electrode PD2, the fourth upper pad electrode PD4 may be positioned on the third upper pad electrode PD3 to entirely cover the upper surface and the side surface of the third upper pad electrode PD3, and the fifth upper pad electrode PD5 may be positioned on the fourth upper pad electrode PD4 to entirely cover the upper surface and the side surface of the fourth upper pad electrode PD 4.

In other words, as shown in fig. 10, the planar area of the fifth upper pad electrode PD5 may be larger than the planar area of the fourth upper pad electrode PD4, the planar area of the fourth upper pad electrode PD4 may be larger than the planar area of the third upper pad electrode PD3, the planar area of the third upper pad electrode PD3 may be larger than the planar area of the second upper pad electrode PD2, and the planar area of the second upper pad electrode PD2 may be larger than the planar area of the first upper pad electrode PD 1. The detailed description thereof will be described below.

The first upper PAD electrode PD1 of the first PAD1 may be positioned on the second interlayer insulating layer 150. The first upper pad electrode PD1 may be electrically connected to the upper connection wiring CNE positioned on the first interlayer insulating layer 130 through the pad contact hole CTP passing through the second interlayer insulating layer 150. The upper connection wiring CNE may be electrically connected to the data wiring described above.

The bottom connection wiring BCL may be positioned on the second surface 100b of the substrate 100 to extend in the first direction DR 1. The bottom connection wiring BCL may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

The second PAD2 may be positioned on the second surface 100b of the substrate 100. The second PAD2 may be positioned on one side of the bottom connection wire BCL in the first direction DR1, and the third PAD3 may be positioned on the other side of the bottom connection wire BCL in the first direction DR 1. Each of the second PAD2 and the third PAD3 may be formed of a transparent conductive oxide such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO).

The lower via layer 120 may be positioned on the second surface 100b of the substrate 100. For example, the lower via layer 120 may be positioned on the other side surface of the bottom connection wire BCL in the third direction DR 3. The lower via layer 120 may partially cover the second PAD2 and the third PAD3, but may expose at least some of the second PAD2 and the third PAD 3. The portion of the second PAD2 exposed through the lower via layer 120 may be in direct contact with the second flat portion 220 of the side wiring 200 and electrically connected to the second flat portion 220 of the side wiring 200, and the portion of the third PAD3 exposed through the lower via layer 120 may be electrically connected to the circuit board CB through the conductive adhesive member CAM. The conductive adhesive member CAM may be an anisotropic conductive film or an anisotropic conductive paste.

The lower via layer 120 may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, and the like.

The lower protection layer 140 may cover the lower via layer 120. For example, the lower protective layer 140 may be positioned on the lower via layer 120, and may not be positioned on the second PAD2 and the third PAD 3. In other words, the second PAD2 and the third PAD3 may each include a portion exposed through the lower protective layer 140. The lower protective layer 140 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

The side wiring 200 may be positioned on or near the first surface 100a, the first chamfer surface 100d1, the first side surface 100c, the second chamfer surface 100d2, and the second surface 100b of the substrate 100. The side wiring 200 may be positioned on the first PAD1 at an edge of one side of the first surface 100a of the substrate 100 in the first direction DR1, and may be electrically connected to the first PAD1. The side wiring 200 may be positioned on the second PAD2 at an edge of one side of the second surface 100b of the substrate 100 in the first direction DR1, and may be connected to the second PAD2. The side wiring 200 may be in contact with the first chamfer surface 100d1, the first side surface 100c, and the second chamfer surface 100d2 of the substrate 100.

The overcoat layer OC may be positioned on the first surface 100a, the first chamfer surface 100d1, the first side surface 100c, the second chamfer surface 100d2, and the second surface 100b of the substrate 100. The overcoat OC may be positioned to cover the side wiring 200. The overcoat OC may be formed of an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

Meanwhile, the first, second and third via layers 160, 170 and 180 extending in the first direction DR1 in the display area DA may not extend near the boundary between the display area DA and the pad area PDA.

The first PAD opening POP1 exposing the upper surface of the fifth upper PAD electrode PD5 of the first PAD1 may be formed in the upper protective layer PVX. The first flat portion 210 of the side wiring 200 may be electrically connected to the first PAD1 through the first PAD opening POP 1.

Hereinafter, the structure of the first PAD1 and the upper connection wiring CNE electrically connected to the first PAD1 will be described in detail.

Fig. 10 is a layout diagram showing the structure of the first pad and the upper connection wiring. Fig. 11 is a sectional view showing a section taken along the line X2-X2' of fig. 10. Fig. 12 is a cross-sectional view showing a cross-section taken along line X3-X3' of fig. 10. Fig. 13 is a sectional view showing a section taken along the line X4-X4' of fig. 10.

Referring to fig. 10 to 13, the first PAD1 may include a first region PAD1a overlapping the side wiring 200 in the third direction DR3, a second region PAD1b not overlapping the side wiring 200 in the third direction DR3, and a third region PAD1c connecting the first region PAD1a and the second region PAD1 b.

As described above, the first PAD1 may include the first upper PAD electrode PD1, the second upper PAD electrode PD2, the third upper PAD electrode PD3, the fourth upper PAD electrode PD4, and the fifth upper PAD electrode PD5. The second upper pad electrode PD2 has a larger planar area than the first upper pad electrode PD1, the third upper pad electrode PD3 has a larger planar area than the second upper pad electrode PD2, the fourth upper pad electrode PD4 has a larger planar area than the third upper pad electrode PD3, and the fifth upper pad electrode PD5 has a larger planar area than the fourth upper pad electrode PD 4. In some embodiments, the first upper pad electrode PD1, the second upper pad electrode PD2, the third upper pad electrode PD3, the fourth upper pad electrode PD4, and the fifth upper pad electrode PD5 may each have a rectangular planar shape, but the disclosure is not limited thereto.

The first, second, third, fourth and fifth upper PAD electrodes PD1, PD2, PD3, PD4 and PD5 may be positioned in the first region PAD1a of the first PAD1, and the first, second and third upper PAD electrodes PD1, PD2 and PD3 may not be positioned in the second and third regions PAD1b and PAD1c of the first PAD 1. For example, the fourth and fifth upper PAD electrodes PD4 and PD5 may extend in the second direction DR2 in the second and third regions PAD1b and PAD1c of the first PAD 1. The first, second, and third upper PAD electrodes PD1, PD2, and PD3 may be positioned only in the first region PAD1a of the first PAD 1.

As shown in fig. 11, the first PAD opening POP1 contacting the side wiring 200 or partially filled with the side wiring 200 may be formed in the first region PAD1a of the first PAD 1. As shown in fig. 12, a second PAD opening POP2 to which a detection device (e.g., for checking whether the first PAD1 and the plurality of pixels PX are electrically connected) may be connected may be formed in the second area PAD1 b. As shown in fig. 13, since the third region PAD1c of the first PAD1 connects the first region PAD1a and the second region PAD1b, whether the first PAD1 and the plurality of pixels PX are electrically connected may be checked using the detection means.

The upper connection wiring CNE may include a first contact portion CNEb contacting the first PAD1, a first peeling portion CNEc extending from the first contact portion CNEb toward one side of the first direction DR1, and a first wiring portion CNEa extending from the first contact portion CNEb toward the other side of the first direction DR 1.

As shown in fig. 11, the first contact portion CNEb of the upper connection wiring CNE may be electrically connected to the first upper pad electrode PD1 through the pad contact hole CTP penetrating the second interlayer insulating layer 150. In some embodiments, the pad contact hole CTP may be biased toward one side of the first upper pad electrode PD1 in the first direction DR1, but the disclosure is not limited thereto.

The first stripped portion CNEc of the upper connection wire CNE may be a pattern protruding from one side of the first contact portion CNEb in the first direction DR1 and extending in a direction toward the first chamfer surface 100d1 (i.e., one side toward the first direction DR1 in the first direction DR 1). As shown in fig. 10, as a result of a process of forming the first chamfer surface 100d1 in a display device manufacturing method to be described below, an irregular first peeling pattern PLA1 may be formed at an end of the first peeling section CNEc on one side in the first direction DR 1. In other words, the first peeling pattern PLA1 may be a pattern formed by tearing a portion of the first peeling section CNEc, and may have an irregular shape. In fig. 10, the first peeling pattern PLA1 is shown as a wave shape having a plurality of uneven portions, but the shape of the first peeling pattern PLA1 is not limited thereto.

The first wiring portion CNEa of the upper connection wiring CNE may be a pattern protruding from the other side of the first contact portion CNEb in the first direction DR1 and extending toward the other side of the first direction DR 1. The first wiring portion CNEa may transmit the electric signal received from the side wiring 200 to the plurality of pixels PX. In some embodiments, the first wiring portion CNEa may extend beyond the pad area PDA to the display area DA and may be electrically connected to the plurality of pixels PX, but the disclosure is not limited thereto. For example, the first wiring portion CNEa may be in contact with a separate element layer, and may transmit an electric signal to the plurality of pixels PX through the element layer.

The width W2 of the first contact portion CNEb in the second direction DR2 may be larger than the width W1 of the first wiring portion CNEa in the second direction DR 2. This can increase the contact area between the first contact portion CNEb and the first upper pad electrode PD 1. Meanwhile, the width W3 of the first peeling section CNEc in the second direction DR2 is smaller than the width W2 of the first contact section CNEb in the second direction DR 2. This may be to reduce or minimize peeling (peeling) of the upper connection wiring CNE by reducing or minimizing friction for forming the first chamfer surface 100d1 in the display device manufacturing process, which will be described below. The detailed description thereof will be described below.

Hereinafter, the structure of the second PAD2 and the bottom connection wiring BCL electrically connected to the second PAD2 will be described in detail.

Fig. 14 is a layout diagram showing the structure of the second pad and the bottom connection wiring. Fig. 15 is a cross-sectional view showing a cross-section taken along line X5-X5' of fig. 14. Fig. 16 is a sectional view showing a section taken along the line X6-X6' of fig. 14. Fig. 17 is a sectional view showing a section taken along the line X7-X7' of fig. 14.

Referring to fig. 14 to 17, the bottom connection wiring BCL may include a second wiring portion BCLa connected to the driver and a PAD electrode portion BCLb covered by the second PAD2 (e.g., at least partially covered by the second PAD 2).

The PAD electrode portion BCLb of the bottom connection wiring BCL may be a portion overlapped with each of the portions PAD2a and PAD2b of the second PAD2 to be described below and electrically connected to the second PAD 2. As shown in fig. 17, the PAD electrode portion BCLb may electrically connect the first portion PAD2a and the second portion PAD2b of the second PAD 2. In some embodiments, the pad electrode portion BCLb may have a rectangular planar shape having a long side in the second direction DR2 and a short side in the first direction DR1, but the disclosure is not limited thereto.

The second wiring portion BCLa of the bottom connection wiring BCL may be a portion protruding from the other side of the pad electrode portion BCLb in the first direction DR1 and extending in a direction toward the driver (i.e., toward the other side of the first direction DR1 in the first direction DR 1). The second wiring portion BCLa may be electrically connected to the driver, and may transmit an electrical signal applied from the driver (see fig. 9). In some embodiments, the second wiring portion BCLa and the pad electrode portion BCLb may be integrally formed, but the disclosure is not limited thereto.

The second PAD2 may include a first portion PAD2a overlapping the side wiring 200 in the third direction DR3 and a second portion PAD2b spaced apart from the first portion PAD2a in the second direction and not overlapping the side wiring 200 in the third direction DR 3.

As shown in fig. 15, the first portion PAD2a of the second PAD2 may be a portion that contacts the side wiring 200 and is electrically connected to the side wiring 200. The first portion PAD2a may be positioned on the bottom connection wiring BCL, and may be electrically connected to the bottom connection wiring BCL. Accordingly, the first portion PAD2a may receive a signal applied from the driver from the bottom connection wiring BCL, and may transmit the signal to the side wiring 200.

The first portion PAD2a may include a second contact portion PAD2aa and a second peeling portion PAD2ab, the second contact portion PAD2aa covering the bottom connection wiring BCL, the second peeling portion PAD2ab protruding from a side of the second contact portion PAD2aa in the first direction DR1 and extending in a direction toward the second chamfer surface 100d2 (i.e., a side toward the first direction DR1 in the first direction DR 1).

As shown in fig. 15, the first portion PAD2a may electrically connect the side wiring 200 to the PAD electrode portion BCLb of the bottom connection wiring BCL.

As a result of a process of forming the second chamfer surface 100d2 in a display device manufacturing method to be described below, an irregular second lift-off pattern PLA2 may be formed at an end portion of the second lift-off portion PAD2ab on one side in the first direction DR 1. In other words, the second peeling pattern PLA2 may be a pattern formed by tearing a portion of the second peeling section PAD2ab, and may have an irregular shape. In fig. 14, the second peeling pattern PLA2 is shown as a wave shape having a plurality of uneven portions, but the shape of the second peeling pattern PLA2 is not limited thereto.

The width W4 of the second contact portion PAD2aa in the second direction DR2 may be larger than the width W5 of the second peeling portion PAD2ab in the second direction DR 2. This can increase the contact area between the second contact portion PAD2aa and the bottom connection wiring BCL. Meanwhile, the width W5 of the second peeled portion PAD2ab in the second direction DR2 is smaller than the width W4 of the second contact portion PAD2aa in the second direction DR 2. This may reduce or minimize peeling of the second PAD2 by reducing or minimizing friction for forming the second chamfer surface 100d2 in the display device manufacturing process, which will be described below. The detailed description thereof will be described below.

As shown in fig. 16, a third PAD opening POP3 to which a detection device (e.g., for checking whether the second PAD2 and the driver are electrically connected) may be connected may be formed in the second portion PAD2b of the second PAD 2. As described above, as shown in fig. 17, since the PAD electrode portion BCLb of the bottom connection wiring BCL electrically connects the first portion PAD2a and the second portion PAD2b, it is possible to check whether the second PAD2 is connected to the driver using the detection device.

Hereinafter, a method of manufacturing the display device 10 according to one or more embodiments will be described.

Fig. 18-28 are flowcharts and views for describing a method of manufacturing a display device according to one or more embodiments.

Referring to fig. 18, a method of manufacturing the display device 10 according to one or more embodiments may include: forming patterns on the front and rear surfaces of the mother substrate MG (see fig. 19) (S100); a unit substrate 100' (see fig. 21) is obtained by scribing the mother substrate MG on which the pattern is formed (S200); forming chamfer surfaces 100d1 and 100d2 by processing edges of the unit substrate 100' (S300); forming a side wiring 200 (S400); and attaching the light emitting element LE, the circuit board CB, and the display driving circuit DC (S500).

First, referring to fig. 19 to 23, patterns are formed on the front and rear surfaces of the mother substrate MG (S100), and the mother substrate MG having the patterns formed thereon is scribed to obtain a unit 10' (S200).

The mother substrate MG is a base substrate in which scribe lines SL configured to divide a plurality of cell areas CA are defined. The cell areas CA are arranged in a matrix form, and the scribe lines SL may define the cell areas CA by intersecting a lateral direction (refer to a horizontal direction of fig. 19) and a longitudinal direction (refer to a vertical direction of fig. 19). The cell region CA may be a region corresponding to the cell 10' obtained by a scribing process (scribing process) for cutting along the scribe line SL of the mother substrate MG. In other words, when the scribing process is performed on the cell region CA, the cell 10' can be obtained.

The scribe line SL of the mother substrate MG may define the edge of the unit substrate 100 'included in the unit 10'. In other words, when cutting is performed along the scribe lines SL of the mother substrate MG, the first side surface 100c ' of the unit substrate 100' of the unit 10' may be formed. The unit 10' may include a unit substrate 100', and may include patterns remaining on the front and rear surfaces 100a ' and 100b ' of the unit substrate 100', which are obtained by scribing patterns formed on the front and rear surfaces of the mother substrate MG, which will be described below.

Referring to fig. 9, patterns formed on the front and rear surfaces of the mother substrate MG may represent a state in which all elements except the light emitting element and the driver are formed. For example, the pattern may represent the following states: the pattern includes an active layer ACT, a first gate metal layer GTL1, a second gate metal layer GTL2, a first data metal layer DTL1, a second data metal layer DTL2, a third data metal layer DTL3, a fourth data metal layer DTL4, and a fifth data metal layer DTL5 as a plurality of conductive layers formed in each cell region CA of the upper surface of the mother substrate MG and includes a buffer layer BF, a gate insulating layer 110, a first interlayer insulating layer 130, a second interlayer insulating layer 150, and an upper via layer including a first via layer 160, a second via layer 170, a third via layer 180, and a fourth via layer 190 as a plurality of insulating layers; and the pattern includes a second PAD2, a third PAD3, a bottom connection wiring BCL, a lower via layer 120, and a lower protective layer 140 formed in each unit area CA of the lower surface of the mother substrate MG.

Since a method of forming the above-described pattern is well known in the art, a detailed description thereof will be omitted.

Once the scribing process for cutting along the scribing lines SL is performed, the mother substrate MG is divided into the plurality of unit substrates 100', and the pattern on the mother substrate MG may remain on the plurality of unit substrates 100' to correspond to each of the plurality of unit substrates 100 '. The unit substrate 100' may have a three-dimensional structure of a rectangular parallelepiped or a three-dimensional structure similar to a rectangular parallelepiped. In other words, as shown in fig. 21, the unit substrate 100' may have a rectangular parallelepiped shape composed of a front surface 100a ', a rear surface 100b ', and a plurality of side surfaces. The plurality of side surfaces of the unit substrate 100 'may include a first side surface 100c', a second side surface, a third side surface, and a fourth side surface. In this case, the front surface 100a ' of the unit substrate 100' may correspond to the first surface 100a of the substrate 100 of the display device 10 described above, the rear surface 100b ' of the unit substrate 100' may correspond to the second surface 100b of the substrate 100 of the display device 10 described above, and the first side surface 100c ' of the unit substrate 100' may correspond to the first side surface 100c of the substrate 100 of the display device 10, but the unit substrate 100' may not have surfaces corresponding to the plurality of chamfered surfaces of the substrate 100 of the display device 10. In other words, the unit substrate 100' may refer to a unit substrate in a state in which a plurality of chamfer surfaces are not formed on the substrate 100, that is, a chamfer surface forming process, which will be described below, may not be performed.

Meanwhile, the patterns formed on the upper and lower surfaces of the mother substrate MG may include an upper connection wiring pattern CNE 'and a second PAD pattern PAD2'. The upper connection wiring pattern CNE 'and the second PAD pattern PAD2' may be positioned in each of the plurality of unit areas CA defined in the mother substrate MG. In other words, the plurality of upper connection wiring patterns CNE 'and the second PAD patterns PAD2' positioned in the unit area CA of the mother substrate MG may correspond to the plurality of upper connection wiring patterns CNE and the second PAD2 positioned in the display device 10, respectively.

The upper connection wiring pattern CNE 'may include a first contact portion CNEb, a first wiring portion CNEa, and a first peeling portion pattern CNEc'. There is a difference between the upper connection wiring pattern CNE' in the cell area CA and the upper connection wiring CNE of the display device 10 in the presence or absence of the first peeling pattern PLA1, and their other configurations may be substantially the same or similar. For example, compared with the first stripped portion CNEc of the upper connection wiring CNE of fig. 10, the difference is that: the first lift-off pattern PLA1 is not formed (not yet formed) in the first lift-off section pattern CNEc 'of the upper connection wiring pattern CNE', and other configurations are substantially the same or similar. In other words, the first peeled portion pattern CNEc' may be a pattern having a portion that is not peeled by a chamfer surface forming process to be described below.

Referring to fig. 22, an end portion of the first peeling section pattern CNEc' at one side in the first direction DR1 may extend to an edge of the cell area CA. In other words, the first peeled portion pattern CNEc' has a shape extending across the scribe line SL toward the scribe line SL on the mother substrate MG in a state before the scribing process is performed. After the scribing process is performed, since a portion of the first peeled portion pattern CNEc 'on the mother substrate MG intersecting the scribing line SL is also scribed while the scribing line SL is being scribed, the first peeled portion pattern CNEc' has a shape extending toward the first side surface 100c 'of the unit substrate 100' formed through the scribing process and contacting an end portion of the front surface 100a 'of the unit substrate 100'.

The second PAD pattern PAD2 'may include a first pattern portion PAD2a' and a second portion PAD2b. The first pattern portion PAD2a 'may include a second contact portion PAD2aa and a second lift-off portion pattern PAD2ab'. The first pattern portion PAD2a' in the unit area CA is different from the first portion PAD2a of the display device 10 in that: whether the second peeling pattern PLA2 is present or not, and other configurations may be substantially the same or similar. For example, compared to the second peeled portion PAD2ab of the first portion PAD2a of fig. 14, the difference is that: the second lift-off pattern PLA2 is not formed (not yet formed) in the second lift-off section pattern PAD2ab 'of the first pattern section PAD2a', and other configurations are substantially the same or similar. In other words, the second peeled portion pattern PAD2ab' may be a pattern having a portion that is not peeled off by a chamfer surface forming process to be described below.

Referring to fig. 23, an end portion of one side of the second peeling section pattern PAD2ab' in the first direction DR1 may extend to an edge of the unit area CA. In other words, the second peeled portion pattern PAD2ab ' has a shape extending across the scribe line SL toward the scribe line SL on the mother substrate MG in a state before the scribing process is performed, and after the scribing process is performed, since a portion of the second peeled portion pattern PAD2ab ' on the mother substrate MG intersecting the scribe line SL is also scribed while the scribe line SL is being scribed, the second peeled portion pattern PAD2ab ' has a shape extending toward the first side surface 100c ' of the unit substrate 100' formed by the scribing process and also contacting an end portion of the front surface 100a ' of the unit substrate 100 '.

Subsequently, referring to fig. 24 to 27, the edges of the unit substrates 100 'of the unit 10' are processed to form a chamfer surface. For example, the process of forming the chamfer surface may be performed using physical friction.

As shown in fig. 24 and 25, the unit substrate 100' may be processed (worked) into the substrate 100 having the plurality of chamfer surfaces formed thereon by removing a portion of the edge of the unit substrate 100' by applying physical friction along the virtual chamfer line CHL near the edge of the unit substrate 100 '. In this case, the unit 10' includes a substrate 100.

Meanwhile, when physical friction is applied along the virtual chamfer line CHL near the edge of the unit substrate 100', some element layers positioned on the front surface 100a ' and some element layers positioned on the rear surface 100b ' of the unit substrate 100' may be removed along the virtual chamfer line CHL together with portions of the edge of the unit substrate 100 '.

Accordingly, since one end of the first peeling part pattern CNEc 'and one end of the second peeling part pattern PAD2ab' are peeled, one end of the first peeling part pattern CNEc 'and one end of the second peeling part pattern PAD2ab' may be treated as the first peeling part CNEc including the first peeling pattern PLA1 and the second peeling part PAD2ab including the second peeling pattern PLA2 as shown in fig. 26 and 27, respectively.

In this case, since the width W3 of the first peeling section pattern CNEc' is smaller than the width W2 of the first contact section CNEb, it may be less affected by physical friction for forming the chamfer surface. The influence of the physical friction for forming the chamfer surface has a correlation proportional to the width W3 of the first peeling section pattern CNEc ', and therefore, when the width W3 of the first peeling section pattern CNEc' is substantially the same as or similar to the width W2 of the first contact section CNEb, it may be relatively greatly influenced by the physical friction for forming the chamfer surface, and thus there is a risk that the first peeling section pattern CNEc 'may not be in proper contact with the first upper pad electrode PD1 because the first peeling section pattern CNEc' is peeled until near the first contact section CNEb. Therefore, by forming the width W3 of the first peeling section pattern CNEc 'to be smaller than the width W2 of the first contact section CNEb, the influence of physical friction for forming the chamfer surface can be reduced, so that the possibility that the first peeling section pattern CNEc' is peeled up to the first contact section CNEb can be reduced or prevented.

Similarly, since the width W5 of the second peeled portion pattern PAD2ab' is smaller than the width W4 of the second contact portion PAD2aa, it may be less affected by physical friction for forming the chamfer surface. The influence of the physical friction for forming the chamfer surface has a correlation proportional to the width W5 of the second peeled portion pattern PAD2ab ', and therefore, when the width W5 of the second peeled portion pattern PAD2ab' is substantially the same as or similar to the width W4 of the second contact portion PAD2aa, it is relatively greatly influenced by the physical friction for forming the chamfer surface, and thus there is a risk that the second peeled portion pattern PAD2ab 'may not be in proper contact with the bottom connection wiring BCL because the second peeled portion pattern PAD2ab' is peeled until the vicinity of the second contact portion PAD2 aa. Therefore, by forming the width W5 of the second peeled portion pattern PAD2ab 'smaller than the width W4 of the second contact portion PAD2aa, the influence of physical friction for forming the chamfer surface can be reduced, so that the possibility that the second peeled portion pattern PAD2ab' is peeled up to the second contact portion PAD2aa can be reduced or prevented.

Subsequently, referring to fig. 28, the side wiring 200 and the overcoat layer OC are formed on the side of the substrate 100 on which the plurality of chamfer surfaces are formed. For example, the process of forming the side wiring 200 may be performed by printing a metal pattern in a Si mold (Si-mold) such that the Si mold contacts with a side of the substrate 100 on which a plurality of chamfer surfaces are formed and transferring the metal pattern.

In the substrate 100 on which the plurality of chamfer surfaces are formed, the bending angle of the side wiring 200 may be gentle due to the plurality of chamfer surfaces, compared to a state in which the plurality of chamfer surfaces are not formed, so that the possibility of chipping or cracking in the side wiring 200 may be reduced or prevented.

Thereafter, the light emitting element LE, the circuit board CB, and the display driving circuit DC are positioned in the unit 10' to manufacture the display device 10.

Hereinafter, a structure of a tiled display including a display device according to one or more embodiments will be described.

Fig. 29 is a diagram schematically illustrating a tiled display using a display device according to one or more embodiments. Fig. 30 is an enlarged view showing a region a of fig. 29. Fig. 31 is a cross-sectional view showing a cross section taken along line XA-XA' of fig. 30.

Referring to fig. 29 to 31, the tiled display TD may include a plurality of display devices (e.g., display device 10), a seam SM, and a front cover 300. For convenience of description, among each of the plurality of display devices shown in fig. 29, a display device located at an upper left side will be referred to as a first display device 11, a display device located at an upper right side will be referred to as a second display device 12, a display device located at a lower left side will be referred to as a third display device 13, and a display device located at a lower right side will be referred to as a fourth display device 14 according to a relative positional relationship. Although the tiled display TD is shown in fig. 29 as including four display devices (first display device 11, second display device 12, third display device 13, and fourth display device 14), the number of display devices that can be included in the tiled display TD is not limited thereto. In this specification, the tiled display TD may be referred to as a tiled display device.

The plurality of display devices 11, 12, 13, and 14 may be arranged in a grid form. The plurality of display devices 11, 12, 13, and 14 may be arranged in a matrix having m rows (where m is a positive integer) and n columns (where n is a positive integer). In fig. 29, the first display device 11 and the second display device 12 are shown adjacent to each other in the row direction, the first display device 11 and the third display device 13 are shown adjacent to each other in the column direction, the third display device 13 and the fourth display device 14 are shown adjacent to each other in the row direction, and the second display device 12 and the fourth display device 14 are shown adjacent to each other in the column direction, but the arrangement of the plurality of display devices constituting the tiled display TD is not limited thereto. That is, the number and arrangement of the display devices in the tiled display TD may be determined according to the size of each of the display devices and the tiled display TD and the shape of the tiled display TD. Hereinafter, for convenience of description, it will be mainly described that the tiled display TD includes four display devices, and each of the plurality of display devices 11, 12, 13, and 14 is positioned in two rows and two columns.

The plurality of display devices 11, 12, 13, and 14 constituting the tiled display TD may have the same size, but the disclosure is not limited thereto. For example, the plurality of display devices 11, 12, 13, and 14 may have different sizes.

Each of the plurality of display devices 11, 12, 13, and 14 may have a rectangular shape including long sides and short sides. The plurality of display devices 11, 12, 13, and 14 may be arranged such that long sides or short sides thereof are connected to each other. Some or all of the plurality of display devices 11, 12, 13, and 14 may be positioned at an edge of the tiled display TD, and may form one side (edge) of the tiled display TD. At least one display device among the plurality of display devices 11, 12, 13, and 14 may be positioned on at least one corner of the tiled display TD, and may form two adjacent sides of the tiled display TD. At least one of the plurality of display devices 11, 12, 13, and 14 may be surrounded by other display devices.

Each of the plurality of display devices 11, 12, 13, and 14 may be substantially the same as the display device 10 described with reference to fig. 1. Accordingly, repeated descriptions of each of the plurality of display devices 11, 12, 13, and 14 are omitted.

The seam SM may include a bonding member or an adhesive member. In this case, the plurality of display devices 11, 12, 13, and 14 may be connected to each other by a bonding member or an adhesive member of the seam SM. The seam SM may be positioned between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

Referring to fig. 30, the seam SM may have a cross shape (+), a cross, or a plane shape of a plus sign in a central region of the tiled display TD where the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 are adjacent to each other. The seam SM may be positioned between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

The first display device 11 may include first pixels PX1 arranged in a matrix form along a row direction (refer to a horizontal direction of fig. 30) and a column direction (refer to a vertical direction of fig. 30) crossing the row direction to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix along a row direction and a column direction to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix along the row and column directions to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix along the row and column directions to display an image. Since each of the first, second, third, and fourth pixels PX1, PX2, PX3, and PX4 is substantially the same as the pixel PX of the display device 10, a detailed description of the structure of each of the first, second, third, and fourth pixels PX1, PX2, PX3, and PX4 will be omitted.

The minimum distance between the first pixels PX1 adjacent in the row direction is defined as a first horizontal separation distance GH1, and the minimum distance between the second pixels PX2 adjacent in the row direction may be defined as a second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially the same.

The seam SM may be positioned between the first pixel PX1 and the second pixel PX2 adjacent in the row direction. The minimum distance G12 between the first pixel PX1 and the second pixel PX2 adjacent in the row direction may be a sum of the minimum distance GHS1 in the row direction between the first pixel PX1 and the joint SM, the minimum distance GHS2 in the row direction between the second pixel PX2 and the joint SM, and the width GSM1 in the row direction of the joint SM.

The first and second horizontal separation distances GH1 and GH2 and the minimum distance G12 between the first and second pixels PX1 and PX2 adjacent in the row direction may be substantially the same. For this, the minimum distance GHS1 in the row direction between the first pixel PX1 and the joint SM may be smaller than the first horizontal separation distance GH1, and the minimum distance GHS2 in the row direction between the second pixel PX2 and the joint SM may be smaller than the second horizontal separation distance GH2. Further, the width GSM1 of the seam SM in the row direction may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

The minimum distance between the third pixels PX3 adjacent in the row direction may be defined as a third horizontal separation distance GH3, and the minimum distance between the fourth pixels PX4 adjacent in the row direction may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially the same.

The seam SM may be positioned between the third pixel PX3 and the fourth pixel PX4 adjacent in the row direction. The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 adjacent in the row direction may be a sum of the minimum distance GHS3 between the third pixel PX3 and the joint SM in the row direction, the minimum distance GHS4 between the fourth pixel PX4 and the joint SM in the row direction, and the width GSM1 of the joint SM in the row direction.

The third horizontal separation distance GH3, the fourth horizontal separation distance GH4, and the minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 adjacent in the row direction may be substantially the same. For this reason, the minimum distance GHS3 in the row direction between the third pixel PX3 and the joint SM may be smaller than the third horizontal separation distance GH3, and the minimum distance GH4 in the row direction between the fourth pixel PX4 and the joint SM may be smaller than the fourth horizontal separation distance GH4. Further, the width GSM1 of the seam SM in the row direction may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

The minimum distance between the first pixels PX1 adjacent in the column direction may be defined as a first vertical separation distance GV1, and the minimum distance between the third pixels PX3 adjacent in the column direction may be defined as a third vertical separation distance GV3. The first and third vertical separation distances GV1 and GV3 may be substantially the same.

The seam SM may be positioned between the first pixel PX1 and the third pixel PX3 adjacent in the column direction. The minimum distance G13 between the first pixel PX1 and the third pixel PX3 adjacent in the column direction may be a sum of the minimum distance GVS1 in the column direction between the first pixel PX1 and the joint SM, the minimum distance GVS3 in the column direction between the third pixel PX3 and the joint SM, and the width GSM2 in the column direction of the joint SM.

The first vertical separation distance GV1, the third vertical separation distance GV3, and the minimum distance G13 between the first pixel PX1 and the third pixel PX3 adjacent in the column direction may be substantially the same. For this, the minimum distance GVS1 in the column direction between the first pixel PX1 and the joint SM may be smaller than the first vertical separation distance GV1, and the minimum distance GVS3 in the column direction between the third pixel PX3 and the joint SM may be smaller than the third vertical separation distance GV3. Further, the width GSM2 of the seam SM in the column direction may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

The minimum distance between the second pixels PX2 adjacent in the column direction may be defined as a second vertical separation distance GV2, and the minimum distance between the fourth pixels PX4 adjacent in the column direction may be defined as a fourth vertical separation distance GV4. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially the same.

The seam SM may be positioned between the second pixel PX2 and the fourth pixel PX4 adjacent in the column direction. The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 adjacent in the column direction may be a sum of the minimum distance GVS2 in the column direction between the second pixel PX2 and the joint SM, the minimum distance GVS4 in the column direction between the fourth pixel PX4 and the joint SM, and the width GSM2 in the column direction of the joint SM.

The second vertical separation distance GV2, the fourth vertical separation distance GV4, and the minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 adjacent in the column direction may be substantially the same. For this reason, the minimum distance GVS2 in the column direction between the second pixel PX2 and the joint SM may be smaller than the second vertical separation distance GV2, and the minimum distance GVS4 in the column direction between the fourth pixel PX4 and the joint SM may be smaller than the fourth vertical separation distance GV4. Further, the width GSM2 of the seam SM in the column direction may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4.

As shown in fig. 30, in order to reduce or prevent the possibility of viewing the seam SM between images displayed by the plurality of display devices 11, 12, 13, and 14, the minimum distance between the pixels PX of adjacent display devices may be substantially the same as the minimum distance between the pixels PX of each of the display devices.

Referring to fig. 31, a plurality of front covers 300 may be positioned on upper portions of the plurality of display devices 11, 12, 13, and 14, respectively. For convenience of description, the front cover 300 positioned on the first display device 11 is referred to as a first front cover, the front cover 300 positioned on the second display device 12 is referred to as a second front cover, the front cover 300 positioned on the third display device 13 is referred to as a third front cover, and the front cover 300 positioned on the fourth display device 14 is referred to as a fourth front cover. The plurality of display devices 11, 12, 13, and 14 and the plurality of front covers 300 corresponding to the plurality of display devices 11, 12, 13, and 14 may be respectively coupled to each other by the adhesive member AD. Fig. 31 shows an arrangement structure of the first display device 11 and the second display device 12 and the first front cover and the second front cover corresponding to the first display device 11 and the second display device 12, respectively. Since the arrangement structure of the third display device 13 and the third front cover and the fourth display device 14 and the fourth front cover is substantially the same as the arrangement structure of the first display device 11 and the second display device 12 and the first front cover and the second front cover corresponding to the first display device 11 and the second display device 12, the first front cover and the second front cover will be mainly described hereinafter, and similar detailed description of the third front cover and the fourth front cover will be omitted.

The first front cover may be positioned on the first display device 11 and may protrude much more than the base 100 of the first display device 11. Accordingly, the gap G100 between the substrate 100 of the first display device 11 and the substrate 100 of the second display device 12 may be larger than the gap G300 between the first front cover and the second front cover.

Each of the plurality of front covers 300 may include a light transmittance controlling layer 310 and an anti-glare layer 320.

As described above, each of the plurality of front covers 300 may be bonded to the corresponding display device 10 by the adhesive member AD. The adhesive member AD may be a transparent adhesive member capable of transmitting light. For example, the adhesive member AD may be an optically transparent adhesive film or an optically transparent resin.

The light transmittance controlling layer 310 may be positioned on the adhesive member AD. The light transmittance controlling layer 310 may be designed to reduce transmittance of external light or light reflected by the first display device 11 and the second display device 12. Further, as described above, since the front cover 300 protrudes much more than the substrate 100, the light transmittance controlling layer 310 included in the front cover 300 may also protrude much more than the substrate 100. Accordingly, the visibility of the gap G100 between the substrate 100 of the first display device 11 and the substrate 100 of the second display device 12 from the outside can be reduced or prevented.

The anti-glare layer 320 may be positioned on the light transmittance controlling layer 310. The anti-glare layer 320 may be designed to diffusely reflect external light to reduce or prevent the visibility of an image from being deteriorated due to external light being reflected as it is. Accordingly, due to the anti-glare layer 320, the contrast of the images displayed by the first display device 11 and the second display device 12 can be increased.

The anti-glare layer 320 may be implemented as a polarizer, and the light transmittance controlling layer 310 may be implemented as a phase retardation layer, but the embodiment of the present specification is not limited thereto.

Hereinafter, a driving method of the tiled display TD according to one or more embodiments will be described.

FIG. 32 is a block diagram illustrating a structure of a tiled display in accordance with one or more embodiments. Fig. 33 is a diagram illustrating a state in which a tiled display using a display device according to one or more embodiments is driven.

Referring to fig. 32 and 33, a tiled display TD according to one or more embodiments may include a HOST system HOST and broadcast tuner 410, a signal processor 420, a display 430, a speaker 440, a user input 450, a Hard Disk Drive (HDD) 460, a network communicator 470, a User Interface (UI) generator 480, and a controller 490 included in each of a plurality of display devices 11, 12, 13, and 14. In fig. 32, the HOST system HOST and the first display apparatus 11 are shown as examples.

HOST system HOST may be implemented as any one of a television system, a home theater system, a set-top box, a navigation system, a Digital Video Disk (DVD) player, a blu-ray player, a PC, a mobile phone system, and a tablet computer.

User commands may be entered into HOST system HOST in various formats. For example, a command entered by a user's touch may be entered into HOST system HOST. Alternatively, the user command may be input to HOST system HOST through a keyboard input or a button input of the remote controller.

HOST system HOST may externally receive original video data (ODATA) corresponding to an original image. HOST system HOST may divide the original video data (ODATA) into the same number as the number of display devices 10. For example, the HOST system HOST may divide the original video DATA (ODATA) into first video DATA (DATA 1) corresponding to the first image, second video DATA (DATA 2) corresponding to the second image, third video DATA (DATA 3) corresponding to the third image, and fourth video DATA (DATA 4) corresponding to the fourth image to correspond to the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14, respectively. The HOST system HOST may transmit the first video DATA (DATA 1) to the first display device 11, the second video DATA (DATA 2) to the second display device 12, the third video DATA (DATA 3) to the third display device 13, and the fourth video DATA (DATA 4) to the fourth display device 14.

The first display device 11 may display a first image according to the first video DATA (DATA 1), the second display device 12 may display a second image according to the second video DATA (DATA 2), the third display device 13 may display a third image according to the third video DATA (DATA 3), and the fourth display device 14 may display a fourth image according to the fourth video DATA (DATA 4). Accordingly, as shown in fig. 33, the user can view the original image in which the first to fourth images displayed on the first to fourth display devices 11 to 14, respectively, are combined.

Each of the plurality of display devices 11, 12, 13, and 14 constituting the tiled display TD may further include a broadcast tuner 410, a signal processor 420, a display part 430, a speaker 440, a user input part 450, an HDD 460, a network communicator 470, a UI generator 480, and a controller 490. Since the configuration included in each of the plurality of display devices 11, 12, 13, and 14 is substantially the same, the configuration included in the first display device 11 will be mainly described hereinafter for convenience of description, and the description of the configuration included in each of the second display device 12, the third display device 13, and the fourth display device 14 will be omitted.

The broadcast tuner 410 may tune a channel frequency (e.g., a predetermined channel frequency) according to the control of the controller 490 to receive a broadcast signal of a corresponding channel through an antenna. The broadcast tuner 410 may include a channel detection module and a Radio Frequency (RF) demodulation module.

The broadcasting signal demodulated by the broadcasting tuner 410 is processed by the signal processor 420 and output to the display part 430 and the speaker 440. Here, the signal processor 420 may include a demultiplexer 421, a video decoder 422, a video processor 423, an audio decoder 424, and an additional data processor 425.

The demultiplexer 421 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal and additional data are restored by the video decoder 422, audio decoder 424 and additional data processor 425, respectively. In this case, the video decoder 422, the audio decoder 424, and the additional data processor 425 restore the separated video signal, audio signal, and additional data in a decoding format corresponding to the encoding format used to transmit the broadcast signal.

Meanwhile, the decoded video signal is converted into a suitable vertical frequency, resolution, screen aspect ratio, etc. by the video processor 423 according to the output standard of the display part 430, and the decoded audio signal is output to the speaker 440.

The display portion 430 is a device on which an image is displayed, and includes the above-described pixels PX, drivers, and the like.

User input 450 may receive signals transmitted by HOST system HOST. The user input part 450 may be provided so that data on user selection and input of commands related to communication of the other display devices 12, 13, and 14 and data on channel selection and UI menu selection and operation transmitted by the HOST system HOST may be input.

The HDD 460 stores various software programs including Operating System (OS) programs, recorded broadcast programs, videos, pictures, and other data, and may be constituted by a storage medium such as a hard disk or a nonvolatile memory.

The network communicator 470 is used for near field communication with the HOST system HOST and other display devices 12, 13 and 14, and may be implemented to include a capability of mobile communication, data communication, and the like,(/>Is a registered trademark of Bluetooth Sig, inc. Of cox, washington), RF, ethernet, etc.

The network communicator 470 may transmit and receive data to and from a communication network according to a technical standard or a communication method for mobile communication (e.g., global system for mobile communication (GSM), code Division Multiple Access (CDMA), code division multiple access 2000 (CDMA 2000) ^TM ) At least one of a base station, an external terminal, and a server in a wireless communication network established by enhanced voice data optimization or enhanced voice data only (EV-DO), wideband CDMA (WCDMA), high Speed Downlink Packet Access (HSDPA), high speed uplink packet access (HSDPA), long Term Evolution (LTE), long term evolution-advanced (LTE-a), 5G, etc.), transmits and receives a wireless signal.

The network communicator 470 may also transmit and receive wireless signals in a communication network according to a wireless internet technology through an antenna pattern as will be described below. The wireless internet technology may include, for example, wireless LAN (WLAN), wireless fidelity (Wi-Fi), wi-Fi direct, digital Living Network Alliance (DLNA), wireless broadband (WiBro), worldwide Interoperability for Microwave Access (WiMAX), high Speed Downlink Packet Access (HSDPA), high Speed Uplink Packet Access (HSUPA), long Term Evolution (LTE), long term evolution-advanced (LTE-a), etc., and the antenna pattern may transmit and receive data according to at least one wireless internet technology within a range including the internet technology not described above.

The UI generator 480 generates a UI menu for communicating with the HOST system HOST and other display apparatuses 12, 13, and 14, and may be implemented by an algorithm code and an On Screen Display (OSD) IC. The UI menu for communicating with the HOST system HOST and the other display apparatuses 12, 13, and 14 may be a menu for designating a counterpart digital TV with which communication is desired and selecting a desired function.

The controller 490 may be responsible for overall control of the first display device 11 and for communication control of the HOST system HOST with the second to fourth display devices 12 to 14, may store corresponding algorithm codes for control, and may be implemented by a Micro Controller Unit (MCU) to execute the stored algorithm codes.

The controller 490 performs control such that corresponding control commands and data are transmitted to the HOST system HOST and the second to fourth display devices 12 to 14 through the network communicator 470 according to the input and selection of the user input part 450. When control commands (e.g., predetermined control commands) and data are input from the HOST system HOST and the second display device 12 to the fourth display device 14, operations are performed according to the corresponding control commands.

Hereinafter, other embodiments of the display device 10 will be described. In the following embodiments, the same components as those in the above embodiments will be denoted by the same reference numerals, and repetitive description thereof will be omitted or simplified, and differences will be mainly described.

Fig. 34 is a layout diagram illustrating a structure of a first pad and an upper connection wiring of a display device according to one or more other embodiments.

Referring to fig. 34, it is shown that a plurality of first peeling sections cnec_1 may be positioned in the display device 10_1. For example, the plurality of first peeling sections cnec_1 may be arranged in parallel to be spaced apart from each other in the second direction DR 2.

As described above, the physical friction that acts in the process of forming the chamfer surface in the display device manufacturing method has a proportional relationship with the width w3_1 of the first peeled portion cnec_1, and thus, according to one or more of the foregoing embodiments, by making the width w3_1 of the first peeled portion cnec_1 of the display device 10_1 smaller than the width W3 of the first peeled portion CNEc of the display device 10, the physical friction that acts in the process of forming the chamfer surface in the display device manufacturing method can be reduced or minimized.

However, in general, when the width of the wiring is narrowed, the resistance value acting on the wiring increases, and thus the flow of current may be interrupted. In other words, when one first peeling section cnec_1 is positioned, the flow of current may be interrupted due to an increase in resistance value due to a decrease in the width w3_1 of the first peeling section cnec_1.

Accordingly, the plurality of first peeling sections cnec_1 may be positioned such that the resistance value of each of the first peeling sections cnec_1 may be reduced, while physical friction that acts in a process of forming a chamfer surface in a manufacturing method of a display device may also be reduced or minimized. The above structure may also be applied to the second PAD2.

Fig. 35 is a layout diagram showing the structure of a first pad and upper connection wirings of a display device according to still another embodiment or embodiments.

Referring to fig. 35, it is shown that the first peeling section cnec_2 may be formed in a net shape in the display device 10_2. For example, the first peeling section cnec_2 of the display device 10_2 may include a vertical peeling section cnec_2a extending in the first direction DR1 and a horizontal peeling section cnec_2b extending in the second direction DR 2.

As described above, the physical friction that acts in the process of forming the chamfer surface in the display device manufacturing method has a proportional relationship with the width w3_2 of the first peeling portion cnec_2, and therefore, by making the width w3_2 of the first peeling portion cnec_2 smaller than the width W3 of the first peeling portion cnec_2, the physical friction that acts in the process of forming the chamfer surface in the display device manufacturing method can be reduced or minimized, and at the same time, the resistance value of the first peeling portion cnec_2 can also be reduced by forming the first peeling portion cnec_2 into a mesh shape. The above structure may also be applied to the second PAD2.

In some embodiments, the width of the vertical peeling section cnec_2a and the width of the horizontal peeling section cnec_2b may be substantially the same, but the disclosure is not limited thereto. For example, the horizontal peeling section cnec_2b may have a larger width than the vertical peeling section cnec_2a.

Referring to fig. 36, it is shown that the display device 10_3 may have a shape in which the width of the first peeling section cnec_3 decreases in a direction toward the first chamfer surface 100d1 (i.e., toward one side of the first direction DR 1). For example, the first peeling section cnec_3 of the display device 10_3 may have substantially the same width as the width W2 of the first contact section CNEb at a portion contacting the first contact section CNEb, and may have a reduced width or a minimum width at a portion adjacent to the first chamfer surface 100d 1.

Accordingly, the resistance value of the first peeling section cnec_3 may be reduced due to the area of the first peeling section cnec_3 being secured, while physical friction, which acts in the process of forming the chamfer surface in the display device manufacturing method, may also be reduced or minimized due to the first peeling section cnec_3 having a reduced width or a minimum width in the portion adjacent to the first chamfer surface 100d 1. The above structure may also be applied to the second PAD2.

Accordingly, the display device according to one or more embodiments may improve device reliability. Further, the display device manufacturing method according to one or more embodiments may provide a display device having improved device reliability.

In summarizing the detailed description, those skilled in the art will understand that many variations and modifications may be made to the embodiments without substantially departing from aspects of the disclosure. Accordingly, the disclosed embodiments are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, the display device comprising:

a substrate comprising a first surface, a second surface opposite the first surface, a first chamfer surface extending from a side of the first surface, a second chamfer surface extending from a side of the second surface, and a first side surface between the first chamfer surface and the second chamfer surface;

a first pad on the first surface of the substrate; and

an upper connection wiring electrically connected to the first pad between the substrate and the first pad on the first surface of the substrate, and the upper connection wiring includes: a first contact portion electrically connected to the first pad; and a first peeling portion extending from the first contact portion in a direction toward the first chamfer surface and having a width smaller than a width of the first contact portion.

2. The display device according to claim 1, wherein the first peeling portion extends toward a boundary between the first surface and the first chamfer surface.

3. The display device according to claim 1, further comprising: a flip-chip type micro light emitting diode element on the first surface of the substrate.

4. The display device according to claim 2, further comprising:

a second pad on the second surface; and

and a side wiring on the first surface, the first chamfer surface, the first side surface, the second chamfer surface, and the second surface, and configured to electrically connect the first pad and the second pad.

5. The display device according to claim 4, wherein the second pad includes a first portion overlapping the side wiring and a second portion spaced apart from the first portion and not overlapping the side wiring,

wherein the first portion of the second pad comprises: a second contact portion in contact with the side wiring; and a second peeling portion extending from the second contact portion in a direction toward the second chamfer surface and having a width smaller than a width of the second contact portion.

6. A tiled display device, the tiled display device comprising:

a plurality of display devices; and

a joint portion between the plurality of display devices,

wherein a first display device among the plurality of display devices includes:

a substrate comprising a first surface, a second surface opposite the first surface, a first chamfer surface extending from one side of the first surface, a second chamfer surface extending from one side of the second surface, and a first side surface connecting the first chamfer surface and the second chamfer surface;

a light emitting element on the first surface;

a first pad on the first surface and spaced apart from the light emitting element; and

an upper connection wiring, on the first surface, between the substrate and the first pad, configured to electrically connect the first pad and the light emitting element, and including a first contact portion electrically connected to the first pad and a first peeling portion extending from the first contact portion in a direction toward the first chamfer surface and having a width smaller than a width of the first contact portion.

7. The tiled display device of claim 6, wherein the substrate comprises glass.

8. The tiled display arrangement of claim 6, wherein the first display arrangement further comprises: and a side wiring on the first surface, the second surface, and the first side surface of the substrate and connected to the first pad.

9. A method of manufacturing a display device, the method comprising:

preparing a mother substrate in which scribe lines defining a plurality of cell regions are defined;

forming upper connection wiring patterns on upper surfaces of the plurality of unit regions;

forming a first pad on the upper connection wiring pattern, and the first pad being electrically connected to the upper connection wiring pattern;

scribing one of the plurality of cell regions from the mother substrate to obtain a cell substrate; and

a chamfer surface is formed by processing the edges of the unit substrates,

wherein the upper connection wiring pattern includes a first contact portion electrically connected to the first pad and a first peeling portion pattern extending from the first contact portion in a direction toward the scribe line and having a width smaller than a width of the first contact portion.

10. The method of manufacturing a display device according to claim 9, wherein the step of forming the chamfer surface comprises: a first lift-off pattern is formed at an end of the first lift-off portion pattern by processing the end of the first lift-off portion pattern.