KR20230115183A - Display device and manufacturing method of the same - Google Patents

Abstract

Provided is a display device with improved device reliability. According to an embodiment of the present invention, the display device includes: a substrate including at least a first surface, a second surface facing the first surface, a first chamfered surface extended from one side of the first surface, a second chamfered surface extended from one side of the second surface, and a first side connecting the first chamfered surface and the second chamfered surface; a first pad arranged on the first surface of the substrate; an upper via layer arranged on the first surface of the substrate and arranged to be separated from the first pad; and an upper protection layer covering the upper via layer. The upper protection layer includes a first exposure opening exposing one side facing the first pad of the upper via layer.

Description

Display device and manufacturing method thereof {DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME}

The present invention relates to a display device and a method for manufacturing the display device.

Electronic devices such as smart phones, tablet PCs, digital cameras, notebook computers, navigation devices, and smart televisions that provide images to users include display devices for displaying images.

The display device includes a display area capable of expressing various colors while being operated in units of pixels or sub-pixels and a bezel area in which wires for driving pixels or sub-pixels are disposed.

Recently, there is an increasing demand for bezel-less technology that reduces or eliminates the bezel area to maximize the display area in display devices. Research and development are continuously progressing.

An object to be solved by the present invention is to provide a display device with improved device reliability.

Another problem to be solved by the present invention is to provide a method of manufacturing a display device having improved device reliability.

The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment for solving the above problems includes at least a first surface, a second surface opposite to the first surface, a first chamfered surface extending from one side of the first surface, and the second surface. A substrate including a second chamfered surface extending from one side of the and a first side surface connecting the first chamfered surface and the second chamfered surface; a first pad disposed on the first surface of the substrate; an upper via layer disposed on the first surface of the substrate and spaced apart from the first pad; and an upper passivation layer covering the upper via layer, wherein the upper passivation layer may include a first exposure opening exposing one side of the upper via layer facing the first pad.

A display device according to another embodiment for solving the above problems is a substrate including at least a display area in which a plurality of pixels are disposed, a pad area disposed on one side of the display area, and an inclined area disposed on one side of the pad area. ; a protective layer covering the display area and the pad area of the substrate; a via layer disposed between the substrate and the passivation layer in the display area; a pad disposed between the substrate and the passivation layer in the pad area, wherein the passivation layer includes: a first exposure opening disposed near a boundary with the pad area in the display area to expose the via layer; and a second exposure opening disposed in the pad area to expose the pad.

A method of manufacturing a display device according to an exemplary embodiment to solve the above problems includes at least a first pad, a via layer spaced apart from the first pad, a first surface on which an insulating layer covering the via layer is disposed, and a second pad A second surface facing the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and the first chamfered surface and preparing a substrate including a first side surface connecting the second chamfered surface; forming an exposure opening in the insulating layer to expose one side of the via layer facing the pad; a side wiring material layer electrically connecting the first pad and the second pad on the first surface, the second surface, the first chamfered surface, the second chamfered surface, and the first side surface of the substrate; forming; Forming a side wiring by irradiating a laser to the side wiring material layer, wherein the first pad may be disposed closer to the first chamfered surface than the via layer.

A tile-type display device according to an exemplary embodiment for solving the above problems includes at least a plurality of display devices and a joint disposed between the plurality of display devices, and includes a first display device among the plurality of display devices. A first surface, a second surface opposite to the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and the a substrate including a first side surface connecting a first chamfered surface and the second chamfered surface; an upper via layer disposed on the first side of the substrate; a first pad disposed on the first surface of the substrate and spaced apart from the upper via layer; light emitting elements disposed on the upper via layer; and an upper passivation layer covering the upper via layer, wherein the upper passivation layer may include a first exposure opening exposing one side of the upper via layer facing the first pad.

Reliability of the display device according to an exemplary embodiment may be improved.

A display device manufacturing method according to an exemplary embodiment may provide a display device having improved device reliability.

Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in this specification.

1 is a perspective view illustrating a front surface of a display device according to an exemplary embodiment.
2 is a perspective view illustrating a rear surface of a display device according to an exemplary embodiment.
3 is a diagram schematically illustrating a structure of a pixel of a display device according to an exemplary embodiment.
4 is a diagram schematically illustrating a structure of a pixel of a display device according to another exemplary embodiment.
5 is a structural diagram schematically illustrating another example of a cross-sectional structure of a pixel according to an exemplary embodiment.
6 is a perspective view illustrating an arrangement relationship between pixels and side wires of a display device according to an exemplary embodiment.
7 is a plan view illustrating a disposition relationship between pixels and side wires of a display device according to an exemplary embodiment.
8 is a rear view illustrating a disposition relationship between side wires and the driving unit of a display device according to an exemplary embodiment.
9 is a cross-sectional view showing a cross section taken along line X1-X1′ of FIG. 8 .
FIG. 10 is a plan view illustrating a profile of an upper protective layer covering the entire surface of the substrate of FIG. 9 .
11 to 16 are diagrams for explaining a method of manufacturing a display device according to an exemplary embodiment.
17 is a diagram schematically illustrating a tile type display using a display device according to an exemplary embodiment.
FIG. 18 is an enlarged view of region A of FIG. 17 .
19 is a cross-sectional view showing a cross section taken along the line X2-X2′ of FIG. 18;
20 is a block diagram showing a structure of a display device according to an exemplary embodiment.
21 is a diagram illustrating a state in which a tile type display using a display device according to an exemplary embodiment is driven.
22 is a structural diagram schematically illustrating a structure of a display device according to another exemplary embodiment.
23 is a plan view illustrating a profile of an upper passivation layer covering a front surface of a substrate of a display device according to another exemplary embodiment.
FIG. 24 is a diagram illustrating a via layer exposed by an exposure opening according to the embodiment of FIG. 23 .
FIG. 25 is a diagram illustrating a via layer covered by a shielding pattern according to the embodiment of FIG. 23 .
26 is a structural diagram schematically illustrating a structure of a display device according to another exemplary embodiment.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or another element is interposed therebetween. Likewise, those referred to as "lower", "left", and "right" include all cases in which other elements are interposed immediately adjacent to or interposed with other elements or other elements in the middle. Like reference numbers designate like elements throughout the specification.

Although first, second, etc. are used to describe various components, these components are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first element mentioned below may also be the second element within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

1 is a perspective view illustrating a front surface of a display device according to an exemplary embodiment. 2 is a perspective view illustrating a rear surface of a display device according to an exemplary embodiment.

In FIG. 1 , a first direction DR1 , a second direction DR2 , and a third direction DR3 are defined. The first direction DR1 and the second direction DR2 are perpendicular to each other, the first direction DR1 and the third direction DR3 are perpendicular to each other, and the second and third directions DR2 and DR3 are may be perpendicular to each other. The first direction DR1 means the vertical direction in the drawing, the second direction DR2 means the horizontal direction in the drawing, and the third direction DR3 means the upper and lower directions in the drawing, that is, the thickness direction. can be understood as In the following specification, unless otherwise specified, "direction" may refer to both directions extending along the direction toward both sides. In addition, when it is necessary to distinguish both “directions” extending to both sides, one side is referred to as “one direction” and the other side is referred to as “the other side of the direction”. Referring to FIG. 1 , a direction indicated by an arrow is referred to as one side, and an opposite direction is referred to as the other side.

Hereinafter, for convenience of explanation, in referring to the display device 10 or surfaces of each member constituting the display device 10, one surface facing the direction in which an image is displayed, that is, one side in the third direction DR3, is referred to. is referred to as an upper surface, and the other surface opposite to the one surface is referred to as a bottom surface. However, it is not limited thereto, and the one surface and the other surface of the member may be referred to as the front and rear surfaces, respectively, or may be referred to as the first surface or the second surface. Also, in describing the relative position of each member of the display device 10 , one side in the third direction DR3 may be referred to as an upper portion and the other side in the third direction DR3 may be referred to as a lower portion.

Referring to FIGS. 1 and 2 , a display device 10 according to an exemplary embodiment includes a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, and an electronic notebook. It can be applied to portable electronic devices such as books, portable multimedia players (PMPs), navigations, and ultra mobile PCs (UMPCs). Alternatively, the display device 10 according to an embodiment may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an internet of things (IOT).

The display device 10 may have a flat shape similar to a rectangle. For example, as shown in FIG. 1 , the display device 10 may have a planar shape similar to a rectangle having a short side in the first direction DR1 and a long side in the second direction DR2 . A corner where the short side of the first direction DR1 and the long side of the second direction DR2 meet may be rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display device 10 is not limited to a quadrangular shape, and may be similarly formed to other polygonal, circular or elliptical shapes.

The display device 10 includes a display area DA on which a screen is displayed on one side (hereinafter referred to as 'upper surface') of the third direction DR3, and an area other than the display area DA where the screen is not displayed. A non-display area NDA may be included. In detail, the non-display area NDA includes a portion of the top surface of the display device 10, both sides of the display device 10 in the second direction DR2 (hereinafter referred to as 'sides'), both sides of the display device 10 in the first direction DR1, It may be disposed on the other side surface (hereinafter referred to as 'bottom surface') of the third direction DR3, but is not limited thereto. In some embodiments, the non-display area NDA may be disposed to surround the edge of the display area DA, but is not limited thereto. Meanwhile, the display area DA and the non-display area NDA of the display device 10 may also be applied to the substrate 100 to be described later.

A display device 10 according to an exemplary embodiment includes a substrate 100, a plurality of pixels PX, a plurality of side wires 200, and a driving unit, wherein the driving unit includes a circuit board CB and a display driving circuit (DC). ) may be included.

The substrate 100 may serve as a base of the display device 10 . In some embodiments, the substrate 100 may include glass as a rigid substrate having rigidity, but is not limited thereto. For example, the substrate 100 may include polyimide as a flexible substrate having flexibility. Hereinafter, for convenience of description, the substrate 100 will be mainly described as including glass as a rigid substrate.

The substrate 100 may have a three-dimensional shape similar to a rectangular parallelepiped, and may have a shape in which corners formed by the top and side surfaces of the rectangular parallelepiped and corners formed by the bottom and side surfaces of the rectangular parallelepiped are bent. In other words, the substrate 100 may have a three-dimensional shape similar to a rectangular parallelepiped, and may have a shape in which edges of the top and bottom surfaces are bent. 1 and 2 illustrate that chamfered surfaces are formed on both sides of the upper and lower surfaces of the substrate 100 in the first direction DR1 and in the second direction DR2, respectively. In some embodiments, the substrate 100 has curved corners, that is, chamfered surfaces may be formed on both sides of the top and bottom surfaces of the substrate 100 in the first direction DR1 and in the second direction DR2, respectively. , but is not limited thereto. For example, the chamfered surface may be formed on only one side of the top and bottom surfaces of the substrate 100 in the first direction DR1 . Hereinafter, for convenience of description, the chamfered surfaces formed on both sides of the upper and lower surfaces of the substrate 100 in the first direction DR1 and in the second direction DR2 will be mainly described.

The substrate 100 may include a first surface 100a, a second surface 100b, a plurality of chamfered surfaces, and a plurality of side surfaces.

The first surface 100a may be an upper surface of the substrate 100 . The first surface 100a may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2 .

The second surface 100b may be a surface facing the first surface 100a in the third direction DR3. The second surface 100b may be a bottom surface of the substrate 100 . The second surface 100b may have a rectangular shape having a cross section in the first direction DR1 and a long side in the second direction DR2.

The plurality of side surfaces are surfaces disposed between the first surface 100a and the second surface 100b, and may be both side surfaces of the substrate 100 in the first direction DR1 and both sides in the second direction DR2. For convenience of description, a side surface disposed on one side of the first direction DR1 among the plurality of side surfaces is referred to as a 'first side surface 100c', and a side surface disposed on one side in the second direction DR2 is referred to as a 'second side surface'. ', the side surface disposed on the other side in the first direction DR1 is referred to as a 'third side surface', and the side surface disposed on the other side in the second direction DR2 is referred to as a 'fourth side surface'.

The plurality of chamfered surfaces are formed between the first surface 100a and the plurality of side surfaces and between the second surface 100b and the plurality of side surfaces in order to prevent chipping defects from occurring in the plurality of side wires 200. It refers to the sides that are placed between the fields and cut obliquely. Due to the plurality of chamfered surfaces, since the bending angle of each of the plurality of side wires 200 can be gentle, chipping or cracking of the plurality of side wires 200 can be prevented from occurring. can For convenience of description, a chamfered surface disposed between the first surface 100a and the first side surface 100c among the plurality of chamfered surfaces is referred to as a 'first chamfered surface 100d1', and the second surface 100b and the chamfered surface disposed between the first side surface 100c is referred to as 'second chamfered surface 100d2', and the chamfered surface disposed between the first surface 100a and the second side surface is referred to as 'third chamfered surface'. ', and the chamfered surface disposed between the second surface 100b and the second side surface is referred to as a 'fourth chamfered surface', and the chamfered surface disposed between the first surface 100a and the third side surface. is referred to as a 'fifth chamfered surface', and a chamfered surface disposed between the second surface 100b and the third side surface is referred to as a 'sixth chamfered surface', and the first surface 100a and the fourth side surface are referred to as The chamfering surface disposed therebetween is referred to as a 'seventh chamfering surface', and the chamfering surface disposed between the second surface 100b and the fourth side surface is referred to as an 'eighth chamfering surface'.

Specifically, the first chamfered surface 100d1 extends from one side of the first surface 100a in the first direction DR1, and the second chamfered surface 100d2 extends from one side of the second surface 100b in the first direction DR1. Extending from one side, the first side surface 100c may connect the first chamfered surface 100d1 and the second chamfered surface 100d2. The third chamfered surface extends from one side of the first surface 100a in the second direction DR2, and the fourth chamfered surface extends from one side of the second surface 100b in the second direction DR2. The second side surface may connect the third chamfered surface and the fourth chamfered surface. The fifth chamfered surface extends from the other side of the first surface 100a in the first direction DR1, and the sixth chamfered surface extends from the other side of the second surface 100b in the first direction DR1. The third side surface may connect the fifth chamfered surface and the sixth chamfered surface. The seventh chamfered surface extends from the other side of the first surface 100a in the second direction DR2, and the eighth chamfered surface extends from the other side of the second surface 100b in the second direction DR2. The fourth side surface may connect the seventh chamfered surface and the eighth chamfered surface.

A plurality of pixels PX may be disposed on the first surface 100a of the substrate 100 to display an image. The plurality of pixels PX may be arranged in a matrix form in the first and second directions DR1 and DR2 . A detailed description of the structure of the plurality of pixels PX will be described later.

Each of the plurality of side wires 200 includes a first pad PAD1 (see FIG. 7) disposed on the first surface 100a and a second pad PAD2 (see FIG. 8) disposed on the second surface 100b. serves to connect The first pads PAD1 may be connected to data lines connected to the plurality of pixels PX disposed on the first surface 100a of the substrate 100 . The plurality of side wires 200 may be arranged spaced apart from each other in the second direction DR2 .

The plurality of side wires 200 may be disposed on the first surface 100a, the second surface 100b, at least two chamfered surfaces among the plurality of chamfered surfaces, and at least one side surface among the plurality of side surfaces. can For example, as shown in FIGS. 1 and 2 , the plurality of side wires 200 include a first pad PAD1 disposed on one side of the first surface 100a of the substrate 100 in the first direction DR1. In order to connect the first and second pads PAD2 disposed on one side of the first direction DR1 of the second surface 100b, the first chamfered surface 100d1 of the first surface 100a and the second surface 100b is formed. , may be disposed on the second chamfered surface 100d2 and the first side surface 100c. A detailed description of the shape of each of the plurality of side wires 200 will be described later.

In some embodiments, the plurality of side wires 200 may be disposed on only one side of the substrate 100 in the first direction DR1 , but is not limited thereto. For example, the plurality of side wires 200 may be disposed on the other side of the substrate 100 in the first direction DR1 , one side in the second direction DR2 , or the other side in the second direction DR2 . In this case, the first pads PAD1 disposed on the first surface 100a of the substrate 100 are additionally added to the other side in the first direction DR1, one side in the second direction DR2, or the other side in the second direction DR2. The second pads PAD2 disposed on the second surface 100b of the substrate 100 may be disposed on the other side of the first direction DR1, one side of the second direction DR2, or the other side of the second direction DR2. can be placed additionally. Hereinafter, for convenience of description, the plurality of side wires 200 will be mainly described as being disposed on only one side of the substrate 100 in the first direction DR1 .

The circuit boards CB may be disposed on the second surface 100b of the substrate 100 . Each of the circuit boards CB is connected to third pads PAD3 (PAD3, see FIG. 8) disposed on the second surface 100b of the substrate 100 using a conductive adhesive member such as an anisotropic conductive film. can As will be described later, since the third pads PAD3 are electrically connected to the second pads PAD2 , the circuit board CB can be electrically connected to the first pads PAD1 through the side wires 200 . there is. The circuit boards CB may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

The display driving circuit DC generates data voltages to connect the circuit board CB, the third pads PAD3, the second pads PAD2, the plurality of side wires 200, and the first pads PAD1. A data voltage may be supplied to the data lines extending from the pixels PX through the pixel PX. The display driving circuit DC may be formed as an integrated circuit (IC) and attached to the circuit board CB. Alternatively, the display driving circuit DC may be directly attached to the second surface 100b of the substrate 100 in a COG (chip on glass) method.

As described above, by using the plurality of side wires 200 to connect the first pads PAD1 disposed on the first surface 100a and the second pads PAD2 disposed on the second surface 100b, Since the flexible film bent along the side surface of the substrate 100 can be omitted, a bezel-less display device 10 with a minimized non-display area NDA can be implemented.

Hereinafter, the structure of the pixel PX of the display device 10 according to an exemplary embodiment will be described.

3 is a diagram schematically illustrating a structure of a pixel of a display device according to an exemplary embodiment. 4 is a diagram schematically illustrating a structure of a pixel of a display device according to another exemplary embodiment. 5 is a structural diagram schematically illustrating another example of a cross-sectional structure of a pixel according to an exemplary embodiment.

Referring to FIGS. 3 and 4 , each of the pixels PX may include a plurality of sub-pixels. 3 and 4, each of the pixels PX includes three sub-pixels SPX1, SPX2, and SPX3, that is, a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. Although it has been exemplified to include, the number of sub-pixels is not limited thereto. Each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may be connected to any one data line among the data lines and at least one scan line among the scan lines.

Each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may have a rectangular, square, or rhombus planar shape. For example, as shown in FIG. 3 , each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 has a long side of the first direction DR1 and a long side of the second direction DR2 . ) may have a rectangular planar shape having a short side. Alternatively, as shown in FIG. 3 , each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 has the same length in the first and second directions DR1 and DR2 . It may have a square or rhombic planar shape including .

The first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may be arranged in the second direction DR2 . Alternatively, one of the second sub-pixel SPX2 and the third sub-pixel SPX3 and the first sub-pixel SPX1 are arranged in the second direction DR2, and the second sub-pixel SPX2 and the third sub-pixel SPX2 and the third sub-pixel SPX1 are arranged in the second direction DR2. The other one of (SPX3) and the first sub-pixel SPX1 may be arranged in the first direction DR1. For example, as shown in FIG. 4 , the first sub-pixel SPX1 and the second sub-pixel SPX2 are arranged in the first direction DR1, and the first sub-pixel SPX1 and the third sub-pixel ( SPX3) may be arranged in the second direction DR2.

The first sub-pixel SPX1 emits first light, the second sub-pixel SPX2 emits second light, and the third sub-pixel SPX3 emits third light. In this case, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength range of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength range of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength range of approximately 370 nm to 460 nm, but embodiments of the present specification are not limited thereto. don't

Each of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element LE (refer to FIG. 5 ) emitting light. there is. For example, the inorganic light emitting device may be a flip chip type micro LED (Light Emitting Diode), but is not limited thereto.

As shown in FIGS. 3 and 4 , the area of the first sub-pixel SPX1 , the area of the second sub-pixel SPX2 , and the area of the third sub-pixel SPX3 may be substantially the same, but are limited thereto. It is not. For example, the area of the first sub-pixel SPX1 , the area of the second sub-pixel SPX2 , and the area of the third sub-pixel SPX3 may be different from each other.

Referring to FIG. 5 , each of the plurality of sub-pixels SPX1 , SPX2 , and SPX3 constituting the pixel PX may include a plurality of conductive layers, a plurality of insulating layers, and a plurality of light emitting elements LE. The plurality of conductive layers and the plurality of insulating layers may form a transistor layer that transmits an electrical signal to the light emitting element LE.

A plurality of sub-pixels disposed on the substrate 100 include an active layer ACT, a first gate metal layer GTL1, a second gate metal layer GTL2, a first data metal layer DTL1 as the plurality of conductive layers, It includes two data metal layers DTL2, a third data metal layer DTL3, a fourth data metal layer DTL4, and a fifth data metal layer DTL5. In addition, the plurality of pixels PX includes a buffer layer BF, a gate insulating layer 110, a first interlayer insulating layer 130, a second interlayer insulating layer 150, and an upper via layer as the plurality of insulating layers, The upper via layer includes a first via layer 160 , a second via layer 170 , a third via layer 180 and a fourth via layer 190 .

The substrate 100 serves to form a base of the display device 10 and may be a base substrate or a base member for supporting a plurality of pixels PX. As described above, the substrate 100 may be a rigid substrate made of glass.

A buffer layer BF may be disposed on the upper surface of the substrate 100, that is, on the first surface 100a. The buffer layer BF may play a role of preventing air or moisture from penetrating into element layers constituting the pixel PX. The buffer layer BF may be formed of a plurality of inorganic films that are alternately stacked. For example, the buffer layer BF may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. Depending on the embodiment, the buffer layer (BF) may be omitted.

An active layer ACT may be disposed on the buffer layer BF. The active layer ACT may include a silicon semiconductor such as polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, and amorphous silicon, or may include an oxide semiconductor.

The active layer ACT may include a channel region, a first region disposed on one side of the channel region, and a second region disposed on the other side of the channel region. The channel region of the active layer ACT may be a region overlapping a gate electrode GE, which will be described later, in the third direction DR3. Each of the first region and the second region of the active layer ACT may be a region that does not overlap with the gate electrode GE. The first region and the second region may be conductive regions by doping ions into a silicon semiconductor or an oxide semiconductor.

A gate insulating layer 110 may be disposed on the active layer ACT. The gate insulating layer 110 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first gate metal layer GTL1 may be disposed on the gate insulating layer 110 . The first gate metal layer GTL1 may include the gate electrode GE and the first capacitor electrode CAE1 of each sub-pixel. The gate electrode GE may form a thin film transistor for driving the pixel PX together with the active layer ACT. The first gate metal layer GTL1 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A first interlayer insulating layer 130 may be disposed on the first gate metal layer GTL1. The first interlayer insulating layer 130 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A second gate metal layer GTL2 may be disposed on the first interlayer insulating layer 130 . The second gate metal layer GTL2 may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in the third direction DR3 to form the capacitor Cst. The second gate metal layer GTL2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A second interlayer insulating layer 150 may be disposed on the second gate metal layer GTL2 . The second interlayer insulating layer 150 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first data metal layer DTL1 including a first connection electrode CE1 and a data line (not shown) may be disposed on the second interlayer insulating layer 150 . The first data metal layer DTL1 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

The first connection electrode CE1 is the first region or the first region of the active layer ACT through a first contact hole CT1 penetrating the first interlayer insulating layer 130 and the second interlayer insulating layer 150. It can be connected to 2 zones.

On the first data metal layer DTL1, a first via layer for flattening a step caused by the active layer ACT, the first gate metal layer GTL1, the second gate metal layer GTL2, and the first data metal layer DTL1 is formed. 160) may be placed. The first via layer 160 is an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

A second data metal layer DTL2 may be disposed on the first via layer 160 . The second data metal layer DTL2 may include a second connection electrode CE2. The second connection electrode CE2 may be connected to the first connection electrode CE1 through the second contact hole CT2 penetrating the first insulating layer and the first via layer 160 . The second data metal layer DTL2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A second via layer 170 may be disposed on the second data metal layer DTL2 . The second via layer 170 is an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

A third data metal layer DTL3 may be disposed on the second via layer 170 . The third data metal layer DTL3 may include a third connection electrode CE3. The third connection electrode CE3 may be connected to the second connection electrode CE2 through the third contact hole CT3 penetrating the second insulating layer and the second via layer 170 . The third data metal layer DTL3 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A third via layer 180 may be disposed on the third data metal layer DTL3 . The third via layer 180 is an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

A fourth data metal layer DTL4 may be disposed on the third via layer 180 . The fourth data metal layer DTL4 may include an anode pad electrode APD and a cathode pad electrode CPD. The anode pad electrode APD may be connected to the third connection electrode CE3 through the fourth contact hole CT4 penetrating the third insulating layer and the third via layer 180 . The cathode pad electrode CPD may be supplied with the first power supply voltage, which is a low potential voltage. The fourth data metal layer DTL4 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A fifth data metal layer DTL5 may be disposed on each of the anode pad electrode APD and the cathode pad electrode CPD. The fifth data metal layer DTL5 may include a transparent conductive layer to increase adhesion with the first contact electrode CTE1 and the second contact electrode CTE2 of the light emitting element LE. The fifth data metal layer DTL5 may be formed of a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A fourth via layer 190 may be further disposed on the third via layer 180 . The fourth via layer 190 may be disposed in a spaced apart space of each of a plurality of sub-pixels. In other words, the fourth via layer 190 may be partially disposed on the third via layer 180 without being entirely disposed thereon. That is, the fourth via layer 190 may serve as a pixel defining layer that divides sub-pixels. The fourth via layer 190 is an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

An upper passivation layer PVX may be disposed on the third via layer 180 , the fifth data metal layer DTL5 , and the fourth via layer 190 . The upper passivation layer PVX covers edges of the transparent conductive layer TCO disposed on the anode pad electrode APD and the transparent conductive layer TCO disposed on the cathode pad electrode CPD, and includes a fourth via layer ( 190) and the upper surface of the third via layer 180 exposed by the fourth via layer 190 may be covered. The upper passivation layer PVX may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

In the upper passivation layer PVX, a first element contact hole exposing the transparent conductive layer TCO disposed on the anode pad electrode APD and a part of the transparent conductive layer TCO disposed on the cathode pad electrode CPD (CTL1) and the second device contact hole (CTL2) may be formed. The first element contact hole CTL1 exposes a part of the transparent conductive layer TCO disposed on the anode pad electrode APD, and the second element contact hole CTL2 exposes a portion of the transparent conductive layer TCO disposed on the anode pad electrode APD. A part of the transparent conductive layer TCO may be exposed.

Each of the plurality of sub-pixels SPX1 , SPX2 , and SPX3 may include one light emitting element LE. The light emitting elements LE are disposed on the transparent conductive layer (TCO) disposed on the anode pad electrode APD exposed by the first element contact hole CTL1 and the second element contact hole CTL2 formed in the upper passivation layer PVX. ) and the transparent conductive layer TCO disposed on the cathode pad electrode CPD. In FIG. 5 , the light emitting element LE is a flip chip type micro LED in which the first contact electrode CTE1 and the second contact electrode CTE2 are disposed to face the anode pad electrode APD and the cathode pad electrode CPD. exemplified.

The light emitting element LE may be an inorganic light emitting element made of an inorganic material such as GaN. The light emitting element LE may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3, each of several to hundreds of μm. For example, each of the lengths of the light emitting element LE in the first direction DR1 , the second direction DR2 , and the third direction DR3 may be about 100 μm or less.

The light emitting elements LE may be formed by being grown on a semiconductor substrate such as a silicon wafer. Each of the light emitting elements LE may be transferred directly from the silicon wafer onto the anode pad electrode APD and the cathode pad electrode CPD of the substrate 100 . Alternatively, each of the light emitting elements LE is formed on the anode pad electrode of the substrate 100 through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate. (APD) and the cathode pad electrode (CPD).

Each of the light emitting elements LE includes a base substrate PSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2. It may be a light emitting structure that

The base substrate PSUB of the light emitting element LE may be a sapphire substrate, but is not limited thereto.

The n-type semiconductor NSEM of the light emitting element LE may be disposed on one surface of the base substrate PSUB. For example, the n-type semiconductor NSEM may be disposed on the lower surface of the base substrate PSUB. The n-type semiconductor (NSEM) may be made of GaN doped with an n-type conductive dopant such as Si, Ge, or Sn.

The active layer MQW of the light emitting element LE may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single or multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto.

Alternatively, the active layer MQW may have a structure in which semiconductor materials having a high band gap energy and semiconductor materials having a low band cap energy are alternately stacked, and include group 3 to group 5 semiconductor materials according to the wavelength band of emitted light. You may.

The p-type semiconductor PSEM may be disposed on one surface of the active layer MQW. The p-type semiconductor (PSEM) may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Se, or Ba.

The first contact electrode CTE1 may be disposed on the p-type semiconductor PSEM, and the second contact electrode CTE2 may be disposed on the other part of one surface of the n-type semiconductor NSEM. Another part of one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed apart from a part of one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

The first contact electrode CTE1 and the anode pad electrode APD may be adhered to each other through a conductive adhesive such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other through a soldering process.

Hereinafter, the arrangement relationship between the pixel PX and the side wiring 200 and the arrangement relationship between the side wiring 200 and the driver will be described.

6 is a perspective view illustrating an arrangement relationship between pixels and side wires of a display device according to an exemplary embodiment. 7 is a plan view illustrating a disposition relationship between pixels and side wires of a display device according to an exemplary embodiment. 8 is a rear view illustrating a disposition relationship between side wires and the driving unit of a display device according to an exemplary embodiment.

6 to 8 , the display device 10 includes a plurality of first pads PAD1 , a plurality of second pads PAD2 , a plurality of third pads PAD3 , and a plurality of bottom connection wires ( BCL) are further included.

The plurality of first pads PAD1 may serve to transfer the electric signal of the driver to each of the plurality of pixels PX. The first pads PAD1 may be disposed on the first surface 100a of the substrate 100 . The first pads PAD1 may be disposed on one side edge of the first surface 100a of the substrate 100 in the first direction DR1 , that is, in the pad area PDA. The pad area PDA is a part of the non-display area NDA, and may refer to the non-display area NDA disposed at one edge of the display area DA in the first direction DR1. The first pads PAD1 may be arranged in the second direction DR2.

The plurality of second pads PAD2 may serve to transfer electrical signals of the driver to the first pads PAD1 through the side wiring 200 . The second pads PAD2 may be disposed on the second surface 100b of the substrate 100 . The second pads PAD2 may be disposed on one edge of the second surface 100b of the substrate 100 in the first direction DR1 . The second pads PAD2 may be arranged in the second direction DR2.

The plurality of third pads PAD3 may serve to transfer electrical signals generated from the driver to the second pads PAD2 through the bottom connection line BCL. The third pads PAD3 may be disposed on the second surface 100b of the substrate 100 . The third pads PAD3 may be disposed closer to the center of the second surface 100b of the substrate 100 than the second pads PAD2 . Third pads PAD3 may be arranged in the second direction DR2 . Third pads PAD3 may be arranged to correspond to terminals formed in the driving part. In other words, it may be arranged to correspond to the terminals formed on the circuit board CB of the driver. In order to connect more third pads PAD3 to the circuit board CB, the distance between the third pads PAD3 adjacent to each other in the second direction DR2 is increased to the second neighboring pads PAD3 in the second direction DR2. It may be smaller than the spacing between the pads PAD2 .

The plurality of bottom connection wires BCL may serve to connect the second pads PAD2 and the third pads PAD3. Since the interval between the second pads PAD2 adjacent to each other in the first direction DR1 and the interval between the third pads PAD3 adjacent to each other in the first direction DR1 are different, the bottom connection line BCL is formed at least once. can be bent The bottom connection line BCL may be integrally formed with the second pad PAD2 and the third pad PAD3. The second pad PAD2, the third pad PAD3, and the bottom connection line BCL are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), or nickel (Ni). , Neodymium (Nd) and copper (Cu), or may be formed of a single layer or multiple layers made of any one of these alloys.

The side wiring 200 may include a first flat part 210 , a first inclined part 240a , a connection part 230 , a second inclined part 240b and a second flat part 220 .

The first flat portion 210 of the side wiring 200 may be a portion disposed on the first surface 100a of the substrate 100, specifically, the pad area PDA of the first surface 100a. The first flat part 210 is disposed on the first pad PAD1 and may be disposed to completely cover the first pad PAD1. The first flat part 210 may be electrically connected to the first pad PAD1.

The first inclined portion 240a of the side wiring 200 may be disposed on the first chamfered surface 100d1 of the substrate 100 . The first inclined portion 240a may be inclined along the direction in which the first chamfered surface 100d1 is inclined. The first inclined portion 240a may be disposed between the first flat portion 210 and the connection portion 230 .

The connection portion 230 of the side wiring 200 may be a portion disposed on the first side surface 100c of the substrate 100 . The connection part 230 may be disposed between the first inclined part 240a and the second inclined part 240b.

The second inclined portion 240b of the side wiring 200 may be disposed on the second chamfered surface 100d2 of the substrate 100 . The second inclined portion 240b may be inclined along the direction in which the second chamfered surface 100d2 is inclined. The second inclined portion 240b may be disposed between the second flat portion 220 and the connection portion 230 .

The second flat portion 220 of the side wiring 200 may be a portion disposed on the second surface 100b of the substrate 100 . The second flat portion 220 may be disposed on the second pad PAD2 and completely cover the second pad PAD2 . The second flat part 220 may be electrically connected to the second pad PAD2 .

The side wiring 200 may include metal powder including metal particles such as silver (Ag) and copper (Cu) and a polymer such as an acrylic resin or an epoxy resin. The metal powder enables the side wiring 200 to have conductivity, and the polymer may serve as a binder connecting metal particles.

The side wiring 200 may be formed by printing a metal paste containing metal particles, a monomer, and a solution on the substrate 100 using a silicon pad and then sintering the substrate 100 using a laser. can In the sintering process, the metal particles in the side wiring 200 react to form a polymer by heat from a laser, and metal particles adhere to each other and agglomerate to lower specific resistance. A detailed description of the sintering process of the side wiring 200 will be described later.

Hereinafter, the structure of one edge in the first direction DR1 of the display device 10 where the boundary between the display area DA and the pad area PDA is formed, that is, the first pad PAD1 and the second pad PAD2 , the arrangement structure of the third pad PAD3 and the pixel PX will be described.

9 is a cross-sectional view showing a cross section taken along line X1-X1′ of FIG. 8 . FIG. 10 is a plan view illustrating a profile of an upper protective layer covering an upper surface of the substrate of FIG. 9 .

9 and 10 , the first pad PAD1 is disposed adjacent to and spaced apart from the outermost pixel PPX, and the second pad PAD2 is disposed on the second surface 100b of the substrate 100. ) can be placed.

For convenience of description, among a plurality of sub-pixels disposed in the display area DA, a sub-pixel disposed most adjacent to the pad area PDA will be referred to as an 'outermost pixel PPX'. The outermost pixel PPX is a sub-pixel disposed at one edge of the display area DA in the first direction DR1, and a sub-pixel adjacent to the outermost pixel PPX is disposed in the first direction of the outermost pixel PPX. (DR1) is disposed only on the other side, and is not disposed on one side of the first direction DR1 of the outermost pixel PPX. Accordingly, the fourth via layer 190 may not be disposed on one side of the outermost pixel PPX in the first direction DR1 , and the fourth via layer 190 may be disposed on the other side in the first direction DR1 . For convenience of description, the fourth via layer 190 disposed on the other side of the outermost pixel PPX in the first direction DR1 will be referred to as the 'outermost fourth via layer 190'.

Since the configuration of the outermost pixel PPX is the same as that of the sub-pixel described above with reference to FIG. 5 , a description thereof will be omitted.

In the pad area PDA, the first data metal layer DTL1 further includes a first upper pad electrode PD1, the second data metal layer DTL2 further includes a second upper pad electrode PD2, and a third upper pad electrode PD2. The data metal layer DTL3 further includes a third upper pad electrode PD3, the fourth data metal layer DTL4 further includes a fourth upper pad electrode PD4, and the fifth data metal layer DTL5 further includes a fifth upper pad electrode PD4. An upper pad electrode PD5 may be further included.

The first pad PAD1 includes a first upper pad electrode PD1 , a second upper pad electrode PD2 , a third upper pad electrode PD3 , a fourth upper pad electrode PD4 , and a fifth upper pad electrode PD5 . ) may be included. The second upper pad electrode PD2 is disposed on the first upper pad electrode PD1, the third upper pad electrode PD3 is disposed on the second upper pad electrode PD2, and the third upper pad electrode PD3 A fourth upper pad electrode PD4 may be disposed on the upper pad electrode PD4, and a fifth upper pad electrode PD5 may be disposed on the fourth upper pad electrode PD4. The upper surface of the first upper pad electrode PD1 directly contacts the lower surface of the second upper pad electrode PD2, and the upper surface of the second upper pad electrode PD2 directly contacts the lower surface of the third upper pad electrode PD3. The upper surface of the third upper pad electrode PD3 is in direct contact with the lower surface of the fourth upper pad electrode PD4, and the upper surface of the fourth upper pad electrode PD4 is in direct contact with the lower surface of the fifth upper pad electrode PD5. can be directly contacted.

The first upper pad electrode PD1 of the first pad PAD1 may be disposed on the second interlayer insulating layer 150 . The first upper pad electrode PD1 may be electrically connected to the top connection wire CNE disposed on the first interlayer insulating layer 130 through the pad contact hole CTP penetrating the second interlayer insulating layer 150 . can The upper surface connection wire CNE may be electrically connected to the aforementioned data line (not shown).

The bottom connection line BCL may be disposed to extend in the first direction DR1 on the second surface 100b of the substrate 100 . The bottom connection wiring (BCL) is one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or It may be formed as a single layer or multiple layers made of these alloys.

The second pad PAD2 may be disposed on the second surface 100b of the substrate 100 . The second pad PAD2 may be disposed on one side of the bottom connection wire BCL in the first direction DR1, and the third pad PAD3 may be disposed on the other side of the bottom connection wire BCL in the first direction DR1. there is. The second pad PAD2 and the third pad PAD3 may be formed of a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The lower via layer 120 may be disposed on the second surface 100b of the substrate 100 . Specifically, the lower via layer 120 may be disposed on the other side of the bottom connection line BCL in the third direction DR3. The lower via layer 120 may partially cover the second and third pads PAD2 and PAD3, but may expose at least a portion of the second and third pads PAD2 and PAD3. A portion of the second pad PAD2 exposed by the lower via layer 120 directly contacts and is electrically connected to the second flat portion 220 of the side wiring 200, and is A portion of the exposed third pad PAD3 may be electrically connected to the circuit board CB by the conductive adhesive member CAM. The conductive adhesive member (CAM) may be an anisotropic conductive film or an anisotropic conductive paste.

The lower via layer 120 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

The lower passivation layer 140 may cover the lower via layer 120 . Specifically, the lower passivation layer 140 may be disposed on the lower via layer 120 and may not be disposed on the second and third pads PAD2 and PAD3 . In other words, each of the second and third pads PAD2 and PAD3 may include a portion exposed by the lower passivation layer 140 . The lower protective layer 140 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The side wiring 200 is disposed on the first surface 100a, the first chamfered surface 100d1, the first side surface 100c, the second chamfered surface 100d2, and the second surface 100b of the substrate 100. It can be. The side wiring 200 may be disposed on a first pad PAD1 disposed on one edge of the first surface 100a of the substrate 100 in the first direction DR1 and electrically connected to the first pad PAD1. there is. The side wiring 200 may be disposed on the second pad PAD2 disposed on one edge of the second surface 100b of the substrate 100 in the first direction DR1 and connected to the second pad PAD2 . The side wiring 200 may contact the first chamfered surface 100d1 , the first side surface 100c , and the second chamfered surface 100d2 of the substrate 100 .

The overcoat layer OC is disposed on the first surface 100a, the first chamfered surface 100d1, the first side surface 100c, the second chamfered surface 100d2, and the second surface 100b of the substrate 100. It can be. The overcoat layer OC may be disposed to cover the side wiring 200 . The overcoat layer (OC) may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can

Meanwhile, the first via layer 160, the second via layer 170, and the third via layer 180 extending in the first direction DR1 from the display area DA are the display area DA and the pad area ( PDA) may not extend any further near the boundary. In other words, the first via layer 160 , the second via layer 170 , and the third via layer 180 no longer extend adjacent to the outermost pixel PPX, but in the first direction DR1 . Sidewalls 160c, 170c, and 180c may be formed.

Specifically, the first via layer 160 no longer extends in the first direction DR1 near the boundary between the display area DA and the pad area PDA and is closed by the first via sidewall 160c. can The second via layer 170 no longer extends in the first direction DR1 near the boundary between the display area DA and the pad area PDA and may be closed by the second via sidewall 170c. The third via layer 180 no longer extends in the first direction DR1 near the boundary between the display area DA and the pad area PDA and may be closed by the third via sidewall 180c. In other words, a sidewall of the first via layer 160 in the first direction DR1 is referred to as a first via sidewall 160c, and a sidewall of the second via layer 170 in the first direction DR1 is referred to as a second via sidewall 160c. It is referred to as a via sidewall 170c, and a sidewall of one side of the third via layer 180 in the first direction DR1 may be referred to as a third via sidewall 180c.

The upper passivation layer PVX is one side surface of the upper via layer including the first via layer 160 , the second via layer 170 , and the third via layer 180 in the first direction DR1 , that is, the first pad A side surface facing PAD1 may be exposed through the first exposure opening OP1. In other words, the upper passivation layer PVX no longer extends near the boundary between the display area DA and the pad area PDA, and the first via sidewall 160c, the second via sidewall 170c, and the third via sidewall A first exposure opening OP1 exposing 180c may be formed. This may be for discharging emission gas (GAS, see FIG. 20 ) that may be generated in a display device manufacturing method described later. A detailed description of this will be described later.

Specifically, the first exposure opening OP1 of the upper passivation layer PVX is the first via layer 160 exposed by the first via sidewall 160c of the first via layer 160 and the second via layer 170. ), the second via sidewall 170c of the second via layer 170, the upper surface of the second via layer 170 exposed by the third via layer 180, and the third via layer 180 The third via sidewall 180c may be exposed. 9 , the first exposure opening OP1 is formed by the first via sidewall 160c of the first via layer 160, the upper surface of the first via layer 160 exposed by the second via layer 170, and the second via layer 160. The second via sidewall 170c of the via layer 170, the upper surface of the second via layer 170 exposed by the third via layer 180, and the third via sidewall 180c of the third via layer 180 ) was exemplified by exposing all of them.

As shown in FIG. 10 , the first exposure opening OP1 may have a planar shape extending in the second direction DR2, but the planar shape of the first exposure opening OP1 is not limited thereto. 10 illustrates that the first exposure opening OP1 has a planar shape extending side by side in the second direction DR2 corresponding to the arrangement of the plurality of side wires 200 .

The upper passivation layer PVX may form a second exposure opening OP2 exposing one sidewall 190c of the outermost fourth via layer 190 in the first direction DR1 . In other words, the second exposure opening OP2 of the upper passivation layer PVX may expose a side surface adjacent to the first pad PAD1 of the outermost fourth via layer 190 . This may be for discharging emission gas (GAS, see FIG. 20 ) that may be generated in a display device manufacturing method described later. A detailed description of this will be described later.

As shown in FIG. 10 , the second exposure opening OP2 may have a planar shape extending in the second direction DR2, but the planar shape of the second exposure opening OP2 is not limited thereto. 10 illustrates that the second exposure opening OP2 has a planar shape extending side by side in the second direction DR2 corresponding to the arrangement of the plurality of side wires 200 .

The upper passivation layer PVX may form a third exposure opening OP3 exposing a top surface of the fifth upper pad electrode PD5 of the first pad PAD1 . The third exposure opening OP3 may also be referred to as a 'pad opening'. The first flat portion 210 of the side wiring 200 may be electrically connected to the first pad PAD1 through the third exposure opening OP3 .

The side wiring 200 may not directly contact the first via sidewall 160c, the second via sidewall 170c, and the third via sidewall 180c exposed by the first exposure opening OP1. Specifically, the side wiring 200 may cover the first pad PAD1 and directly contact the second interlayer insulating layer 150 in the first direction DR1 separation space between the first pad PAD1 and the upper via layer. can This may be for discharging emission gas (GAS, see FIG. 20 ) that may be generated in a display device manufacturing method described later. A detailed description of this will be described later.

The overcoat layer OC covers the side wiring 200 and directly contacts the first via sidewall 160c, the second via sidewall 170c, and the third via sidewall 180c exposed by the first exposure opening OP1. can do. In some embodiments, the overcoat layer OC may entirely cover the first via sidewall 160c and the second via sidewall 170c and partially cover the third via sidewall 180c, but is not limited thereto. For example, the overcoat layer OC may entirely cover the first via sidewall 160c, the second via sidewall 170c, and the third via sidewall 180c. The overcoat layer OC may be formed after exhaust gas (GAS) is exhausted in a manufacturing process of the display device 10 described below.

With the configuration as described above, the display device 10 according to an exemplary embodiment exhausts the gas (GAS) that may be generated during the manufacturing process through the first exposure opening OP1 or the second exposure opening OP2, so that the bubble does not appear. (bubble) phenomenon may be prevented, and thus device reliability of the display device 10 may be improved.

Hereinafter, a method of manufacturing the display device 10 according to an exemplary embodiment will be described.

11 to 16 are diagrams for explaining a method of manufacturing a display device according to an exemplary embodiment.

Referring to FIG. 11 , in a method of manufacturing a display device 10 according to an exemplary embodiment, a pattern is formed on the front and rear surfaces of a substrate 100 (S100), and an insulating layer (upper passivation layer (PVX)) is etched to Forming an exposed area (S200), transferring the side wiring material layer 200′ (S300), and forming the side wiring 200 by sintering the transferred side wiring material layer 200′ (S400). ) may be included.

First, referring to FIG. 12 , patterns are formed on the front and rear surfaces of the substrate 100 of the display device 10 (S100). The above-described buffer layer (BF), gate insulating layer 110, first interlayer insulating layer 130, second interlayer insulating layer 150, and upper via layer are formed on the entire surface of the substrate 100, that is, the first surface 100a. , upper passivation layer PVX, active layer ACT, first gate metal layer GTL1, second gate metal layer GTL2, first data metal layer DTL1, second data metal layer DTL2, third data metal layer (DTL3), the fourth data metal layer DTL4, and the fifth data metal layer DTL5 are disposed, and the aforementioned second pad PAD2 and lower via layer are disposed on the back surface of the substrate 100, that is, the second surface 100b. 120 , the second pad PAD2 , and the lower passivation layer 140 may be disposed. Since a method of forming patterns on the front and rear surfaces of the substrate 100 of the display device 10 is well known to those skilled in the art, a detailed description thereof will be omitted.

Referring to FIG. 13 , an exposed area is formed by etching the upper passivation layer PVX among the insulating layers formed on the first surface 100a of the display device 10 (S200). The exposure area may have a concept including the aforementioned first exposure opening OP1 , second exposure opening OP2 , and third exposure opening OP3 .

The process of etching the upper passivation layer PVX to form the first exposure opening OP1 , the second exposure opening OP2 , and the third exposure opening OP3 may include, for example, the first exposure opening OP1 of the upper passivation layer PVX. A photoresist is disposed on the remaining areas except for areas corresponding to the exposure opening OP1, the second exposure opening OP2, and the third exposure opening OP3, and an upper protective layer (PVX) is formed using the photoresist as an etch stop film. ) may be performed by etching.

Accordingly, as described above, the first via sidewall 160c, the second via sidewall 170c, and the third via sidewall 180c are exposed by the first exposure opening OP1, and A sidewall of the outermost fourth via layer 190 in the first direction DR1 may be exposed, and a top surface of the first pad PAD1 may be exposed by the third exposure opening OP3 .

Next, referring to FIG. 14 , the side wiring material layer 200′ is transferred to the substrate 100 (S300). The side wiring material layer 200' includes substantially the same material as the side wiring 200, and becomes the side wiring 200 when the side wiring material layer 200' undergoes a sintering process described below.

As described above, the side wiring material layer 200 ′ may be a metal paste containing metal particles, a monomer, and a solution printed on the substrate 100 by a silicon pad.

15 and 16, the transferred side wiring material layer 200' is sintered to form the side wiring 200 (S400). As described above, the metal particles included in the side wiring material layer 200′ may come into close contact with each other and aggregate through the sintering process, thereby lowering specific resistance.

A process of sintering the side wiring material layer 200′ may be performed using a laser (L). When the sintering process is performed using the laser L, heat necessary for sintering the side wiring material layer 200' is provided in a short period of time, so the process time can be shortened. However, as the necessary heat is provided in a short period of time, the upper via layer adjacent to the first pad PAD1 , that is, the first via sidewall 160c of the first via layer 160 and the second via layer 170 Excessive heat may be provided to the via sidewall 170c, the third via sidewall 180c of the third via layer 180, and one sidewall 190c of the outermost fourth via layer 190 in the first direction DR1. there is. Accordingly, the first via sidewall 160c of the first via layer 160, the second via sidewall 170c of the second via layer 170, the third via sidewall 180c of the third via layer 180, and The emission gas GAS may be discharged from the sidewall 190c of one side of the outermost fourth via layer 190 in the first direction DR1 .

If the upper passivation layer PVX does not form the first exposure opening OP1 and the second exposure opening OP2, the first via sidewall 160c of the first via layer 160 and the second via layer ( 170), the third via sidewall 180c of the third via layer 180, and one sidewall 190c of the outermost fourth via layer 190 in the first direction DR1. When covered, the gas (GAS) emitted cannot be exhausted, so the upper passivation layer (PVX), the first via sidewall 160c of the first via layer 160, and the second via sidewall of the second via layer 170 ( 170c), the discharge gas (GAS) is discharged between the third via sidewall 180c of the third via layer 180 and the one side wall 190c of the outermost fourth via layer 190 in the first direction DR1. A space to be collected, that is, a bubble may be formed. When the bubble is formed, reliability of the device is lowered, and thus it is necessary to prevent it.

Therefore, the first via sidewall 160c of the first via layer 160, the second via sidewall 170c of the second via layer 170, and the third via layer 180 are formed in the upper passivation layer PVX. A first exposure opening OP1 exposing the sidewall 180c of three vias and a second exposure opening OP2 exposing one sidewall 190c of the outermost fourth via layer 190 in the first direction DR1 are formed. By doing so, it is possible to prevent the generation of the bubbles by exhausting the gas (GAS) discharged from the sintering process.

Then, a process of forming the light emitting element LE and the overcoat layer OC may be performed to manufacture the display device 10 as shown in FIG. 9 .

Hereinafter, a structure of a tile type display using the display device 10 according to an exemplary embodiment will be described.

17 is a diagram schematically illustrating a tile type display using a display device according to an exemplary embodiment. FIG. 18 is an enlarged view of region A of FIG. 17 . 19 is a cross-sectional view showing a cross section taken along the line X2-X2′ of FIG. 18;

Referring to FIGS. 17 to 21 , the tile type display TD may include a plurality of display devices 10 , a joint part SM, and a front cover 300 . For convenience of description, the display device 10 positioned at the upper left is referred to as the 'first display device 11' according to the relative positional relationship between the plurality of display devices 10 shown in FIG. 17 and the display positioned at the upper right The device 10 is referred to as a 'second display device 12', the display device 10 positioned at the bottom left is referred to as a 'third display device 13', and the display device 10 positioned at the bottom right is referred to as the 'fourth display device 14'. In FIG. 17 , the tile-type display device 10 includes four display devices 10 of a first display device 11 , a second display device 12 , a third display device 13 , and a fourth display device 14 . ), the number of display devices 10 that can be included in the tiled display TD is not limited thereto.

The plurality of display devices 11, 12, 13, and 14 may be arranged in a lattice form. The plurality of display devices 11, 12, 13, and 14 may be arranged in a matrix form in M (M is a positive integer) rows and N (N is a positive integer) columns. In FIG. 17 , the first display device 11 and the second display device 12 are adjacent to each other in the first direction DR1 , and the first display device 11 and the third display device 13 are adjacent to each other in the second direction ( DR2), the third display device 13 and the fourth display device 14 are adjacent to each other in the first direction DR1, and the second display device 12 and the fourth display device 14 are adjacent to each other in the first direction DR1. Although adjacent to each other in the second direction DR2 is illustrated, the arrangement of the plurality of display devices constituting the tile type display TD is not limited thereto. That is, the number and arrangement of display devices in the tile type display TD may be determined according to the size of each of the display device 10 and the tile type display TD and the shape of the tile type display TD. Hereinafter, for convenience of description, the tile-type display TD includes four display devices, and the plurality of display devices 11, 12, 13, and 14 are respectively disposed in two rows and two columns. let it do

The plurality of display devices 11, 12, 13, and 14 constituting the tile-type display TD may have the same size, but are not limited thereto. For example, the plurality of display devices 11, 12, 13, and 14 may have different sizes.

Each of the plurality of display devices 11, 12, 13, and 14 may have a rectangular shape including a long side and a short side. The plurality of display devices 11 , 12 , 13 , and 14 may be disposed with long sides or short sides connected to each other. Some or all of the plurality of display devices 11 , 12 , 13 , and 14 are disposed at the edge of the tile-type display TD and may form one side of the tile-type display TD. At least one display device 10 among the plurality of display devices 11, 12, 13, and 14 may be disposed on at least one corner of the tile-type display TD, and two adjacent display devices 10 of the tile-type display TD may be disposed. feces can form. At least one display device among the plurality of display devices 11, 12, 13, and 14 may be surrounded by other display devices.

Each of the plurality of display devices 11, 12, 13, and 14 may be substantially the same as the display device 10 described in conjunction with FIG. 1 . Therefore, a description of each of the plurality of display devices 11, 12, 13, and 14 is omitted.

The joint SM may include a coupling member or an adhesive member. In this case, the plurality of display devices 11, 12, 13, and 14 may be connected to each other through a coupling member or an adhesive member of the joint SM. The connection portion SM is between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, and between the second display device 12 and the fourth display device 12. It may be disposed between the display devices 14 and between the third display device 13 and the fourth display device 14 .

Referring to FIG. 18 , the joint SM is a tiled display where the first display device 11 , the second display device 12 , the third display device 13 , and the fourth display device 14 are adjacent to each other. In the central region of (TD), it may have a planar shape of a tens, a cross, or a plus sign. The connection portion SM is between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, and between the second display device 12 and the fourth display device 12. It may be disposed between the display devices 14 and between the third display device 13 and the fourth display device 14 .

The first display device 11 has a matrix form in a 'row direction (horizontal direction with reference to FIG. 18)' and a 'column direction (vertical direction with reference to FIG. 18)' crossing the row direction to display images. It may include arrayed first pixels PX1. The second display device 12 may include second pixels PX2 arranged in a matrix form in the row direction and the column direction to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix form in the row direction and the column direction to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix form in the row direction and the column direction to display an image. Since the first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the fourth pixel PX4 are substantially the same as the pixel PX of the display device 10 described above, the first pixel PX1 ), a detailed description of structures of the second pixel PX2 , the third pixel PX3 , and the fourth pixel PX4 will be omitted.

A minimum distance between neighboring first pixels PX1 in the first direction DR1 is defined as a first horizontal separation distance GH1, and a minimum distance between neighboring second pixels PX2 in the first direction DR1. It may be defined as the second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially the same.

A connection portion SM may be disposed between the first pixel PX1 and the second pixel PX2 neighboring in the row direction. The minimum distance G12 between the first pixel PX1 and the second pixel PX2 adjacent in the row direction is the minimum distance GHS1 between the first pixel PX1 and the joint part SM in the row direction. , the minimum distance GHS2 between the second pixel PX2 and the connection part SM in the row direction, and the width GSM1 of the connection part SM in the row direction.

The minimum distance G12, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 between the first and second pixels PX1 and PX2 neighboring in the row direction may be substantially the same. can To this end, the minimum distance GHS1 between the first pixel PX1 and the connection part SM in the row direction is smaller than the first horizontal separation distance GH1, and the connection part SM with the second pixel PX2 in the row direction. The minimum distance GHS2 between the parts SM may be smaller than the second horizontal separation distance GH2. Also, the width GSM1 of the joint part SM in the row direction may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

The minimum distance between neighboring third pixels PX3 in the row direction is defined as a third horizontal separation distance GH3, and the minimum distance between neighboring fourth pixels PX4 in the row direction is a fourth horizontal separation distance ( GH4). The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially the same.

A junction part SM may be disposed between the third pixel PX3 and the fourth pixel PX4 neighboring in the row direction. The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 neighboring in the row direction is the minimum distance GHS3 between the third pixel PX3 and the joint part SM in the row direction. , the minimum distance GHS4 between the fourth pixel PX4 and the joint SM in the row direction, and the width GSM1 of the joint SM in the row direction.

The minimum distance G34, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 between the third and fourth pixels PX3 and PX4 neighboring in the first direction DR1 are substantially can be the same as To this end, the minimum distance GHS3 between the third pixel PX3 and the connection part SM in the row direction is smaller than the third horizontal separation distance GH3, and the connection part SM with the fourth pixel PX4 in the row direction. The minimum distance GHS4 between the parts SM may be smaller than the fourth horizontal separation distance GH4. Also, the width GSM1 of the joint part SM in the row direction may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

The minimum distance between neighboring first pixels PX1 in the column direction is defined as a first vertical separation distance GV1, and the minimum distance between neighboring third pixels PX3 in the column direction is a third vertical separation distance ( GV3) can be defined. The first vertical separation distance GV1 and the third vertical separation distance GV3 may be substantially the same.

A connection portion SM may be disposed between the first pixel PX1 and the third pixel PX3 neighboring in the column direction. The minimum distance G13 between the neighboring first pixel PX1 and the third pixel PX3 in the column direction is equal to the minimum distance GVS1 between the first pixel PX1 and the joint SM in the column direction. , the minimum distance GVS3 between the third pixel PX3 and the joint SM in the column direction, and the width GSM2 of the joint SM in the column direction.

The minimum distance G13, the first vertical separation distance GV1, and the third vertical separation distance GV3 between the first pixel PX1 and the third pixel PX3 adjacent in the column direction may be substantially the same. can To this end, the minimum distance GVS1 between the first pixel PX1 and the connection part SM in the column direction is smaller than the first vertical separation distance GV1 and the connection part SM with the third pixel PX3 in the column direction. The minimum distance GVS3 between the parts SM may be smaller than the third vertical separation distance GV3. Also, the width GSM2 of the joint part SM in the column direction may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

The minimum distance between neighboring second pixels PX2 in the column direction is defined as a second vertical separation distance GV2, and the minimum distance between neighboring fourth pixels PX4 in the column direction is a fourth vertical separation distance ( GV4) can be defined. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially the same.

A connection portion SM may be disposed between the second pixel PX2 and the fourth pixel PX4 neighboring in the column direction. The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 neighboring in the column direction is the minimum distance GVS2 between the second pixel PX2 and the joint SM in the column direction. , the minimum distance GVS4 between the fourth pixel PX4 and the connection part SM in the column direction, and the distance GSM4 of the connection part SM in the column direction.

The minimum distance G24 , the second vertical separation distance GV2 , and the fourth vertical separation distance GV4 between the second and fourth pixels PX2 and PX4 neighboring in the column direction may be substantially the same. can To this end, the minimum distance GVS2 between the second pixel PX2 and the connection part SM in the column direction is smaller than the second vertical separation distance GV2, and the connection part SM with the fourth pixel PX4 in the column direction. The minimum distance GVS4 between the parts SM may be smaller than the fourth vertical separation distance GV4. Also, the width GSM2 of the joint part SM in the column direction may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4 .

In order to prevent the joint SM between the images displayed by the plurality of display devices 11, 12, 13, and 14 from being recognized, as shown in FIG. 18, the pixels of the display devices 10 adjacent to each other ( The minimum distance between the PXs may be substantially the same as the minimum distance between the pixels PXs of each of the display devices 10 .

Referring to FIG. 19 , a plurality of front covers 300 may be disposed above each of the plurality of display devices 11, 12, 13, and 14. For convenience of description, the front cover 300 disposed on the first display device 11 is referred to as a 'first front cover', and the front cover 300 disposed on the second display device 12 is referred to as a 'first front cover'. It is referred to as a 'second front cover', and the front cover 300 disposed on the third display device 13 is referred to as a 'third front cover', and the front cover disposed on the fourth display device 14 ( 300) is referred to as a 'fourth front cover'. The plurality of display devices 11, 12, 13, and 14 and the plurality of front covers 300 corresponding thereto may be adhered to each other through the adhesive member AD. 19 illustrates an arrangement structure of the first display device 11 and the second display device 12 and the first front cover and the second front cover corresponding thereto. The arrangement structure of the third display device 13, the third front cover, the fourth display device 14, and the fourth front cover includes the first display device 11 and the second display device 12 and their corresponding Since the arrangement structure of the first front cover and the second front cover is substantially the same, hereinafter, the first front cover and the second front cover will be mainly described, and the third front cover and the fourth front cover will be described. A detailed description thereof is omitted.

The first front cover may be disposed on the first display device 11 and protrude beyond the substrate 100 of the first display device 11 . Therefore, the distance G100 between the substrate 100 of the first display device 11 and the substrate 100 of the second display device 12 is the distance G300 between the first front cover and the second front cover. ) can be greater than

Each of the plurality of front covers 300 may include a light transmittance control layer 310 and an anti-glare layer 320 .

As described above, each of the plurality of front covers 300 may be adhered to the corresponding display device 10 by the adhesive member AD. The adhesive member AD may be a transparent adhesive member capable of transmitting light. For example, the adhesive member AD may be an optically clear adhesive film or an optically clear resin.

A light transmittance adjusting layer 310 may be disposed on the adhesive member AD. The light transmittance control layer 310 may be designed to reduce transmittance of external light or light reflected from the first display device 11 and the second display device 12 . Also, since the front cover 300 protrudes more than the substrate 100 as described above, the light transmittance adjusting layer 310 included in the front cover 300 may also protrude more than the substrate 100 . Accordingly, it is possible to prevent the gap G100 between the substrate 100 of the first display device 11 and the substrate 100 of the second display device 12 from being visually recognized from the outside.

An anti-glare layer 320 may be disposed on the light transmittance adjusting layer 310 . The anti-glare layer 320 may be designed to diffusely reflect external light to prevent deterioration in visibility of an image by reflecting external light as it is. Accordingly, the contrast ratio of images displayed by the first display device 11 and the second display device 12 may be increased due to the anti-glare layer 320 .

The anti-glare layer 320 may be implemented as a polarizer, and the light transmittance control layer 310 may be implemented as a phase retardation layer, but the embodiments of the present specification are not limited thereto.

Hereinafter, a driving method of the tile type display TD according to an exemplary embodiment will be described.

20 is a block diagram showing the structure of a tiled display according to an exemplary embodiment. 21 is a diagram illustrating a state in which a tile type display using a display device according to an exemplary embodiment is driven.

Referring to FIGS. 20 and 21 , the tiled display TD according to an exemplary embodiment includes a broadcast tuning unit 410 included in a host system HOST and a plurality of display devices 11, 12, 13, and 14, respectively. , signal processing unit 420, display unit 430, speaker 440, user input unit 450, HDD 460, network communication unit 470, UI generation unit 480 and control unit 490 may be included. there is. 20 illustrates the host system HOST and the first display device 11 .

The host system (HOST) may be implemented as any one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a mobile phone system, and a tablet.

A user's command may be input to the host system (HOST) in various formats. For example, the host system HOST may receive a command by a user's touch input. Alternatively, a user's command may be input to the host system HOST by inputting a keyboard or a button of a remote controller.

The host system HOST may receive original video data ODATA corresponding to an original video from the outside. The host system HOST may divide the original video data ODATA by the number of display devices 10 . For example, the host system HOST corresponds to the first display device 11 , the second display device 12 , the third display device 13 , and the fourth display device 14 , and the original video data ( ODATA) to the first video data DATA1 corresponding to the first image, the second video data DATA2 corresponding to the second image, the third video data DATA3 corresponding to the third image, and the fourth image. It can be divided into corresponding fourth video data (DATA4). The host system HOST transmits first video data DATA1 to the first display device 11, second video data DATA2 to the second display device 12, and third video data DATA3. ) may be transmitted to the third display device 13 and fourth video data DATA4 may be transmitted to the fourth display device 14 .

The first display device 11 displays a first image according to the first video data DATA1, and the second display device 12 displays a second image according to the second video data DATA2. The display device 13 may display a third image according to the third video data DATA3, and the fourth display device 14 may display a fourth image according to the fourth video data DATA4. Accordingly, the user can view the original image in which the first to fourth images displayed on the first to fourth display devices 10 11 , 12 , 13 , and 14 are combined.

Each of the plurality of display devices 11, 12, 13, and 14 constituting the tile-type display (TD) includes a broadcast tuning unit 410, a signal processing unit 420, a display unit 430, a speaker 440, and a user input unit ( 450), a HDD 460, a network communication unit 470, a UI generator 480, and a control unit 490 may be further included. Since the configurations included in the plurality of display devices 11, 12, 13, and 14 are substantially the same, hereinafter, for convenience of explanation, the configuration included in the first display device 11 will be mainly described, and the second display device 11 will be described. A description of components included in the device 12, the third display device 13, and the fourth display device 14 will be omitted.

The broadcast tuning unit 410 may tune a predetermined channel frequency under the control of the controller 490 to receive a broadcast signal of a corresponding channel through an antenna. The broadcast tuning unit 410 may include a channel detection module and an RF demodulation module.

The broadcast signal demodulated by the broadcast tuning unit 410 is processed by the signal processing unit 420 and output to the display unit 430 and the speaker 440 . Here, the signal processor 420 may include a demultiplexer 421, a video decoder 422, a video processor 423, an audio decoder 424, and an additional data processor 425.

The demultiplexer 421 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by the video decoder 422, the audio decoder 424, and the additional data processor 425, respectively. At this time, the video decoder 422, the audio decoder 424, and the additional data processor 425 restore a decoding format corresponding to the encoding format when transmitting the broadcast signal.

Meanwhile, the decoded video signal is converted by the video processing unit 423 to match the vertical frequency, resolution, aspect ratio, etc. that meet the output standard of the display unit 430, and the decoded audio signal is output to the speaker 440.

The display unit 430 is a device for displaying an image, and includes the aforementioned pixels PX, a driving unit, and the like.

The user input unit 450 may receive a signal transmitted by the host system HOST. The user input unit 450 receives commands related to communication with other display devices (DV2 to DV4) as well as data related to channel selection transmitted by the host system (HOST), UI (User Interface) menu selection and manipulation. It may be prepared so that data for selection and input can be input.

The storage unit 460 stores various software programs including OS programs, recorded broadcast programs, videos, photos, and other data, and may be formed of a storage medium such as a hard disk or non-volatile memory.

The network communication unit 470 is for short-distance communication with the host system (HOST) and other display devices (DV2 to DV4), and is a communication module including an antenna pattern capable of implementing mobile communication, data communication, Bluetooth, RF, Ethernet, etc. can be implemented

The network communication unit 470 implements technical standards or communication methods for mobile communication (eg, Global System for Mobile communication (GSM), Code Division Multi Access (CDMA), Code Division Multi Access (CDMA2000)) through an antenna pattern described later. 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed Downlink Packet Access), HSUPA (High Speed Uplink Packet Access), LTE (Long Term Evolution) , LTE-A (Long Term Evolution-Advanced), 5G, etc.) may transmit and receive radio signals with at least one of a base station, an external terminal, and a server on a mobile communication network.

The network communication unit 470 may transmit and receive radio signals in a communication network according to wireless Internet technologies through an antenna pattern described later. Wireless Internet technologies include, for example, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), WiBro (Wireless Broadband), WiMAX (World Interoperability for Microwave Access), HSDPA (High Speed Downlink Packet Access), HSUPA (High Speed Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc., and the antenna pattern is Data is transmitted and received according to at least one wireless Internet technology within a range including unlisted Internet technologies.

The UI generator 480 creates a UI menu for communication with the host system (HOST) and other display devices (DV2 to DV4), and can be implemented by algorithm codes and OSD ICs. The UI menu for communication with the host system (HOST) and other display devices (DV2 to DV4) may be a menu for specifying a digital TV to be communicated with and selecting a desired function.

The control unit 490 is in charge of overall control of the first display device 11, and is in charge of communication control of the host system HOST and the second to fourth display devices 12, 13, and 14. It can be implemented by a Micro Controller Unit (MCU) in which the corresponding algorithm code is stored and the stored algorithm code is executed.

The control unit 490 transmits corresponding control commands and data to the host system HOST and the second to fourth display devices 12, 13, and 14 through the network communication unit 470 according to input and selection by the user input unit 450. control to transmit. Of course, when a predetermined control command and data are input from the host system HOST and the second to fourth display devices 12, 13, and 14, an operation is performed according to the corresponding control command.

Hereinafter, another embodiment of the display device 10 will be described. In the following embodiments, the same reference numerals refer to components identical to those of the previously described embodiments, and redundant descriptions will be omitted or simplified, and description will focus on differences.

22 is a structural diagram schematically illustrating a structure of a display device according to another exemplary embodiment.

Referring to FIG. 22 , the display device 10_1 according to the present exemplary embodiment illustrates that the upper passivation layer PVX_1 may be partially disposed in the first exposure opening OP1 . For example, the upper passivation layer PVX_1 according to the present embodiment is partially disposed in the first exposure opening OP1 so as to cover the first via sidewall 160c of the first via layer 160 and the second via layer 170. The upper surface of the first via layer 160 exposed by ), the second via sidewall 170c of the second via layer 170, and the second via layer 170 exposed by the third via layer 180 It may cover at least a part of the upper surface and the third via sidewall 180c of the third via layer 180 .

This may be because the upper passivation layer PVX_1 remains unetched in an area corresponding to the first exposure opening OP1 during the above-described display device manufacturing process.

The upper passivation layer PVX_1 is the portion of the first via layer 160 exposed by the first via sidewall 160c of the first via layer 160 and the second via layer 170 in the first exposure opening OP1. The upper surface, the second via sidewall 170c of the second via layer 170, the upper surface of the second via layer 170 exposed by the third via layer 180, and the third via layer 180 At least a portion of the via sidewall 180c is covered, but a portion of the first via sidewall 160c, a portion of the second via sidewall 170c, and a portion of the third via sidewall 180c are still exposed. Emission gas (GAS) that can be generated from can be discharged.

23 is a plan view illustrating a profile of an upper passivation layer covering a front surface of a substrate of a display device according to another exemplary embodiment. FIG. 24 is a diagram illustrating a via layer exposed by an exposure opening according to the embodiment of FIG. 23 . FIG. 25 is a diagram illustrating a via layer covered by a shielding pattern according to the embodiment of FIG. 23 .

23 to 25 illustrate that each of the first and second exposure openings OP1_2 and OP2_2 of the display device 10_2 according to the present embodiment may be formed in plurality and may be spaced apart from each other. . For example, a plurality of first exposure openings OP1_2 are disposed and spaced apart from each other in the second direction DR2 and disposed side by side, and a plurality of second exposure openings OP2_2 are disposed and mutually spaced apart from each other in the second direction DR2. They can be spaced apart and arranged side by side.

In some embodiments, each of the plurality of first exposure openings OP1_2 may have the same area and may be spaced apart at regular intervals, but is not limited thereto. For example, each of the plurality of first exposure openings OP1_2 may have different areas and may be spaced apart from each other at different intervals. Likewise, in some embodiments, each of the plurality of second exposure openings OP2_2 may have the same area and may be spaced apart at regular intervals, but is not limited thereto. For example, each of the plurality of second exposure openings OP2_2 may have different areas and may be spaced apart from each other at different intervals. In FIG. 23 , for convenience of description, it is illustrated that the plurality of first exposure openings OP1_2 and the plurality of second exposure openings OP2_2 have the same area and are spaced apart at equal intervals.

The plurality of first exposure openings OP1_2 may be spaced apart from each other with the first shielding pattern CP1_2 interposed therebetween. The first shielding pattern CP1_2 may serve to define a plurality of first exposure openings OP1_2. Similarly, the plurality of second exposure openings OP2_2 may be spaced apart from each other with the second shielding pattern CP2_2 interposed therebetween. The second shielding pattern CP2_2 may serve to define a plurality of second exposure openings OP2 . As described above, since the first exposure opening OP1 and the second exposure opening OP2 are formed by etching the upper passivation layer PVX, the first shielding pattern CP1_2 is formed by etching the upper passivation layer PVX. It refers to a portion disposed between the plurality of first exposure openings OP1, and the second shielding pattern CP2_2 is between the plurality of second exposure openings OP2 among the unetched portions of the upper passivation layer PVX. It can mean the part placed in . Meanwhile, since the shapes of the first exposure opening OP1 and the first shielding pattern CP1_2 are substantially the same as those of the second exposure opening OP2 and the second shielding pattern CP2_2, hereinafter, the first exposure opening ( OP1) and the first shielding pattern CP1_2 will be mainly described, and a detailed description of the second exposure opening OP2 and the second shielding pattern CP2_2 will be omitted.

As shown in FIG. 24 , the first exposure opening OP1 according to the present embodiment includes the first via exposed by the first via sidewall 160c of the first via layer 160 and the second via layer 170. The top surface of the layer 160, the second via sidewall 170c of the second via layer 170, the top surface of the second via layer 170 exposed by the third via layer 180, and the third via layer ( 180), the entire third via sidewall 180c may be exposed, but is not limited thereto. For example, as described with reference to FIG. 22 , the first via sidewall 160c of the first via layer 160, the upper surface of the first via layer 160 exposed by the second via layer 170, and the second via The second via sidewall 170c of the layer 170, the upper surface of the second via layer 170 exposed by the third via layer 180, and the third via sidewall 180c of the third via layer 180 At least some of them may be exposed.

As shown in FIG. 25 , the first shielding pattern CP1_2 according to the present embodiment includes the first via exposed by the first via sidewall 160c of the first via layer 160 and the second via layer 170 . The top surface of the layer 160, the second via sidewall 170c of the second via layer 170, the top surface of the second via layer 170 exposed by the third via layer 180, and the third via layer ( 180) may entirely cover the third via sidewall 180c, but is not limited thereto. For example, the first via sidewall 160c of the first via layer 160, the upper surface of the first via layer 160 exposed by the second via layer 170, and the second via layer 170 The second via sidewall 170c, the upper surface of the second via layer 170 exposed by the third via layer 180, and at least a portion of the third via sidewall 180c of the third via layer 180 may be covered. there is.

Through the configuration described above, the first shielding pattern CP1_2 is formed between a portion of the upper passivation layer PVX disposed on the pad area PDA and another portion of the upper passivation layer PVX disposed on the display area DA. ) is interposed to partially connect the one portion and the other portion of the upper passivation layer PVX, thereby preserving the structural stability of the upper passivation layer PVX and reducing emission gas (GAS) that may occur in the manufacturing method of the display device. can be ejected.

26 is a structural diagram schematically illustrating a structure of a display device according to another exemplary embodiment.

Referring to FIG. 26 , in the display device 10_3 according to the present exemplary embodiment, one side surface of the lower via layer 120 disposed on the second surface 100b of the substrate 100 in the first direction DR1 protects the lower portion. may be exposed by layer 140 . In other words, the lower passivation layer 140 may form a fourth exposure opening OP4 exposing a portion of the lower via layer 120 adjacent to the second pad PAD2 .

The side wiring 200 may cover the second pad PAD2 , but may not contact one surface of the lower via layer 120 exposed by the fourth exposure opening OP4 in the first direction DR1 . Accordingly, in the process of sintering the side wiring 200, not only can the emission gas (GAS) that can be generated in the upper via layer be released, but also the emission gas (GAS) that can be generated in the lower via layer 120 can be exposed in the fourth exposure. It can be discharged through the opening OP4.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

10: display device
100: substrate
200: side wiring
PVX: top protective layer
OP1: first exposure opening
OP2: second exposure opening

Claims (27)

A first surface, a second surface opposite the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and the first chamfered surface and a substrate including a first side surface connecting the second chamfered surface;
a first pad disposed on the first surface of the substrate;
an upper via layer disposed on the first surface of the substrate and spaced apart from the first pad;
Including an upper protective layer covering the upper via layer,
The upper passivation layer includes a first exposure opening exposing one side of the upper via layer facing the first pad. According to claim 1,
A second pad disposed on the second surface of the substrate, the first surface, the first chamfered surface, the first side surface, and the second chamfered surface disposed on the first pad and the second pad. A display device further including a side wiring electrically connected to the display device. According to claim 2,
Further comprising an interlayer insulating layer disposed between the first pad and the upper via layer and the substrate,
The side wiring is in direct contact with the interlayer insulating layer in a separation space between the first pad and the upper via layer. According to claim 3,
The side wiring is spaced apart from one side of the upper via layer facing the first pad. According to claim 4,
Further comprising an overcoat layer covering the side wiring,
The overcoat layer directly contacts one side of the upper via layer facing the first pad. According to claim 5,
Further comprising a lower via layer disposed on the second pad and a lower protective layer covering the lower via layer,
The second pad is disposed closer to the second chamfer than the lower via layer;
The lower passivation layer includes a lower exposure opening exposing one side adjacent to the second chamfered surface of the lower via layer. According to claim 6,
The side wiring is spaced apart from one side adjacent to the second chamfered surface of the lower via layer. According to claim 7,
The overcoat layer directly contacts one side adjacent to the second chamfered surface of the lower via layer. According to claim 1,
The upper via layer includes a first via layer disposed on the substrate, a second via layer disposed on the first via layer, and a third via layer disposed on the second via layer,
A thin film transistor is disposed between the first via layer and the substrate;
A light emitting element is disposed on the third via layer,
The light emitting element is electrically connected to the thin film transistor. According to claim 9,
One side facing the first pad of the upper via layer exposed by the first exposure opening is opposite to the first pad of the first via layer, and facing the first pad of the second via layer. A display device including at least one of a viewing side and a side facing the first pad of the third via layer. According to claim 10,
The light emitting elements are arranged in plurality and spaced apart from each other,
The upper via layer further includes a plurality of fourth via layers positioned between the plurality of light emitting elements on the third via layer,
The plurality of fourth via layers include an outermost fourth via layer most adjacent to the first pad,
The upper passivation layer includes a second exposure opening exposing one side of the outermost fourth via layer adjacent to the first pad. According to claim 9,
The light emitting element is a flip chip type micro light emitting diode display device. a substrate including a display area in which a plurality of pixels are disposed, a pad area disposed on one side of the display area, and an inclined area disposed on one side of the pad area;
a protective layer covering the display area and the pad area of the substrate;
a via layer disposed between the substrate and the passivation layer in the display area;
Including a pad disposed between the substrate and the passivation layer in the pad region,
The protective layer is:
a first exposure opening disposed near a boundary with the pad area in the display area to expose the via layer; and
and a second exposure opening disposed in the pad area to expose the pad. According to claim 13,
Further comprising a side wiring disposed in the pad region and the slope region,
The side wiring is electrically connected to the pad at the second exposure opening. According to claim 14,
The side wiring is spaced apart from the first exposure opening. According to claim 15,
The side wires are arranged in plurality and spaced apart from each other in a first direction,
The first exposure opening extends in the first direction to correspond to the plurality of side wires. According to claim 16,
The plurality of pixels include an outermost pixel closest to the pad area,
The protective layer further includes a third exposure opening adjacent to the outermost pixel,
The third exposure opening is spaced apart from the first exposure opening with the outermost pixel interposed therebetween. According to claim 15,
The side wires are arranged in plurality and spaced apart from each other in a first direction,
The display device of claim 1 , wherein a plurality of first exposure openings are disposed and spaced apart from each other in the first direction. A first pad and a via layer spaced apart from the first pad, a first surface on which an insulating layer covering the via layer is disposed, a second surface on which a second pad is disposed and facing the first surface, the first surface Preparing a substrate including a first chamfered surface extending from one side of the second chamfered surface, a second chamfered surface extending from one side of the second surface, and a first side surface connecting the first chamfered surface and the second chamfered surface step;
forming an exposure opening in the insulating layer to expose one side of the via layer facing the pad;
a side wiring material layer electrically connecting the first pad and the second pad on the first surface, the second surface, the first chamfered surface, the second chamfered surface, and the first side surface of the substrate; forming; and
Forming a side wiring by irradiating a laser to the side wiring material layer,
The first pad is disposed closer to the first chamfer than the via layer. According to claim 19,
The forming of the side wiring further includes discharging an exhaust gas generated by irradiating the via layer with the laser. According to claim 20,
The exhaust gas is discharged through the exposure opening. a plurality of display devices and a joint disposed between the plurality of display devices;
Among the plurality of display devices, a first display device,
A first surface, a second surface opposite the first surface, a first chamfered surface extending from one side of the first surface, a second chamfered surface extending from one side of the second surface, and the first chamfer a substrate including a first side surface connecting a surface and the second chamfered surface;
an upper via layer disposed on the first side of the substrate;
a first pad disposed on the first surface of the substrate and spaced apart from the upper via layer;
light emitting elements disposed on the upper via layer; and
Including an upper protective layer covering the upper via layer,
The upper passivation layer includes a first exposure opening exposing one side of the upper via layer facing the first pad. 23. The method of claim 22,
Each of the light emitting devices is a flip chip type micro light emitting diode device. 23. The method of claim 22,
The substrate is a tile-type display device made of glass. 23. The method of claim 22,
The first display device,
and a side wiring disposed on the first surface, the second surface, and the first side surface of the substrate and connected to the first pad. According to claim 25,
The first display device,
a bottom connection wiring disposed on the second surface of the substrate; and
Further comprising a flexible film connected to the bottom connection wiring through a conductive adhesive member,
The side wiring is connected to the bottom connection wiring. 23. The method of claim 22,
The plurality of display devices are arranged in a matrix form in M rows and N columns.

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