CN116486860A

CN116486860A - Word line driving circuit, word line driving method, and memory

Info

Publication number: CN116486860A
Application number: CN202210050699.7A
Authority: CN
Inventors: 楚西坤
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-01-17
Filing date: 2022-01-17
Publication date: 2023-07-25

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a word line driving circuit, a word line driving method, and a memory, including: the driving inverter, the input end is used for receiving the word line control signal, the output end is used for outputting the word line driving signal, the word line driving signal is used for driving at least one sub word line driver; the sub word line driver includes a first input terminal, a second input terminal, a third input terminal, and an output terminal; a sub word line driver synchronizing data input from the second input terminal or data input from the third input terminal to the output terminal based on the data input from the first input terminal; the output end of the first control module is connected with the second input end and is configured to pull up the first driving signal based on the first control signal; and the output end of the second control module is connected with the second input end and is configured to pull down the first driving signal based on the first control signal, and the voltage pull-down rate of the first driving signal meets a preset value so as to improve the reliability of the PMOS in the sub word line driving circuit.

Description

Word line driving circuit, word line driving method, and memory

Technical Field

The present disclosure relates to the field of semiconductor circuit design, and more particularly, to a word line driving circuit, a word line driving method, and a memory.

Background

The dynamic random access memory (Dynamic Random Access Memory, DRAM) operates on the principle of using the amount of charge stored in a capacitor to represent whether a binary bit is a 1 or 0, wherein the selection of the capacitor is controlled by a transistor in series with the capacitor, and the selection of the transistor is controlled by a word line and a bit line.

In the driving process of the DRAM word lines, the voltage difference of the gate and the source of the PMOS in the sub word line driving circuit in a waiting state is larger, and the problem of serious PMOS leakage exists, so that the reliability of the sub word line driving circuit is reduced.

How to reduce the leakage current of the sub-word line driving circuit is a technical problem to be solved.

Disclosure of Invention

The embodiment of the disclosure provides a word line driving circuit, a word line driving method and a memory, which reduce leakage current of a sub word line driving circuit when the sub word line driving circuit is in a waiting state so as to improve reliability of the sub word line driving circuit.

The disclosed embodiments provide a word line driving circuit including: the driving inverter, the input end is used for receiving the word line control signal, the output end is used for outputting the word line driving signal, the word line driving signal is used for driving at least one sub word line driver; the sub word line driver comprises a first input end, a second input end, a third input end and an output end, wherein the first input end is used for receiving a word line driving signal, the second input end is used for receiving the first driving signal, the third input end is used for receiving a word line closing voltage, and the output end is used for connecting a word line; the sub word line driver is configured to synchronize data input from the second input terminal or data input from the third input terminal to the output terminal based on the data input from the first input terminal; the output end of the first control module is connected with the second input end and is configured to pull up the first driving signal based on the first control signal; the output end of the second control module is connected with the second input end and is configured to pull down the first driving signal based on the first control signal, and the voltage pull-down rate of the first driving signal meets a preset value; the first control module and the second control module are activated based on different levels of the first control signal.

In the driving stage, the first control module pulls up a first driving signal based on a first control signal, and the word line driving signal controls the sub-word line driver to synchronize data input by the second input end to the word line, namely, the pulled up first driving signal is transmitted to the word line so as to conduct the corresponding word line; in the process of switching from the driving stage to the waiting stage, the word line driving signal controls the sub word line driver to synchronize data input by the third input end to the word line, namely, the word line closing voltage is transmitted to the word line to close the corresponding word line, the second control module pulls down the first driving signal based on the first control signal, at the moment, the word line driving signal received by the first input end of the sub word line driver is at a high level, the first driving signal received by the second input end is at a low level, a voltage difference exists between the first input end and the second input end, and the limitation of the voltage pull-down rate of the first driving signal is carried out through the second control module, so that the first driving signal shows a slow descending trend in the waiting stage, and the average voltage difference between the first input end and the second input end of the sub word line driver is reduced, so that the leakage current of the sub word line driving circuit is reduced, and the reliability of the sub word line driving circuit is improved.

In addition, the preset value of the voltage pull-down rate of the first driving signal is: the voltage pull-down rate is less than 5V/ns.

In addition, the sub word line driver includes: a drive PMOS tube and a first drive NMOS tube; the grid electrode of the first driving NMOS tube is connected with the grid electrode of the driving PMOS tube and is used as a first input end; driving a source electrode of the PMOS tube to serve as a second input end; the drain electrode of the first driving NMOS tube is used as a third input end; the drain electrode of the drive PMOS tube and the source electrode of the first drive NMOS tube are used as output ends; in the waiting stage, a word line driving signal received by a grid electrode of a driving PMOS tube is high level, a first driving signal received by a source electrode is low level, leakage currents of the grid electrode and the source electrode exist in the driving PMOS tube, and the first driving signal is enabled to be in a slow descending trend in the waiting stage through the limitation of a second control module on the voltage pull-down rate of the first driving signal, so that the average voltage difference between the grid electrode and the source electrode of the driving PMOS tube is reduced in the waiting stage, the leakage currents of the driving PMOS tube are reduced, and the reliability of the sub word line driving circuit is improved.

In addition, the word line driving circuit further includes: controlling the inverter and the second driving NMOS tube; the input end of the control inverter is used for receiving a second control signal, and the output end is used for outputting a second driving signal; the drain electrode of the second driving NMOS tube is connected with the drain electrode of the first driving NMOS tube; the grid electrode of the second driving NMOS tube is used for receiving a second driving signal; the source electrode of the second driving NMOS tube is used for connecting a word line; and synchronously pulling down the word line voltage through the second driving MOS transistor so as to improve the pulling-down rate of the word line potential.

In addition, the first control module includes: the first MOS pipe, the second control module includes: a second MOS tube; the drain electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is connected with the second input end, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is used for receiving a first control signal, the source electrode of the first MOS tube is used for receiving word line starting voltage, and the drain electrode of the second MOS tube is grounded; when the second MOS tube is conducted, the voltage pull-down rate of the first driving signal meets a preset value; and by limiting the pull-down rate of the second MOS tube to the first driving signal when the second MOS tube is conducted, the pull-down rate of the second control module to the first driving signal is realized.

In addition, the first control module includes: the first MOS tube and the second control module comprise a second MOS tube and a third MOS tube; the drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube and is connected with the second input end, the drain electrode of the third MOS tube is connected with the source electrode of the second MOS tube, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is used for receiving a first control signal, the source electrode of the first MOS tube is used for receiving a word line starting voltage, the drain electrode of the second MOS tube is grounded, and the grid electrode of the third MOS tube is used for receiving a floating control signal; under the same overdrive voltage, the signal conduction capacity of the third MOS tube is smaller than that of the second MOS tube, and when the second MOS tube and the third MOS tube are conducted together, the voltage pull-down rate of the first drive signal meets a preset value; through the newly-added third MOS tube, the signal conduction capacity of the third MOS tube is smaller than that of the second MOS tube under the same overdrive voltage, when the third MOS tube is conducted, the voltage pull-down rate of the second MOS tube to the first drive signal FXT is delayed, the pull-down rate of the second control module to the first drive signal is realized, and in addition, the voltage difference between the grid electrode and the source electrode of the second NMOS tube is prevented from being too large to be damaged when the first NMOS tube is conducted through the third MOS tube.

In addition, the first MOS tube is PMOS, and the second MOS tube is NMOS.

In addition, the third MOS tube is NMOS.

In addition, the driving inverter includes: a sub-driving PMOS tube and a sub-driving NMOS tube; the source electrode of the sub-driving PMOS tube is used for receiving the first power supply voltage, the drain electrode of the sub-driving NMOS tube is used for receiving the second power supply voltage, the drain electrode of the sub-driving PMOS tube is connected with the source electrode of the sub-driving NMOS tube and used for outputting a word line driving signal, and the grid electrode of the sub-driving PMOS tube is connected with the grid electrode of the sub-driving NMOS tube and used for receiving a word line control signal; one of the first power supply voltage and the second power supply voltage is a high level voltage, and the other is a low level voltage.

In addition, the control inverter includes: a control PMOS tube and a control NMOS tube; the source electrode of the control PMOS tube is used for receiving the third power supply voltage, the drain electrode of the control NMOS tube is used for receiving the fourth power supply voltage, the drain electrode of the control PMOS tube is connected with the source electrode of the control NMOS tube and used for outputting a second driving signal, and the grid electrode of the control PMOS tube is connected with the grid electrode of the control NMOS tube and used for receiving a second control signal; one of the third power supply voltage and the fourth power supply voltage is a high level voltage, and the other is a low level voltage.

The high level voltage is the internal power supply voltage or the word line on voltage of the memory to which the word line driving circuit belongs, and the low level voltage is 0 or the word line off voltage.

In addition, the low level voltage and the high level voltage are supplied from an external voltage.

The embodiment of the disclosure also provides a word line driving method, which is applied to the word line driving circuit, and comprises the following steps: in the driving stage, providing a word line control signal, synchronizing data input by a second input end to an output end, and providing a first control signal to enable a first control module to pull up a first driving signal; and in the waiting stage, stopping providing the word line control signal, synchronizing the data input by the third input end to the output end, and simultaneously providing the first control signal to enable the second control module to pull down the first driving signal, wherein the voltage pull-down rate of the second control module to the first driving signal meets a preset value.

In addition, the word line driving method further includes: in the driving stage, a second control signal is provided to close the second driving MOS tube; in the waiting stage, a second control signal is provided to open the second driving MOS transistor and pull down the word line potential.

The embodiment of the disclosure also provides a memory, and the word line driving circuit is applied to control word lines in the memory.

Drawings

Fig. 1 is a schematic circuit diagram of a word line driving circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a first control module and a second control module according to an embodiment of the disclosure;

fig. 3 is another schematic structural diagram of a first control module and a second control module provided in an embodiment of the disclosure;

fig. 4 is a schematic circuit diagram of a driving inverter according to an embodiment of the disclosure;

fig. 5 is a schematic circuit diagram of a control inverter according to an embodiment of the disclosure;

fig. 6 is a timing diagram of signals in a driving stage and a waiting stage according to another embodiment of the disclosure.

Detailed Description

In the driving process of the DRAM word lines, the voltage difference of the gate and the source of the PMOS in the sub word line driving circuit in a waiting state is larger, and the problem of serious PMOS leakage exists, so that the reliability of the sub word line driving circuit is reduced; how to reduce the leakage current of the sub-word line driving circuit is a technical problem to be solved.

The embodiment of the disclosure provides a word line driving circuit, which reduces leakage current of a sub word line driving circuit when the sub word line driving circuit is in a waiting state so as to improve reliability of the sub word line driving circuit.

Those of ordinary skill in the art will understand that in various embodiments of the present disclosure, numerous technical details are set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic circuit diagram of a word line driving circuit provided in this embodiment, fig. 2 is a schematic circuit diagram of a first control module and a second control module provided in this embodiment, fig. 3 is another schematic circuit diagram of the first control module and the second control module provided in this embodiment, fig. 4 is a schematic circuit diagram of a driving inverter provided in this embodiment, fig. 5 is a schematic circuit diagram of a controlling inverter provided in this embodiment, fig. 6 is a schematic timing diagram of signals in a driving stage and a waiting stage provided in this embodiment, and the word line driving circuit provided in this embodiment is described in further detail with reference to the accompanying drawings, specifically as follows:

referring to fig. 1, a word line driving circuit includes: the driving inverter 101, at least one sub word line driver 102, a first control module 113, a second control module 123, and a control inverter 104.

Inverter 101 is driven with an input for receiving word line control signal MWL, an output for outputting word line drive signal MWLB, and word line drive signal MWLB for driving at least one sub-word line driver 102. I.e., each word line control signal MWL is used to control at least one sub-word line driver 102, and thus a plurality of word lines WL.

For the sub-word line driver 102, the sub-word line driver 102 includes a first input terminal S1 for receiving the word line driving signal MWLB, a second input terminal S2 for receiving the first driving signal FXT, a third input terminal S3 for receiving the word line off voltage V, and an output terminal S _KK The output terminal S is used to connect the word line WL.

The sub word line driver 102 is configured to synchronize data input from the second input terminal S2 or data input from the third input terminal S3 to the output terminal S based on data input from the first input terminal S1.

The output end of the first control module 113 is connected to the source electrode of the driving PMOS tube 132, and is configured to pull up the first driving signal FXT based on the first control signal K1.

The output end of the second control module 123 is connected to the source electrode of the driving PMOS tube 132, and is configured to pull down the first driving signal FXT based on the first control signal K1, and the voltage pull-down rate of the first driving signal FXT meets a preset value, where the first control module 113 and the second control module 123 are started based on different levels of the first control signal K1.

Different levels of the first control signal K1 are used for starting the first control module 113 and the second control module 123; for example, if the first control module 113 is started based on the first control signal K1 at a high level, the second control module 123 is started based on the first control signal K1 at a low level; if the first control module 113 is activated based on the first control signal K1 of the first level, the second control module 123 is activated based on the first control signal K1 of the high level.

In the driving phase, the first control module 113 pulls up the first driving signal FXT based on the first control signal K1, and the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data inputted from the second input terminal S2 to the word line WL, i.e., the pulled up first driving signal FXT is transmitted to the word line WL to turn on the corresponding word line WL; during the transition from the driving phase to the waiting phase, the word line driving signal MWThe LB control sub-word line driver 102 synchronizes the data input from the third input terminal S3 to the word line WL, i.e., the word line off voltage V _KK The first control module 123 pulls down the first driving signal FXT based on the first control signal K1, at this time, the word line driving signal MWLB received by the first input terminal S1 of the sub word line driver 102 is at a high level, the first driving signal FXT received by the second input terminal S2 is at a low level, a voltage difference exists between the first input terminal S1 and the second input terminal S2, and the first driving signal FXT has a slow decreasing trend in a waiting period due to the limitation of the voltage pull-down rate of the first driving signal FXT by the second control module 123, so that an average voltage difference between the first input terminal S1 and the second input terminal S2 of the sub word line driver 102 is reduced in the waiting process, thereby reducing a leakage current of the sub word line driving circuit and improving reliability of the sub word line driving circuit.

In some embodiments, with continued reference to FIG. 1, the sub-word line driver 102 includes: a drive PMOS transistor 132 and a first drive NMOS transistor 112.

The gate of the first driving NMOS transistor 112 is connected to the gate of the driving PMOS transistor, and serves as a first input terminal S1, the source of the driving PMOS transistor 132 serves as a second input terminal S2, the drain of the first driving NMOS transistor serves as a third input terminal S3, and the drain of the driving PMOS transistor 132 and the source of the first driving NMOS transistor 112 serve as output terminals S.

That is, the word line driving signal MWL simultaneously controls and drives the PMOS transistor 132 and the first driving NMOS transistor 112, and when the word line driving signal MWLB is at a high level, the first driving NMOS transistor 112 is turned on, and the word line is turned off by the voltage V _KK To the word line WL, thereby turning off the word line WL; when the word line driving signal MWLB is at a low level, the driving PMOS transistor 132 is turned on, and the first driving signal FXT is transmitted to the word line WL, thereby turning on the word line WL.

It should be noted that, in other embodiments, the driving PMOS transistor may also be an NMOS transistor, and meanwhile, the first NMOS transistor and the second NMOS transistor are PMOS transistors, that is, the high level word line driving signal MWLB is used as the on signal of the bit line WL, and the low level word line driving signal MWLB is used as the on signal of the bit line WL.

In some embodiments, with continued reference to fig. 1, the word line driving circuit further comprises: the inverter 104 and the second driving NMOS transistor 122 are controlled.

The input end of the control inverter 104 is configured to receive the second control signal K2, the output end S is configured to output the second driving signal FXB, the drain electrode of the second driving NMOS transistor 122 is connected to the drain electrode of the first driving NMOS transistor 112, the gate electrode of the second driving NMOS transistor is configured to receive the second driving signal FXB, and the source electrode of the second driving NMOS transistor is configured to be connected to the word line WL.

Turn off word line voltage V _KK During the transfer to the word line WL, the word line is turned off by the voltage V due to the excessively long word line WL _KK The efficiency of transmission to the entire word line WL is too low, so when the first NMOS transistor 112 is turned on, the second NMOS transistor 122 is turned on by the second driving signal FXB, and the word line turn-off voltage V is simultaneously supplied to the word line WL at another place of the word line WL _KK To ensure that the word line WL is turned off and to speed up the turn-off efficiency of the word line WL.

In some embodiments, the preset value of the voltage pull-down rate of the first driving signal is: the voltage pull-down rate is less than 5V/ns, specifically, the rate at which the second control module 123 pulls down the first driving signal FXT based on the first control signal K1 may be 5V/10ns, 5V/50ns, 5V/100ns, 5V/500ns, 3V/10ns, 3V/50ns, 3V/100ns, or 3V/500ns. Since the turn-on voltage of the word line WL is usually 2V-5V, i.e. the first driving signal FXT is 2V-5V when used to drive the word line WL, in order to reduce the gate-source voltage difference of the driving PMOS transistor 132, the pull-down rate of the second control module 123 to the first driving signal FXT is reduced, so as to increase the source voltage of the driving PMOS transistor 132, i.e. reduce the gate-source voltage difference of the driving PMOS transistor 132; in addition, by reducing the pull-down rate of the second control module 123 to the first driving signal FXT to nanosecond level, the gate-source voltage difference of the driving PMOS transistor 132 is effectively reduced, and the normal operation of the memory is not affected.

In some embodiments, referring to fig. 2, the first control module 113 includes a first MOS transistor, and the second control module 123 includes a second MOS transistor, wherein a drain of the first MOS transistor is connected to a source of the second MOS transistor and is connected to the second input terminal S2, a firstThe grid electrode of the MOS tube is connected with the grid electrode of the second MIOS tube and is used for receiving the first control signal K1, and the source electrode of the first MOS tube is used for receiving the word line starting voltage V _PP And when the second MOS tube is conducted, the voltage pull-down rate of the first driving signal FXT meets the preset value.

By limiting the pull-down rate of the first driving signal FXT when the second MOS transistor is turned on, the pull-down rate of the first driving signal FXT by the second control module 123 is realized; in some embodiments, the active region width-to-length ratio of the second MOS tube is reasonably set to limit the pull-down rate of the second MOS tube; in some embodiments, the threshold voltage of the second MOS transistor is increased by increasing the thickness of the gate oxide layer to limit the pull-down rate of the second MOS transistor.

In some embodiments, referring to fig. 3, the first control module 113 includes a first MOS transistor, the second control module 123 includes a second MOS transistor and a third MOS transistor, where a drain of the first MOS transistor is connected to a source of the third MOS transistor and is connected to the second input terminal S2, a drain of the third MOS transistor is connected to a source of the second MOS transistor, a gate of the first MOS transistor is connected to a gate of the second MOS transistor and is configured to receive the first control signal FXT, and a source of the first MOS transistor is configured to receive the word line turn-on voltage V _PP The drain electrode of the second MOS tube is grounded GND, and the grid electrode of the third MOS tube is used for receiving a floating control signal K3; under the same overdrive voltage, the signal conduction capacity of the third MOS tube is smaller than that of the second MOS tube, and when the second MOS tube and the third MOS tube are conducted together, the voltage pull-down rate of the first drive signal FXT meets a preset value.

Through the newly added third MOS tube, under the same overdrive voltage, the signal conduction capacity of the third MOS tube is smaller than that of the second MOS tube, when the third MOS tube is conducted, the voltage pull-down rate of the second MOS tube to the first drive signal FXT is delayed, the pull-down rate of the second control module 123 to the first drive signal FXT is realized, and in addition, when the first NMOS tube is conducted, the damage caused by the overlarge voltage difference between the grid electrode and the source electrode of the second NMOS tube is avoided through the third MOS tube.

In some embodiments, the active region width-to-length ratio of the third MOS transistor is set reasonably to limit the pull-down rate of the third MOS transistor, so as to limit the pull-down rate after the third MOS transistor and the second MOS transistor are connected in series; in some embodiments, the threshold voltage of the second MOS transistor is increased by increasing the thickness of the gate oxide layer to limit the pull-down rate of the second MOS transistor, thereby limiting the pull-down rate of the third MOS transistor after the third MOS transistor and the second MOS transistor are connected in series.

For the circuits of the first control module 113 and the second control module 123 shown in fig. 2 and 3, in some examples, the signal conduction capability of the first MOS transistor is the same as the signal conduction capability of the second MOS transistor; because the voltage pull-up capability of the PMOS transistor is strong, the voltage pull-down capability of the NMOS transistor is strong, in this embodiment, the first MOS transistor is PMOS, and the second MOS transistor is NMOS, so that the pull-up/pull-down rates of the first control module 113 and the second control module 123 in the driving stage are enhanced; in other embodiments, the first MOS transistor may also be an NMOS transistor, and the second MOS transistor may also be a PMOS transistor.

Further, for the circuit shown in fig. 3, when the third MOS transistor and the second MOS transistor are the same type of MOS transistor, the control on the pull-up/pull-down rate of the second control module 123 is facilitated, and when the MOS transistors are set to be the same type of MOS transistor, the layout of the MOS transistor may be set in the same active region, so that the layout area of the second control module 123 is reduced, that is, in this embodiment, the third MOS transistor is an NMOS; in other embodiments, the third MOS transistor may be a PMOS as well; in addition, in some embodiments, the type of the third MOS transistor may also be different from the type of the second MOS transistor, that is, one of the second MOS transistor and the third MOS transistor is NMOS, and the other is PMOS.

In some embodiments, referring to fig. 4, driving inverter 101 includes: a sub-driving PMOS transistor 111 and a sub-driving NMOS transistor 121. The gate of the sub-driving PMOS transistor 111 is connected to the gate of the sub-driving NMOS transistor 121, and is configured to receive the word line control signal MWL, the drain of the sub-driving PMOS transistor 111 is connected to the source of the sub-driving NMOS transistor 121, and is configured to output the word line driving signal MWLB, the source of the sub-driving PMOS transistor 111 is configured to receive the first power voltage, the drain of the sub-driving NMOS transistor is configured to receive the second power voltage, and one of the first power voltage and the second power voltage is a high level voltage, and the other is a low level voltage.

In some embodiments, referring to fig. 5, controlling inverter 104 includes: a control PMOS transistor 114 and a control NMOS transistor 124. The source electrode of the control PMOS transistor 114 is configured to receive the third power supply voltage, the drain electrode of the control NMOS transistor 124 is configured to receive the fourth power supply voltage, the drain electrode of the control PMOS transistor 114 is connected to the source electrode of the control NMOS transistor 124, and is configured to output the second driving signal, and the gate electrode of the control PMOS transistor 114 is connected to the gate electrode of the control NMOS transistor 124, and is configured to receive the second control signal K2; one of the third power supply voltage and the fourth power supply voltage is a high level voltage, and the other is a low level voltage.

For the circuits of fig. 4 and 5, in some embodiments, the sub-driving PMOS transistor 111 may also be NMOS, and correspondingly, the sub-driving NMOS transistor 121 may also be PMOS; in some embodiments, the control PMOS 114 may also be NMOS, and correspondingly, the control NMOS 124 may also be PMOS.

In one example, the high level voltage is the internal supply voltage V of the memory of the word line driving circuit 101 _DD Or word line turn-on voltage V _PP The low level voltage is 0 or the word line closing voltage V _KK 。

It should be noted that, since the high level in the inverter 104 is only used to control the on/off of the second driving NMOS tube 122, the potential of the word line WL is not affected, and the internal power supply voltage V of the memory is used by the word line driving circuit 101 _DD As a high-level voltage in the control inverter 104, the overall power consumption of the word line driving circuit can be reduced.

In one example, the low level voltage and the high level voltage are provided by external voltages.

In the driving phase, the first control module 113 pulls up the first driving signal FXT based on the first control signal K1, and the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data inputted from the second input terminal S2 to the word line WL, i.e., the pulled up first driving signal FXT is transmitted to the word line WL to turn on the corresponding word line WL; during the transition from the driving phase to the waiting phase, the word line driving signal MWLB controls the sub-word line driver 102 to input the data at the third input terminal S3Step to word line WL, i.e. word line off voltage V _KK The first control module 123 pulls down the first driving signal FXT based on the first control signal K1, at this time, the word line driving signal MWLB received by the first input terminal S1 of the sub word line driver 102 is at a high level, the first driving signal FXT received by the second input terminal S2 is at a low level, a voltage difference exists between the first input terminal S1 and the second input terminal S2, and the first driving signal FXT has a slow decreasing trend in a waiting period due to the limitation of the voltage pull-down rate of the first driving signal FXT by the second control module 123, so that an average voltage difference between the first input terminal S1 and the second input terminal S2 of the sub word line driver 102 is reduced in the waiting process, thereby reducing a leakage current of the sub word line driving circuit and improving reliability of the sub word line driving circuit.

Each unit referred to in this embodiment is a logic unit, and in practical application, one logic unit may be one physical unit, or may be a part of one physical unit, or may be implemented by a combination of multiple physical units. Furthermore, in order to highlight the innovative part of the present disclosure, elements that are not so close to solving the technical problem presented by the present disclosure are not introduced in the present embodiment, but it does not indicate that other elements are not present in the present embodiment.

It should be noted that the features disclosed in the word line driving circuit provided in the above embodiments may be arbitrarily combined without collision, and a new refresh circuit embodiment may be obtained.

Another embodiment of the present disclosure provides a word line driving method applied to the above word line driving circuit to improve the reliability of PMOS in the sub word line driving circuit.

Fig. 6 is a timing diagram of signals in a driving stage and a waiting stage according to the present embodiment, and the word line driving method according to the present embodiment is described in further detail with reference to the following drawings, specifically:

referring to fig. 6 in combination with fig. 1 to 5, the word line driving method includes:

in the driving phase, the word line control signal MWL is provided to synchronize the data input from the second input terminal S2 to the output terminal S, and the first control signal K1 is provided to enable the first control module 113 to pull up the first driving signal FXT.

In the waiting period, the supply of the word line control signal MWL is stopped, the data input by the third input terminal S3 is synchronized to the output terminal S, and the first control signal K1 is provided to enable the second control module 123 to pull down the first driving signal FXT, and the voltage pull-down rate of the second control module 123 to the first driving signal FXT meets the preset value.

In the driving phase, the first control module 113 pulls up the first driving signal FXT based on the first control signal K1, and the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data inputted from the second input terminal S2 to the word line WL, i.e., the pulled up first driving signal FXT is transmitted to the word line WL to turn on the corresponding word line WL; in the process of switching from the driving stage to the waiting stage, the word line driving signal MWLB controls the sub-word line driver 102 to synchronize the data input by the third input terminal S3 to the word line WL, that is, the word line closing voltage VKK is transmitted to the word line WL to close the corresponding word line WL, and the second control module 123 pulls down the first driving signal FXT based on the first control signal K1, at this time, the word line driving signal MWLB received by the first input terminal S1 of the sub-word line driver 102 is at a high level, the first driving signal FXT received by the second input terminal S2 is at a low level, a voltage difference exists between the first input terminal S1 and the second input terminal S2, and the limitation of the voltage pull-down rate of the first driving signal FXT by the second control module 123 causes the first driving signal FXT to show a slow down trend in the waiting stage, so that the average voltage difference between the first input terminal S1 and the second input terminal S2 of the sub-word line driver 102 is reduced in the waiting stage, thereby reducing the leakage current of the sub-word line driving circuit and improving the reliability of the sub-word line driving circuit.

In some embodiments, the word line driving method further comprises:

in the driving stage, a second control signal K2 is provided to close a second driving MOS tube; in the waiting period, a second control signal K2 is supplied to turn on the second driving MOS transistor while pulling down the word line WL potential.

Still another embodiment of the present disclosure provides a memory, in which the word line driving circuit is used to perform word line control in the memory, and when the sub word line driving circuit is in a standby state, a PMOS gate-source voltage difference of the sub word line driving circuit is reduced, so that a leakage current of a PMOS gate source is reduced, and the reliability of PMOS in the sub word line driving circuit is improved.

In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR2 memory specifications.

In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR3 memory specifications.

In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR4 memory specifications.

In some embodiments, the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip meets DDR5 memory specifications.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A word line driving circuit, comprising:

the driving inverter, the input end is used for receiving the word line control signal, the output end is used for outputting the word line driving signal, the said word line driving signal is used for driving at least one sub word line driver;

the sub word line driver comprises a first input end, a second input end, a third input end and an output end, wherein the first input end is used for receiving the word line driving signal, the second input end is used for receiving the first driving signal, the third input end is used for receiving word line closing voltage, and the output end is used for connecting word lines;

the sub word line driver is configured to synchronize data input from the second input terminal or data input from the third input terminal to the output terminal based on the data input from the first input terminal;

the output end of the first control module is connected with the second input end and is configured to pull up the first driving signal based on a first control signal;

the output end of the second control module is connected with the second input end and is configured to pull down the first driving signal based on the first control signal, and the voltage pull-down rate of the first driving signal meets a preset value;

the first control module and the second control module are activated based on different levels of the first control signal.

2. The word line driving circuit of claim 1, wherein the predetermined value of the voltage pull-down rate of the first driving signal is: the voltage pull-down rate is less than 5V/ns.

3. The word line driving circuit of claim 1, wherein the sub word line driver comprises: a drive PMOS tube and a first drive NMOS tube;

the grid electrode of the first driving NMOS tube is connected with the grid electrode of the driving PMOS tube and is used as the first input end;

the source electrode of the driving PMOS tube is used as the second input end;

the drain electrode of the first driving NMOS tube is used as the third input end;

and the drain electrode of the drive PMOS tube and the source electrode of the first drive NMOS tube are used as the output end.

4. The word line driving circuit of claim 3, further comprising: controlling the inverter and the second driving NMOS tube;

the input end of the control inverter is used for receiving a second control signal, and the output end of the control inverter is used for outputting a second driving signal;

the drain electrode of the second driving NMOS tube is connected with the drain electrode of the first driving NMOS tube;

the grid electrode of the second driving NMOS tube is used for receiving the second driving signal;

and the source electrode of the second driving NMOS tube is used for connecting a word line.

5. The word line driving circuit of claim 1, wherein the first control module comprises: the first MOS pipe, the second control module includes: a second MOS tube;

the drain electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is connected with the second input end, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is used for receiving the first control signal, the source electrode of the first MOS tube is used for receiving word line starting voltage, and the drain electrode of the second MOS tube is grounded; when the second MOS tube is conducted, the voltage pull-down rate of the first driving signal meets the preset value.

6. The word line driving circuit of claim 1, wherein the first control module comprises: the second control module comprises a second MOS tube and a third MOS tube;

the drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube and is connected with the second input end, the drain electrode of the third MOS tube is connected with the source electrode of the second MOS tube, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is used for receiving the first control signal, the source electrode of the first MOS tube is used for receiving word line starting voltage, the drain electrode of the second MOS tube is grounded, and the grid electrode of the third MOS tube is used for receiving floating control signals;

and under the same overdrive voltage, the signal conduction capacity of the third MOS tube is smaller than that of the second MOS tube, and when the second MOS tube and the third MOS tube are jointly conducted, the voltage pull-down rate of the first drive signal meets a preset value.

7. The word line driving circuit of claim 5 or 6, wherein the first MOS transistor is PMOS and the second MOS transistor is NMOS.

8. The word line driving circuit of claim 6, wherein the third MOS transistor is an NMOS.

9. The word line driving circuit of claim 1, wherein the driving inverter comprises: a sub-driving PMOS tube and a sub-driving NMOS tube;

the source electrode of the sub-driving PMOS tube is used for receiving a first power supply voltage, the drain electrode of the sub-driving NMOS tube is used for receiving a second power supply voltage, the drain electrode of the sub-driving PMOS tube is connected with the source electrode of the sub-driving NMOS tube and used for outputting the word line driving signal, and the grid electrode of the sub-driving PMOS tube is connected with the grid electrode of the sub-driving NMOS tube and used for receiving the word line control signal;

one of the first power supply voltage and the second power supply voltage is a high level voltage, and the other is a low level voltage.

10. The word line driving circuit of claim 4, wherein the control inverter comprises: a control PMOS tube and a control NMOS tube;

the source electrode of the control PMOS tube is used for receiving a third power supply voltage, the drain electrode of the control NMOS tube is used for receiving a fourth power supply voltage, the drain electrode of the control PMOS tube is connected with the source electrode of the control NMOS tube and used for outputting the second driving signal, and the grid electrode of the control PMOS tube is connected with the grid electrode of the control NMOS tube and used for receiving the second control signal;

one of the third power supply voltage and the fourth power supply voltage is a high level voltage, and the other is a low level voltage.

11. The word line driving circuit according to claim 9 or 10, wherein the high level voltage is an internal power supply voltage or a word line on voltage of a memory to which the word line driving circuit belongs, and the low level voltage is 0 or the word line off voltage.

12. The word line driving circuit according to claim 9 or 10, wherein the low level voltage and the high level voltage are supplied from an external voltage.

13. A word line driving method applied to the word line driving circuit of any one of claims 1 to 12, comprising:

in the driving stage, providing a word line control signal, synchronizing data input by a second input end to an output end, and providing a first control signal to enable a first control module to pull up a first driving signal;

and in the waiting stage, stopping providing the word line control signal, synchronizing the data input by the third input end to the output end, and simultaneously providing the first control signal to enable the second control module to pull down the first driving signal, wherein the voltage pull-down rate of the second control module to the first driving signal meets a preset value.

14. The word line driving method of claim 13, further comprising:

providing a second control signal to close the second driving MOS tube in the driving stage;

and in the waiting stage, providing a second control signal to open the second driving MOS transistor and pull down the word line potential.

15. A memory, wherein the word line driving circuit according to any one of claims 1 to 12 is used for word line control in the memory.