CN116484406A - Chip response method, target chip and computer readable storage medium - Google Patents

Abstract

The present invention relates to the field of communications technologies, and in particular, to a chip response method, a target chip, and a computer readable storage medium. The method is applied to a target chip and comprises the following steps: receiving a target instruction sent by a host; the target instruction corresponds to a response signal of the target chip in a preset time window; generating a delay signal of the response signal based on the target instruction; and outputting the delay signal as an adjustment response signal of the target instruction. In the embodiment of the invention, the response signal is delayed and then sent to the host, so that the information stolen by the third party device is data with disordered time sequence, the third party device is prevented from being cracked, and the safety of communication data is improved.

Description

Chip response method, target chip and computer readable storage medium

[ field of technology ]

The present invention relates to the field of communications technologies, and in particular, to a chip response method, a target chip, and a computer readable storage medium.

[ background Art ]

In the communication field, there is a communication method between a host and a chip, and a command is usually sent by the host and the chip responds. However, during the data transmission process between the host and the chip, there may be a situation that the third party device steals the communication data, which causes a potential safety hazard of data communication. Therefore, how to avoid the data being stolen and cracked by the third party device is a current urgent problem to be solved.

[ invention ]

In order to solve the above problems, embodiments of the present invention provide a chip response method, a target chip, and a computer readable storage medium, by generating a delay signal of a relative response signal, a signal acquired by a third party device is disordered and interfered to a certain extent, so as to avoid the third party device from stealing communication data between a host and a chip.

In a first aspect, an embodiment of the present invention provides a chip response method, applied to a target chip, including:

receiving a target instruction sent by a host;

generating a corresponding response signal based on the target instruction; the target instruction corresponds to a response signal of the target chip in a preset time window;

generating a delay signal of the response signal based on the target instruction;

and outputting the delay signal as an adjustment response signal of the target instruction.

In one possible implementation, a control unit and an output contact are provided in the target chip, the control unit being connected to the output contact;

the response signal is generated by the control unit;

the delay signal is sent to the host via the output contact.

In one possible implementation, generating the delay signal of the response signal based on the target instruction includes:

and the control unit carries out delay processing on the response signal to obtain the delay signal and outputs the delay signal to the output contact.

In one possible implementation, a delay unit is provided between the control unit and the output contact;

the control unit outputs the response signal to the delay unit;

and the delay unit delays the response signal output by the control unit to obtain the delay signal and outputs the delay signal to the output contact.

In one possible implementation, the method further includes:

the control unit carries out advanced processing on the response signals to obtain corresponding advanced signals;

and the delay unit delays the advance signal output by the control unit to obtain the delay signal and outputs the delay signal to the output contact.

In one possible implementation, the method further includes:

the control unit carries out delay processing on the response signal to obtain a preliminary delay signal;

and the delay unit performs delay processing on the preliminary delay signal output by the control unit to obtain the delay signal and outputs the delay signal to the output contact.

In one possible implementation, the response signal is composed of a high level signal and a low level signal, the advance signal and the preliminary delay signal are composed of the high level signal and/or the low level signal;

and the delay unit delays the high-level signal and/or the low-level signal to obtain the delay signal and outputs the delay signal to the output contact.

In one possible implementation manner, the delay unit delays the high level signal and/or the low level signal to obtain the delayed signal, including:

delaying outputting the high-level signal in a first clock period within the preset time window and/or delaying outputting the low-level signal in a second clock period within the preset time window;

the host outputs a clock signal to the target chip; the clock signal includes a plurality of unit clock cycles, each of the unit clock cycles including a first clock cycle and a second clock cycle.

In one possible implementation manner, the delay unit delays the high level signal and/or the low level signal to obtain the delayed signal, including:

outputting the high-level signal after delaying a first time period in a first clock period in the preset time window and occupying the residual time period of the first clock period; the first duration is less than or equal to half of the first clock cycle;

outputting the low-level signal after the second time period of the high-level signal is continued in the second clock period in the preset time window, and occupying the remaining time period of the second clock period; the second duration is less than or equal to half of the second clock cycle.

In a second aspect, an embodiment of the present invention provides a target chip, including: a processor, a memory, and a computer program, wherein the computer program is stored in the memory, the computer program comprising instructions that, when executed, cause the image forming apparatus to perform the method of any of claims 1-7.

It should be understood that, in the second aspect of the embodiment of the present invention, the technical solutions of the first aspect of the embodiment of the present invention are consistent, and the beneficial effects obtained by each aspect and the corresponding possible implementation manner are similar, and are not repeated.

In the embodiment of the invention, after the target instruction sent by the host is received, the delay signal of the response signal is generated based on the target instruction, and then the delay signal is fed back to the host, so that the acquisition of the third party device is escaped through delay, and the signal acquired by the third party device is disordered or interfered to a certain extent, so that the communication content between the host and the target chip is prevented from being cracked and stolen by the third party device.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flowchart of a chip response method according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a communication system according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a target chip according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a delay signal according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another delay signal according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another delay signal according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another delay signal according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a control module according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of response signal delay according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of another response signal delay according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of another target chip according to an embodiment of the present invention.

[ detailed description ] of the invention

For a better understanding of the technical solutions of the present specification, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.

It should be understood that the described embodiments are only some, but not all, of the embodiments of the present description. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present invention based on the embodiments herein.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Fig. 1 is a flow chart of a chip response method according to an embodiment of the present invention. The method can be applied to a target chip, as shown in fig. 1, and the method comprises the following processing steps:

step 101, receiving a target instruction sent by a host. The target instruction corresponds to a response signal of the target chip within a preset time window. When the host sends the target command to the target chip, the target chip needs to feed back a response signal to the host within a certain time period to answer the target command (i.e. needs to feed back the response signal to the host within a preset time window). Fig. 2 is a schematic structural diagram of a communication system according to an embodiment of the present invention. The communication system includes a host 100 and a chip 200 as shown in fig. 2, the host 100 is provided with a communication port 101, the slave is provided with an interface module 201, a communication link is established between the communication port 101 and the interface module 201, and information transmission can be performed between the host 100 and the chip 200 through the communication link. Specifically, the communication port 101 and the interface module 201 may be electrically connected in contact by a stylus, a contact, or a dome, thereby establishing a communication link. In other embodiments, the communication link may be a contactless communication link, i.e. a wireless communication link, where the communication port 101 and the interface module 201 may include an antenna or coil for transmitting wireless signals. In some possible implementations, the communication link may also be referred to as a data bus. In general, when the host 100 and the chip 200 communicate, bidirectional transmission and reception of information (i.e., duplex communication) are realized by adopting a time-sharing transmission and reception method. The host 100 according to the embodiments of the present application is a device capable of implementing data processing, control, or related operations, and the chip 200 is configured to be mounted on the host 100 to assist the host 100 in performing related functions. The chip 200 includes an SDA channel, which is a channel for transmitting data, through which the host 100 transmits data to the chip 200 and the chip 200 responds to the data to the host 100, and when the host 100 needs to transmit data to the chip 200, the chip 200 needs to release the bus, and at this time, the control right of the bus is in the host 100, the host 100 transmits data to the chip 200, and at this time, the chip 200 is in a signal input state, which may also be referred to as a high impedance state; when the chip 200 responds to the data, the bus is taken over, and at this time, the control right of the bus is in the chip 200 to send the data to the host 100, and at this time, the chip 200 is in a signal output state. When the chip 200 is in the input state with the host 100, the detection device can detect whether other irrelevant signals exist on the bus to interfere with the communication process.

In one example, the host may be a computer and the chip may be a peripheral/device of the computer. In yet another example, the host may be a mobile terminal (e.g., a cell phone, tablet, PDA, etc.), and the chip is an accessory or peripheral device, apparatus, such as a lithium battery chip, a wearable device chip, etc., of the mobile terminal.

In some embodiments, the host may be a printing device, and the target chip may be a consumable chip. The printing equipment is provided with a communication port, the consumable chip is provided with an interface module, a communication link is established between the communication port and the interface module, and the printing equipment and the consumable chip can transmit information through the communication link. For example, during imaging, consumable chips are used to provide identification information and record material usage information. In the prior art, when a printing device sends a signal to a consumable chip, the printing device is a sender, and the consumable chip is a receiver; and when the consumable chip sends a signal to the printing equipment, the consumable chip is a sender, and the printing equipment is a receiver. Fig. 3 is a schematic structural diagram of a target chip according to an embodiment of the present invention. As shown in fig. 3, the target chip 210 includes an interface module 211, a storage module 212, a control module 213, and a processing module 214.

As shown in fig. 3, when the target chip 210 is a consumable chip, it may include an interface module 211, a memory module 212, a control module 213, and a processing module 214. The memory module 212 is used to store information about the consumable chip, such as rewritable or read-only information about the date of manufacture of the consumable chip, the manufacturer, the color of the recording material (e.g., ink, toner), the capacity of the recording material, the remaining or consumed amount of the recording material, the number of printable pages, the number of printed pages, etc. In the present invention, the memory module 212 may be a common nonvolatile memory, such as EPROM, EEPROM, FLASH, ferroelectric memory, phase change memory, etc., or may be a volatile memory plus power supply scheme, such as sram+battery or capacitor, dram+battery or capacitor.

The control module 213 may be a single chip Microcomputer (MCU), a microcontroller, an FPGA, a logic circuit (ASIC), etc., and is configured to control communication between the consumable chip and the printing device, read information from the storage module 212, and store information to the storage module 212. The interface module 211, the memory module 212, the control module 213 and the processing module 214 are integrally disposed in the same circuit, which may be designed as an integrated circuit (ASIC) embodied in the form of a wafer, and the consumable chip includes the wafer and a circuit board carrying the wafer.

Before the host sends the target instruction or the effective data to the target chip, the host needs to perform self-checking, and after the self-checking is completed, the target instruction or the designated information is sent to the target chip, where the target instruction or the designated information may be information that the host detects the performance of the host, for example, whether the host is stuck, whether the host has unstable voltage, or whether short circuit occurs between terminals of the target chip, and the embodiment is not limited specifically. After the target chip receives the target instruction or the specified information, a processing module in the target chip carries out matching verification and analysis processing on the target instruction or the specified information to obtain a corresponding response signal. The response signal may include a first response signal and a second response signal. The first response signal is a response signal for confirming that the correct target instruction or the specified information is received, and is expressed as a high level signal. The second response signal is a signal for representing the self-detection condition of the consumable chip, such as a signal whether the consumable chip is ready for communication or whether the memory can be rewritten normally, a signal that the consumable chip is ready for communication or the memory can be rewritten normally is characterized as normal, and a signal that the consumable chip is not ready for communication or the memory cannot be rewritten normally is characterized as abnormal.

Step 102, generating a delay signal of the response signal based on the target instruction. In some embodiments, the delay signal of the response signal may be generated directly based on the target instruction. Alternatively, the response signal may be generated based on the target instruction, and then the response signal may be subjected to signal processing to obtain the delay signal. For example, the response signal is delayed to obtain a delayed signal.

Step 103, outputting the delay signal as an adjustment response signal of the target instruction.

The host transmits a periodic clock signal SCK, which is alternately and repeatedly low and high, to the target chip through the clock terminal, and typically, the target chip transmits a response signal to the host as a start flag on a rising edge or a falling edge of the clock signal, that is, if the third party device wants to steal information of the communication process, the rising edge or the falling edge of the clock signal is generally used as a start flag of data transmission, so that data collection is started. In each unit clock period, the clock signal has a low level stage and a high level stage, wherein the low level stage is called a first clock stage, and the high level stage is called a second clock stage.

Based on the reasons, the embodiment of the invention causes certain interference to the third party acquisition device by carrying out delay processing on the response signals and feeding back the response signals to the host, thereby avoiding the acquisition and cracking of the communication content. In one specific example, the delayed signal is as shown in fig. 4. The host supplies the power supply voltage VDD of a high level and the reset signal RST of a high level to the target chip, and outputs the alternate clock signal SCK, and periods D1 to D9 represent unit periods in which the clock signal SCK repeats low level and high level in each period, so that the target chip can perform normal data receiving and transmitting operations. The host will first perform a self-test process before sending valid data to the target chip, and then send a target instruction or specified information to the target chip. In the self-detection process of receiving the target instruction or the specified information by the target chip, the target chip sends a low-level signal in a period D1, the target chip sends the low-level signal in a period D2-D7 or the target chip is in a signal input state, the target chip sends a first response signal and a second response signal to the host during the period of changing the clock signal from the low level to the high level D8, and the specific level is that the response signals are sent in a delayed manner, when the clock signal is in the low level, the first response signal of the high level is sent to the host after a time interval, namely, in the first clock stage of the D8, the target chip sends the low-level signal, then sends the high-level signal in the first clock stage for a period of time, and then sends the second response signal of the low-level signal to the host after a time interval.

In another specific example, the delayed signal is as shown in fig. 5. In the self-detection process of receiving the target instruction or the specified information by the target chip, the target chip sends a low-level signal in a period D1, the target chip sends the low-level signal in a period D2-D7 or the target chip is in a signal input state, the target chip sends a first response signal and a second response signal to the host during a period of changing the clock signal from a low level to a high level D8, and the specific level is that the response signals are sent in a delayed manner, when the clock signal is in the low level, the first response signal of the high level is sent to the host after a time interval, namely, in a first clock stage of D8, the target chip sends the low-level signal and then sends the high-level signal, and in a second clock stage of D8, the second response signal of the low-level signal is sent to the host. This embodiment corresponds to that the first response signal of high level is not directly transmitted to the host when the clock signal is a falling edge, but is delayed, and the low level signal is transmitted to the host first at the timing of the falling edge.

In another specific example, the delayed signal is as shown in fig. 6. In the self-detection process of receiving the target instruction or the specified information by the target chip, the target chip sends a low-level signal in a period D1, sends the low-level signal in a period D2-D7 or the target chip is in a signal input state, and sends a first response signal and a second response signal to the host during a period of changing the clock signal from the low level to the high level D8, wherein the specific level is that the target chip sends the first response signal of the high level to the host in a first clock stage of D8, delays for a period of time after the first clock stage is full, namely, continues to send the high-level signal in the first clock stage for a period of time in a second clock stage of D8, and then sends the second response signal of the low-level signal to the host.

In another specific example, the delayed signal is as shown in fig. 7. In the self-detection process of receiving the target instruction or the specified information by the target chip, the target chip sends a low-level signal in a period D1, sends the low-level signal in a period D2-D7 or sends the target chip to be in a signal input state, and sends the first response signal and the second response signal to the host during a period when the clock signal changes from the low level to the high level D8, wherein the specific level is that in the first clock stage of D8, a time interval is delayed, that is, the target chip sends the low-level signal to the host first, then sends the high-level first response signal to the host, and sends the low-level second response signal to the host when the first clock stage is not occupied yet, and in the second clock stage of D8, the low-level second response signal is continued.

In some embodiments, a control unit is specifically provided in the control module 213 shown in fig. 3, and an output contact (e.g., SDA terminal) is specifically provided in the interface module 211. The above-described response signal is generated by the control unit. The delay signal is sent to the host via the output contact.

The target chip itself may delay the response signal, that is, the control end (control module 213) of the target chip outputs a response signal with normal timing, and the middle of the response signal passes through the delay circuit, and finally, the final output section (output contact) of the target chip outputs a delay signal.

In some embodiments, the cracker may crack the signal timing (i.e. front gate data) sent by the control unit by other means, such as directly reading the program in the encrypted MCU by the RF programmer, and monitoring the electromagnetic radiation characteristics of the chip to implement the attack. The cracker can avoid timing disorder by directly stealing the response signal sent by the control end of the target chip.

Based on this, the embodiment of the present invention avoids the above-described problem by causing the control module itself to output a timing-disturbed delay signal. Specifically, the embodiment of the invention provides a structural schematic diagram of a control module. As shown in fig. 8, the control module 213 specifically includes a delay unit 2131 and a control unit 2132. The delay unit 2131 may include a delay circuit (not shown in the drawing) which may be implemented by a gate stage.

The control unit 2132 may delay the response signal to obtain the delay signal, output the delay signal to the output contact, and transmit the delay signal to the host through the output contact. That is, the control unit 2132 itself outputs a delay signal, and the delay unit 2131 does not operate.

In some embodiments, the delay unit is located in particular between the control unit and the output contact. The control unit comprises two signal output channels which are respectively used for outputting a high-level signal and a low-level signal, and the high-level signal and the low-level signal are summarized at the output contact points to form a complete response signal. The control unit outputs the response signal to the delay unit, and the delay unit delays the response signal output by the control unit to obtain a delay signal and outputs the delay signal to the output contact. Or the control unit performs advanced processing on the response signals to obtain corresponding advanced signals. And then the delay unit carries out delay processing on the advance signal output by the control unit to obtain a delay signal and outputs the delay signal to the output contact. Or the control unit firstly delays the response signal to obtain a preliminary delay signal. And then the delay unit delays the preliminary delay signal output by the control unit to obtain a delay signal and outputs the delay signal to the output contact.

Wherein the response signal is composed of a high level signal and a low level signal. The advance signal and the preliminary signal are composed of a high-level signal and/or a low-level signal. The delay unit delays the high level signal and/or the low level signal to obtain a delayed signal and outputs the delayed signal to the output contact.

Specifically, the foregoing may include the following embodiments:

1. the high level signal is delayed and output in the first clock period, and the low level signal with normal time sequence is output in the second clock period. Such as the delay signal timing provided by the embodiments shown in fig. 5 and 7.

2. The high level signal is delayed and output in the first clock period, and the low level signal is delayed and output in the second clock period. Such as the delayed signal timing provided by the embodiment shown in fig. 4.

3. The high level signal of the normal time sequence is output in the first clock period, and the low level signal is output in the second clock period in a delay way. Such as the delayed signal timing provided by the embodiment shown in fig. 6.

In order to ensure that both the delayed high level signal and the low level signal can be recognized by the host, the delayed high level signal may occupy at least more than half of the first clock cycle. Correspondingly, the delayed low level signal may occupy at least more than half of the second clock period. Taking the timing diagram provided in the embodiment shown in fig. 4 as an example, the high level signal is output after the first period is delayed in the first clock period in the preset time window (i.e., the D8 period) and the remaining period of the first clock period is occupied. The first duration is less than or equal to half of the first clock cycle. And outputting a low-level signal after the second time period of the high-level signal is continued in a second clock period in a preset time window (namely, the D8 period) and occupying the remaining time period of the second clock period. The second duration is less than or equal to half of the second clock period.

In the above-described embodiment, the delay unit may perform delay processing on both the high-level signal and the low-level signal. Alternatively, only the high-level signal or only the low-level signal is subjected to delay processing.

As shown in fig. 9, the control unit outputs a high-level signal and a low-level signal at the same time, and the delay unit delays only the low-level signal, so that the signal finally output by the control module is a response signal or a delay signal of a normal time sequence of first high level and then low level. If the control module outputs a response signal, the response signal can be subjected to delay processing to obtain a delay signal. In this embodiment, whether the cracker directly steals data from the front door (i.e., the control unit in the control module) or steals data from the back door (i.e., the output contact of the target chip), the signal with disordered timing is obtained, so that information is prevented from being stolen.

In another embodiment, the control unit may issue the response signal in advance and be delayed by the delay signal. Specifically, the control unit performs advanced processing on the response signal to obtain a corresponding advanced signal. The delay unit carries out delay processing on the advance signal output by the control unit, obtains a delay signal and outputs the delay signal to the output contact. Wherein, since the target chip outputs the normal response signal, the second response signal (i.e., the low level signal) is output within a certain time after the first response signal (i.e., the high level signal) is output. The control unit may transmit the second response signal in advance and delay the second response signal by the delay unit. As shown in fig. 9, the delay unit delays only the low level, the control unit sends out the low level signal in advance and sends out the high level signal normally, and after the delay unit delays the low level signal, the signal finally output by the control module is a response signal or a delay signal with high level and low level.

For example, the control unit should originally issue a high level signal and a low level signal in the D8 period. The control unit may issue a low level signal half a period in advance (i.e., the latter half of the D7 period) and a high level signal half a period later (i.e., the former half of the D8 period). The delay unit delays only the low level signal. Specifically, the delay unit may delay the low level signal by one period, and the signal output by the control module is a response signal of normal timing sequence in which the first half period of the D8 period is high level and the second half period of the D8 period is low level, and then the response signal may be further delayed to obtain a delayed signal.

In some embodiments, the delay unit may delay both the high level signal and the low level signal sent by the control unit. As shown in fig. 10, the control unit may delay the response signal to obtain a preliminary delay signal, and the delay unit delays the preliminary delay signal output from the control unit to obtain a delay signal and outputs the delay signal to the output contact. For example, the control unit firstly delays the high-level signal and the low-level signal by half a period respectively, and then delays the high-level signal and the low-level signal which have been delayed by half a period again by the delay unit, so that the response signal finally output by the control module is delayed by one period altogether.

Or the control unit sends out a high-level signal and a low-level signal in advance, and the delay unit delays the high-level signal and the low-level signal respectively to obtain a response signal or a delay signal with normal time sequence. For example, the control unit should originally issue a low level signal and a high level signal at the time D8, respectively. The control unit may issue a low level signal one cycle in advance (i.e., the first half cycle of D7) and a high level signal half cycle later (i.e., the second half cycle of D7) when actually transmitting. The delay unit delays the low level signal for one half period (namely the latter half period of the D8), delays the high level signal for one half period (namely the first half period of the D8), and finally outputs a response signal with a high level and a low level.

The delay unit is used for respectively delaying the high-level signal and the low-level signal, and the obtained delay signals are output to the output contact, so that the front door data acquired by a cracker is not error information with disordered time sequence, and the communication content between the target chip and the host is prevented from being stolen and cracked.

Fig. 11 is a schematic structural diagram of a target chip according to an embodiment of the present invention, where, as shown in fig. 11, the target chip may include a processor, a memory, and a computer program, where the computer program is stored in the memory, and the computer program includes instructions, when the instructions are executed, cause the target chip to execute the chip response method provided in the embodiments shown in fig. 1 to 10 of the present specification.

As shown in fig. 11, the target chip is in the form of a general purpose computing device. Components of the target chip may include, but are not limited to: one or more processors 1110, a communication interface 1120, and a memory 1130, a communication bus 1140 that connects the various system components, including the memory 1130, the communication interface 1120, and the processor 1110.

Communication bus 1140 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include industry Standard architecture (Industry Standard Architecture; hereinafter ISA) bus, micro channel architecture (Micro Channel Architecture; hereinafter MAC) bus, enhanced ISA bus, video electronics standards Association (Video Electronics Standards Association; hereinafter VESA) local bus, and peripheral component interconnect (Peripheral Component Interconnection; hereinafter PCI) bus.

The target chip typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by the target chip and includes both volatile and nonvolatile media, removable and non-removable media.

The memory 1130 may include computer system readable media in the form of volatile memory, such as random access memory (Random Access Memory; hereinafter: RAM) and/or cache memory. The target chip may further include other removable/non-removable, volatile/nonvolatile computer system storage media. Memory 1130 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the present description.

A program/utility having a set (at least one) of program modules may be stored in the memory 1130, such program modules include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules typically carry out the functions and/or methods of the embodiments described herein.

The processor 1110 executes various functional applications and data processing by running a program stored in the memory 1130, for example, implementing the chip response method provided in the embodiment shown in fig. 1 to 10 of the present specification.

Embodiments of the present specification provide a computer-readable storage medium storing computer instructions that cause a computer to execute the chip response method provided by the embodiments shown in fig. 1 to 10 of the present specification.

Any combination of one or more computer readable media may be utilized as the above-described computer readable storage media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory; EPROM) or flash Memory, an optical fiber, a portable compact disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present specification. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present specification, the meaning of "plurality" means at least two, for example, two, three, etc., unless explicitly defined otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present specification in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present specification.

Depending on the context, the word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection". Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should be noted that the devices according to the embodiments of the present disclosure may include, but are not limited to, a personal Computer (Personal Computer; hereinafter referred to as a PC), a personal digital assistant (Personal Digital Assistant; hereinafter referred to as a PDA), a wireless handheld device, a Tablet Computer (Tablet Computer), a mobile phone, an MP3 display, an MP4 display, and the like.

In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

In addition, each functional unit in each embodiment of the present specification may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a connector, or a network device, etc.) or a Processor (Processor) to perform part of the steps of the methods described in the embodiments of the present specification. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (hereinafter referred to as ROM), a random access Memory (Random Access Memory) and various media capable of storing program codes such as a magnetic disk or an optical disk.

The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims (10)

1. A chip response method, wherein the method is applied to a target chip, and comprises:

receiving a target instruction sent by a host; the target instruction corresponds to a response signal of the target chip in a preset time window;

generating a delay signal of the response signal based on the target instruction;

and outputting the delay signal as an adjustment response signal of the target instruction.

2. The method of claim 1, wherein a control unit and an output contact are provided in the target chip, the control unit being connected to the output contact;

the response signal is generated by the control unit;

the delay signal is sent to the host via the output contact.

3. The method of claim 2, wherein generating the delay signal of the response signal based on the target instruction comprises:

and the control unit carries out delay processing on the response signal to obtain the delay signal and outputs the delay signal to the output contact.

4. Method according to claim 2, characterized in that a delay unit is arranged between the control unit and the output contact;

the control unit outputs the response signal to the delay unit;

and the delay unit delays the response signal output by the control unit to obtain the delay signal and outputs the delay signal to the output contact.

5. The method according to claim 4, wherein the method further comprises:

the control unit carries out advanced processing on the response signals to obtain corresponding advanced signals;

and the delay unit delays the advance signal output by the control unit to obtain the delay signal and outputs the delay signal to the output contact.

6. The method according to claim 4, wherein the method further comprises:

the control unit carries out delay processing on the response signal to obtain a preliminary delay signal;

and the delay unit performs delay processing on the preliminary delay signal output by the control unit to obtain the delay signal and outputs the delay signal to the output contact.

7. The method according to any one of claims 5 or 6, wherein the response signal is constituted by a high level signal and a low level signal, the advance signal and the preliminary delay signal are constituted by the high level signal and/or the low level signal;

and the delay unit delays the high-level signal and/or the low-level signal to obtain the delay signal and outputs the delay signal to the output contact.

8. The method according to claim 7, wherein the delaying unit delays the high level signal and/or the low level signal to obtain the delayed signal, comprising:

delaying outputting the high-level signal in a first clock period within the preset time window and/or delaying outputting the low-level signal in a second clock period within the preset time window;

the host outputs a clock signal to the target chip; the clock signal includes a plurality of unit clock cycles, each of the unit clock cycles including a first clock cycle and a second clock cycle.

9. The method according to claim 8, wherein the delaying unit delays the high level signal and/or the low level signal to obtain the delayed signal, comprising:

outputting the high-level signal after delaying a first time period in a first clock period in the preset time window and occupying the residual time period of the first clock period; the first duration is less than or equal to half of the first clock cycle;

outputting the low-level signal after the second time period of the high-level signal is continued in the second clock period in the preset time window, and occupying the remaining time period of the second clock period; the second duration is less than or equal to half of the second clock cycle.

10. A target chip, comprising: a processor, a memory, and a computer program, wherein the computer program is stored in the memory, the computer program comprising instructions that, when executed, cause the target chip to perform the method of any of claims 1-9.