CN116483762A - Chip with one pin for configuring multiple chip addresses or working modes - Google Patents

Chip with one pin for configuring multiple chip addresses or working modes Download PDF

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Publication number
CN116483762A
CN116483762A CN202210051844.3A CN202210051844A CN116483762A CN 116483762 A CN116483762 A CN 116483762A CN 202210051844 A CN202210051844 A CN 202210051844A CN 116483762 A CN116483762 A CN 116483762A
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Prior art keywords
resistor
configuration
chip
int
pin
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刘桂云
王小康
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Huimang Microelectronics Shenzhen Co ltd
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Huimang Microelectronics Shenzhen Co ltd
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Priority to CN202210051844.3A priority Critical patent/CN116483762A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a chip with a plurality of chip addresses or working modes configured by one pin, which comprises a configuration pin, wherein the configuration pin is used for being externally connected with a configuration resistor, the resistance value of the configuration resistor is provided with a plurality of gears, and different gears correspond to different chip addresses or working modes, and the chip comprises: the current control branch circuit and the current mirror branch circuit are provided with an adjusting resistor, and the output end of the current mirror branch circuit is connected with the configuration pin; a voltage comparison circuit for comparing the voltage drops across the tuning resistor and the configuration resistor; the control circuit is used for combining the comparison results output by the voltage comparison circuit in real time, searching the gear of the configuration resistor by configuring the adjusting resistors of different gears, and further determining the chip address or the working mode according to the gear of the configuration resistor.

Description

Chip with one pin for configuring multiple chip addresses or working modes
Technical Field
The present invention relates to the field of chips, and more particularly, to a chip with a plurality of chip addresses or operation modes configured by one pin.
Background
On i2c or some other system bus, typicallyThe host accesses the target device by a unique device address, and the i2c protocol specifies a 7bit device address-X 3 X 2 X 1 X 0 A 2 A 1 A 0 'wherein' X 3 X 2 X 1 X 0 'device addresses for different types of devices,' A 2 A 1 A 0 'different addresses of the same type of device,' A 2 A 1 A 0 ' from '000' to '111' means that 8 similar devices can be mounted on the bus at most, and the device or the chip is realized by respectively connecting 3 address configuration pins of the device or the chip with power or ground. Some chips are required to be configured into different working modes through chip pins in different application occasions, and when the working modes are more, the chips are difficult to realize by one pin.
The above, whether configuring multiple addresses or multiple modes, is implemented based on multiple configuration pins, not only increasing chip area and packaging cost, but also increasing PCB routing.
Disclosure of Invention
The present invention is directed to solving the above-mentioned problems of the prior art, and provides a chip with a plurality of chip addresses or operation modes configured by one pin.
The technical scheme adopted for solving the technical problems is as follows: a chip with a plurality of chip addresses or working modes is configured by using one pin, the chip comprises a configuration pin, the configuration pin is used for externally connecting one end of a configuration resistor, the other end of the configuration resistor is grounded, the resistance of the configuration resistor is provided with a plurality of gears, and different gears correspond to different chip addresses or working modes, and the chip comprises:
the current mirror circuit comprises a current control branch and a current mirror branch for mirroring current from the current control branch, an adjusting resistor is arranged in the current control branch, and the output end of the current mirror branch is connected with the configuration pin;
the voltage comparison circuit is respectively connected with the configuration pin and the adjusting resistor and is used for comparing the voltage drops of the adjusting resistor and the configuration resistor;
and the control circuit is respectively connected with the adjusting resistor and the voltage comparison circuit and is used for combining comparison results output by the voltage comparison circuit in real time, searching the gear of the configuration resistor by configuring the adjusting resistors with different gears, and further determining a chip address or a working mode according to the gear of the configuration resistor.
Preferably, the chip address or the working mode is M, M is a positive integer, the resistance value of the configuration resistor is provided with M gears, the resistance value of the adjusting resistor is provided with M-1 gears, and the resistance value corresponding to each gear is the resistance value between two adjacent gears of the configuration resistor.
Preferably, the adjustment resistor of any gear is set to be an average value of resistance values of two adjacent gears of the configuration resistor.
Preferably, the resistances of the configuration resistor and the adjusting resistor are increased/decreased with the increase of the gear, the higher resistance of the two resistances of the adjacent gears of the configuration resistor is 1+y times of the lower resistance, the higher resistance of the two resistances of the adjacent gears of the adjusting resistor is 1+y times of the lower resistance, and y is a positive number.
Preferably, the value of y decreases as the number of gear steps of the configuration resistor increases.
Preferably, the gear positions of the configuration resistor and the adjusting resistor are expressed in N-bit binary system, 2 N-1 ＜M≤2 N N is a positive integer;
the step of searching the configuration resistor by configuring the adjusting resistors of different steps according to the comparison result output by the voltage comparison circuit in real time comprises the following steps: all binary digits of the gear of the configuration resistor are initially confirmed to be a first numerical value, the ith binary digit is sequentially taken as a target digit according to the sequence from the high order to the low order of the binary digits, and after one target digit is newly confirmed each time, the following configuration operation is carried out: and assuming that the gear of the configuration resistor is a second value, and the other bits are the latest confirmed values, setting the gear of the adjusting resistor according to the latest assumed gear of the configuration resistor, if the comparison result of the voltage comparison circuit is that the voltage drop on the configuration resistor is larger than the voltage drop on the adjusting resistor, determining that the configuration resistor is the second value, otherwise, determining that the configuration resistor is the first value.
Wherein the second value is 1 and the first value is 0, or the second value is 0 and the first value is 1, i is an integer, and 0 is less than or equal to i < N.
Preferably, the current control branch circuit comprises a first PMOS tube, an operational amplifier and the regulating resistor, the current mirror branch circuit comprises a second PMOS tube, the sources of the first PMOS tube and the second PMOS tube are both connected with a positive power supply, the drain electrode of the first PMOS tube is grounded through the regulating resistor, the output end of the operational amplifier is connected with the grid electrodes of the first PMOS tube and the second PMOS tube, one input end of the operational amplifier is connected with a reference voltage, the other input end of the operational amplifier is connected between the drain electrode of the first PMOS tube and the regulating resistor, and the regulating end of the regulating resistor is connected with the control circuit.
Preferably, the voltage comparison circuit comprises a comparator, one input end of the comparator is connected with the configuration pin, the other input end of the comparator is connected between the drain electrode of the first PMOS tube and the regulating resistor, and the output end of the comparator is connected with the control circuit.
Preferably, the current mirror circuit further comprises a mirror ratio trimming circuit for eliminating process errors of the regulating resistor by changing a mirror ratio of a current mirror branch to the current control branch.
Preferably, the mirror ratio trimming circuit is configured to set a mirror ratio of the current mirror branch to the current control branch to an accuracy of the adjustment resistor.
The chip with one pin for configuring a plurality of chip addresses or working modes has the following beneficial effects: according to the invention, the comparison result output by the voltage comparison circuit in real time is combined, the adjusting resistors of different gears are configured to search the gears of the configuration resistor, and then the chip address or the working mode is determined according to the gears of the configuration resistor, so that the determination of a plurality of chip addresses or the working modes can be completed by only occupying one chip configuration pin, and the problems of increased chip area and packaging cost and increased PCB wiring caused by occupying a plurality of pin configuration addresses or working modes in the center in the prior art are solved.
Drawings
For a clearer description of an embodiment of the invention or of a technical solution in the prior art, the drawings that are needed in the description of the embodiment or of the prior art will be briefly described, it being obvious that the drawings in the description below are only embodiments of the invention, and that other drawings can be obtained, without inventive effort, by a person skilled in the art from the drawings provided:
FIG. 1 is a schematic circuit diagram of a chip of the present invention with a pin configured with multiple chip addresses or modes of operation;
fig. 2 is a schematic diagram of the search principle of gear.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Exemplary embodiments of the present invention are illustrated in the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and not limited to the technical solutions of the present application, and the embodiments of the present invention and the technical features in the embodiments may be combined with each other without conflict.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The terms including ordinal numbers such as "first", "second", and the like used in the present specification may be used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first component may be termed a second component, and, similarly, a second component may be termed a first component, without departing from the scope of the present invention.
Referring to FIG. 1, the chip of the present embodiment with one pin for configuring multiple chip addresses or operation modes includes a configuration pin for externally connecting a configuration resistor R ext Is provided with a resistor R ext The other end of which is grounded. The chip includes a current mirror circuit, a voltage comparison circuit 104, and a control circuit 101.
Wherein the resistor R is configured ext The resistance value of (2) has a plurality of gears and different gears correspond to different chip addresses or working modes, and in this embodiment, the number of chip addresses or working modes is M, 2 N-1 ＜M≤2 N N is a positive integer, and the resistor R is configured ext Has M gear positions. The invention detects the configuration resistor R externally connected between the chip configuration pin and the ground when the chip is electrified and started ext To determine a particular chip address or operating mode.
Wherein the current mirror circuit comprises a current control branch 102 and a current mirror branch 103 for mirroring current from the current control branch 102, and a regulating resistor R is arranged in the current control branch 102 int The output of the current mirror branch 103 is connected to the configuration pin. In this embodiment, specifically, the current control branch 102 includes a first PMOS transistor M1, an op amp, and the adjusting resistor R int The current mirror branch 103 includes a second PMOS transistor M2, sources of the first PMOS transistor M1 and the second PMOS transistor M2 are both connected to a positive power supply, and a drain of the first PMOS transistor M1 passes through the adjusting resistor R int The output end of the operational amplifier amp is connected with the first PMOS tube M1 and the second PMThe grid electrode of the OS tube M2, one input end of the operational amplifier amp is connected with a reference voltage, and the other input end of the operational amplifier amp is connected with the drain electrode of the first PMOS tube M1 and the regulating resistor R int Between, the regulating resistor R int Is connected to the control circuit 101.
The regulating resistor R int Has M-1 gears. Regulating resistor R int The resistance value corresponding to each gear is the configuration resistance R ext Resistance between two adjacent gears, preferably the regulating resistance R of any gear int Is set as the regulating resistor R int An average value of the resistance values of two adjacent gear positions.
The configuration resistor R ext And the regulating resistor R int The resistance values of the configuration resistor R are all increased/decreased along with the increase of gear ext The higher resistance value of the two adjacent gear positions is 1+y times of the lower resistance value, and the regulating resistor R int The higher resistance value of the two adjacent gear positions is 1+y times of the lower resistance value, y is a positive number, and the value of y is along with the configuration resistor R ext The number of gear steps of (a) increases and decreases.
Wherein, the voltage comparison circuit 104 and the configuration pin and the adjusting resistor R int Are respectively connected to compare the regulating resistance R int And the configuration resistor R ext Pressure drop across the valve. In this embodiment, specifically, the voltage comparing circuit 104 includes a comparator comp, one input end of the comparator comp is connected to the configuration pin, and the other input end of the comparator comp is connected to the drain electrode of the first PMOS transistor M1 and the adjusting resistor R int The output terminal of the comparator comp is connected to the control circuit 101.
Wherein, the control circuit 101 and the adjusting resistor R int And the voltage comparison circuits 104 are respectively connected to combine the comparison results outputted by the voltage comparison circuits 104 in real time, and the adjusting resistors R with different gear positions are configured int Searching for the configuration resistor R ext Further according to the gear of the configuration resistorR ext The gear of (a) determines the chip address or the operating mode.
In order to improve the searching efficiency, in this embodiment, the resistor R is configured ext Said regulating resistor R int Is represented in binary of N bits, 2 N-1 ＜M≤2 N N is a positive integer. The control circuit 101 searches for the adjustment resistance R int The process of the gear of (2) is as follows:
1) Configuring the resistor R ext All binary digits of the gear of (2) are initially identified as a first value;
2) Taking the ith binary bit as a target bit in sequence from the high bit to the low bit of the binary bit (i is an integer, i is more than or equal to 0 and less than N, and selecting the target bit in sequence from the high bit to the low bit of the binary bit, namely, i is a value from N-1 until i is 0), and after each time one target bit is newly determined, performing the following configuration operation: assuming that the target bit is the second value and the other bits are the latest confirmed values, setting the gear of the adjusting resistor according to the latest assumed gear of the configuration resistor, if the comparison result of the voltage comparison circuit 104 is the configuration resistor R ext The voltage drop is larger than the regulating resistance R int And if the voltage drop is higher than the preset voltage drop, determining the configuration resistance target bit as a second value, otherwise, determining the configuration resistance target bit as a first value.
Wherein the second value is 1 and the first value is 0, or the second value is 0 and the first value is 1.
The matching property of the resistor in the semiconductor process is good, but the resistance value precision is poor, so that R is caused int Each gear may deviate from the target value by a certain percentage (different batches or different Die, usually within + -20%) uniformly, when the gears are less, a larger y can be taken, the adjacent resistance gears are pulled apart, and R is covered by a larger resistance difference margin int Error, but when there are more gears, R is required to reduce the difficulty of circuit design intmax /R intmin When the resistance difference margin is controlled within a reasonable range and a larger y cannot be taken, for example, y=0.5, the resistance difference margin is + -20% and only the resistance difference margin can be coveredR int Error. If external R is used ext The precision is higher (such as 1%), the mismatch of a designed current mirror and the input offset of comp are smaller, and R is selected int When the temperature coefficient is smaller, an image ratio trimming circuit can be added in the design of more resistance gears, and the adjusting resistance R is eliminated by changing the image ratio of the current image branch 103 and the current control branch 102 int Is a process error of (a). For example, R int actual ＝c％*R int target At this time I int actual ＝V int /(c％*R int target ) And I ext target ＝V int /R int target Then set b/a=i ext target /I int actual It is sufficient to=c%.
The working principle of this embodiment is illustrated below based on the circuit of fig. 1, taking N as 3 as an example (i.e. the chip address is 3 bits, denoted A2A1 A0).
In FIG. 1, op amp, M 1 And adjustable resistor R inside chip int In fact, a negative feedback loop is formed, always having V int ＝V ref . We compare the control circuit 101 to R int Is adjusted by R set [x:0]Expressed by R set [x:0]To represent the set R int X represents the subscript of a binary bit, R is because N takes 3 in this embodiment set [x:0]Namely R is set [2:0]I.e. R set [2]R set [1]R set [0]。I int R set along with int And change through M 2 Mirror out, I ext Flow through R ext Generating V on pin ext Compare V with comparator comp ext ＝I ext *R ext And V int ＝I int *R int 。
Typically M will 2 And M 1 Is set to b/a=1, i.e. has I ext ＝I int When R is ext >R int Output O of comp at the time cmp Is logic high '1', when R ext <R int When O cmp Is a logic low '0'. The following table gives a better resistance gear settingFor example, the table is sequentially from top to bottom, the resistance increases from bottom to top, and R is as follows ext And R is int The upper gear is (1+y) times the lower gear, and R of either gear is taken int Is arranged as two adjacent R's from top to bottom ext Average value of gear position, so that R int With adjacent two R ext The margin of the resistance difference is maximized to + -y/(y+2).
Table 1 resistor gear setting table
R ext For 8 gear, the control circuit 101 sets different R set [2:0]With the purpose of using R of different gear int Search R ext . As shown in fig. 2, R is initialized set [2:0]= '100', if O cmp = '1', determine R set [2:0]The most significant bit is '1' and otherwise '0', it should be noted here that the logic high and low is merely for more convenience in describing the scheme, but does not limit the scope of the scheme, and vice versa if the two inputs of comparator comp in fig. 1 are swapped. If it is determined that R set [2:0]The most significant bit is '1', R is then again set [2:0]The next highest order of (2) is set to '1', and R is searched downward set [2:0]= '110'; conversely, if R is determined set [2:0]The most significant bit is '0', R is then again set [2:0]The next highest order of (2) is set to '1', and R is searched downward set [2:0]= '010'. By this, R is obtained after searching a total of 3 times ext Corresponding' A 2 A 1 A 0 ’。
In summary, the chip with one pin configured with multiple chip addresses or working modes has the following advantages: according to the invention, the comparison result output by the voltage comparison circuit in real time is combined, the adjusting resistors of different gears are configured to search the gears of the configuration resistor, and then the chip address or the working mode is determined according to the gears of the configuration resistor, so that the determination of a plurality of chip addresses or the working modes can be completed by only occupying one chip configuration pin, and the problems of increased chip area and packaging cost and increased PCB wiring caused by occupying a plurality of pin configuration addresses or working modes in the center in the prior art are solved.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims (10)

1. A chip for configuring a plurality of chip addresses or operation modes by using one pin, wherein the chip comprises one configuration pin (pin) for externally connecting a configuration resistor (R ext ) Is arranged at one end of the configuration resistor (R ext ) Is grounded at the other end of the configuration resistor (R ext ) The resistance value of the chip is provided with a plurality of gears, and different gears correspond to different chip addresses or working modes, and the chip comprises:
a current mirror circuit comprising a current control branch (102) and a current mirror branch (103) for mirroring a current from the current control branch (102), the current control branch (102) being provided with a regulating resistor (R) int ) The output end of the current mirror branch (103) is connected with the configuration pin (pin);
a voltage comparison circuit (104) connected to the configuration pin (pin) and the regulating resistor (R int ) Are respectively connected to compare the regulating resistance (R int ) And the configuration resistor (R ext ) Pressure drop across;
a control circuit (101) connected to the regulating resistor (R int ) And the voltage comparison circuits (104) are respectively connected for the junctionBy configuring the adjusting resistors (R) of different gear positions according to the comparison result output by the voltage comparison circuit (104) in real time int ) To search for the configuration resistor (R ext ) And further according to the configuration resistance (R ext ) The gear of (a) determines the chip address or the operating mode.
2. The chip of claim 1, wherein the chip addresses or modes of operation are M, M is a positive integer, the configuration resistor (R ext ) Has M gear positions, and the regulating resistor (R int ) Has M-1 gears, and the corresponding resistance value of each gear is the configuration resistor (R ext ) Resistance between two adjacent gear positions.
3. Chip with one pin for configuring multiple chip addresses or operating modes according to claim 2, characterized in that the regulating resistance (R int ) Is set as the configuration resistor (R ext ) An average value of the resistance values of two adjacent gear positions.
4. Chip with one pin for configuring multiple chip addresses or operation modes according to claim 2, characterized in that the configuration resistor (R ext ) And the regulating resistor (R int ) Is increased/decreased with the increase of the gear, the configuration resistor (R ext ) The higher of the two resistances of the adjacent gear stages of (a) is 1+y times the lower, the regulating resistance (R int ) The higher resistance of the two adjacent gear positions is 1+y times of the lower resistance, and y is a positive number.
5. The chip of claim 4, wherein said y has a value corresponding to said configuration resistor (R ext ) The number of gear steps of (a) increases and decreases.
6. According to the weightsA chip for configuring a plurality of chip addresses or operation modes with one pin as claimed in claim 2, wherein said configuration resistor (R ext ) And the regulating resistor (R int ) The gears of (2) are all represented by N-bit binary system N-1 ＜M≤2 N N is a positive integer;
the comparison result combined with the real-time output of the voltage comparison circuit (104) is obtained by configuring the adjusting resistors (R int ) To search for the configuration resistor (R ext ) Comprising: the configuration resistor (R ext ) All binary digits of the gear of (a) are initially confirmed to be first numerical values, the ith binary digit is sequentially taken as a target digit according to the sequence from the high order to the low order of the binary digits, and after each target digit is newly confirmed, the following configuration operation is carried out: assuming that the gear of the configuration resistor is a second value and the other bits are the most recently confirmed values, setting the gear of the adjusting resistor according to the most recently assumed gear of the configuration resistor, if the comparison result of the voltage comparison circuit (104) is that the configuration resistor (R ext ) The voltage drop over the resistor is greater than the regulating resistance (R int ) And if the voltage drop is higher than the preset voltage drop, determining the configuration resistance target bit as a second value, otherwise, determining the configuration resistance target bit as a first value.
Wherein the second value is 1 and the first value is 0, or the second value is 0 and the first value is 1, i is an integer, and 0 is less than or equal to i < N.
7. The chip with one pin for configuring multiple chip addresses or operation modes according to claim 1, wherein the current control branch (102) comprises a first PMOS transistor (M1), an op amp (amp), and the regulating resistor (R int ) The current mirror branch circuit (103) comprises a second PMOS tube (M2), sources of the first PMOS tube (M1) and the second PMOS tube (M2) are both connected with a positive power supply, and a drain electrode of the first PMOS tube (M1) passes through the regulating resistor (R) int ) The output end of the operational amplifier (amp) is connected with the grid electrodes of the first PMOS tube (M1) and the second PMOS tube (M2) in a grounding way, and one output end of the operational amplifier (amp) is connected with the grid electrodes of the first PMOS tube (M2)The other input end of the operational amplifier (amp) is connected with the drain electrode of the first PMOS tube (M1) and the regulating resistor (R int ) Between, the regulating resistance (R int ) Is connected to the control circuit (101).
8. The chip for configuring multiple chip addresses or operation modes with one pin according to claim 7, wherein said voltage comparing circuit (104) comprises a comparator (comp), one input terminal of said comparator (comp) being connected to said configuration pin (pin), the other input terminal of said comparator (comp) being connected to the drain of said first PMOS transistor (M1) and to said regulating resistor (R int ) And the output end of the comparator (comp) is connected with the control circuit (101).
9. The chip with one pin for configuring a plurality of chip addresses or operation modes according to claim 1, wherein the current mirror circuit further comprises a mirror ratio trimming circuit for eliminating the regulating resistor (R by changing a mirror ratio of a current mirror branch (103) to the current control branch (102) int ) Is a process error of (a).
10. A chip with one pin for configuring multiple chip addresses or operation modes according to claim 9, wherein the mirror ratio trimming circuit is configured to set the mirror ratio of the current mirror branch (103) to the current control branch (102) to the regulating resistance (R int ) Is a precision of (a).
CN202210051844.3A 2022-01-17 2022-01-17 Chip with one pin for configuring multiple chip addresses or working modes Pending CN116483762A (en)

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CN202210051844.3A CN116483762A (en) 2022-01-17 2022-01-17 Chip with one pin for configuring multiple chip addresses or working modes

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CN202210051844.3A CN116483762A (en) 2022-01-17 2022-01-17 Chip with one pin for configuring multiple chip addresses or working modes

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CN116483762A true CN116483762A (en) 2023-07-25

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