CN116477564A - Method for compensating anisotropic corrosion convex angle on (100) silicon - Google Patents
Method for compensating anisotropic corrosion convex angle on (100) silicon Download PDFInfo
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- CN116477564A CN116477564A CN202310363882.7A CN202310363882A CN116477564A CN 116477564 A CN116477564 A CN 116477564A CN 202310363882 A CN202310363882 A CN 202310363882A CN 116477564 A CN116477564 A CN 116477564A
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- 238000005260 corrosion Methods 0.000 title claims abstract description 42
- 230000007797 corrosion Effects 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 29
- 239000010703 silicon Substances 0.000 title claims abstract description 29
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims abstract description 96
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000004094 surface-active agent Substances 0.000 claims abstract description 20
- 239000000243 solution Substances 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000007991 ACES buffer Substances 0.000 claims description 2
- 239000002736 nonionic surfactant Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000012545 processing Methods 0.000 abstract description 5
- 238000000347 anisotropic wet etching Methods 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 2
- 238000002474 experimental method Methods 0.000 abstract description 2
- GPRLSGONYQIRFK-MNYXATJNSA-N triton Chemical compound [3H+] GPRLSGONYQIRFK-MNYXATJNSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
- B81C1/00539—Wet etching
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00404—Mask characterised by its size, orientation or shape
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- G—PHYSICS
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- G16C—COMPUTATIONAL CHEMISTRY; CHEMOINFORMATICS; COMPUTATIONAL MATERIALS SCIENCE
- G16C60/00—Computational materials science, i.e. ICT specially adapted for investigating the physical or chemical properties of materials or phenomena associated with their design, synthesis, processing, characterisation or utilisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2113/00—Details relating to the application field
- G06F2113/26—Composites
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
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- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a method for compensating anisotropic corrosion convex angle on (100) silicon, which adopts a mask convex angle compensation pattern, wherein the compensation pattern is a polygonal shape which is symmetrical on two sides and is surrounded by an OABCDE extending outwards from a convex angle vertex O, and corrosion is carried out in two steps: the first step forms most depth with extremely low lobe corrosion rate by using TMAH corrosion liquid containing surfactant, the second step eliminates the side wall formed in the first step by using {110} surface corrosion rate high by pure TMAH solution, and finally the complete boss structure is obtained. The invention greatly reduces the area required by the convex angle compensation pattern in the (100) silicon anisotropic wet etching, has simple and regular pattern, is easy to design, and has simple and convenient process flow and easy operation. The related experiments prove that the technology is feasible in the processing of small-size deep-corrosion boss structures.
Description
Technical Field
The invention relates to the field of micro-electro-mechanical system (MEMS) processing technology, in particular to a lobe compensation method of a (100) silicon wafer in anisotropic wet etching.
Background
MEMS technology is a leading-edge research field developed in microelectronics, and is a cross technical field involving multiple disciplines of machinery, materials, physics, biology, etc. The MEMS device has the advantages of small volume, low power consumption, low cost, high reliability, mass production and the like, and has wide application in the fields of aerospace, automobiles, biomedical treatment, consumer electronics and the like.
Bulk silicon processes are an important part of MEMS processing processes, wherein anisotropic etching of monocrystalline silicon materials by using alkaline etching solutions such as potassium hydroxide (KOH) solution or tetramethylammonium hydroxide (TMAH) solution is a key technology in bulk silicon processes, and the etching method has the advantages of stable and controllable rate, flat and smooth etched surface and the like, and can be used for processing square and rectangular boss structures or other complex silicon microstructures.
The chamfering phenomenon exists when the boss structure is manufactured by anisotropic corrosion, and the reason is that the corrosion rate of the corrosive liquid to silicon in each crystal direction is different, so that the manufacture of the complete boss structure is a key technology in the wet corrosion process. There are generally two technical routes to solve the chamfering problem: as soon as additional compensation patterns are added on the original mask patterns, as shown in the Chinese patent application publication specifications CN1598060A and CN1442511A, mask compensation patterns with specific shapes are reported respectively; secondly, the chamfer corrosion rate of the etching solution is reduced by adding other chemical substances to the etching solution, as reported in chinese patent application publication CN104966670a as an example of adding triton and isopropanol solution to TMAH solution.
However, the two technical routes still have problems in practical application. For the first technical route, the size of the compensation pattern is generally in a linear relation with the corrosion depth, and when the compensation pattern is processed for manufacturing a structure with small area of deep corrosion, the compensation patterns can be overlapped with each other due to the expansion of the size, so that the expected compensation effect cannot be achieved. For the second technical route, the chamfer corrosion ratio can be reduced by adding the triton into the TMAH solution, but the chamfer phenomenon by using the method is still not negligible when the method is applied to small-size deep corrosion, and a complete boss structure is difficult to obtain.
Disclosure of Invention
The invention aims to solve the problems in the prior art facing (100) silicon anisotropic wet etching to solve the chamfering etching, and provides a lobe compensation method capable of facing small-size deep etching application.
In order to achieve the technical purpose, the invention adopts the following technical scheme: the anisotropic etching lobe compensation method for (100) silicon is one complete process capable of compensating anisotropic etching lobe of (100) silicon, and includes one kind of mask lobe compensation pattern and corresponding etching technological process. The corrosion process flow is integrally divided into two steps: and (3) sequentially corroding the silicon wafer in the TMAH solution and the pure TMAH solution with the surfactant by controlling the layout size and the corrosion depth. The first step uses TMAH corrosive liquid containing surfactant to form most depth with extremely low lobe corrosion rate, the second step uses {110} surface corrosion rate high by pure TMAH solution to eliminate the side wall formed in the first step, and finally the complete boss structure can be obtained.
Fig. 3 is a schematic diagram of a mask lobe compensation pattern, where a symmetric polygon surrounded by OABCDE is a compensation pattern extending outward from a lobe vertex O, where +.aoe is a concave angle of the compensation pattern (corresponding to a mask lobe without the compensation pattern), OA is parallel to CB and a <110> positioning edge, OE is parallel to CD, AB is parallel to ED, OA is perpendicular to OE, angle BAO is 45 degrees, H represents a distance from point O to BC, L represents a length of OA, and a size of the compensation pattern is determined by the following formula:
wherein D represents the depth of corrosion,represents the corrosion rate of the fast-line in TMAH solution with added surfactant and in pure TMAH solution, respectively,/->Represents the {110} plane corrosion rate in TMAH solution and pure TMAH solution with added surfactant,/-, respectively>Represents the {100} plane corrosion rate, α, in the TMAH solution with the surfactant added and in the pure TMAH solution, respectively 1 、α 2 Representing the rapid corrosion direction and the rapid corrosion direction in the TMAH solution added with the surfactant and the pure TMAH solution respectively<110>Included angle of crystal orientation.
The depth of corrosion in the two steps is determined by the following equation:
wherein D is 1 D is the corrosion depth of the silicon wafer in TMAH solution added with surfactant 2 Is the etching depth of the silicon wafer in the pure TMAH solution.
The specific dimensions of the mask lobe compensation pattern and the two-step etch depth can also be accomplished using related numerical simulation software such as Intellisuite, ACES.
In the TMAH solution added with the surfactant, the added surfactant is a nonionic surfactant, such as triton-100, NC-200 (CAS No. 171286-94-5) and the like. The addition volume fraction of the surfactant is 0.01% -1%, most preferably 0.1%; the mass fraction of the TMAH solution is 5-40%, and 25% is commonly used.
The material of the mask is preferably silicon oxide or a silicon oxide/silicon nitride composite material, and the etching temperature is generally 60-80 ℃.
Preferably, after the first etching step is completed, the silicon wafer is washed with deionized water, and then the second etching step is performed.
The invention has the technical effects that: the invention greatly reduces the area required by the convex angle compensation pattern in the (100) silicon anisotropic wet etching, has simple and regular pattern, is easy to design, and has simple and convenient process flow and easy operation. The related experiments prove that the technology is feasible in the processing of small-size deep-corrosion boss structures.
Drawings
FIG. 1 is a schematic illustration of (100) silicon corner etching;
FIG. 2 is a schematic diagram of (100) a silicon etched fast line < lm0> and its angle α with the <110> direction;
FIG. 3 is a schematic illustration of a mask lobe compensation pattern of the method of the present invention;
FIG. 4 is a schematic cross-sectional view of FIGS. 5, 6, 7, 8;
FIG. 5 shows the etching time t 1 FIG. 4 is a cross-sectional view of the A-A position;
FIG. 6 shows the etching time t 2 In the case of the cross-section at position A-A shown in FIG. 4, t 2 >t 1 ；
FIG. 7 shows the etching time t 3 In the case of the cross-section at position A-A shown in FIG. 4, t 3 >t 2 >t 1 ；
FIG. 8 shows the etching time t 4 In the case of the cross-section at position A-A shown in FIG. 4, t 4 >t 3 >t 2 >t 1 ；
FIG. 9 is a schematic diagram of one embodiment of a mask lobe compensation pattern of the present invention;
FIG. 10 shows the structure after the etching process of the present invention;
in the figure: 1-etching mask without lobe compensation, 2-slow etching {111} plane, 3-fast etching plane, 4-lobe compensation mask pattern of the present invention, 5-t 1 Etching contour line at moment, 6-t 2 Time erosion profile, 7-t 3 Etching contour line at moment, 8-t 4 Etching contour lines at the moment, 9-mask repair according to the inventionOne embodiment of the compensation graph is shown.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings.
Fig. 1 is a schematic view of (100) silicon corner etching, illustrating the phenomenon of (100) silicon corner etching without the addition of a compensation pattern.
Fig. 2 illustrates (100) silicon etched fast-line < lm0> and its angle alpha with the <110> direction, where the etched fast-line is the intersection of the fast-line plane and the (100) plane.
The mass fraction of TMAH solution adopted in the embodiment is 25%, the added surfactant is triton-100, and the added volume fraction is 0.1%; the corrosion temperature is 60 ℃, alpha 1 ＝22°， α 2 ＝17°，It should be noted that these angles, rates are not the only values, and in fact the rates may be affected by factors such as reagent concentration, experimental temperature, experimental setup, laboratory environment, etc.
Fig. 3 is a schematic diagram of a mask lobe compensation graph according to the present disclosure, according to the calculation formula:
the calculated results are h=0.655d, l=0.624d, d 1 ＝0.752D，D 2 ＝0.248D。
In addition, h=0.9d, l=0.5d, d were calculated from simulation software intellisite 1 ＝0.69D，D 2 ＝0.31D。
Fig. 4 is a schematic cross-sectional view of fig. 5, 6, 7, 8.
FIGS. 5, 6, 7, 8 are t 1 、t 2 、t 3 、t 4 The A-A position cross-section shown in FIG. 4 illustrates the principles and methods of practicing the present invention. After forming a mask (mask material is usually silicon oxide or silicon oxide/silicon nitride composite material) on a (100) silicon wafer, firstly placing the silicon wafer in TMAH solution added with the triton 100 for corrosion at 60 ℃, wherein the volume fraction of the triton 100 is 0.1%, the mass fraction of the TMAH is 25%, and after t 1 Corrosion in time with depth D 1 The A-A cross-section shown in FIG. 5 illustrates that the cross-section is defined by the {110} plane, which is due to the slow etch rate of the {110} plane by the TMAH solution of the Curve 100. The wafer was then removed and rinsed with deionized water and etched in a 25% TMAH solution, FIGS. 6 and 7 show the {110} plane being etched and the {100} side walls being exposed to a profile in pure TMAH solution, and finally FIG. 8 shows the etch D in pure TMAH solution 2 After the depth of (2), a structure consisting of {111} slow etched surfaces is formed.
As shown in FIG. 9, the mask lobe compensation pattern is prepared by etching at 60deg.C to a depth of 100 μm with 0.1% by volume of triton+25% by mass of TMAH, and using simulation software, H is equal to 90 μm, L is 50 μm, and etching depth D is equal to 1 Depth of corrosion D of 69 μm 2 31 μm. After the etching is completed, a boss structure as shown in fig. 10 can be obtained.
The scope of the present disclosure is defined not by the description of the specific embodiments but by the claims and their equivalents, and all modifications within the scope of the claims and their equivalents are to be construed as being included in the present disclosure.
Claims (9)
1. A method for compensating anisotropic etching convex angle on (100) silicon is characterized in that a mask convex angle compensation pattern is adopted to carry out etching in two steps: the method comprises the steps of firstly, corroding a silicon wafer in TMAH solution with a surfactant, and secondly, corroding the silicon wafer in pure TMAH solution; wherein the mask lobe compensation pattern is a bilaterally symmetrical polygon surrounded by OABCDE extending outwards from the lobe vertex O, the angle AOE is a concave angle of the compensation pattern, OA is parallel to CB and a <110> positioning edge, OE is parallel to CD, AB is parallel to ED, OA is perpendicular to OE, angle BAO is 45 degrees, H represents the distance from point O to BC, and L represents the length of OA; the size of the compensation pattern is determined by the following equation:
wherein D represents the depth of corrosion,represents the corrosion rate of the fast-line in TMAH solution with added surfactant and in pure TMAH solution, respectively,/->Represents the {110} plane corrosion rate in TMAH solution and pure TMAH solution with added surfactant,/-, respectively>Represents the {100} plane corrosion rate, α, in the TMAH solution with the surfactant added and in the pure TMAH solution, respectively 1 、α 2 Representing the rapid corrosion direction and the rapid corrosion direction in the TMAH solution added with the surfactant and the pure TMAH solution respectively<110>An included angle of the crystal orientation;
the depth of corrosion in the two steps is determined by the following equation:
wherein D is 1 D is the corrosion depth of the silicon wafer in TMAH solution added with surfactant 2 The etching depth of the silicon wafer in the pure TMAH solution is set;
alternatively, H, L, D is obtained using simulation software 1 And D 2 Is a value of (2).
2. The method of claim 1, wherein the simulation software is intellisite or ACES.
3. The method of claim 1, wherein the surfactant is a nonionic surfactant.
4. A method according to claim 3, wherein the surfactant is triton-100 or NC-200.
5. The method of claim 1, wherein the TMAH solution has a mass fraction of 5% to 40% and the surfactant-added TMAH solution has a surfactant-added volume fraction of 0.01% to 1%.
6. The method of claim 1 wherein the wafer is rinsed with deionized water after the first etching step is completed and then subjected to a second etching step.
7. The method of claim 1, wherein the mask is made of silicon oxide or a composite of silicon oxide/silicon nitride, and the etching temperature is 60-80 ℃.
8. The method of claim 1, wherein the TMAH solution has a mass fraction of 25%, and the surfactant-added TMAH solution is triton-100 added with a volume fraction of 0.1%; etching at 60 degrees centigrade, alpha 1 ＝22°，α 2 ＝17°，/> H=0.655d, l=0.624d, d is calculated according to the formula 1 ＝0.752D，D 2 ＝0.248D。
9. The method of claim 1, wherein the TMAH solution has a mass fraction of 25%, and the surfactant-added TMAH solution is triton-100 added with a volume fraction of 0.1%; corrosion was performed at 60 degrees celsius and h=0.9d, l=0.5d, d was calculated using simulation software intellisite 1 ＝0.69D，D 2 ＝0.31D。
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