CN116472614A - 具有纳米线芯的铁电场效应晶体管 - Google Patents

具有纳米线芯的铁电场效应晶体管 Download PDF

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CN116472614A
CN116472614A CN202180077996.4A CN202180077996A CN116472614A CN 116472614 A CN116472614 A CN 116472614A CN 202180077996 A CN202180077996 A CN 202180077996A CN 116472614 A CN116472614 A CN 116472614A
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layer
fefet
ferroelectric
nanowire
box
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龚南博
安藤崇志
G·科恩
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International Business Machines Corp
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International Business Machines Corp
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Abstract

提供一种铁电场效晶体管(FeFET)。该FeFET包括掩埋氧化物(BOX)层；纳米线层，其包括在所述FeFET的源极和漏极区处的所述BOX层上形成的衬垫，以及在所述衬垫之间并且在所述BOX层中形成的凹陷之上延伸的纳米线芯；覆盖所述纳米线芯的金属电极；铁电层，其覆盖所述金属电极；界面层，覆盖该铁电层；以及形成在FeFET的沟道区之上的多晶硅层，该多晶硅层覆盖界面层。

Description

具有纳米线芯的铁电场效应晶体管
技术领域
本公开一般涉及基于半导体的电子器件以及制造基于半导体的电子器件的方法。更具体地，本申请涉及包括纳米线沟道的铁电栅控场效应晶体管(FeFET)器件及其制造方法。当铁电层的铁电氧化物中的极化被切换时，FeFET器件的耐久特性可以是界面层(IL)中的大电场的函数。可能需要改进FeFET器件的铁电层的性能。
发明内容
本公开的实施例涉及铁电场效应晶体管(FeFET)。该FeFET包括掩埋氧化物(BOX)层；纳米线层，其包括在所述FeFET的源极和漏极区处的所述BOX层上形成的衬垫，以及在所述衬垫之间并且在所述BOX层中形成的凹陷之上延伸的纳米线芯；覆盖所述纳米线芯的金属电极；铁电层，其覆盖所述金属电极；界面层，覆盖铁电层；以及形成在FeFET的沟道区之上的多晶硅层，该多晶硅层覆盖界面层。
本公开的其它实施例涉及制造铁电场效应晶体管(FeFET)的方法。该方法包括形成掩埋氧化物(BOX)层。该方法包括在BOX层上形成纳米线层，该纳米线层包括在FeFET的源极和漏极区处在BOX层上形成的衬垫以及在衬垫之间延伸的纳米线芯。该方法还包括：底切在所述纳米线芯下方的所述BOX层，以从所述BOX层释放所述纳米线芯；在所述纳米线芯周围形成金属电极；在金属电极周围形成铁电层；在铁电层周围形成界面层；以及在FeFET的沟道区之上形成多晶硅层，该多晶硅层覆盖界面层。
上述发明内容并非旨在描述本公开的每个所示实施例或每种实施方式。
附图说明
本申请中包括的附图并入说明书中并形成说明书的一部分。它们示出了本公开的实施例，并且与说明书一起解释了本公开的原理。附图仅说明某些实施例，而不限制本公开。
图1A和1B分别示出了根据实施例的FeFET器件在制造过程的中间阶段的俯视图和截面图。
图2A和2B分别示出了根据实施例的图1A和1B的FeFET器件在制造过程的后续阶段的俯视图和截面图。
图3A和3B分别示出了根据实施例的图2A和2B的FeFET器件在制造过程的后续阶段的俯视图和截面图。
图4A和4B分别示出了根据实施例的在制造工艺的后续阶段的图3A和3B的FeFET器件的俯视图和截面图。
图5A和5B分别示出了根据实施例的在制造工艺的后续阶段的图4A和4B的FeFET器件的俯视图和截面图。
图6A、6B和6C分别示出了根据实施例的图1A和1B的FeFET器件在制造过程的后续阶段的俯视图、截面图和截面侧视图。
图7示出了根据实施例的在制造工艺中的后续阶段的图6B的FeFET器件的截面图。
图8示出了根据实施例的在制造工艺中的后续阶段的图7的FeFET器件的截面图。
图9示出了根据实施例的制造FeFET器件的方法。
应当理解，附图中的元件是为了简单和清楚而示出的。为了简单起见并且为了帮助理解所示实施例，可能没有示出在商业上可行的实施例中可能有用或必要的公知元件。
具体实施方式
本公开描述了半导体结构和制造半导体结构的方法。更具体地，本申请涉及铁电栅控场效应晶体管(FeFET)以及制造FeFET器件的方法。通常，FeFET是一种场效应晶体管，其包括夹在器件的栅电极和源-漏导电区之间的铁电材料。铁电材料中的永久电场极化导致这种类型的器件在没有任何电偏置的情况下保持晶体管的状态(导通或截止)。FeFET晶体管可以用于FeFET存储器件中，该存储器件是一种单晶体管非易失性存储器。
本文参照相关附图描述本公开的各种实施例。在不脱离本公开的范围的情况下，可以设计出替代实施例。注意，在以下描述和附图中的元件之间阐述了各种连接和位置关系(例如，上方、下方、相邻等)。除非另外指明，这些连接和/或位置关系可以是直接的或间接的，并且本公开不旨在在这方面进行限制。因此，实体的耦接可以指直接或间接耦接，并且实体之间的位置关系可以是直接或间接位置关系。作为间接位置关系的一个例子，本说明书中提到在层“B”上形成层“A”包括这样的情况，其中一个或多个中间层(例如层“C”)在层“A”和层“B”之间，只要层“A”和层“B”的相关特性和功能基本上不被中间层改变。
以下定义和缩写用于解释权利要求和说明书。如本文所用，术语“包含”、“包括”、“具有”、“含有”、“有”、“带有”、“包含有”、“包括有”或其任何其它变型旨在涵盖非排他性的包括。例如，包括一系列要素的组合物、混合物、工艺、方法、制品或装置不一定仅限于那些要素，而是可以包括未明确列出的或此类组合物、混合物、工艺、方法、制品或装置固有的其他要素。
为了下文描述的目的，术语“上”、“下”、“右”、“左”、“垂直”、“水平”、“顶部”、“底部”及其派生词应涉及所描述的结构和方法，如附图中所定向的。术语“覆盖”、“在顶部上”、“定位在”或“定位在顶部”表示第一元件例如第一结构存在于第二元件例如第二结构上，其中中间元件例如界面结构可存在于第一元件和第二元件之间。术语“直接接触”是指第一元件(例如第一结构)和第二元件(例如第二结构)在两个元件的界面处没有任何中间导电、绝缘或半导体层的情况下连接。应注意，术语“对……具有选择性”，例如，“第一元件对第二元件具有选择性”意指第一元件可被蚀刻，且第二元件可充当蚀刻停止层。
为了简洁起见，在此可能详细描述或可能不详细描述与半导体器件和集成电路(IC)制造有关的常规技术。此外，本文所述的各种任务和过程步骤可并入具有本文未详细描述的额外步骤或功能性的更综合程序或过程中。特别是，半导体装置和基于半导体的IC的制造中的各种步骤是公知的，因此为了简洁起见，许多传统步骤将在此仅简要提及或将被完全省略而不提供公知的工艺细节。
通常，用于形成将被封装到IC中的微芯片的各种工艺分为四个一般类别，即，膜沉积、去除/蚀刻、半导体掺杂和图案化/光刻。
沉积是将材料生长、涂覆或以其它方式转移到晶片上的任何工艺。可用的技术包括物理气相沉积(PVD)、化学气相沉积(CVD)、电化学沉积(ECD)、分子束外延(MBE)以及最近的原子层沉积(ALD)等。另一种沉积技术是等离子体增强化学气相沉积(PECVD)，其是一种使用等离子体内的能量来在晶片表面引发反应的工艺，否则该工艺将需要与常规CVD相关联的更高温度。在PECVD沉积期间的高能离子轰击还可以改善膜的电学和机械性能。
去除/蚀刻是从晶片去除材料的任何工艺。实例包括蚀刻工艺(湿法或干法)、化学机械平坦化(CMP)等。去除工艺的一个例子是离子束蚀刻(IBE)。通常，IBE(或研磨)是指干法等离子体蚀刻方法，其利用远程宽束离子/等离子体源，通过物理惰性气体和/或化学反应气体手段来去除衬底材料。与其它干法等离子体刻蚀技术类似，IBE具有诸如刻蚀速率、各向异性、选择性、均匀性、纵横比和最小化衬底损伤的优点。干法去除工艺的另一个例子是反应离子蚀刻(RIE)。通常，RIE使用化学反应等离子体去除沉积在晶片上的材料。利用RIE，等离子体在低压(真空)下通过电磁场产生。来自RIE等离子体的高能量离子攻击晶片表面并与其反应以去除材料。
半导体掺杂是通过掺杂例如晶体管源极和漏极，通常通过扩散和/或通过离子注入来改变电特性。这些掺杂工艺之后是炉退火或快速热退火(“RTA”)。退火用于激活注入的掺杂剂。对于FeFET器件，器件的铁电层可用于将信息存储为“0”或“1”，并且RTA工艺可用于创建铁电膜。导体(例如，多晶硅、铝、铜等)和绝缘体(例如，各种形式的二氧化硅、氮化硅等)的膜用于连接和隔离晶体管及其部件。半导体衬底的各个区域的选择性掺杂允许衬底的导电性随着电压的施加而改变。通过形成这些各种组件的结构，可构建数百万个晶体管并将其布线在一起以形成现代微电子装置的复杂电路。
半导体光刻是在半导体衬底上形成三维浮雕图像或图案，以便随后将图案转移到衬底上。在半导体光刻中，图案由称为光致抗蚀剂的光敏聚合物形成。为了构建构成晶体管的复杂结构和连接电路的数百万个晶体管的许多布线，重复多次光刻和蚀刻图案转移步骤。印刷在晶片上的每个图案与先前形成的图案对准，并且逐渐地建立导体、绝缘体和选择性掺杂区域以形成最终器件。
如上文简要讨论的，当铁电层的铁电氧化物材料中的极化状态被切换时，FeFET器件的耐受特性可以是界面层(IL)中的大电场的函数。由于该大电场，IL的退化可能比极化疲劳更早地发生，并且这可能导致FeFET器件的耐久性失效。根据本实施例，通过基于器件的几何形状调整(或减小)IL中的高电场，FeFET器件可以能够实现更鲁棒的性能特性(例如，器件能够在耐久性故障之前实现增加数量的读/写循环)。在某些实施方案中，可以通过改变装置的几何设计，并且通过将界面层放置在电场不强的位置处来降低高电场。
通常，导电圆柱形结构(或圆柱形壳体)的电场是圆柱半径的函数。特别是，通过应用高斯定律，可以获得具有均匀线性电荷密度的无限圆柱形导体的电场。考虑到半径r＞R的圆柱形式的高斯表面，电场在圆柱的每个点具有相同的幅度并且指向外。因此，电通量是电场乘以圆柱体的面积。此外，考虑到圆柱形结构中的电场是半径的函数，其外部中的电场将更小。通过使界面层位于铁电层外部来调整根据本实施例的FeFET器件的结构的几何形状，内部铁电层将经历相对大的电场。而且，因为界面层(IL)形成在铁电层的外部，所以IL将经受相对小的电场。如本文所述，因为IL的退化可以导致FeFET器件的耐久性失效，并且因为高电场可以导致IL的退化，所以将IL定位在铁电层外部，在该处IL将经历较小的电场，可以最小化IL的退化，并且有助于延长FeFET器件的寿命。
本技术提供了一种栅极全包围(GAA)纳米线铁电场效应晶体管(FeFET)及其制造方法。本发明的方法使用硅(Si)纳米线和Si处理来描述。然而，本技术也可以其它半导体材料实施，例如锗(Ge)或III-V半导体。当使用不含Si的半导体时，本教导的处理步骤通常是相同的，除了生长温度和所施加的掺杂剂种类适合于所使用的特定半导体。例如，可以使用含Si半导体材料，诸如Si、硅锗(SiGe)、Si/SiGe、碳化硅(SiC)或碳化硅锗(SiGeC)。
现在参考附图，其中相同的数字表示相同或相似的元件，并且首先参考图1A和1B，根据实施例，示出了包括衬底102和掩埋氧化物(BOX)层104的FeFET器件100。在某些示例中，衬底102可以是Si衬底，尽管可以使用其他合适的材料。如图1B的横截面图所示，在下层基底102的顶部上形成掩埋氧化物层104。如图1B所示，纳米线106横穿掩埋氧化物层104的凹陷部分103。在某些实施例中，纳米线106可以包括Si或硅化物，或任何其它合适的材料。如图1A的自顶向下视图中所示，纳米线106可以包括在BOX层104凹陷部分103的任一侧(例如，左侧的源极侧和右侧的漏极侧)上的方形衬垫部分107。例如，构图的纳米线106的宽度尺寸可以在从约10nm到约30nm的范围内。在某些示例中，可以通过常规光刻(例如，光学或电子束)继之以反应离子蚀刻(RIE)来完成纳米线106的图案化。即，可以通过蚀刻BOX层104并且使BOX层104使纳米线106下方凹陷以形成凹陷部分103来悬置(从BOX层104释放)纳米线106。纳米线106因此在BOX层104的不同侧之间形成悬置桥。可以利用例如稀释的氢氟酸(DHF)蚀刻来实现BOX层104的凹陷。DHF蚀刻可以是各向同性蚀刻。因此，蚀刻的横向分量底切窄纳米线106下方的BOX层104。
在某些实施例中，可以进一步处理悬置的纳米线106以将纳米线106的截面轮廓从一般的正方形(或矩形)形状改变为一般的圆形截面形状(也参见图6C)。在某些实施例中，一般的环栅(GAA)MOSFET结构的纳米线106的悬置部分的直径为大约10nm或更小。在某些实施例中，可靠地获得亚10nm范围的高度均匀和平滑的硅纳米线的工艺可以包括顺序进行氢退火然后进行高温氧化的制造技术(同时利用常规CMOS工艺)。在生产纳米线106的示例工艺中，首先通过标准光刻技术构图纳米线106。然后，可以通过H2退火工艺实现纳米线106的无掩模减薄/平滑化。退火工艺可以将纳米线106的悬置部分的截面形状从一般正方形(或矩形)形状改变为一般圆形截面形状(也参见图6C)。在某些实施例中，然后可以通过氧化工艺进一步减小纳米线106的直径的尺寸。氧化工艺可以进一步减小纳米线尺寸，而没有可测量的线边缘粗糙度(LER)劣化。
现在参考图2A和2B，分别示出了在制造工艺中的后续阶段的图1A和1B的FeFET器件100的俯视图和截面图。如图2A和2B所示，沉积金属电极108(例如TiN、Ir、TaN等)以覆盖(coat)悬置纳米线106的圆柱形部分，并且还形成为延伸到纳米线106的接触衬垫107中的右边一个。如图2B所示，选择覆盖纳米线106的悬置部分的金属电极108的厚度，使得BOX层104的凹陷部分103的量仍然存在。在纳米线106的悬置部分的大致圆柱形横截面轮廓之后，金属电极108的悬置部分也具有大致圆柱形横截面轮廓(也参见图6C)。
现在参考图3A和3B，分别示出了在制造工艺中的后续阶段的图2A和2B的FeFET器件100的俯视图和截面图。如图3A和3B所示，在FeFET器件100的右侧和左侧(即，源极侧和漏极侧)上形成绝缘体氧化物层110。绝缘体氧化物层110可以包括二氧化硅(SiO2)、氮氧化硅(SiON)、氧化铪(HfO2)或任何其它合适的高κ电介质，并且可以使用物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)或在SiO2和SiON的情况下使用氧化炉在衬垫107上沉积。绝缘体氧化物层110也可以被认为是允许FeFET器件100的有源极区分离的一种类型的隔离物。
现在参考图4A和4B，分别示出了在制造工艺中的后续阶段的图3A和3B的FeFET器件100的俯视图和截面图。如图4A和4B所示，在形成绝缘体氧化层110之后，在金属电极108周围形成铁电氧化层112。在纳米线106的悬置部分和金属电极108的大致圆柱形截面轮廓之后，铁电氧化物层112也具有大致圆柱形截面轮廓(也参见图6C)。在某些实施例中，例如，铁电氧化物层112可以包括HfO2。HfO2可以是未掺杂的或掺杂的。HfO2的掺杂剂可包括例如Si、Al、Zr、La、N等。铁电氧化层112可通过原子层沉积(ALD)或任何其它合适的材料沉积技术形成。在某些实施例中，铁电氧化物层112呈斜方晶相并可具有例如从1nm至30nm厚的范围的厚度。
现在参考图5A和5B，分别示出了在制造工艺中的后续阶段的图4A和4B的FeFET器件100的俯视图和截面图。如图5A和5B所示，在形成铁电氧化层112之后，在铁电氧化层112周围形成界面层114。在纳米线106的悬置部分、金属电极108和铁电氧化物层112的一般为圆柱形的截面轮廓之后，现在形成的界面层114也具有一般为圆柱形的截面轮廓(也参见图6C)。界面层114可以通过原子层沉积(ALD)或任何其它合适的材料沉积技术形成。如上所述，由于通常向其施加高水平的电场，界面层114可能是FeFET器件100的退化源。然而，在本实施例中，因为界面层114在金属电极108和铁电氧化物层112两者的外部，所以其位于距纳米线106的中心轴更大的距离处(即，在更大的半径处)。因此，界面层114将经历相对较小的电场，并且可能较不易于电场劣化。这样，可以改善FeFET器件100的耐久特性。在某些实施例中，界面层114可以具有例如从1nm到5nm厚的范围的厚度。界面层114可以由SiO2、SiON、SiN等中的一个或多个组成。
现在参照图6A、6B和6C，分别示出了在制造工艺中的后续阶段的图5A和5B的FeFET器件100的俯视图、截面图和截面侧视图。如图6A和6B所示，在纳米线106的衬垫部分107上以及界面层114的悬置的圆柱形部分周围沉积多晶硅层116。因此，多晶硅层被沉积以覆盖位于源极区S和漏极区之间的FeFET器件100的沟道区C，如图6B所示。图6C是图6B沿线A-A的截面侧视图，示出了纳米线106、金属电极108、绝缘体氧化物层110、铁电氧化物层112、界面层114和多晶硅层116的同心层。在某些实施例中，在形成多晶硅层116之后，可以对FeFET器件100执行CMP工艺，这可以使多晶硅层116的某些上部平坦化(即，与图6C中示出的多晶硅层116的完美圆形截面描绘相反。
现在参考新的图7，示出了在制造工艺中的后续阶段的图6B的FeFET器件100的截面图。如图7所示，在多晶硅层116中形成源极区710和漏极区712。源极区710和漏极区712是多晶硅层116被重掺杂的区域。掺杂可以通过诸如离子注入、随后退火或来自掺杂源的掺杂剂扩散之类的方法来引入。掺杂多晶硅也可通过各种沉积方法选择性地添加到源极区710和漏极区712。
现在参考新的图8，示出了在制造工艺中的后续阶段的图7的FeFET器件100的截面图。如图8所示，在源极区710、多晶硅层116和漏极区712上沉积电介质膜810。然后，在电介质膜810中开出通孔以进入源极区710、漏极区712和栅极(即，金属电极108)。然后，使用诸如钨的金属来形成源极接触814、漏极接触816和栅极接触818。
现在参考图9，该图示出了根据实施例的制造FeFET器件的方法900。如图9所示，在操作702提供衬底。如上所述，衬底可以是硅衬底，或者可以由任何其它合适的材料构成。在操作904，在衬底上形成掩埋氧化物(BOX)层。在操作906，形成纳米线层。该纳米线层包括在FeFET器件的源极和漏极区侧上的衬垫，以及连接衬垫的纳米线芯。因此，至少在最初，纳米线层具有大致杠铃形状。还应当理解，在制造工艺的这个阶段，纳米线芯具有通常正方形或矩形的横截面区域。而且，在该阶段，纳米线芯由下面的BOX层支撑，并且其尚未悬置。此外，在操作906，从BOX层释放纳米线芯(即，在纳米线芯之下的BOX层中形成凹陷)，使得纳米线芯部现在悬置在FeFET器件的源极和漏极区之间的中间空气中。在某些实施例中，如上所述，在从BOX层释放纳米线芯之后，可以进一步处理纳米线芯以利用退火和/或氧化(或任何其他合适的材料去除工艺)将横截面形状从正方形形状改变为圆形(或通常为圆形)形状。在操作908，形成金属电极以覆盖纳米线芯。在操作910，在FeFET的源极和漏极区域中的纳米线层的至少一部分衬垫上形成绝缘体氧化物层。在操作912，形成铁电氧化物层以覆盖金属电极。在操作914，形成界面层以覆盖铁电氧化物层。因此，界面层以圆柱壳的一般形状形成，并且它在比上述其它层距纳米线芯的中心轴更大的距离处形成。因此，界面层上的电场的大小可以相对于其他层减小，因为该层的半径更大(参见以上对高斯定律的讨论)。在操作916，形成源极和漏极电极。应当理解，在其它实施例中，操作可以不是与以上参考图9所描述的相同的顺序，和/或也可以包括附加的中间操作。
已经出于说明的目的呈现了对各种实施例的描述，并且不旨在是穷举的或限于所公开的实施例。在不背离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域的普通技术人员将是显而易见的。选择本文所使用的术语以最好地解释实施例的原理、实际应用或对市场上存在的技术改进，或使本领域的其他普通技术人员能够理解本文所公开的实施例。

Claims (20)

1.一种铁电场效应晶体管(FeFET)，包括：
掩埋氧化物(BOX)层；
纳米线层，包括
在FeFET的源极和漏极区的BOX层上形成的衬垫，以及
在所述衬垫之间并且在形成于所述BOX层中的凹陷上方延伸的纳米线芯；
覆盖所述纳米线芯的金属电极；
覆盖所述金属电极的铁电层；
涂覆所述铁电层的界面层；以及
形成在所述FeFET的沟道区之上的多晶硅层，所述多晶硅层覆盖所述界面层。
2.根据权利要求1所述的FeFET，其中所述纳米线芯的截面形状是圆形的。
3.根据前述权利要求中任一项所述的FeFET，还包括：
绝缘体氧化物层，其形成在所述FeFET的所述源极区和所述漏极区中，所述绝缘体氧化物层被配置成分隔所述FeFET的有源极区，
其中，所述多晶硅层也形成在所述绝缘体氧化物层的至少一部分上。
4.根据权利要求3所述的FeFET，其中所述绝缘体氧化物层包括选自二氧化硅(SiO2)、氮氧化硅(SiON)、氧化铪(HfO2)和任何其它合适的高κ介电材料中的至少一种。
5.根据前述权利要求中任一项所述的FeFET，其中所述纳米线层包括Si或硅化物中的至少一种。
6.根据前述权利要求中任一项所述的FeFET，其中所述铁电氧化物层包含HfO2基铁电体。
7.根据前述权利要求中任一项所述的FeFET，其中所述铁电氧化物层具有1nm至30nm范围内的厚度。
8.根据前述权利要求中任一项的FeFET，其中所述界面层包含选自SiO2、SiON和SiN的至少一种。
9.根据前述权利要求中任一项所述的FeFET，其中所述界面层具有圆柱壳形状。
10.根据前述权利要求中任一项的FeFET，其中所述界面层具有1nm至5nm范围内的厚度。
11.一种制造铁电场效应晶体管(FeFET)的方法，包括：
形成掩埋氧化物BOX层；
在所述BOX层上形成纳米线层，所述纳米线层包括
在FeFET的源极和漏极区的所述BOX层上形成的衬垫，以及
在所述衬垫之间延伸的纳米线芯；
底切在所述纳米线芯下方的所述BOX层，以从所述BOX层释放所述纳米线芯；
在所述纳米线芯周围形成金属电极；
在所述金属电极周围形成铁电层；
在所述铁电层周围形成界面层；以及
在所述FeFET的沟道区域上方形成多晶硅层，所述多晶硅层覆盖所述界面层。
12.根据权利要求11的制造FeFET的方法，还包括使所述纳米线芯经受退火工艺和氧化工艺中的至少一种，以将所述纳米线芯的形状改变为圆柱形状。
13.根据权利要求11至12中任一项的制造FeFET的方法，还包括：
形成绝缘体氧化物层，所述绝缘体氧化物层形成于所述FeFET的源极与漏极区域中，述绝缘体氧化物层被配置成分隔所述FeFET的有源极区，
其中，所述多晶硅层也形成在所述绝缘体氧化物层的至少一部分上。
14.根据权利要求13所述的制造FeFET的方法，其中所述绝缘体氧化物层包括选自二氧化硅(SiO2)、氮氧化硅(SiON)、氧化铪(HfO2)和任何其它合适的高κ介电材料中的至少一种。
15.根据权利要求11至14中任一项所述的制造FeFET的方法，其中所述纳米线层包含Si或硅化物中的至少一种。
16.根据权利要求11至15中任一项所述的制造FeFET的方法，其中所述铁电氧化物层包含HfO2基铁电体。
17.根据权利要求11至16中任一项所述的制造FeFET的方法，其中所述铁电氧化物层具有1nm至30nm范围内的厚度。
18.根据权利要求11-17中任一项所述的制造FeFET的方法，其中所述界面层包括选自SiO2、SiON和SiN中的至少一种。
19.根据权利要求11至18中任一项所述的制造FeFET的方法，其中所述界面层具有圆柱壳形。
20.根据权利要求11至19中任一项所述的制造FeFET的方法，其中所述界面层具有1nm至5nm范围内的厚度。
CN202180077996.4A 2020-11-20 2021-11-15 具有纳米线芯的铁电场效应晶体管 Pending CN116472614A (zh)

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