CN116470856A - Demodulation weak signal amplifying circuit of optical fiber sensor - Google Patents

Demodulation weak signal amplifying circuit of optical fiber sensor Download PDF

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Publication number
CN116470856A
CN116470856A CN202310480765.9A CN202310480765A CN116470856A CN 116470856 A CN116470856 A CN 116470856A CN 202310480765 A CN202310480765 A CN 202310480765A CN 116470856 A CN116470856 A CN 116470856A
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resistor
operational amplifier
triode
twenty
weak signal
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CN116470856B (en
Inventor
刘爱春
方创首
宋翺
范良龙
刘冠中
尤宝鑫
李严兴
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National Institute of Natural Hazards
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National Institute of Natural Hazards
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/12Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of attenuating means
    • H03F1/13Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of attenuating means in discharge-tube amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K9/00Demodulating pulses which have been modulated with a continuously-variable signal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses an optical fiber sensor demodulation weak signal amplifying circuit which is characterized by comprising a first input end, a second input end, a first output end, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a fifteenth resistor, wherein one end of the first input end is connected with one end of an inverting end and one end of the fifteenth resistor of the first operational amplifier, the same-phase end of the first operational amplifier is connected with one end of the first resistor and one end of the second resistor, and the other end of the first resistor is connected with a power supply.

Description

Demodulation weak signal amplifying circuit of optical fiber sensor
Technical Field
The invention relates to the technical field of switching power supplies, in particular to a demodulation weak signal amplifying circuit of an optical fiber sensor.
Background
Publication No.: CN214959461U discloses a weak signal amplifying circuit of an optical fiber sensor, which comprises an APD-based photoelectric conversion circuit, a first-stage amplifying circuit and a second-stage amplifying circuit which are sequentially connected, wherein the first-stage amplifying circuit is connected with the second-stage amplifying circuit through a capacitor C1, so that the weak current signal collected by the optical fiber sensor is converted and amplified to a voltage signal through the first amplifying circuit, then filtered through the capacitor C1, and finally re-amplified to the voltage signal through the second amplifying circuit in proportion, thereby facilitating the later circuit processing, but the optical signal still has different attenuation according to the environment and the distance after being amplified and transmitted to a carrier stage, is unfavorable for demodulation after entering a terminal, and needs to be corrected.
Disclosure of Invention
Aiming at the technical problems, the invention aims to provide an optical fiber sensor demodulation weak signal amplifying circuit, which comprises a first input end VI1, a second input end VI2, a first output end VO1, a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a fifteenth resistor R15, wherein one end of the first input end VI1 is connected with one end of the first operational amplifier U1, one end of the fifteenth resistor R15 is connected with the same phase end of the first operational amplifier U1, one end of the first resistor R1 and one end of the second resistor R2, the other end of the first resistor R1 is connected with a power supply, the output end of the first operational amplifier U1 is connected with one end of a third resistor R3 and one end of a fourth resistor R4, the other end of the third resistor R3 is connected with the first input end VI1, the other end of the fourth resistor R4 is connected with the inverting end of the second operational amplifier U2 and one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected with the output end of the second operational amplifier U2 and the first output end VO1, the same-phase end of the second operational amplifier U2 is connected with one end of a sixth resistor R6 and one end of a seventh resistor R7, the other end of the seventh resistor R7 is connected with the second input end VI2, and the other end of a fifteenth resistor R15, the other end of the second resistor R2 and the other end of the sixth resistor R6 are connected with a grounding end; the first input end VI1 is an optical carrier signal, the second input end VI2 is a baseband signal, the first output end VO1 is a single-path signal, the third resistor R3, the fifteenth resistor R15 and the first operational amplifier U1 form negative feedback, the first resistor R1 and the second resistor R2 provide bias basic signals for the first operational amplifier U1, the first input end VI1 provides input signals for the inverting end of the first operational amplifier U1, the first operational amplifier U1 amplifies the carrier signal, a subtracting circuit is formed by the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the second operational amplifier U2, and the second operational amplifier U2 finishes amplifying the carrier output of the optical signal from the output signal to the first output end VO 1.
The circuit further comprises a first capacitor C1, a first triode Q1, a second triode Q2, a third NMOS transistor Q3, a fourth triode Q4, a fifth NMOS transistor Q5, a sixth triode Q6, a first diode D1, a second diode D2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a third operational amplifier U3, a fourth operational amplifier U4, one end of the first capacitor C1 and the other end of the seventh resistor R7, one end of the eighth resistor R8, one end of the ninth resistor R9, one end of the fourth operational amplifier U4, the inverting end of the third operational amplifier U3, the same-phase end connection of the eighth resistor R8, the other end connection of the first resistor Q1, the first triode Q1, the emitter of the first triode Q1 and the power supply connection, the base of the first triode Q1 and the tenth resistor R9, the base of the second triode Q2 and the third NMOS transistor Q3, the source of the first diode Q3, the first diode Q1, the anode of the third diode Q3, the third diode Q11, the third diode Q4, the drain electrode of the fourth resistor R4, the third triode Q4, the drain electrode of the third resistor R4, the third resistor R3 and the third triode Q4, the drain electrode of the third resistor Q4 and the third triode Q4, the drain electrode of the third resistor Q4 and the third resistor Q4, the drain electrode of the drain 4 and the drain 4, the drain electrode of the drain 4 and the drain 4 of the third resistor 3 of the third triode Q3 and the drain 4, the emitter of the sixth triode Q6, the cathode of the second diode D2 and the grounding end are connected; the first capacitor C1, the eighth resistor R8 and the ninth resistor R9 are used for delaying and releasing, the third NMOS tube Q3 and the fourth triode Q4 are used for prepositive output of baseband signals and respectively output to the fifth NMOS tube Q5 and the third NMOS tube Q3 which are correspondingly connected with the output ends of the third NMOS tube Q3, the tenth resistor R10 and the twelfth resistor R12 divide voltage signals, the thirteenth resistor R13 and the eleventh resistor R11 are used for base bias of the fourth triode Q4 and the sixth triode Q6, the inverting end of the third operational amplifier U3 and the non-inverting end of the fourth operational amplifier U4 input signals with different amplitudes, the fourth operational amplifier U4 is smaller than the amplitude of the third operational amplifier U3, the fourth operational amplifier U4 is output in a power-on state, the third NMOS tube Q3 is conducted, the drains of the third NMOS tube Q3 and the fifth NMOS tube Q5 are provided with power supplies, the first diode D1 is conducted in the output state of the fourth operational amplifier U4, the second triode Q2 is amplified, the sixth triode Q6 is saturated to enable the fourth triode Q4 to be unbiased, the second triode Q2 is amplified to enable the first triode Q1 to be conducted, the potential of the first capacitor C1 rises to be free of output of the third operational amplifier U3 and the fourth operational amplifier U4 through the integral of the eighth resistor R8 and the first capacitor C1, the sixth triode Q6 is cut off, the potential of the second triode Q2 and the first diode D1 is lower than the bias potential of the fourth triode Q4, the second triode Q2 is conducted to enable the circuit to be continuously integrated to be output by the third operational amplifier U3, the fifth NMOS transistor Q5 is conducted to enable the fourth triode Q4 to be saturated, the second diode D2 is conducted, the sixth triode Q6 is unbiased, the potential of the first capacitor C1 is stepped back, the output of a baseband output signal and a carrier signal is completed, transmission attenuation before synthesis is prevented, and the embodiment can open or remove the second input end VI 2.
Further, the photoelectric device further comprises a fifth photodiode U5, a fourteenth resistor R14, a fifteenth resistor R15 and a seventh photoelectric triode Q7, wherein the fifth photodiode U5 and the seventh photoelectric triode Q7 are packaged in an optical coupling mode, the collector of the seventh photoelectric triode Q7 is connected with one end of the fourteenth resistor R14, the other end of the fourteenth resistor R14 is connected with a power supply, the emitter of the seventh photoelectric triode Q7 is connected with one end of the fifteenth resistor R15, the other end of the fifteenth resistor R15 is connected with a grounding end, the cathode of the fifth photodiode U5 is connected with the grounding end, and the anode of the fifth photodiode U5 is connected with an optical transmitter; the fifth photodiode U5 and the seventh phototransistor Q7 are optically coupled, the fourteenth resistor R14 is current limited, the fifteenth resistor R15 is also used to current-transfer the voltage into the first operational amplifier U1, the fifth photodiode U5 receives the optical transmitter signal, the fifth photodiode U5 and the seventh phototransistor Q7 are coupled out, and the first input VI1 is opened or removed in this embodiment.
The circuit further comprises a sixteenth resistor R16, a seventeenth resistor R17 and an eighteenth resistor R18, wherein one end of the sixteenth resistor R16 is connected with a power supply, the other end of the sixteenth resistor R16 is connected with the inverting end of the third operational amplifier U3 and one end of the seventeenth resistor R17, the other end of the seventeenth resistor R17 is connected with the same-phase end of the fourth operational amplifier U4 and one end of the eighteenth resistor R18, and the other end of the eighteenth resistor R18 is connected with a grounding end; the sixteenth resistor R16, the seventeenth resistor R17 and the eighteenth resistor R18 divide the voltage to provide signals with different magnitudes for the inverting terminal of the third operational amplifier U3 and the non-inverting terminal of the fourth operational amplifier U4.
Further, the circuit further comprises a nineteenth resistor R19 and a twentieth resistor R20, one end of the nineteenth resistor R19 is connected with a power supply, the other end of the nineteenth resistor R19 is connected with the drain electrode of the fifth NMOS tube Q5, the drain electrode of the third NMOS tube Q3 and one end of the twentieth resistor R20, and the other end of the twentieth resistor R20 is connected with a grounding end; the nineteenth resistor R19 and the twentieth resistor R20 supply power to the third NMOS transistor Q3 and the fifth NMOS transistor Q5.
Further, the circuit further comprises a twenty-first resistor R21, one end of the twenty-first resistor R21 is connected with the grid electrode of the third NMOS tube Q3, and the other end of the twenty-first resistor R21 is connected with the ground terminal; the twenty-first resistor R21 and the twenty-third resistor R23 are used for parasitic release in the MOS tube.
Further, the transistor further comprises a twenty-second resistor R22, and two ends of the twenty-second resistor R22 are connected in series between the emitter of the first triode Q1 and the collector of the second triode Q2.
Further, the device further comprises a twenty-third resistor R23, one end of the twenty-third resistor R23 is connected with the grid electrode of the fifth NMOS tube Q5, and the other end of the twenty-third resistor R23 is connected with the ground terminal.
Further, the sixteenth resistor R16 is an adjustable potentiometer; the twenty-second resistor R22 is connected in series for current limiting, the sixteenth resistor R16 can be replaced by an adjustable potentiometer, and the connection method belongs to the prior art and is not described herein.
Compared with the prior art, the invention has the beneficial effects that:
the carrier signal is output through the subtracting circuit after the optical transmitter or other optical signals are converted and amplified, and the baseband signal required by the synthesized signal is output and modulated, so that the attenuation caused by transmission during synthesis is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a demodulation weak signal amplifying circuit of an optical fiber sensor.
Detailed Description
In order that the objects and advantages of the invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, it being understood that the following text is only intended to describe one or more specific embodiments of the invention and is not intended to limit the scope of the invention as defined in the appended claims.
Referring to the drawings, the invention relates to an optical fiber sensor demodulation weak signal amplifying circuit, which comprises a first input end VI1, a second input end VI2, a first output end VO1, a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a fifteenth resistor R15, wherein one end of the first input end VI1 is connected with the inverting end of the first operational amplifier U1 and one end of the fifteenth resistor R15, the non-inverting end of the first operational amplifier U1 is connected with one end of the first resistor R1, one end of the second resistor R2 is connected with the other end of the first resistor R1, the other end of the first resistor R1 is connected with a power supply, the output end of the first operational amplifier U1 is connected with one end of the third resistor R3, one end of the fourth resistor R4 is connected with one end of the third resistor R3, the other end of the third resistor R3 is connected with the first input end VI1, the other end of the fourth resistor R4 is connected with the inverting end of the second operational amplifier U2, one end of the fifth resistor R5 is connected with one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected with the inverting end of the fifth resistor U2, the other end of the fifth resistor R5 is connected with the non-inverting end of the second resistor R2, the other end of the first operational amplifier U2 is connected with the first end of the first end I2 is connected with the other end of the first end I2, the second I2 is connected with the other end I2, the other end I is connected with the other end I2.
Specifically, the circuit further comprises a first capacitor C1, a first triode Q1, a second triode Q2, a third NMOS transistor Q3, a fourth triode Q4, a fifth NMOS transistor Q5, a sixth triode Q6, a first diode D1, a second diode D2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a third operational amplifier U3, a fourth operational amplifier U4, one end of the first capacitor C1 and the other end of the seventh resistor R7, one end of the eighth resistor R8, one end of the ninth resistor R9, one end of the fourth operational amplifier U4, the inverting end of the third operational amplifier U3, the same-phase end of the eighth resistor R8, the other end of the fourth resistor Q1, the emitter of the third triode Q1, the emitter of the fourth resistor Q8, the power supply connection, the first base of the third triode Q2 and the third NMOS transistor Q3, the fourth diode Q1, the fourth resistor R11, the fourth resistor R3, the fourth resistor R4, the fourth resistor R3, the drain of the fourth resistor Q4, the third resistor Q4, the drain of the third resistor Q4, the fourth resistor Q4, the third resistor Q4, the drain of the third resistor Q4, the drain of the fourth resistor Q4, the third resistor Q8, the third resistor Q4, the drain of the fourth resistor Q4, the fourth resistor Q3 and the third resistor Q4, the third resistor Q3 and the drain 4 are connected, the emitter of the sixth triode Q6, the cathode of the second diode D2 and the grounding end are connected.
Specifically, the photoelectric device further comprises a fifth photodiode U5, a fourteenth resistor R14, a fifteenth resistor R15 and a seventh photoelectric triode Q7, wherein the fifth photodiode U5 and the seventh photoelectric triode Q7 are packaged in an optical coupling mode, a collector of the seventh photoelectric triode Q7 is connected with one end of the fourteenth resistor R14, the other end of the fourteenth resistor R14 is connected with a power supply, an emitter of the seventh photoelectric triode Q7 is connected with one end of the fifteenth resistor R15, the other end of the fifteenth resistor R15 is connected with a grounding end, a cathode of the fifth photodiode U5 is connected with the grounding end, and an anode of the fifth photodiode U5 is connected with an optical transmitter.
Specifically, the circuit further comprises a sixteenth resistor R16, a seventeenth resistor R17 and an eighteenth resistor R18, one end of the sixteenth resistor R16 is connected with a power supply, the other end of the sixteenth resistor R16 is connected with the inverting end of the third operational amplifier U3 and one end of the seventeenth resistor R17, the other end of the seventeenth resistor R17 is connected with the same-phase end of the fourth operational amplifier U4 and one end of the eighteenth resistor R18, and the other end of the eighteenth resistor R18 is connected with a grounding end.
Specifically, the circuit further comprises a nineteenth resistor R19 and a twentieth resistor R20, one end of the nineteenth resistor R19 is connected with a power supply, the other end of the nineteenth resistor R19 is connected with the drain electrode of the fifth NMOS tube Q5, the drain electrode of the third NMOS tube Q3 and one end of the twentieth resistor R20, and the other end of the twentieth resistor R20 is connected with a grounding end.
Specifically, the circuit further comprises a twenty-first resistor R21, one end of the twenty-first resistor R21 is connected with the grid electrode of the third NMOS tube Q3, and the other end of the twenty-first resistor R21 is connected with the ground terminal.
Specifically, the transistor further comprises a twenty-second resistor R22, and two ends of the twenty-second resistor R22 are connected in series between the emitter of the first triode Q1 and the collector of the second triode Q2.
Specifically, the device further comprises a twenty-third resistor R23, one end of the twenty-third resistor R23 is connected with the grid electrode of the fifth NMOS tube Q5, and the other end of the twenty-third resistor R23 is connected with the ground terminal.
Specifically, the sixteenth resistor R16 is an adjustable potentiometer.
Specifically, the first input end VI1 is an optical carrier signal, the second input end VI2 is a baseband signal, the first output end VO1 is a single-path signal, the third resistor R3, the fifteenth resistor R15, and the first operational amplifier U1 form a negative feedback, the first resistor R1 and the second resistor R2 provide bias base signals for the first operational amplifier U1, the first input end VI1 provides input signals for an inverting end of the first operational amplifier U1, the first operational amplifier U1 amplifies the carrier signal, a subtraction circuit is formed by the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the second operational amplifier U2 finishes amplifying the carrier wave from the output signals to the first output end VO 1; the first capacitor C1, the eighth resistor R8 and the ninth resistor R9 are used for delaying and releasing, the third NMOS tube Q3 and the fourth triode Q4 are used for prepositive output of baseband signals and respectively output to the fifth NMOS tube Q5 and the third NMOS tube Q3 which are correspondingly connected with the output ends of the third NMOS tube Q3, the tenth resistor R10 and the twelfth resistor R12 divide voltage signals, the thirteenth resistor R13 and the eleventh resistor R11 are used for base bias of the fourth triode Q4 and the sixth triode Q6, the inverting end of the third operational amplifier U3 and the non-inverting end of the fourth operational amplifier U4 input signals with different amplitudes, the fourth operational amplifier U4 is smaller than the amplitude of the third operational amplifier U3, the fourth operational amplifier U4 is output in a power-on state, the third NMOS tube Q3 is conducted, the drains of the third NMOS tube Q3 and the fifth NMOS tube Q5 are provided with power supplies, the first diode D1 is conducted in the output state of the fourth operational amplifier U4, the second triode Q2 is amplified, the sixth triode Q6 is saturated to enable the fourth triode Q4 to be unbiased, the second triode Q2 is amplified to enable the first triode Q1 to be conducted, the potential of the first capacitor C1 rises to enable neither the third operational amplifier U3 nor the fourth operational amplifier U4 to be output through the eighth resistor R8 and the integral of the first capacitor C1, the sixth triode Q6 is cut off, the potential of the second triode Q2 and the first diode D1 is lower than the bias potential of the fourth triode Q4, the second triode Q2 is conducted to enable the circuit to be continuously integrated to the output of the third operational amplifier U3, the fifth NMOS transistor Q5 is conducted to enable the fourth triode Q4 to be saturated, the second diode D2 is conducted, the sixth triode Q6 is unbiased, the potential of the first capacitor C1 is in a step-like manner to fall back, the output of a baseband output signal and a carrier signal is completed, and transmission attenuation before synthesis is prevented, and the embodiment can open or remove the second input end VI 2; the fifth photodiode U5 and the seventh phototransistor Q7 are optically coupled, the fourteenth resistor R14 is current-limited, the fifteenth resistor R15 is also used for converting current into voltage to enter the first operational amplifier U1, the fifth photodiode U5 receives the optical transmitter signal, the fifth photodiode U5 and the seventh phototransistor Q7 are coupled out, and in this embodiment, the first input terminal VI1 is opened or removed; the sixteenth resistor R16, the seventeenth resistor R17 and the eighteenth resistor R18 divide the voltage to provide signals with different amplitude values for the inverting terminal of the third operational amplifier U3 and the non-inverting terminal of the fourth operational amplifier U4; the nineteenth resistor R19 and the twentieth resistor R20 supply power for the third NMOS tube Q3 and the fifth NMOS tube Q5; the twenty-first resistor R21 and the twenty-third resistor R23 are used for parasitic release in the MOS tube; the twenty-second resistor R22 is connected in series for current limiting, the sixteenth resistor R16 can be replaced by an adjustable potentiometer, and the connection method belongs to the prior art and is not described herein.

Claims (9)

1. The optical fiber sensor demodulation weak signal amplifying circuit is characterized by comprising a first input end, a second input end, a first output end, a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a fifteenth resistor, wherein one end of the first input end is connected with an inverting end of the first operational amplifier and one end of the fifteenth resistor, an in-phase end of the first operational amplifier is connected with one end of the first resistor, one end of the second resistor is connected with a power supply, the other end of the first resistor is connected with one end of the third resistor, one end of the fourth resistor is connected with the first input end, the other end of the fourth resistor is connected with an inverting end of the second operational amplifier, one end of the fifth resistor is connected with an output end of the second operational amplifier, the in-phase end of the second operational amplifier is connected with one end of the sixth resistor, one end of the seventh resistor is connected with the other end of the second input end of the seventh resistor, and the other end of the fifteenth resistor is connected with the other end of the second input end of the second resistor, and the other end of the sixth resistor is connected with the other end of the sixth resistor.
2. The optical fiber sensor demodulation weak signal amplification circuit according to claim 1, further comprising a first capacitor, a first triode, a second triode, a third NMOS tube, a fourth triode, a fifth NMOS tube, a sixth triode, a first diode, a second diode, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third operational amplifier, and a fourth operational amplifier, wherein one end of the first capacitor is connected with the other end of the seventh resistor, one end of the eighth resistor, one end of the ninth resistor, one end of the fourth operational amplifier, one end of the inverting terminal of the third operational amplifier, one end of the same phase of the third operational amplifier, one end of the eighth resistor is connected with a first triode collector, one end of the first triode is connected with a power supply, one end of the first triode base is connected with a second triode collector, one end of the second triode base is connected with a third NMOS tube source, one end of the first diode anode, one end of the eleventh resistor, one end of the tenth resistor, one end of the eleventh resistor, one end of the fourth triode collector is connected with the thirteenth resistor, one end of the third NMOS gate is connected with the output end of the fourth operational amplifier, one end of the third NMOS, one end of the third capacitor is connected with the drain of the fourth operational amplifier, one end of the ninth resistor, one end of the inverting terminal of the fourth operational amplifier is connected with the inverting terminal of the fourth operational amplifier, one end of the eighth resistor is connected with the other end of the eighth resistor, one end of the third triode is connected with the other end of the third triode, one end of the emitter is connected with the emitter, one end of the emitter is connected with the power supply, one end of the first triode, one end of the third triode is connected with the anode, one end of the cathode, one end of the third resistor is connected with the output, the cathode of the second diode is connected with the grounding terminal.
3. The optical fiber sensor demodulation weak signal amplification circuit according to claim 1, further comprising a fifth photodiode, a fourteenth resistor, a fifteenth resistor, and a seventh photodiode, wherein the fifth photodiode and the seventh photodiode are optically packaged, a collector of the seventh photodiode is connected to one end of the fourteenth resistor, the other end of the fourteenth resistor is connected to a power supply, an emitter of the seventh photodiode is connected to one end of the fifteenth resistor, the other end of the fifteenth resistor is connected to a ground terminal, a cathode of the fifth photodiode is connected to the ground terminal, and an anode of the fifth photodiode is connected to an optical transmitter.
4. The optical fiber sensor demodulation weak signal amplification circuit according to claim 1, further comprising a sixteenth resistor, a seventeenth resistor and an eighteenth resistor, wherein one end of the sixteenth resistor is connected with a power supply, the other end of the sixteenth resistor is connected with an inverting end of the third operational amplifier and one end of the seventeenth resistor, the other end of the seventeenth resistor is connected with an in-phase end of the fourth operational amplifier and one end of the eighteenth resistor, and the other end of the eighteenth resistor is connected with a grounding end.
5. The optical fiber sensor demodulation weak signal amplification circuit according to claim 2, further comprising a nineteenth resistor and a twentieth resistor, wherein one end of the nineteenth resistor is connected to a power supply, the other end of the nineteenth resistor is connected to a drain of the fifth NMOS transistor, a drain of the third NMOS transistor, one end of the twentieth resistor, and the other end of the twentieth resistor is connected to a ground terminal.
6. The fiber sensor demodulation weak signal amplification circuit according to claim 2, further comprising a twenty-first resistor, wherein one end of the twenty-first resistor is connected with the gate of the third NMOS transistor, and the other end of the twenty-first resistor is connected with the ground.
7. The fiber optic sensor demodulation weak signal amplification circuit according to claim 2, further comprising a twenty-second resistor, wherein two ends of the twenty-second resistor are connected in series between the first triode emitter and the second triode collector.
8. The fiber sensor demodulation weak signal amplification circuit according to claim 2, further comprising a twenty-third resistor, wherein one end of the twenty-third resistor is connected to the gate of the fifth NMOS transistor, and the other end of the twenty-third resistor is connected to the ground.
9. The fiber optic sensor demodulation weak signal amplification circuit according to claim 4, wherein the sixteenth resistor is an adjustable potentiometer.
CN202310480765.9A 2023-04-28 2023-04-28 Demodulation weak signal amplifying circuit of optical fiber sensor Active CN116470856B (en)

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Publication number Priority date Publication date Assignee Title
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