CN116469439A - Computer readable storage medium, method and apparatus for reading data using optimized read voltmeter - Google Patents
Computer readable storage medium, method and apparatus for reading data using optimized read voltmeter Download PDFInfo
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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Abstract
The invention relates to a computer readable storage medium, a method and a device for reading data by using an optimized read voltmeter, wherein the method for reading data by using the optimized read voltmeter is executed by a microcontroller unit of a flash memory controller and comprises the following steps: determining a set of read voltages of a specific memory cell type according to current environmental parameters of the NAND flash memory module and contents of an optimized read voltage table, wherein the optimized read voltage table comprises a plurality of records, each record comprises a set of read voltage parameters and environmental parameters to which the set of read voltage parameters are related; and reading data from a page of the NAND flash memory module at the set of read voltages. By optimizing the use of the read voltmeter, the number of times the read retry mechanism is initiated may be reduced.
Description
Technical Field
The present invention relates to a storage device, and more particularly, to a computer readable storage medium, a method and apparatus for reading data using an optimized read voltmeter.
Background
Flash memory is generally classified into NOR flash memory and NAND flash memory. The NOR flash memory is a random access device, and a central processing unit (Host) can provide any address accessing the NOR flash memory on an address pin, and timely obtain data stored on the address from a data pin of the NOR flash memory. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory, like NOR flash memory, cannot access any random addresses, but instead the cpu needs to write serial byte values into the NAND flash memory for defining the type of Command (Command) (e.g., read, write, erase, etc.), and the address used on the Command. The address may point to one page (the smallest block of data for a write operation in flash) or one block (the smallest block of data for an erase operation in flash). Improving the accuracy of data reading is always an important issue affecting the overall performance of the flash memory controller. The invention provides a computer readable storage medium, a method and a device for reading data by using an optimized reading voltmeter, which are used for improving the reading accuracy of the data.
Disclosure of Invention
In view of this, how to alleviate or eliminate the above-mentioned drawbacks of the related art is a real problem to be solved.
The invention relates to a method for reading data using an optimized read voltmeter, executed by a microcontroller unit of a flash memory controller, comprising: determining a set of read voltages of a specific memory cell type according to current environmental parameters of the NAND flash memory module and contents of an optimized read voltage table, wherein the optimized read voltage table comprises a plurality of records, each record comprises a set of read voltage parameters and environmental parameters to which the set of read voltage parameters are related; and reading data from a page of the NAND flash memory module at the set of read voltages.
The invention also relates to a computer readable storage medium for storing program code that can be loaded and executed by a microcontroller unit of a flash memory controller, and which when executed by said microcontroller unit implements a method of using an optimized read voltmeter as described above for reading data.
The invention also relates to a device for reading data by optimizing a reading voltmeter, comprising: the flash memory interface is coupled with the NAND flash memory module; and a microcontroller unit coupled to the flash memory interface. The microcontroller unit is used for determining a group of read voltages of a specific storage unit type according to the current environment parameters of the NAND flash memory module and the content of an optimized read voltage table, wherein the optimized read voltage table comprises a plurality of records, each record comprises a group of read voltage parameters and the environment parameters related to the group of read voltage parameters; and driving the flash interface to read data from a page of the NAND flash module at the set of read voltages.
One of the advantages of the above embodiment is that the number of times the read retry mechanism is initiated can be reduced by optimizing the use of the read voltmeter.
Other advantages of the present invention will be explained in more detail in connection with the following description and accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application.
Fig. 1 is a schematic diagram of a network environment according to an embodiment of the invention.
Fig. 2 is a block diagram of an arithmetic device according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a NAND flash memory module according to an embodiment of the invention.
Fig. 4 is a block diagram of a cloud storage system according to an embodiment of the invention.
FIG. 5 is a flow chart of a data reading method according to some embodiments.
Fig. 6 is a flowchart of a data reading method according to an embodiment of the invention.
FIG. 7 is a sequence diagram of the collection and reporting of read performance data according to an embodiment of the present invention.
FIG. 8 is a sequence diagram of updating an optimized read voltmeter according to an embodiment of the present invention.
Wherein the symbols in the drawings are briefly described as follows:
100: a network; 112: a personal computer; 114: a mobile telephone; 116: a tablet computer; 120: a cloud storage system; 130: a server; 20: an arithmetic device; 210: a processing unit; 212: a data collection and feedback module; 214: a form update starting module; 220: NAND flash memory storage; 230: a NAND flash memory module; 240: a flash memory controller; 242: a data reading monitoring module; 244: a reporting module; 246: a table updating module; 250: a random access memory; 260: a communication interface; 310: a flash memory interface; 331: an interface; 333#0 to 333#15: a NAND flash memory cell; ch#0 to ch#3: a channel; ce#0 to ce#3: a start signal; 410: a processing unit; 412: a data collection and feedback module; 414: a form update starting module; 420#0 to 420#n: NAND flash memory storage (solid state disk); 430: a RAID controller; 450: a random access memory; 460: a communication interface; S510-S550: the method comprises the steps of; s605 to S610: the method comprises the steps of; 710: a request; 720: replying; 730: a data reading transaction; 750: a read efficiency data processing module; 810: a form transfer module; 820. 830: and (5) requesting.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operation processes, components, and/or groups, but do not preclude the addition of further features, values, method steps, operation processes, components, groups, or groups of the above.
In the present invention, terms such as "first," "second," "third," and the like are used for modifying elements of the claims, and are not intended to denote a prior order, a first order, or a sequence of steps of a method, for example, for distinguishing between elements having the same name.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.
The invention provides a mechanism for dynamically updating and optimizing a read voltmeter (Optimization Read Voltage (RV) Table, which can be applied to operation equipment in a network environment and a NAND flash memory storage device in a cloud storage system, and the optimized read voltmeter is used in the process of reading data from the NAND flash memory storage device. The NAND flash memory storage device may be a NAND flash memory card, a NAND flash memory module, a solid state disk (Solid State Drive, SSD), or the like. Referring to fig. 1, the computing device may be a personal computer 112, a mobile phone 114, a tablet computer 116, a notebook computer (Laptop PC), a digital camera, a digital video camera, or other consumer electronics product equipped with a NAND flash memory card, a NAND flash memory module, a solid state disk, or any combination thereof, for storing various user data, such as digital files, high resolution images, video files, and the like. The computing device may upload various user data to the cloud storage system 120 via the network 100 and store the user data, and download the user data from the cloud storage system 120, so that various applications may be loaded and processed. The cloud storage system 120 may include one or more redundant arrays of independent disks (Redundant Array of Independent Disks, RAID), and each redundant array of independent disks includes a plurality of solid state disks.
Referring to fig. 2, an embodiment of a hardware architecture of the computing device 20 (e.g., personal computer 112, mobile phone 114, tablet 116) is shown. The processing unit 210, the NAND flash memory storage 220, the random access memory (Random Access Memory, RAM) 250, and the communication interface 260 may be provided in the operation device 20, and connected to each other through a bus architecture. The processing unit 210 (also referred to as a Host Side) may be implemented in a variety of ways, such as using general purpose hardware (e.g., a single processor, a multiprocessor with parallel processing capabilities, a graphics processor, or other computing-capable processor), and provides the functionality described below when executing software and/or firmware instructions. RAM 250 may be implemented as dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), or a combination of both, for storing data, e.g., variables, tables, etc., that are needed during execution. The communication interface 260 may be a local network (Local Area Network, LAN) module, a wireless local network module, a bluetooth module, a 2G/3G/4G/5G telecommunications module, or any combination of the above modules for communicating with the server 130 in the flash research laboratory over the network 100. The NAND flash memory Device 220 (also referred to as a Device Side) includes a NAND flash memory module 230 and a flash controller 240, wherein the flash controller 240 is configured to access data in the NAND flash memory module 230 according to a command issued by the processing unit 210. In detail, the flash controller 240 may include a microcontroller unit (Microcontroller Unit, MCU) and cooperate with other elements in the flash controller 240 to perform specific functions when appropriate program code is loaded and executed. For example, the MCU drives a Host Interface (Host Interface) to receive a Host command and necessary user data from the processing unit 210, and drives a Flash Interface (Flash Interface) according to the Host command to read data from a specified address of the NAND Flash module 230, write data to the specified address of the NAND Flash module 230, erase data of the specified address of the NAND Flash module 230, and the like. The MCU performs background operations to enhance the performance of the NAND flash memory module 230, such as garbage collection (Garbage Collection, GC) procedures, wear-Leveling (WL) procedures, and the like.
The processing unit 210 and the host interface of the flash controller 240 may communicate with each other through a communication protocol such as universal serial bus (Universal Serial Bus, USB), advanced technology attachment (advanced technology attachment, ATA), serial advanced technology attachment (serial advanced technology attachment, SATA), peripheral component interconnect express (peripheral component interconnect express, PCI-E), universal flash storage (Universal Flash Storage, UFS), embedded multimedia Card (eMMC), and the like. The flash interface of the flash controller 240 and the NAND flash module 230 may communicate with each other in a Double Data Rate (DDR) communication protocol, such as open NAND flash (Open NAND Flash Interface, ONFI), double Data Rate switch (DDR Toggle), or other communication protocols. The flash interface uses a plurality of electronic signals to coordinate Data and command transfer between the flash controller 240 and the NAND flash module 230, including Data lines (Data lines), clock signals (Clock signals) and Control signals (Control signals). The data line can be used for transmitting commands, addresses, read-out and written data; the control signal lines may be used to transmit control signals such as Chip Enable (CE), address fetch Enable (Address Latch Enable, ALE), command fetch Enable (Command Latch Enable, CLE), write Enable (WE), and the like.
The NAND flash memory module 230 provides a large amount of memory space, typically hundreds of Gigabytes (GB), even multiple Terabytes (TB), for storing a large amount of user data, such as high resolution pictures, movies, etc. The NAND flash memory module 230 includes a control circuit and a memory array, wherein the memory Cells in the memory array may be configured as single-layer Cells (Single Level Cells, SLCs), multi-layer Cells (Multiple Level Cells, MLCs), triple-layer Cells (Triple Level Cells, TLCs), quad-layer Cells (QLCs), or any combination thereof. Referring to fig. 3, the interface 331 in the NAND flash memory module 230 may include four input/output channels (I/O channels, hereinafter referred to as channels) ch#0 to ch#3, each of which connects four NAND flash memory units, for example, the channel ch#0 connects the NAND flash memory units 333#0, 333#4, 333#8, and 333#12. Each NAND flash memory cell may be packaged as a separate chip (die). The flash interface 310 of the flash controller 240 may activate the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the activation signals ce#0 to ce#3 through the interface 331, and then read user data from the activated NAND flash memory units or write user data to the activated NAND flash memory units in a parallel manner.
When each memory cell in a physical block is an SLC and is capable of recording two states, each physical word line stores a single page of user data, which requires a Read Voltage (RV) to determine which of the two states the charge in each SLC is. When each memory cell in a physical block is an MLC capable of recording four states, each physical wordline stores double pages (including most significant bit page-Most Significant Bit Page, and least significant bit page-Least Significant Bit Page) of user data, which requires three read voltages to determine which of the four states the charge in each MLC is. When each memory cell in one physical block is TLC capable of recording eight states, each physical word line stores three pages (including the most significant bit page, the middle significant bit page-Center Significant Bit Page, and the least significant bit page) of user data, which requires seven read voltages to determine which of the eight states the charge in each TLC is. When each memory cell in one physical block is a QLC and sixteen states can be recorded, each physical word line stores four pages (including top-valid bit page-Top Significant Bit Page, most-valid bit page, middle-valid bit page, and least-valid bit page) of user data, which requires fifteen read voltages to determine which of sixteen states the charge in each QLC is.
The manufacturer of the NAND flash memory module 230 provides a recommended read voltage for different types of physical pages so that the flash controller 240 can read data from the memory cells of the NAND flash memory module 230 accordingly. For example, the manufacturer of the NAND flash memory module 230 may provide the following proposed read voltages {0.8V,1.4V,2.4V,3.2V,3.9V,4.8V,5.7V }, for indicating that the flash memory controller 240 may read data of the most, middle, and least significant bit pages from memory cells configured as three-layer cells.
Referring to fig. 4, an embodiment of a hardware architecture of the cloud storage system 120 is shown. The processing unit 410, the random access memory 450, the communication interface 460, and the RAID controller 430 may be disposed in the cloud storage system 120, and the RAID controller 430 connects the plurality of solid state disks 420#0 to 420#n (may be generally referred to as NAND flash memory storage devices). The processing unit 410, the random access memory 450, the communication interface 460, and the solid state disks 420#0 to 420#n are similar to the processing unit 210, the random access memory 250, the communication interface 260, and the solid state disk 220 of fig. 2, respectively, and are not described again for brevity. RAID controller 430 may organize solid state disks 420#0 through 420# into RAID groups. In some embodiments, two or more (n > =2) solid state disks may be configured as RAID 1, forming a data mirror (data mirroring), but not including parity or stripe partitioning (striping). Data is written into at least two solid state disks in a uniform manner, so that a group of mirrored solid state disks is generated. Any one of the solid state disks in the group can service the read request. In other embodiments, two or more (n > =2) solid state disks may be configured as RAID 2, forming a bit-level stripe, collocated with a specific Hamming-code parity (Hamming-code). And calculating the Hamming code parity check according to the corresponding bits in different solid state disks, and storing the Hamming code parity check in at least one solid state disk of the parity check. In still other embodiments, three or more (n > =3) solid state disks may be configured as RAID 5, forming a stripe of block-level (chunk-level), collocated with distributed parity. The parity check information is dispersed in the solid state disk, so that the solid state disk can still normally operate under the condition of lacking one solid state disk. When a single solid state disk is damaged, the missing data can be calculated from the scattered parity check, so that the data cannot be lost. In still other embodiments, four or more (n > =4) solid state disks may be configured as RAID 6, forming a block-level stripe, collocated with twice the distributed parity. The parity check information is dispersed in the solid state disk, so that the solid state disk can still normally operate under the condition of lacking two solid state disks. Double parity provides error tolerance for failure of up to two solid state disks.
As the period of programming/erasing increases, the ambient temperature changes, the number of times of storage increases when the NAND flash memory module 230 is operated, the stability of the data stored in the NAND flash memory module 230 may be deteriorated. In the previous embodiment, the manufacturer of the NAND flash memory module 230 provides a Read Retry Table (Read Retry Table) in which sets of RV parameters are recorded in addition to the proposed Read voltages described above. The RV parameters of each group are associated with an extreme case. In the read retry mechanism, flash controller 240 repeatedly performs a loop until the read data is correct, or until all RV parameter sets have been tried. The read retry mechanism appears to be a Blind-try (try) procedure. Referring to the flowchart of the data reading method shown in fig. 5, the method is executed by the MCU in the flash controller 240, and is used to drive the flash interface in the flash controller 240 according to the host read command sent by the host side, so as to read data from one or more designated pages of the NAND flash memory module 230, which is described in detail as follows:
step S510: the drive flash interface reads data and a cyclic redundancy check Code (Cyclic Redundancy Check, CRC Code) from a first or next designated page of the NAND flash module 230 at a recommended read voltage provided by the manufacturer of the NAND flash module 230.
Step S520: it is determined whether the read page is a non-error-replying (Uncorrectable Error Correction Code, UECC) page. If so, the flow continues with the process of step S530; otherwise, the flow proceeds to the process of step S550. In detail, the MCU can be matched with the CRC code to judge whether the data of the read page is correct or not. If the check is passed, this page is represented as the correct page. If the check cannot be passed, the MCU initiates an error correction procedure, attempting to correct the error bits in the read page by an error correction code (Error Correcting Code, ECC). If the correction is successful, this page is represented as the correct page. If the error correction procedure fails, this page is represented as a UECC page.
Step S530: a read retry mechanism is initiated. The read retry mechanism repeatedly performs a loop until the read data is correct or all RV parameter sets have been tried. The cycle comprises the following operations: adjusting the read voltage according to a set of RV parameters; reading data with the adjusted read voltage; and judging whether the read data is correct.
Step S540: and judging whether the read page is still a UECC page. If so, ending the flow and entering a device error state; otherwise, the flow proceeds to the process of step S550. In detail, when all RV parameter sets have been tried and the error bits in the read page cannot be corrected, it is determined that the read page is a UECC page.
Step S550: and judging whether the read page is the last designated page or not. If so, the flow ends and enters the state of the next operation; otherwise, the flow proceeds to the process of step S510 for reading the next designated page.
However, because the RV parameters in the read retry table are associated with extreme cases, the success rate of the read retry mechanism is low. In addition, excessive Iterations (Iterations) of the adjustment and verification loop will momentarily slow down the read speed, resulting in poor read efficiency.
In order to avoid starting the read retry mechanism as much as possible, embodiments of the present invention propose a plurality of optimized read voltmeters and a method of using the optimized read voltmeters. The manufacturer of the NAND flash memory storage device 220 may store these optimized read voltage tables at designated locations of the NAND flash memory module 230 prior to shipment. Each optimized read voltmeter is associated with a memory cell type, comprising a plurality of records, each record comprising a set of RV parameters (which may be RV offset values or otherwise represented), and a set of environmental parameters to which the set of RV parameters are associated. For example, when the memory cells in the NAND flash memory module 230 may be configured as SLC, MLC, or TLC, SLC, MLC, and TLC optimized read voltage tables may be stored in the NAND flash memory module 230. Each RV offset value may be represented using an Adjustment Scale (Adjustment Scale), e.g., "0" for no Adjustment, "+1" for 0.01V increase, "+2" for 0.02V increase, "-1" for 0.01V decrease, "-2" for 0.02V decrease, and so on. The environment parameters may include Data durability (Data Endurance), data Retention (Data Retention), temperature volatility (Temperature Swing), read disturb (Read disturb), NAND Flash identification code (NAND Flash ID), and the like. The data endurance indicates the degree of usage, which can be expressed using the average erase count (Average of Erase Count), which is the average of the erase counts of all physical blocks. Data retention indicates the length of Time that data can be stored, which can be expressed using a Time Scale (Time Scale), for example, "0.25" for less than or equal to one quarter, "0.5" for less than or equal to half a year but greater than one quarter, "1" for less than or equal to one year but greater than half a year, and so on. Temperature fluctuation refers to the temperature range at which operation is performed and may be represented using a temperature scale (Temperature Scale), for example, "0" represents 0 ℃ to 9.99 ℃, and "1" represents 10 ℃ to 19.99 ℃, and so on. The read disturb indicates the read frequency, which can be expressed using an average number of reads (Average of Read Count), which is the average of the number of reads for all physical blocks. The NAND flash memory identification code carries information about the manufacturer, the type of product, the date of manufacture, etc. Taking MLC optimized read voltmeter as an example, the data structure of each record may be represented as { RV0, RV1, RV2, EP0, EP1, EP2, EP3, EP4}, where "RV0" to "RV2" represent 3 voltage offset values, and "EP0" to "EP4" represent environmental parameters such as data endurance, data retention, temperature volatility, read disturb, NAND flash identification code, respectively. Taking TLC optimized read voltmeter as an example, the data structure of each record may be represented as { RV0, RV1, RV2, RV3, RV4, RV5, RV6, EP0, EP1, EP2, EP3, EP4}, where "RV0" to "RV6" represent 7 voltage offset values, and "EP0" to "EP4" represent environmental parameters such as data endurance, data retention, temperature volatility, read disturb, NAND flash identification code, etc.
In addition to optimizing the read voltage table, the flash controller 240 also stores the current environmental parameters locally in the NAND flash memory module 230 in response to the current operating state of the NAND flash memory module 230.
Referring to the flowchart of the data reading method shown in fig. 6, the method is performed by the MCU in the flash controller 240, and is described in detail as follows:
step S605: a set of read voltages for a particular memory cell type is determined based on the current environmental parameters of the NAND flash memory module 230 and the contents of the optimized read voltage table. In detail, before actually reading the data (i.e., before entering a cycle of actually reading the data), the MCU first acquires the current environmental parameter of the NAND flash memory module 230, and searches a corresponding optimized read voltmeter for each memory cell type for acquiring a set of RV offset values adapted to the current environmental parameter. The particular memory cell type may be SLC, MLC, TLC, QLC, etc. The current environmental parameters of the NAND flash memory module 230 may include data endurance, data retention, temperature volatility, read disturb, NAND flash memory identification code, and the like. The data endurance, data retention, temperature volatility, and read disturb of the NAND flash memory module 230 may be expressed in terms of a current average erase count of the NAND flash memory module 230, a length of time for storing data therein, a current operating temperature range, and a current average read count, respectively. The MCU may first filter out records of NAND flash memory identification codes not belonging to the NAND flash memory module 230 from the optimized read voltmeter; finding out the matching record with the environmental parameter closest to the current environmental parameter in the left record of the optimized reading voltmeter; and generating the set of read voltages according to the content in the matching record. The MCU may apply any similarity comparison algorithm, decision tree, rule of thumb (heuristics), etc. known to those skilled in the art for finding a set of environmental parameters closest to the current environmental parameters among the sets of environmental parameters, and the present invention is not limited thereto.
Then, a read voltage is determined based on the set of RV offset values that are searched. The read voltage can be determined using the following equation (1):
RV adj,i ＝RV rcm,i +RV off,i
wherein RV is provided with adj,i Representing the ith final determined read voltage, RV rcm,i Representing the ith recommended read voltage, RV, provided by the manufacturer of NAND flash memory module 230 off,i Represents the i-th RV offset value searched, i is from 0 to RV max Integer between-1, RV max Representing the total number of RV offset values for the corresponding memory cell types (e.g., the total number of RV offset values corresponding to TLC is 7). Suppose the recommended read voltage for reading a TLC block is {0.8V,1.4V,2.4V,3.2V,3.9V,4.8V,5.7V }, and the searched RV offset value is { +1,0, -2}: the final read voltages were {0.81V,1.41V,2.4V,3.2V,3.9V,4.8V,5.68V }. Optimizing read powerThe pressure gauge and the use thereof not only can reduce Bit Error Rate (BER), but also can avoid frequent start-up of a read retry mechanism.
Step S610: the flash interface is driven to read the data and CRC code from the first or next designated page of the NAND flash memory module 230 at the determined read voltage.
The technical details of steps S520 to S550 in fig. 6 can be described with reference to the corresponding paragraphs in fig. 5, and are not repeated for brevity.
However, the set of RV parameters of the optimized read voltmeter stored in NAND flash memory module 230 may not be suitable under certain operating conditions or certain operating conditions may be outside of the range of the environmental parameters of the plurality of sets previously provided in the optimized read voltmeter. In order to solve the above-mentioned problems, the embodiments of the present invention further provide a dynamic update method of an optimized read voltmeter, which is used for modifying RV parameters corresponding to a specific set of environment parameters in a specified optimized read voltmeter, or newly adding a plurality of sets of environment parameters corresponding to the most recently detected environment parameters and RV parameter sets corresponding to the same to the specified optimized read voltmeter.
Refer to the block diagram of fig. 2. After one or more host Read commands are successfully executed, the MCU in the flash controller 240 generates Read-performance Data (READ-performance Data) when loading and executing the program code of the Data Read monitor module (Data-Read Monitoring Module) 242, and stores the Read-performance Data in the RAM in the flash controller 240 as a Data Read Transaction (Data-Read Transaction). The read performance data includes current environmental parameters of the NAND flash memory module 230, a specific memory cell type and a Bit Error Rate (BER), which is used to measure the quality of the data read transaction, with higher values representing lower quality.
Reference is made to the block diagram of fig. 2 and the sequence diagram of fig. 7. To complete the collection of the read performance data, the MCU in the flash controller 240 may load and execute program code of a Reporting Module 244 in the background for monitoring whether the processing unit 210 requests the read performance data. The processing unit 210 may periodically load and execute program code of a Data Collection-and-feedback Module (Data Collection-and-feedback Module) 212 for issuing requests 710 for reading performance Data to the reporting Module 244 via the internal bus. When the return module 244 receives the request 710, it reads all data read transactions from the RAM in the flash controller 240 and transmits a reply 720 carrying the data read transaction 730 to the data collection and feedback module 212 via the internal bus. After the specified number of data read transactions 730 have been collected by the data collection and feedback module 212, the data read transactions 730 are transmitted over the network 100 to a read performance data processing module 750 executed by the server 130 in the flash research laboratory. The engineer may select a data read transaction whose BER exceeds a Threshold (Threshold) through a human-machine interface provided by the read performance data processing module 750 and use an artificial intelligence engine, statistical tool or other algorithm to identify poorly set environmental parameters based on the content of the selected data read transaction. The engineer can design and experiment according to the content of the poorly set environmental parameters, and modify the corresponding optimized reading voltmeter according to the experimental result. The engineer may modify a record in the corresponding optimized read voltage table for changing the RV offset value for the specified group associated with the environmental parameter for the specified group. Alternatively, the engineer may add a new record in the corresponding optimized read voltmeter containing a new set of environmental parameters and their associated set of RV offset values.
Reference is made to the block diagram of fig. 2 and the sequence diagram of fig. 8. To complete the updating of the optimized read voltmeter, the processing unit 210 may load and execute the program code of the Table update initiation module (Table-update Triggering Module) 214 in the background for listening to whether the server 130 in the flash research laboratory requests updating of the optimized read voltmeter; the MCU in the flash controller 240 may load and execute program code of a Table update Module (Table-update Module) 246 in the background for listening to whether the processing unit 210 requests an update of an optimized read voltmeter for a particular memory cell type. After the update of the optimized read voltmeter of the specific storage unit type is completed, the processing unit of the server 130 sends a request 820 for updating the optimized read voltmeter of the specific storage unit type to the table update start module 214 through the network 100 when loading and executing the program code of the table transfer module (Table Delivery Module), wherein the identification code of the optimized read voltmeter to be updated and the record of the updated optimized read voltmeter are carried. When the table update initiation module 214 receives the request 820, it sends a request 830 for updating the optimized read voltage table of the specific memory cell type to the table update module 246 via the internal bus, wherein the identifier code of the optimized read voltage table to be updated (including the information of the specific memory cell type) is carried, and the record of the updated optimized read voltage table is transferred to the table update module 246. When the table update module 246 receives the request 830 to update the optimized read voltmeter for the specific memory cell type and the record of the updated optimized read voltmeter, it drives the flash interface in the flash controller 240 to write the record of the updated optimized read voltmeter to the designated location in the NAND flash module 230, so that the data read operation of the specific memory cell type can adjust the RV voltage with reference to the updated optimized read voltmeter. For technical details of the data read operation of the optimized read voltmeter after updating using a particular memory cell type, reference is made to the relevant description of fig. 6.
Although the above paragraphs illustrate the functions to be performed by the data gathering and feedback module 212 and the form update initiation module 214 executing in the computing device 20 of fig. 2 and the interactions with the server 130 in the flash research laboratory, the technical details described therein are equally applicable to the data gathering and feedback module 412 and the form update initiation module 414 executing in the cloud storage system 120 of fig. 4. Any one of the solid state disks 420#0 to 420#n of the cloud storage system 120 may be implemented by the NAND flash memory storage device 220 in fig. 2, and thus, the flash memory controller of any one of the solid state disks 420#0 to 420#n may perform the functions of the data reading monitoring module 242, the reporting module 244, and the table updating module 246 as described above.
All or part of the steps in the method described in the present invention may be implemented by a computer program, such as an application program in the host side, a firmware translation layer (Firmware Translation Layer, FTL) in the device side, a driver for specific hardware, or a software program. In addition, other types of programs as shown above may also be implemented. Those skilled in the art will appreciate that the methodologies of the embodiments of the present invention are capable of being written as program code and that these are not described in the interest of brevity. A computer program implemented according to a method of an embodiment of the invention may be stored on a suitable computer readable storage medium, such as a DVD, CD-ROM, U-disk, hard disk, or may be located on a network server accessible via a network, such as the internet, or other suitable medium.
Although the components described above are included in fig. 2-4, it is not excluded that many more additional components may be used to achieve a better technical result without violating the spirit of the invention. In addition, although the flowcharts of fig. 5 to 6 are performed in the order specified, the order among these steps may be modified by those skilled in the art without violating the spirit of the invention, and therefore, the present invention is not limited to using only the order as described above. Furthermore, one skilled in the art may integrate several steps into one step or perform more steps in addition to these steps, sequentially or in parallel, and the invention should not be limited thereby.
The foregoing is only illustrative of the preferred embodiments of the present invention, and it is not intended to limit the scope of the invention, since further modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is therefore defined by the appended claims.
Claims (13)
1. A method of using an optimized read voltmeter to read data, performed by a microcontroller unit of a flash memory controller, the method of using an optimized read voltmeter to read data comprising:
determining a set of read voltages of a specific memory cell type according to current environmental parameters of the NAND flash memory module and contents of an optimized read voltage table, wherein the optimized read voltage table comprises a plurality of records, each record comprises a set of read voltage parameters and environmental parameters to which the set of read voltage parameters are related; and
data is read from a page of the NAND flash memory module at the set of read voltages.
2. The method of claim 1, wherein the particular memory cell type is a single-tier cell, a multi-tier cell, a triple-tier cell, or a quad-tier cell.
3. The method of using an optimized read voltmeter for reading data of claim 1, comprising:
filtering records of NAND flash memory identification codes which do not belong to the NAND flash memory module from the optimized reading voltmeter;
finding out the matching record with the environmental parameter closest to the current environmental parameter in the left records of the optimized read voltmeter; and
generating the set of read voltages according to the set of read voltage parameters in the matching record.
4. The method of claim 1, wherein the current environmental parameters include a current average erase count of the NAND flash memory module, a length of time for storing data therein, a current temperature range at run time, and a current average read count; and the environmental parameters in each record comprise average erasing times, storage time length of data, temperature range in operation and average reading times.
5. The method of claim 1, wherein the set of read voltage parameters includes a plurality of read voltage offset values, the set of read voltages determined using the formula:
RV adj,i ＝RV rcm,i +RV off,i
RV adj,i representing the ith read in the set of read voltagesVoltage taking RV rcm,i Representing the ith recommended read voltage, RV, provided by the manufacturer of the NAND flash memory module off,i Representing the ith read voltage offset value in the matching record, i being 0 to RV max Integer between-1, RV max Representing the total number of RV offset values for that particular memory cell type.
6. The method of using an optimized read voltmeter for reading data of claim 1, comprising:
when the page is judged as not being capable of replying to the wrong page, a read retry mechanism is started for repeatedly executing a loop until the read data is correct or until all sets of read voltage parameters in the read retry table are tried.
7. A computer readable storage medium storing program code executable by a microcontroller unit of a flash memory controller, wherein the program code when executed by the microcontroller unit implements the method of using an optimized read voltmeter to read data as claimed in any of claims 1 to 6.
8. An apparatus for reading data using an optimized read voltmeter, comprising:
the flash memory interface is coupled with the NAND flash memory module; and
the microcontroller unit is coupled with the flash memory interface and is used for determining a group of read voltages of a specific storage unit type according to the current environment parameters of the NAND flash memory module and the content of an optimized read voltage table, wherein the optimized read voltage table comprises a plurality of records, each record comprises a group of read voltage parameters and the environment parameters related to the group of read voltage parameters; and driving the flash interface to read data from a page of the NAND flash module at the set of read voltages.
9. The apparatus for reading data using an optimized read voltmeter of claim 8, wherein the particular memory cell type is a single-tier cell, a multi-tier cell, a triple-tier cell, or a quad-tier cell.
10. The apparatus for reading data using an optimized read voltmeter of claim 8, wherein said microcontroller unit filters records of NAND flash identification codes not belonging to said NAND flash memory module from said optimized read voltmeter; finding out the matching record with the environmental parameter closest to the current environmental parameter in the left records of the optimized read voltmeter; and generating the set of read voltages according to the set of read voltage parameters in the matching record.
11. The apparatus for reading data using an optimized read voltmeter according to claim 8, wherein the current environmental parameters include a current average erase count of the NAND flash memory module, a length of time for storing data therein, a current temperature range at run time, and a current average read count; and the environmental parameters in each record comprise average erasing times, storage time length of data, temperature range in operation and average reading times.
12. The apparatus for reading data using an optimized read voltmeter of claim 8, wherein the set of read voltage parameters comprises a plurality of read voltage offset values, the set of read voltages determined using the formula:
RV adj,i ＝RV rcm,i +RV off,i
RV adj,i representing the ith read voltage of the set of read voltages, RV rcm,i Representing the ith recommended read voltage, RV, provided by the manufacturer of the NAND flash memory module off,i Representing the ith read voltage offset value in the matching record, i being 0 to RV max Integer between-1, RV max Representing the total number of RV offset values for that particular memory cell type.
13. The apparatus for using an optimized read voltmeter to read data as claimed in claim 8, wherein said micro controller unit initiates a read retry mechanism for repeatedly performing a loop until the read data is correct or until all sets of read voltage parameters in the read retry table have been tried when said page is determined to be unable to reply to an erroneous page.
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