CN116456712A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
- Publication number
- CN116456712A CN116456712A CN202210010113.4A CN202210010113A CN116456712A CN 116456712 A CN116456712 A CN 116456712A CN 202210010113 A CN202210010113 A CN 202210010113A CN 116456712 A CN116456712 A CN 116456712A
- Authority
- CN
- China
- Prior art keywords
- word line
- layer
- active region
- substrate
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Landscapes
- Semiconductor Memories (AREA)
Abstract
The application discloses a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a first word line structure in a first direction in a substrate; etching the substrate downwards to form a columnar active region, wherein the depth of the columnar active region is greater than that of the first word line structure; filling an isolation layer between the columnar active areas; etching the first word line structure and the isolation layer to form a first word line groove in a first direction, wherein the first word line groove penetrates through the columnar active region; a low dielectric constant layer, a first conductive layer and an insulating layer are formed in the first word line trench, and the first conductive layer is electrically connected with the first word line structure. Since the first word line structure is not present in the isolation layer; thus, the adjacent memory cells of the semiconductor structure are separated by the filled isolation layer and the low dielectric constant layer, electrons are difficult to migrate from one memory cell to the adjacent memory cell, and the row hammering effect caused by the electron migration is reduced.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
DRAM (Dynamic Random Access Memory), dynamic random access memory, is a relatively common system memory, wherein each memory cell (cell) comprises a transistor and a corresponding capacitor, and 0 and 1 are represented by the amount of charge stored in the capacitor; to avoid leakage causing data errors, the capacitor needs to be periodically refreshed. In order to increase the integration of DRAM to increase the operation speed of each memory cell and to cope with the strong demand for DRAM from the markets of PC, smart phone, tablet, etc., the embedded word line DRAM (i.e., buried word line DRAM) structure has been developed in recent years to meet the above demand.
In the related art, one Row (Row) in the memory matrix is activated, and when it is repeatedly refreshed (refresh), noise or interference is generated to the adjacent Row, and thus Data (Data) of one or more cells in the adjacent Row is erroneous, which is called a so-called Row hammer effect (Row Hammer Effect).
Disclosure of Invention
The invention provides a semiconductor structure and a preparation method thereof, which are used for solving the hammering effect of a semiconductor device.
According to a first aspect of embodiments of the present application, there is provided a method for manufacturing a semiconductor structure, which may include:
providing a substrate;
forming a first word line structure in a first direction in a substrate;
etching the substrate downwards to form a columnar active region, wherein the depth of the columnar active region is greater than that of the first word line structure;
filling an isolation layer between the columnar active areas;
etching the first word line structure and the isolation layer to form a first word line groove in a first direction, wherein the first word line groove penetrates through the columnar active region;
and forming a low dielectric constant layer, a first conductive layer and an insulating layer in the first word line groove, wherein the first conductive layer is electrically connected with the first word line structure.
In some alternative embodiments of the present application, forming a first word line structure in a first direction on a substrate includes:
etching the substrate to form a second word line groove in the first direction;
a first word line structure is formed within the second word line trench.
In some alternative embodiments of the present application, etching the substrate to form a second word line trench in a first direction includes:
depositing a first word line mask on the substrate, wherein the extending direction of the exposed groove of the first word line mask is a first direction;
the substrate is etched using the first word line mask as a mask to form a second word line trench in a first direction.
In some alternative embodiments of the present application, before forming the first word line structure in the second word line trench, the method for manufacturing the semiconductor structure further includes:
depositing a gate oxide layer in the second word line trench, wherein the gate oxide layer covers the second word line trench;
a barrier layer is deposited over the gate oxide layer.
In some alternative embodiments of the present application, forming a first word line structure within a second word line trench includes:
depositing a first word line metal layer in the second word line trench; the first word line metal layer fills the second word line groove and covers the upper surface of the substrate;
the first word line metal layer is planarized to enable the upper surface of the first word line metal layer to be flush with the upper surface of the substrate, and a first word line structure is formed.
In some alternative embodiments of the present application, etching the first word line structure down to the substrate to form a columnar active region includes:
depositing a line mask over the first word line structure;
partially etching the line mask to form an island-shaped mask;
and etching the substrate by taking the island-shaped mask as a mask to form a columnar active region.
In some optional embodiments of the present application, filling the isolation layer around the columnar active region includes:
filling isolation materials around the columnar active region, wherein the isolation materials cover the upper surface of the island-shaped mask;
the isolation material is planarized to form an isolation layer, an upper surface of which is flush with an upper surface of the columnar active region.
In some alternative embodiments of the present application, etching the first word line structure and the isolation layer along the second direction to form a first word line trench in the first direction includes:
forming a second word line mask on the surfaces of the first word line structure and the isolation layer, wherein the extending direction of the exposed groove of the second word line mask is the first direction;
the first word line structure and the isolation layer are etched with the second word line mask as a mask to form first word line trenches passing through the plurality of columnar active regions and the isolation layer.
In some optional embodiments of the present application, after etching the first word line structure and the isolation layer along the second direction to form the first word line trench, the method for manufacturing the semiconductor structure further includes:
the second word line mask and a portion of the isolation layer are removed such that an upper surface of the isolation layer is flush with an upper surface of the columnar active region.
In some alternative embodiments of the present application, depositing a first conductive layer and an insulating layer in a first word line trench includes:
depositing a first word line conducting layer in the first word line groove, wherein the upper surface of the first word line conducting layer is lower than the upper surface of the columnar active region;
and depositing an insulating layer on the first word line conductive layer, wherein the upper surface of the insulating layer is flush with the upper surface of the columnar active region.
In some alternative embodiments of the present application, the low dielectric constant layer includes an air gap, and the low dielectric constant layer, the first conductive layer and the insulating layer are formed in the first word line trench, including:
depositing a sacrificial layer on the inner wall of the first word line groove;
depositing a first conductive layer in the first word line trench;
removing the sacrificial layer to form an air gap;
an insulating layer is deposited over the first conductive layer, the insulating layer sealing the air gap.
According to a second aspect of embodiments of the present application, there is provided a semiconductor structure, which may include:
a substrate including a columnar active region;
the first word line structure is formed in the columnar active region, the depth of the columnar active region is larger than that of the first word line structure, and the upper surface of the first word line structure is lower than that of the columnar active region;
an isolation layer filled between the columnar active regions;
the first conductive layer is positioned above the first word line structure, extends through the columnar active region and the isolation layer along the first direction, and is electrically connected with the first word line structure;
a low dielectric constant layer formed on the sidewall of the first conductive layer;
and the insulating layer is deposited on the surface of the first conductive layer.
In some alternative embodiments of the present application, the low dielectric constant layer includes an air gap.
In some alternative embodiments of the present application, the depth of the columnar active region is greater than the depth of the first word line structure.
In some alternative embodiments of the present application, the top surface of the low dielectric constant layer is level with or higher than the upper surface of the first conductive layer.
In some optional embodiments of the present application, the first conductive layer includes a plurality of first conductive structures spaced apart, and a width of the first word line structure in a second direction is less than or equal to a width of the first conductive structure in the second direction, the second direction being perpendicular to the first direction.
In some alternative embodiments of the present application, the top surface of the first word line structure is higher than the bottom surface of the first trench.
According to a third aspect of embodiments of the present application, there is provided a memory device, which may comprise a semiconductor structure as in any of the second aspects of embodiments.
The technical scheme of the application has the following beneficial technical effects:
according to the method, the embedded word line is divided into two parts, the first word line structure only exists in the columnar source regions, and the first word line structure does not exist in the isolation layer between the columnar source regions; word line conductive layers of different active areas are connected through a first conductive layer; such a structure makes it difficult for electrons to migrate from one memory cell to an adjacent memory cell, separated by a filled isolation layer and a low dielectric constant layer, thereby reducing the row hammer effect caused by electron migration.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of a structure for forming a second word line trench in an exemplary embodiment of the present application;
FIG. 3 is a schematic diagram of a structure for forming a first word line structure in an exemplary embodiment of the present application;
FIG. 4 is a schematic diagram of a structure for forming a line-type mask in an exemplary embodiment of the present application;
FIG. 5 is a schematic diagram of a structure for forming a pillar word line structure in an exemplary embodiment of the present application;
fig. 6 is a schematic structural view of forming a columnar active region in an exemplary embodiment of the present application;
FIG. 7 is a schematic illustration of a structure for filling isolation layers in an exemplary embodiment of the present application;
FIG. 8 is a schematic diagram of a structure for forming a second word line mask in an exemplary embodiment of the present application;
FIG. 9 is a schematic diagram of a structure for forming a first word line trench in an exemplary embodiment of the present application;
FIG. 10 is a schematic diagram of a semiconductor structure in an exemplary embodiment of the present application;
fig. 11 is a cross-sectional view of a semiconductor structure in an exemplary embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present application.
A layer structure schematic diagram according to an embodiment of the present application is shown in the drawings. The figures are not drawn to scale, wherein certain details may be exaggerated and some details may be omitted for clarity. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
It will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the description of the present application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The following describes in detail a method for manufacturing a semiconductor structure according to the embodiment of the present application through specific embodiments and application scenarios thereof with reference to the accompanying drawings.
As shown in fig. 1, in a first aspect of the embodiments of the present application, a method for preparing a semiconductor structure is provided, which may include:
s110: providing a substrate 1101;
s120: forming a first word line structure 1102 in a first direction in a substrate 1101;
s130: etching the substrate 1101 downward to form a columnar active region 1103, wherein the depth of the columnar active region 1103 is greater than the depth of the first word line structure 1102;
s140: filling an isolation layer 1109 between the columnar active regions 1103;
s150: etching the first word line structure 1102 and the isolation layer 1109 to form a first word line groove 1111 in a first direction, wherein the first word line groove 1111 penetrates through the columnar active region;
s160: a low dielectric constant layer, a first conductive layer 1104 and an insulating layer 1105 are formed in the first word line trench 1111, the first conductive layer 1104 electrically connecting the first word line structure 1102.
In the method of the above embodiment, the columnar active region 1103 is formed by etching down to the substrate 1101, the buried word line is divided into two parts, the first word line structure 1102 is only present in the columnar active region 1103, and the first word line structure 1102 is not present in the isolation layer 1109; the word line conductive layers of different active regions are connected through a first conductive layer 1104; this makes it difficult for electrons to migrate from one memory cell to an adjacent memory cell, separated by the filled spacer layer 1109 and the low dielectric constant layer, between adjacent memory cells of the semiconductor structure, thereby reducing the row hammer effect caused by electron migration.
For more clear explanation, the following description will be given for the above steps, respectively:
first, step S110: a substrate is provided.
In one embodiment, the material of the substrate includes, but is not limited to, silicon or germanium crystals, silicon-on-insulator (Silicon On Insulator, SOI) structures or epitaxial layer structures on silicon, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium), alloy semiconductors (e.g., siGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or combinations thereof).
Step S120 follows: a first word line structure in a first direction is formed in substrate 1101.
As shown in fig. 2-3, in one embodiment, the first word line structure may be formed by etching the substrate 1101 to form a second word line trench (not shown) in a first direction; a first word line structure 1102 is formed within the second word line trench. Wherein, etching the substrate to form the second word line trench in the first direction may include: depositing a first word line mask on the substrate, wherein the extending direction of the exposed groove of the first word line mask is a first direction; the substrate is etched using the first word line mask as a mask to form a second word line trench in a first direction. The first wordline mask may be a photoresist layer, after forming the photoresist layer on the substrate 1101, exposedThe photoresist layer is irradiated to obtain photoresist patterns, openings 1106 are formed between the photoresist patterns, the openings 1106 expose the substrate 1101, and the substrate is etched by taking the photoresist patterns as masks, so that second word line grooves in the first direction are formed. Then, siO is deposited in the second word line groove 2 The layer is used as a gate oxide layer, then TiN is deposited as a metal barrier layer, then W is deposited as a first word line metal layer, and finally, planarization is performed to planarize the surface, thus obtaining a first word line structure 1102.
Step S130 follows: and etching the substrate downwards to form a columnar active region, wherein the depth of the columnar active region is greater than that of the first word line structure.
In one embodiment, the process of forming the columnar active region may include: depositing a line-shaped SiN material as a mask 1107 over the first word line structure, as shown in fig. 4; the line mask is partially etched to form island mask 1108, wherein the partially etched line mask may sever the line SiN material through a mask comprising an array of holes. Next, the first word line structure 1102 is etched using the island mask 1108 as a mask to form a pillar word line structure as shown in fig. 5, and then the substrate is etched to form a pillar active region 1103 as shown in fig. 6.
Step S140 follows: an isolation layer 1109 is filled between the pillar-shaped active regions 1103.
In one embodiment, the plurality of pillar active regions 1103, and the filling of the isolation layer 1109 around the pillar active region 1103 may include: filling isolation materials among the columnar active regions 1103, wherein the isolation materials cover the upper surfaces of the island-shaped masks; the spacer material is planarized to form a spacer 1109, and the upper surface of the spacer 1109 is flush with the upper surface of the pillar active region 1103 as shown in fig. 7. Wherein the isolation material can be SiO 2 . Planarization may be polished using CMP techniques to improve the accuracy and performance of the finished product.
Step S150 follows: the first word line structure 1102 and the isolation layer 1109 are etched to form first word line trenches 1111 in a first direction, and the first word line trenches 1111 penetrate the pillar-shaped active regions.
In one embodiment, forming the first wordline trench may include: forming a second word line mask 1110 on the surface of the first word line structure and the isolation layer, as shown in fig. 8, wherein the extending direction of the trench exposed by the second word line mask 1110 is the first direction; the first word line structure 1102 and the isolation layer 1109 are etched using the second word line mask 1110 as a mask to form a first word line trench 1111 in the isolation layer. The first word line trench 1111 may include forming a second word line mask on the surface of the first word line structure and the isolation layer, the exposed trench of the second word line mask extending in a first direction; the first word line structure and the isolation layer are etched using the second word line mask as a mask to form a first word line trench 1111 in the isolation layer, the first word line trench 1111 penetrating the pillar-shaped active region, as shown in fig. 9, the etching depth may be 1/3-2/3 word line depth, and may specifically be 1/2 word line depth.
Finally, step S160: a low dielectric constant layer, a first conductive layer 1104 and an insulating layer 1105 are formed in the first word line trench 1111, the first conductive layer 1104 electrically connecting the first word line structure 1102.
In one embodiment, a low dielectric constant layer may be deposited in the first word line groove 1111, and the low dielectric constant layer may be SICOH, with a thickness of 3-8 nm, a dielectric constant of 2.8 or less, which is not easy to cause parasitic capacitance between the first conductive layers 1104, and a hardness of 0.2-2 GPa, so as to achieve good insulation breakdown prevention.
In one embodiment, the low dielectric constant layer includes an air gap, and forming the low dielectric constant layer, the first conductive layer, and the insulating layer in the first word line trench includes: a sacrificial layer (not shown) is deposited in the first word line trench 1111; depositing a first conductive layer 1104 within the first word line trench 1111; removing the sacrificial layer to form an air gap; an insulating layer 1105 is deposited over the first conductive layer 1104, the insulating layer sealing the air gap.
In one embodiment, the material of the sacrificial layer may be hydrocarbon, silicon oxide, BACL, etc., and the top and bottom sacrificial layers are removed by an ashing process, a wet etching process, or a dry etching process to form an air gap. The air gap may be formed by removing the top and bottom sacrificial layers by means of plasma etching,for example, using O 2 、H 2 The mode of combining the etching gas with the plasma bombardment ensures that O 2 、H 2 Changing into water vapor, combining with plasma sputtering to gradually wash the sacrificial layer from top to bottom, and simultaneously O 2 And H 2 The first conductive layer 1104 is subjected to oxidation-reduction reaction all the time to protect the first conductive layer 1104 from being sputtered by plasma bombardment, so that air gaps are formed on two sides of the first conductive layer 1104, and then an insulating layer is deposited to obtain a semiconductor structure with the air gaps, and the air gaps can reduce parasitic capacitance between the first conductive layers 1104.
In one embodiment, forming the first word line structure 1102 in the first direction in the substrate 1101 may include:
etching the substrate 1101 to form a second word line trench in the first direction;
a first word line structure 1102 is formed within the second word line trench.
In an embodiment, etching the substrate to form the second word line trench in the first direction may include:
depositing a first word line mask on the substrate, wherein the extending direction of the exposed groove of the first word line mask is a first direction;
the substrate is etched using the first word line mask as a mask to form a second word line trench in a first direction.
In an embodiment, before the first word line structure 1102 is formed in the second word line trench, the method for manufacturing the semiconductor structure may further include:
depositing a gate oxide layer in the second word line trench, wherein the gate oxide layer covers the second word line trench;
and depositing a barrier layer on the gate oxide layer, wherein the barrier layer covers the bottom surface and the side wall of the gate oxide layer.
In one embodiment, forming the first word line structure 1102 in the second word line trench may include:
depositing a first word line metal layer in the second word line trench; the first word line metal layer fills the second word line groove and covers the upper surface of the substrate;
the first word line metal layer is planarized to enable the upper surface of the first word line metal layer to be flush with the upper surface of the substrate, and a first word line structure is formed.
In an embodiment, etching the substrate 1101 downward to form a columnar active region 1103 may include:
depositing a line mask 1107 over the first word line structure 1102;
partially etching the line mask 1107 to form an island mask 1108;
the substrate 1101 is etched with the island-shaped mask 1108 as a mask to form a columnar active region 1103.
In one embodiment, filling the isolation layer 1109 between the pillar active regions 1103 may include:
filling isolation materials between the columnar active regions 1103, wherein the isolation materials cover the upper surfaces of the island-shaped masks;
the spacer material is planarized to form a spacer 1109, and an upper surface of the spacer 1109 is flush with an upper surface of the columnar active region 1103. The planarization operation specifically employs CMP (Chemical Mechanical Polishing ) to planarize the surface layer.
In one embodiment, etching the first word line structure 1102 and the isolation layer 1109 to form the first word line trench 1111 in the first direction may include:
forming a second word line mask on the surfaces of the first word line structure 1102 and the isolation layer 1109, wherein the extending direction of the exposed groove of the second word line mask is the first direction;
the first word line structure 1102 and the isolation layer 1109 are etched using the second word line mask as a mask to form first word line trenches 1111 through the plurality of pillar-shaped active regions and the isolation layer.
In an embodiment, after etching the first word line structure and the isolation layer to form the first word line trench 1111, the method for manufacturing the semiconductor structure may further include:
the second word line mask and a portion of the isolation layer 1109 are removed so that the upper surface of the isolation layer 1109 is flush with the upper surface of the pillar active region 1103.
In one embodiment, depositing the first conductive layer 1104 and the insulating layer 1105 in the first word line trench 1111 may include:
depositing a first conductive layer 1104 in the first word line trench 1111, the upper surface of the first conductive layer 1104 being lower than the upper surface of the pillar active region 1103;
an insulating layer 1105 is deposited on the first conductive layer 1104, and the upper surface of the insulating layer 1105 is flush with the upper surface of the columnar active region 1103.
Then, a first conductive layer 1104 is deposited to connect in series with a first word line metal layer in the first word line structure, and then an insulating layer 1105 is covered, as shown in fig. 10, where the materials of the first conductive layer and the first word line metal layer are tungsten metal, and the material of the insulating layer is SiN. In one embodiment, the material of the first word line metal layer may be polysilicon (dual gate poly), avoiding the case of interference by the word line, and reducing GIDL (gate-induce drain leakage, gate induced drain leakage current).
In the embodiment of the present application, the etching gas may use SF 6 /CF 4 /Cl 2 /CHF 3 /O 2 Ar or mixed gas to achieve a certain selection ratio.
Silicon nitride (SiN) sidewall deposition may be performed by ALD (atomic layer deposition), wherein the ALD reactant gas may be NH3 or N 2 /H 2 The reaction gases are mixed.
The silicon nitride (SiN) coating layer can be LPCVD, and the reaction gas can be SiH4 or SiH 2 Cl 2 The method comprises the steps of carrying out a first treatment on the surface of the LPCVD is: low pressure chemical vapor deposition high temperature oxidation (Low Pressure Chemical Vapor Deposition High Temperature Oxidation).
SiO 2 Deposition can be performed by ALD of SiO 2 Deposition, the reaction gas can be silane and O 2 。
As shown in fig. 11, in a second aspect of the embodiments of the present application, there is provided a semiconductor structure, which may include:
a substrate 1101 including a columnar active region 1103;
the first word line structure 1102 is formed in the columnar active region 1103, the depth of the columnar active region is larger than that of the first word line structure 1102, the upper surface of the first word line structure 1102 is lower than that of the columnar active region 1103, and A-A' is in the first direction;
an isolation layer 1109 filling between the columnar active regions;
a first conductive layer 1104 above the first word line structure and extending in a first direction through the pillar-shaped active region and the isolation layer, the first conductive layer electrically connecting the first word line structure 1102, B-B' being in a second direction;
an insulating layer 1105 is deposited on the surface of the first conductive layer 1104.
The buried word line of the semiconductor structure of this embodiment is divided into two parts, the first word line structure is only present in the columnar active regions 1103, and the first word line structure is not present in the isolation layer 1109 between the columnar active regions 1103; the word line conductive layers of different active regions are connected through a first conductive layer 1104; such a structure makes it difficult for electrons to migrate from one memory cell to an adjacent memory cell, separated by the filled spacer 1109, thereby reducing the row hammer effect caused by the electron migration.
The material of the substrate in this embodiment includes, but is not limited to, silicon or germanium crystals, silicon-on-insulator (Silicon On Insulator, SOI) structures or epitaxial layer structures on silicon, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium), alloy semiconductors (e.g., siGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or combinations thereof). The material of the isolation layer can be SiO 2 The material of the first conductive layer may be tungsten (W), and the material of the insulating layer may be SiN.
In one embodiment, a dielectric layer is further formed between the isolation layer 1109 and the first conductive layer 1104. The dielectric layer can be SICOH, has a thickness of 3-8 nm, has a dielectric constant of 2.8 or below, is not easy to cause parasitic capacitance influence, has a hardness of 0.2-2 GPa, and can play a role in good insulation breakdown prevention.
In an embodiment, the depth of the pillar active region 1103 may be greater than the depth of the first word line structure.
In an embodiment, the plurality of pillar-shaped active regions 1103 may have a top surface of the first word line structure higher than a bottom surface of the first conductive layer 1104. Thus, the first conductive layer 1104 can be connected to the first word line structure of the adjacent pillar source region 1103.
In a third aspect of embodiments of the present application, a memory is provided, including the semiconductor structure described above. The semiconductor structure, the first word line structure exists only in the columnar active region 1103, and the first word line structure does not exist in the isolation layer 1109; the first word line structures 1102 of the different columnar active regions 1103 are connected through a first conductive layer 1104; such a structure makes it difficult for electrons to migrate from one memory cell to an adjacent memory cell by separating the adjacent memory cells (cells) by the filled isolation layer 1109 and the low dielectric constant layer, thereby reducing the row hammer effect caused by the electron migration.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.
Claims (16)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first word line structure in a first direction in the substrate;
etching the substrate downwards to form a columnar active region, wherein the depth of the columnar active region is larger than that of the first word line structure;
filling an isolation layer between the columnar active areas;
etching the first word line structure and the isolation layer to form a first word line groove in the first direction, wherein the first word line groove penetrates through the columnar active region;
and forming a low dielectric constant layer, a first conductive layer and an insulating layer in the first word line groove, wherein the first conductive layer is electrically connected with the first word line structure.
2. The method of fabricating a semiconductor structure of claim 1, wherein forming a first word line structure in a first direction on the substrate comprises:
etching the substrate to form a second word line groove in the first direction;
the first word line structure is formed within the second word line trench.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein etching the substrate to form a second word line trench in a first direction comprises:
depositing a first word line mask on the substrate, wherein the extending direction of the exposed groove of the first word line mask is the first direction;
and etching the substrate by taking the first word line mask as a mask to form a second word line groove in the first direction.
4. The method of manufacturing a semiconductor structure of claim 2, wherein prior to forming the first word line structure in the second word line trench, the method of manufacturing a semiconductor structure further comprises:
depositing a gate oxide layer in the second word line trench, wherein the gate oxide layer covers the second word line trench;
and depositing a barrier layer on the gate oxide layer.
5. The method of manufacturing a semiconductor structure according to claim 2, wherein forming the first word line structure in the second word line trench comprises:
depositing a first word line metal layer within the second word line trench; the first word line metal layer fills the second word line trench and covers the upper surface of the substrate;
and flattening the first word line metal layer to enable the upper surface of the first word line metal layer to be flush with the upper surface of the substrate, so as to form a first word line structure.
6. The method of claim 1, wherein etching the first word line structure down to the substrate to form a columnar active region comprises:
depositing a line mask over the first word line structure;
partially etching the line mask to form an island-shaped mask;
and etching the substrate by taking the island-shaped mask as a mask to form a columnar active region.
7. The method of claim 6, wherein filling the spacer around the columnar active region comprises:
filling isolation materials around the columnar active areas, wherein the isolation materials cover the upper surfaces of the island-shaped masks;
the isolation material is planarized to form an isolation layer, an upper surface of which is flush with an upper surface of the columnar active region.
8. The method of manufacturing a semiconductor structure of claim 1, wherein etching the first word line structure and the isolation layer to form a first word line trench in the first direction comprises:
forming a second word line mask on the surfaces of the first word line structure and the isolation layer, wherein the extending direction of the exposed groove of the second word line mask is the first direction;
and etching the first word line structure and the isolation layer by taking the second word line mask as a mask to form a first word line groove penetrating through the plurality of columnar active areas and the isolation layer.
9. The method of manufacturing a semiconductor structure according to claim 8, wherein after the etching the first word line structure and the isolation layer to form the first word line trench in the first direction, the method further comprises:
and removing the second word line mask and part of the isolation layer so that the upper surface of the isolation layer is flush with the upper surface of the columnar active region.
10. The method of claim 1, wherein depositing a first conductive layer and an insulating layer in the first word line trench comprises:
depositing a first word line conductive layer in the first word line trench, wherein the upper surface of the first word line conductive layer is lower than the upper surface of the columnar active region;
and depositing an insulating layer on the first word line conducting layer, wherein the upper surface of the insulating layer is flush with the upper surface of the columnar active region.
11. The method of claim 1, wherein the low-k layer comprises an air gap, and the forming the low-k layer, the first conductive layer, and the insulating layer in the first word line trench comprises:
depositing a sacrificial layer on the inner wall of the first word line groove;
depositing a first conductive layer within the first word line trench;
removing the sacrificial layer to form an air gap;
an insulating layer is deposited over the first conductive layer, the insulating layer sealing the air gap.
12. A semiconductor structure, comprising:
a substrate including a columnar active region;
a first word line structure formed in the pillar active region, the pillar active region having a depth greater than a depth of the first word line structure, an upper surface of the first word line structure being lower than an upper surface of the pillar active region;
an isolation layer filling between the columnar active regions;
a first conductive layer located above the first word line structure and extending through the columnar active region and the isolation layer in a first direction, the first conductive layer being electrically connected to the first word line structure;
a low dielectric constant layer formed on the side wall of the first conductive layer;
and the insulating layer is deposited on the surface of the first conductive layer.
13. The semiconductor structure of claim 12, wherein the low dielectric constant layer comprises an air gap.
14. The semiconductor structure of claim 12, wherein a top surface of the low dielectric constant layer is level with or higher than an upper surface of the first conductive layer.
15. The semiconductor structure of claim 12, wherein the first conductive layer comprises a plurality of first conductive structures spaced apart, the first word line structures having a width in a second direction that is less than or equal to a width of the first conductive structures in a second direction, the second direction being perpendicular to the first direction.
16. A memory comprising the semiconductor structure of any of claims 12-15.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210010113.4A CN116456712A (en) | 2022-01-06 | 2022-01-06 | Semiconductor structure and preparation method thereof |
| PCT/CN2022/087046 WO2023130607A1 (en) | 2022-01-06 | 2022-04-15 | Preparation method for semiconductor structure, semiconductor structure, and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210010113.4A CN116456712A (en) | 2022-01-06 | 2022-01-06 | Semiconductor structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116456712A true CN116456712A (en) | 2023-07-18 |
Family
ID=87073010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210010113.4A Pending CN116456712A (en) | 2022-01-06 | 2022-01-06 | Semiconductor structure and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116456712A (en) |
| WO (1) | WO2023130607A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005277183A (en) * | 2004-03-25 | 2005-10-06 | Sharp Corp | Nonvolatile semiconductor memory and its manufacturing method |
| US10910379B2 (en) * | 2019-03-15 | 2021-02-02 | Micron Technology, Inc. | Integrated assemblies comprising memory cells and shielding material between the memory cells, and methods of forming integrated assemblies |
| CN112447584A (en) * | 2019-08-30 | 2021-03-05 | 长鑫存储技术有限公司 | Semiconductor structure, preparation method thereof and storage device |
| CN113270405B (en) * | 2020-02-14 | 2024-08-02 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113871342A (en) * | 2021-09-13 | 2021-12-31 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN113871343A (en) * | 2021-09-13 | 2021-12-31 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
-
2022
- 2022-01-06 CN CN202210010113.4A patent/CN116456712A/en active Pending
- 2022-04-15 WO PCT/CN2022/087046 patent/WO2023130607A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023130607A1 (en) | 2023-07-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11778811B2 (en) | Semiconductor memory device and method of fabricating the same | |
| CN100550420C (en) | The manufacture method of vertical transistor | |
| US7332392B2 (en) | Trench-capacitor DRAM device and manufacture method thereof | |
| CN113035872B (en) | Semiconductor structure and manufacturing method thereof | |
| CN109216357B (en) | Semiconductor structure and manufacturing method thereof | |
| KR101194890B1 (en) | Semiconductor device and method for forming the same | |
| US10424586B2 (en) | Memory device including a trench isolation structure between buried word lines and manufacturing method thereof | |
| CN111564442B (en) | Semiconductor structure and preparation method | |
| US11653498B2 (en) | Memory device with improved data retention | |
| US11812605B2 (en) | Semiconductor structure with air gaps for buried semiconductor gate and method for forming the same | |
| CN115188760B (en) | Method for forming semiconductor structure | |
| KR20170043683A (en) | Method for manufaturing semiconductor device | |
| TW202133349A (en) | Semiconductor device and method of manufacturing the same | |
| US8580633B2 (en) | Method for manufacturing a semiconductor device with gate spacer | |
| US11239111B1 (en) | Method of fabricating semiconductor device | |
| US11177215B2 (en) | Integrated circuit device | |
| US20060019447A1 (en) | Process for the self-aligning production of a transistor with a U-shaped gate | |
| US20230120017A1 (en) | Semiconductor structure and method for fabricating same | |
| US20020123198A1 (en) | Method of fabricating a self-aligned shallow trench isolation | |
| TWI769797B (en) | Dynamic random access memory and method of fabricating the same | |
| CN116456712A (en) | Semiconductor structure and preparation method thereof | |
| CN113871342A (en) | Semiconductor structure and forming method thereof | |
| US11856754B2 (en) | Method of manufacturing semiconductor structure, semiconductor structure, and memory | |
| CN117529105B (en) | Semiconductor structure and forming method thereof | |
| US20220199623A1 (en) | Method for manufacturing semiconductor structure with capacitor landing pad |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |