CN116455517A

CN116455517A - Encoding method, decoding method, apparatus, device, system, and readable storage medium

Info

Publication number: CN116455517A
Application number: CN202210114845.8A
Authority: CN
Inventors: 何向; 王心远; 任浩
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-01-05
Filing date: 2022-01-30
Publication date: 2023-07-18

Abstract

The application discloses an encoding method, a decoding method, a device, equipment, a system and a readable storage medium, and belongs to the technical field of communication. The coding method comprises the following steps: acquiring 2 including a control block and a data block ⁿ A group code stream block; pair 2 ⁿ Performing first coding on the group code stream blocks to obtain target code blocks, wherein the target code blocks comprise data units and are based on 2 ⁿ The type of control block determination of the block of the group code stream, the data unit is based on 2 ⁿ Coding mode pair 2 determined by control block and data block of group code stream block ⁿ And the data blocks included in the group code stream block are subjected to first coding. The decoding method comprises the following steps: obtaining a target code block, and performing first decoding on the target code block according to the type and the data unit of the target code block to obtain 2 ⁿ The system comprises a plurality of code stream blocks, wherein any code stream block comprises a data block and a control block obtained based on a type and a data unit, and the data block included in any code stream block is obtained by performing first decoding on the data unit based on a decoding mode determined by the type and the data unit.

Description

Encoding method, decoding method, apparatus, device, system, and readable storage medium

The present application claims priority from chinese patent application No. 202210007010.2 entitled "data processing method, first network device and chip" filed on 1 month 5 2022, the entire contents of which are incorporated herein by reference in the examples of the present application.

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to an encoding method, a decoding method, an apparatus, a device, a system, and a readable storage medium.

Background

With the development of communication technology, the manner of processing data in the data transmission process is also becoming more and more diversified. For example, messages of the media access control (media access control, MAC) layer are delivered via a media independent interface (media independent interface, MII) to the physical coding sublayer (physical coding sublayer, PCS). For example, the message is sent down to the PCS via an 800 gigabit (G) MII, which 800GMII represents an MII with a transmission MAC rate of 800 gigabits/second (gigabit per second, gb/s). The data bit width of the MII is 72 bits, and includes an 8-bit control block (TXC) and a 64-bit data block (TXD). The TXC and TXD are obtained by processing message stream contents from the MAC layer through an adaptation sublayer (reconciliation sublayer, RS). The PCS encodes according to the TXC/TXD content, reduces overhead, and can provide necessary synchronization and protection functions.

In the related art, a PCS at a transmitting end performs 64-bit (bit, B)/66B coding on a control block and a data block from an MII, and the coding obtains a 66-bit code block. When the high-speed physical link is used for data transmission, every four 66-bit code blocks are transcoded into 256B/257B coded code blocks with the length of 257 bits, forward error correction (forward error correction, FEC) coding is carried out on the 257-bit code blocks, and FEC code words obtained by FEC coding are transmitted. After receiving the FEC codeword, the receiving end performs FEC decoding on the FEC codeword to obtain a 257-bit code block. And correcting errors in the FEC code words in the FEC decoding process, and marking error codes in the FEC code words which are uncorrectable. Each 257-bit code block is inverted into four 64B/66B coded code blocks with the length of 66 bits, and the four 66-bit code blocks are decoded to obtain a control block and a data block in an MII format.

Since FEC encoding can provide data protection and most of the processing in PCS is based on 257 bit code blocks, the 64B/66B codec process is not necessary. If the 64B/66B codec process is reserved, the subsequent transcoding/inversion process will result in unnecessary delay, power consumption and chip area occupation.

Disclosure of Invention

The application provides an encoding method, a decoding method, a device, equipment, a system and a readable storage medium, which are used for improving encoding and decoding efficiency.

In a first aspect, there is provided a coding method, the method comprising: acquisition 2 ⁿ The system comprises a group of code stream blocks, wherein any group of code stream blocks comprises a control block and a data block, and n is an integer greater than 1; for said 2 ⁿ Performing first coding on the group code stream blocks to obtain target code blocks, wherein the target code blocks comprise data units and are based on the data units 2 ⁿ The type of the control block determination of the group code stream block, the data unit being based on the 2 ⁿ The control block of the group code stream block and the coding mode determined by the data block are used for the data block 2 ⁿ And the data blocks of the group code stream block are obtained by first encoding.

In the encoding method provided by the application, for 2 including a control block and a data block ⁿ First encoding the group code stream block to obtain a target code block without 2 ⁿ Each group of code stream blocks in the group of code stream blocks is subjected to 64B/66B coding to obtain 2 ⁿ 66 bit code blocks, 2 pairs ⁿ And transcoding the 66-bit code blocks to obtain target code blocks. Therefore, the coding efficiency is improved, and the time delay, the power consumption and the chip area occupation caused by the coding process are reduced.

In a possible implementation manner, the type is used for indicating that the target code block is a data code block; the data unit is based on the 2 ⁿ The order of the group code stream blocks is to the 2 ⁿ And carrying out the first coding on the data blocks of the group code stream blocks.

In a possible implementation manner, the type is used for indicating that the target code block is a control code block; the data unit includes a code block identification ID and code block content, the code block content based on the 2 ⁿ The control block and the data block of the group code stream block are determined to be in the sequence of 2 ⁿ The data blocks of the group code stream block are obtained by the first coding, and the code block ID is based on the 2 ⁿ The code block ID is used for indicating the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding in the code block content.

In one possible implementation, the code block IDs include a first ID for indicating a type of the data block of each group of code stream blocks and a second ID for indicating a position of the content of each group of code stream blocks after the first encoding in the code block content.

In one possible implementation, the code block ID includes m bits, where m is an integer greater than or equal to 4.

In one possible implementation, the code block ID is provided with hamming distance protection.

In one possible implementation, the target code block is an error code block, and the error code block includes data for identifying an error.

The encoding method provided by the application can perform the first encoding on the code stream blocks of different types to obtain the target code blocks, and has wider applicability.

In one possible implementation, the target code block pairs the 2 based on the error detection result ⁿ Processing the group code stream block to obtain the error detection result based on the step 2 ⁿ The control block and the data block of the group code stream block are obtained. By processing the code stream block with the error, the data with the error can be distinguished from the correct data when the data transmission is carried out later, and the reliability of the data is ensured.

In a possible implementation, the error detection result includes the 2 ⁿ Group code stream blockContent order error or content error of said target code block based on said 2 ⁿ The first coding is performed on the code stream blocks with correct content sequence and correct content and error blocks in the group code stream blocks, and the error blocks are based on the 2 ⁿ The code stream blocks with wrong content sequence or wrong content in the group code stream blocks are obtained.

In one possible implementation, the control block includes t bits, the data block includes 8t bits, and t is a positive integer.

In one possible implementation, the value of n is 2, the value of t is 8, and the target code block is 257 bits.

In one possible implementation, the method 2 ⁿ The group code stream blocks are all from the media independent interface MII.

In one possible implementation manner, after the obtaining the target code block, the method further includes: performing second coding on the target code block according to the FEC code pattern to obtain first data; and sending the first data. And performing second coding on the target code block according to the FEC code pattern to obtain first data, so that the receiving end can correct the received first data, and the accuracy of data transmission is ensured.

In a second aspect, there is provided a decoding method, the method comprising: obtaining a target code block, wherein the target code block comprises a type and a data unit; according to the type of the target code block and the data unit, performing first decoding on the target code block to obtain 2 ⁿ And the code stream blocks comprise data blocks and control blocks obtained based on the type and the data units, wherein the data blocks are obtained by performing first decoding on the data units based on the type and the decoding mode determined by the data units, and n is an integer greater than 1.

In the decoding method provided by the application, the target code block is subjected to first decoding to obtain 2 comprising a control block and a data block ⁿ The code stream blocks are assembled without transcoding the target code blocks to obtain 2 ⁿ 66 bit code blocks, 2 pairs ⁿ Decoding the 66 bit code blocks to obtain 2 ⁿ And (5) assembling code stream blocks. Thus, decoding efficiency is improvedThe delay, the power consumption and the chip area occupation caused by the decoding process are reduced.

In a possible implementation manner, the type is used for indicating that the target code block is a data code block; said 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by performing the first decoding on the content with the length of 8t corresponding to the ith group of code stream blocks in the data unit, wherein t is a positive integer, and i is greater than or equal to 1 and less than or equal to 2 ⁿ Or the integer of i is 0 or more and 2 or less ⁿ -an integer of 1.

In a possible implementation manner, the type is used for indicating that the target code block is a control code block, the data unit includes a code block identification ID and code block content, and the code block ID is used for indicating the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first encoding in the code block content; said 2 ⁿ The control block included in the ith group of code stream blocks among the group of code stream blocks is obtained based on the type and the code block ID, said 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by performing the first decoding on the code block contents based on the decoding mode determined by the type and the code block ID, wherein i is greater than or equal to 1 and less than or equal to 2 ⁿ Or the integer of i is 0 or more and 2 or less ⁿ -an integer of 1.

In one possible implementation manner, the code block IDs include a first ID and a second ID, where the first ID is used to indicate a type of a data block of each group of code stream blocks, and the second ID is used to indicate a position of the content of each group of code stream blocks after the first encoding in the code block content; the control block included in the ith group of code stream blocks is obtained based on the type, the bit corresponding to the ith group of code stream blocks in the first ID and the bit corresponding to the ith group of code stream blocks in the second ID, and the data block included in the ith group of code stream blocks is obtained by performing the first decoding on the code block content based on a decoding mode determined by the type, the bit corresponding to the ith group of code stream blocks in the first ID and the bit corresponding to the ith group of code stream blocks in the second ID.

In one possible implementation, the type of the data block included in the i-th group of code stream blocks is determined based on the content of the control block included in the i-th group of code stream blocks and the content of the data block included in the i-th group of code stream blocks.

In a possible implementation, the data unit includes a code block identification ID, the type and the code block ID being used to indicate that the target code block is an error code block; said 2 ⁿ Each group of code stream blocks comprises a control block with a first value, wherein 2 is as follows ⁿ And the data blocks included in each group of code stream blocks in the group of code stream blocks are second values, and the first values and the second values are used for indicating that the code stream blocks are error code stream blocks.

Because the decoding method provided by the application can perform the first decoding on different types of target code blocks to obtain 2 ⁿ The method has wider applicability.

In one possible implementation, the acquiring the target code block includes: receiving second data, the second data being obtained based on the first data encoded with forward error correction FEC; and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error correction processing.

In one possible implementation, the target code block is an error code block obtained by error correcting the second data but not successfully correcting the error.

In one possible implementation, the acquiring the target code block includes: receiving second data, the second data being obtained based on the first data encoded with forward error correction FEC; and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error detection but no error correction processing.

In one possible implementation, the target code block is an error code block obtained by detecting an error from the second data but not correcting the error.

In one possible implementation, the method 2 ⁿ The group code stream block is obtained by performing the first decoding on the target code block according to an error detection result, and the type and the data unit of the target code block, and the error detection result is obtained based on the type and the data unit of the target code block.

In one possible implementation, the error detection result includes a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is obtained by performing the first decoding on the second code block according to the type and the data unit of the second code block, and the second code block is obtained by converting the target code block and has the same bit number as the target code block. The receiving end can distinguish error data and correct data by processing the target code block with error, so that the reliability of the data is ensured.

In one possible implementation, the error detection result includes a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is pair 2 ⁿ The first code stream block of the group is converted, the 2 ⁿ The group of first code stream blocks is obtained by performing the first decoding on the target code blocks according to the type of the target code blocks and the data unit. The receiving end can distinguish error data and correct data by processing the target code block with error, so that the reliability of the data is ensured.

In one possible implementation, the method 2 ⁿ The group code stream blocks are all in the MII format of the media independent interface.

In a third aspect, there is provided an encoding apparatus, the apparatus comprising:

an acquisition module for acquiring 2 ⁿ The system comprises a group of code stream blocks, wherein any group of code stream blocks comprises a control block and a data block, and n is an integer greater than 1;

a first coding module for the 2 ⁿ Performing first coding on the group code stream blocks to obtain target code blocks, wherein the target code blocks comprise data units and are based on the data units 2 ⁿ The type of the control block determination of the group code stream block, the data unit being based on the 2 ⁿ The control block of the group code stream block and the coding mode determined by the data block are used for the data block 2 ⁿ And the data blocks of the group code stream block are obtained by first encoding.

In one possible implementation, the target code block pairs the 2 based on the error detection result ⁿ Processing the group code stream block to obtain the error detection result based on the step 2 ⁿ The control block and the data block of the group code stream block are obtained.

In a possible implementation, the error detection result includes the 2 ⁿ Content order error or content error of group code stream block, the target code block is based on the 2 ⁿ The first coding is performed on the code stream blocks with correct content sequence and correct content and error blocks in the group code stream blocks, and the error blocks are based on the 2 ⁿ The code stream blocks with wrong content sequence or wrong content in the group code stream blocks are obtained.

In one possible implementation, the apparatus further includes: the second coding module is used for carrying out second coding on the target code block according to the Forward Error Correction (FEC) code pattern to obtain first data; and the sending module is used for sending the first data.

In a fourth aspect, there is provided a decoding apparatus, the apparatus comprising:

the acquisition module is used for acquiring a target code block, wherein the target code block comprises a type and a data unit;

a decoding module, configured to perform a first decoding on the target code block according to the type and the data unit of the target code block to obtain 2 ⁿ A group of code stream blocks, any one of which includes a data block and a control block derived based on the type and the data unit, the dataThe block is obtained by performing the first decoding on the data unit based on the type and the decoding mode determined by the data unit, and n is an integer greater than 1.

In a possible implementation manner, the type is used for indicating that the target code block is a control code block; the data unit comprises code block Identification (ID) and code block content, wherein the code block ID is used for indicating the type of a data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding in the code block content; said 2 ⁿ The control block included in the ith group of code stream blocks among the group of code stream blocks is obtained based on the type and the code block ID, said 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by performing the first decoding on the code block contents based on the decoding mode determined by the type and the code block ID, wherein i is greater than or equal to 1 and less than or equal to 2 ⁿ Or the integer of i is 0 or more and 2 or less ⁿ -an integer of 1.

In one possible implementation, the acquiring module is configured to receive second data, where the second data is obtained based on the first data encoded with the FEC pattern; and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error correction processing.

In one possible implementation, the acquiring module is configured to receive second data, where the second data is obtained based on the first data encoded with the FEC pattern; and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error detection but no error correction processing.

In a kind ofIn a possible implementation manner, the method 2 ⁿ The group code stream block is obtained by performing the first decoding on the target code block according to an error detection result, and the type and the data unit of the target code block, and the error detection result is obtained based on the type and the data unit of the target code block.

In one possible implementation, the error detection result includes a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is obtained by performing the first decoding on the second code block according to the type and the data unit of the second code block, and the second code block is obtained by converting the target code block and has the same bit number as the target code block.

In one possible implementation, the error detection result includes a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is pair 2 ⁿ The first code stream block of the group is converted, the 2 ⁿ The group of first code stream blocks is obtained by performing the first decoding on the target code blocks according to the type of the target code blocks and the data unit.

In a fifth aspect, there is provided a network device comprising a processor coupled to a memory, the memory having stored therein at least one program instruction or code that is loaded and executed by the processor to cause the network device to implement the encoding method of any of the first aspects or to implement the decoding method of any of the second aspects.

In a sixth aspect, there is provided a computer readable storage medium having stored therein at least one program instruction or code which when loaded and executed by a processor causes a computer to implement the encoding method of any one of the first aspects or the decoding method of any one of the second aspects.

In a seventh aspect, a communication system is provided, the system comprising a first network device for performing the encoding method of any of the first aspects and a second network device for performing the decoding method of any of the second aspects.

In an eighth aspect, there is provided another communication apparatus comprising: a transceiver, a memory, and a processor. Wherein the transceiver, the memory, and the processor communicate with each other through an internal connection path, the memory is configured to store instructions, the processor is configured to execute the instructions stored by the memory to control the transceiver to receive signals and control the transceiver to transmit signals, and when the processor executes the instructions stored by the memory, the processor is caused to execute the encoding method of any one of the first aspects or the decoding method of any one of the second aspects.

Illustratively, the processor is one or more and the memory is one or more.

The memory may be integrated with the processor or may be separate from the processor, for example.

In a specific implementation process, the memory may be a non-transient (non-transitory) memory, for example, a Read Only Memory (ROM), which may be integrated on the same chip as the processor, or may be separately disposed on different chips, where the type of the memory and the manner of disposing the memory and the processor are not limited in this application.

In a ninth aspect, there is provided a computer program product comprising: computer program code which, when run by a computer, causes the computer to perform the encoding method of any of the first aspects or the decoding method of any of the second aspects.

In a tenth aspect, there is provided a chip comprising a processor for calling from a memory and executing instructions stored in the memory, such that a communication device on which the chip is mounted performs the encoding method of any one of the first aspects or performs the decoding method of any one of the second aspects.

In an eleventh aspect, there is provided another chip comprising: the device comprises an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, the processor is used for executing codes in the memory, and when the codes are executed, the processor is used for executing the encoding method of any one of the first aspects or executing the decoding method of any one of the second aspects.

Drawings

FIG. 1 is a schematic diagram of an implementation environment of an encoding method and a decoding method according to an embodiment of the present application;

FIG. 2 is a flow chart of an encoding method provided by an embodiment of the present application;

fig. 3 is a schematic diagram of a process for obtaining a target code block according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a target code block according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of another target code block according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another target code block according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of another target code block according to an embodiment of the present application;

fig. 8 is a schematic diagram of a data block of four groups of code stream blocks according to an embodiment of the present application;

FIG. 9 is a schematic diagram of another data block of four groups of code stream blocks according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a data block of another four-group code stream block according to an embodiment of the present application;

FIG. 11 is a schematic illustration of a termination block provided in an embodiment of the present application;

FIG. 12 is a schematic diagram of data blocks of another four-group code stream block according to an embodiment of the present application;

FIG. 13 is a schematic diagram of another data block of four groups of code stream blocks according to an embodiment of the present application;

FIG. 14 is a schematic diagram of data blocks of another four-group code stream block according to an embodiment of the present application;

FIG. 15 is a schematic diagram of a data block of another four-group code stream block according to an embodiment of the present application;

FIG. 16 is a schematic diagram of another data block of four groups of code stream blocks according to an embodiment of the present application;

FIG. 17 is a schematic diagram of another data block of four groups of code stream blocks according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of another target code block according to an embodiment of the present application;

FIG. 19 is a flow chart of a decoding method provided in an embodiment of the present application;

fig. 20 is a schematic structural diagram of another target code block according to an embodiment of the present application;

fig. 21 is a schematic structural diagram of an encoding device according to an embodiment of the present application;

fig. 22 is a schematic structural diagram of a decoding device according to an embodiment of the present application;

fig. 23 is a schematic structural diagram of a network device according to an embodiment of the present application;

fig. 24 is a schematic structural diagram of another network device according to an embodiment of the present application;

fig. 25 is a schematic structural diagram of another network device according to an embodiment of the present application.

Detailed Description

The terminology used in the description of the embodiments of the present application is for the purpose of describing the examples of the present application only and is not intended to be limiting of the present application. Embodiments of the present application are described below with reference to the accompanying drawings.

In the field of communication technology, as the demand for data transmission increases, the demand for transmission rate increases. As an ethernet technology, with rapid development of ethernet, a rate of data transmission through ethernet is increasing. For example, 100 Gigabit Ethernet (GE) has been used for data transmission using a single channel 25Gb/s transmission rate. On the basis of ensuring the rapid transmission of data, in order to ensure the reliability of data transmission, when the Ethernet is applied to transmit data, the physical layer introduces FEC codes, and error codes in received data are corrected by transmitting FEC code words obtained by the codes. Because of the presence of the check code in the FEC codeword, the transmission rate required to transmit the FEC codeword is higher for the transmission rate required to transmit the same payload in the same time.

In order to reduce the transmission rate required for transmitting FEC codewords, transcoding is employed on the ethernet standard to achieve a reduction in the transmission rate required for transmitting FEC codewords by reducing the overhead of the code blocks before FEC encoding. For example, each four 64B/66B encoded code blocks are transcoded into one 256B/257B encoded code block, and the transmission rate required to transmit the FEC codeword based on the 257 bit code block is relatively low, since the overhead of one 257 bit code block is lower than the overhead of four 66 bit code blocks. When using the 100G channel for data transmission, the transmission rate required for transmitting the FEC codeword based on the transcoded code block is 103.125Gb/s, which is the same as the transmission rate required for transmitting the 66-bit code block that is not FEC encoded.

After the receiving end obtains the FEC code word, decoding the FEC code word to obtain 257 bit code blocks, inverting the 257 bit code blocks into four 66 bit code blocks, and decoding the four 66 bit code blocks to obtain a control block and a data block in MII format. Since the errors in the FEC codeword can be identified based on the FEC errors and the vast majority of processing in the PCS is based on 257 bit code blocks, the 64B/66B codec process and the corresponding transcoding/inversion process will result in unnecessary delay, power consumption and chip area occupation.

In this regard, the embodiments of the present application provide an encoding method and a decoding method. In the embodiment of the application, during the encoding process, 2 is not needed ⁿ Each group of code stream blocks in the group of code stream blocks is subjected to 64B/66B coding, and then 2 is subjected to ⁿ Transcoding the 66-bit code blocks to obtain target code blocks, and decodingIn the process of (2), the target code block does not need to be transcoded to obtain 2 ⁿ 66 bit code blocks, 2 pairs ⁿ Decoding the 66 bit code blocks to obtain 2 ⁿ And (5) assembling code stream blocks. Therefore, the efficiency of encoding and decoding is improved, and the time delay, the power consumption and the occupied chip area caused by the encoding and decoding process are reduced.

The encoding method and the decoding method provided by the embodiment of the application can be suitable for the current Ethernet interface or other scenes needing to transmit data. Taking the implementation scenario shown in fig. 1 as an example, the implementation scenario includes a plurality of chips, and information interaction can be performed between the chips, so as to realize data transmission. Illustratively, both chip 102 and chip 104 support FEC encoding and FEC decoding, and channel 105 between chip 102 and chip 104 is capable of transmitting FEC encoded data. The chip 102 may be pair 2 ⁿ The group code stream block is first encoded to obtain a target code block, the target code block is second encoded according to a first FEC code pattern to obtain first data, and the first data is sent to the chip 104 through the channel 105. Illustratively, errors may occur in the transmission of the first data in channel 105, and the received data is referred to as the second data. After receiving the second data, the chip 104 may perform second decoding on the second data using the first FEC code pattern to obtain a target code block, and perform first decoding on the target code block to obtain 2 ⁿ And (5) assembling code stream blocks.

Where n is an integer greater than 1, the first FEC pattern includes, but is not limited to, any one or a concatenated combination of a RS code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Hamming code, an extended-BCH code, an extended-Hamming code, a fire code, a turbo (turbo) code, a turbo product code (turbo product code, TPC), a step (stage) code, and a low-density parity-check (LDPC) code.

Alternatively, the implementation scenario shown in fig. 1 may include multiple network devices, with the chip 102 located on the first network device 101 and the chip 104 located on the second network device 103. Each network device may include at least one chip, only two network devices are illustrated in fig. 1, each network device including one chip as an example.

In connection with the implementation scenario shown in fig. 1, the encoding method provided in the embodiment of the present application is shown in fig. 2. Illustratively, the encoding method provided by the embodiments of the present application is performed by the chip 102 in fig. 1, including, but not limited to, step 201 and step 202.

Step 201, acquire 2 ⁿ And the code stream blocks comprise control blocks and data blocks, and n is an integer greater than 1.

The number of the code stream blocks is not limited, and n is an integer greater than 1. In one possible implementation, the 2 ⁿ The group code stream blocks are all from the MII. With respect to MII-based acquisition 2 ⁿ The manner of grouping the code stream blocks is not limited in this embodiment. For example, the MII may be 2 acquired using the institute of Electrical and electronics Engineers (the Institute of Electrical and Electronics Engineers, IEEE) 802.3 standard, such as defined by IEEE802.3-2018 and other versions of the IEEE802.3 standard ⁿ And (5) assembling code stream blocks. For example, n has a value of 2, that is, four groups of code stream blocks are acquired.

In one possible implementation, for 2 ⁿ Any group of code stream blocks in the group of code stream blocks, wherein a control block of any group of code stream blocks comprises t bits, a data block of any group of code stream blocks comprises 8t bits, and t is a positive integer. Wherein 8t represents 8 times t, and 8t may also be represented as 8*t. Illustratively, t has a value of 8, i.e., for any set of code stream blocks, the control block of any set of code stream blocks includes 8 bits and the data block of any set of code stream blocks includes 64 bits. In one possible implementation, the control blocks include t bits that are control bits, i.e., the control blocks include t control bits; the 8t bits included in the data block are all data, that is, the 8t bits included in the data block are data.

Illustratively, a control block comprising 8 control bits is denoted as TXC <7:0>, a data block comprising 64 bits of data is denoted as TXD <63:0>, and the order of the respective bits of the control block and the data block is from most significant bit (most significant bit, MSB) to least significant bit (least significant bit, LSB).

In one possible implementation, the data included in TXD <63:0> includes, but is not limited to, MAC frame data and control data, and TXD <63:0> has 8 bits as one data segment. TXC <7:0> is used for marking each data segment in TXD <63:0> so as to perform different processing on the MAC frame data and the control data, and further correctly recover the MAC frame data and the control data at the receiving side.

Illustratively, for convenience of the following description, the names of the data segments are defined, and the 8-bit MAC frame data within TXD <63:0> is referred to as a data word (data character), expressed in/D/with its corresponding txc=0; the 8-bit control data is referred to as control word (control character), expressed in/C/which corresponds to txc=1. Illustratively, the 8-bit control word (/ C /) is different in meaning, including, but not limited to, the following 7 types: error control words (error machine,/E /), start control words (start machine,/S /), stop control words (terminate character,/T /), ordered set control words (ordered set character,/O /), idle control words (idle machine,/I /), low power idle control words (low power idle,/LI /) and other legal 8-bit control words. Specific meanings and values of the control words may refer to IEEE802.3-2018, and embodiments of the present application are not repeated.

Illustratively, when the control block of the code stream block is a first specified value, the data block of the code stream block does not include a control word, the data block of the code stream block is called a MAC frame data block (D), and the type of the code stream block is a data code stream block. The first specified value is used for indicating that the type of the code stream block is a data code stream block. For example, the first specified value is 0x00, TXC <7:0> =0x00 of the code stream block, TXD <63:0> of the code stream block does not include a control word, the data block of the code stream block is a MAC frame data block, and the type of the code stream block is a data code stream block. When the control block of the code stream block is not the first specified value, the data block of the code stream block comprises at least one control word, the data block of the code stream block is called a control block (C), and the type of the code stream block is a control code stream block. For example, TXC <7:0> -of the code stream block! =0x00, the TXD <63:0> of the code stream block includes at least one control word, the data block of the code stream block is a control data block, and the type of the code stream block is a control code stream block. Illustratively, the control data blocks (C) differ in function, including but not limited to the following 7 types: error block (E), start block (S), stop block (T), ordered-set block (ordered set block, O), idle block (I), low-power idle block (low power idle block, LPI), and other control data blocks.

Step 202, pair 2 ⁿ Performing first coding on the group code stream blocks to obtain target code blocks, wherein the target code blocks comprise data units and are based on 2 ⁿ The type of control block determination of the block of the group code stream, the data unit is based on 2 ⁿ Coding mode pair 2 determined by control block and data block of group code stream block ⁿ And the data blocks of the group code stream block are obtained by first encoding.

Illustratively, the control blocks of each group of code stream blocks are all 8 bits, the data blocks are all 64 bits, and the four groups of code stream blocks are first encoded to obtain a 257-bit target code block, for example, the target code block is a 257-bit encoded block (257 b encoded block). In the embodiment of the present application, n=2 is taken as an example, and when n is other value, the first encoding process may be performed on every four groups of code stream blocks, so as to obtain a plurality of target code blocks. For example, n=3, that is, eight groups of code stream blocks are obtained, a target code block may be obtained by performing first encoding on the first four groups of code stream blocks, and a target code block may be obtained by performing first encoding on the second four groups of code stream blocks.

In one possible implementation, pair 2 ⁿ The group code stream block is first encoded to obtain a target code block including, but not limited to, the following coding mode one and coding mode two.

Coding mode one, based on 2 ⁿ The control block of the group code stream block determines the type of the target code block as a data code block; based on 2 ⁿ Sequential pair 2 of group code stream blocks ⁿ Performing first coding on the data blocks of the group code stream blocks to obtain data units; based on the type and the data unit, a target code block is obtained.

For example, for the target code block obtained by the first encoding mode, the type is used for indicating that the target code block is a data code block; data unit baseAt 2 ⁿ Sequential pair 2 of group code stream blocks ⁿ And performing first coding on the data blocks of the group code stream blocks to obtain the data blocks.

In one possible implementation, at 2 ⁿ And under the condition that the control blocks of the group code stream blocks are all of the first appointed value, determining the type of the target code block as the data code block. For example, the control blocks of each group of code stream blocks are denoted as TXC<7:0>The first designated value is 0x00, TXC in each group of code stream blocks<7:0>And under the condition of 0x00, the types of the code stream blocks of each group are data code stream blocks.

In one possible implementation, 2 is based on ⁿ Sequential pair 2 of group code stream blocks ⁿ Performing first coding on the data blocks of the group code stream blocks to obtain data units, wherein the first coding comprises the following steps: based on 2 ⁿ The sequence of the group code stream blocks is respectively 2 ⁿ The data blocks of the group code stream block include bits as bits of the data unit to obtain the data unit.

Illustratively, the sequence numbers of the four groups of code stream blocks are denoted by j, j=0, 1,2, or 3.TXD_j <63:0> represents a data block of a j-th group of code stream blocks, tx_coded <256:0> represents a target code block, wherein tx_coded <0> represents a type of the target code block, tx_coded < (64j+64): (64j+1) > represents (64j+64) -th to (64j+1) -th bits of the target code block, and respective bits of tx_coded <256:0> are expressed as follows in expression 1 and expression 2:

tx_coded <0> =1 (expression 1)

tx_coded < (64j+64): (64j+1) > = txd_j <63:0>, j = 0,1,2 or 3 (expression 2)

In expression 1, tx_coded <0> =1 indicates that the type is a data code block, and in expression 2, tx_coded < (64j+64): (64j+1) > =txd_j <63:0> indicates that a plurality of bits of the data block of each group of code stream blocks are respectively taken as a plurality of bits of the data unit.

For example, when j=0, tx_coded <64:1> =txd_0 <63:0>, indicating that the 63 th to 0 th bits of the data block of the 0 th group of code stream blocks are taken as the 64 th to 1 st bits of the target code block, respectively. When j=1, tx_coded <128:65> =txd_1 <63:0>, meaning that the 63 st to 0 th bits of the data block of the 1 st group of code stream blocks are respectively taken as the 128 th to 65 th bits of the target code block. When j=2, tx_coded <192:129> =txd_2 <63:0>, meaning that the 63 st to 0 th bits of the data block of the 2 nd group of code stream blocks are taken as the 192 st to 129 th bits of the target code block, respectively. When j=3, tx_coded <256:193> =txd_3 <63:0>, meaning that the 63 rd bit to the 0 th bit of the data block of the 3 rd group of code stream blocks are taken as the 256 th bit to the 193 rd bit of the target code block, respectively.

Illustratively, fig. 3 shows a schematic diagram of a process for obtaining a target code block. As shown in fig. 3, for the four obtained groups of code stream blocks, the control blocks of each group of code stream blocks are denoted as TXC <7:0>, and the data blocks are denoted as TXD <63:0>. The TXC <7:0> of the four groups of code stream blocks is 0x00, and the type of the target code block is a data code block. Illustratively, the type of the target code block corresponds to bit 0 of the target code block, and assigning bit 0 to 1 indicates that the type is a data code block. The embodiments of the present application are not limited with respect to the manner in which the 0 th bit is assigned to represent the type as a data code block. Based on the order of the four groups of code stream blocks, a plurality of bits of the data blocks of the four groups of code stream blocks are respectively used as a plurality of bits of the data unit, so as to obtain the data unit. Thus, the target bit can be obtained based on the type and the data unit.

Illustratively, the structure of the resulting target code block is shown in fig. 4, where bit 0 of the target code block is used to represent the type of the target code block, and bit 0 is assigned a value of 1 to represent the type as the data code block. Bits 1 to 256 of the target code block are used to represent the data unit of the target code block, where D0 represents 64 bits of the data block of the 0 th group of code stream blocks, D1 represents 64 bits of the data block of the 1 st group of code stream blocks, D2 represents 64 bits of the data block of the 2 nd group of code stream blocks, and D3 represents 64 bits of the data block of the 3 rd group of code stream blocks.

Coding mode two, based on 2 ⁿ The control block of the group code stream block determines the type of the target code block as a control code block; based on 2 ⁿ A control block and a data block of the group code stream block, obtaining a code block Identifier (ID) for indicating the type of the data block of each group code stream block and eachThe content of the code block after the first coding is in the position of the code block content; based on 2 ⁿ Sequence pair 2 determined by control block and data block of group code stream block ⁿ Performing first coding on the data blocks of the group code stream blocks to obtain code block contents; the target code block is derived based on the type and the data unit, wherein the data unit includes a code block ID and code block content. The value of the code block ID corresponds to 2 of the target code block ⁿ The combinations of the group code stream blocks are in one-to-one correspondence. The value of the code block ID is equal to 2 ⁿ The correspondence between the combinations of the group code stream blocks can be set as needed, for example, when the code block ID is 0x01, it indicates the consecutive 2 corresponding to the target code block ⁿ The first group of blocks is the Start of ethernet frame (Start), 2 later ⁿ -1 group of code stream blocks are all ethernet frame Data (Data). Or when the code block ID is 0xF0, representing the continuous 2 corresponding to the target code block ⁿ Group code stream block 2 ⁿ The group code stream block is the end of ethernet frame, first 2 ⁿ -1 code stream block is Data (Data) of an ethernet frame. Or when the code block ID is 0xD1, representing the continuous 2 corresponding to the target code block ⁿ All the code stream blocks of the group code stream block are Idle. For the value of code block ID and 2 above ⁿ The correspondence between combinations of the group code stream blocks is not limited to the cases listed in the embodiments of the present application, and the present application is not limited thereto. The above-mentioned code block ID is an example, and the values are not limited to the values of the above-mentioned examples in practical application, as long as the code block ID can be obtained and 2 ⁿ The combinations of the group code stream blocks may have a one-to-one correspondence, which is not limited in the embodiment of the present application.

For the target code block obtained by adopting the second coding mode, the type is used for indicating that the target code block is a control code block; the data unit includes a code block ID and code block content, the code block content based on 2 ⁿ Sequence pair 2 determined by control block and data block of group code stream block ⁿ The data block of the group code stream block is obtained by first encoding, and the code block ID is based on 2 ⁿ The control block and the data block of the group code stream block are obtained, and the code block ID is used for indicating the type of the data block of each group code stream block and the position of the content of each group code stream block after the first coding in the content of the code block . Illustratively, 2 ⁿ The order of determination of the control blocks and the data blocks of the group code stream block is 2 ⁿ The order of reception of the group code stream blocks.

In one possible implementation, at 2 ⁿ And if the control block of at least one group of code stream blocks is a second designated value, determining the type of the target code block as the control code block, wherein the second designated value is used for indicating that the type of the code stream block is the control code stream block. That is, at 2 ⁿ In the case that at least one group of code stream blocks is a control code stream block, the target code block is a control code block. Wherein the second specified value is different from the first specified value. For example, the control blocks of each group of code stream blocks are denoted as TXC<7:0>For example, the first specified value is 0x00, and at least one group of code stream blocks among the code stream blocks has TXC<7:0>In the case of the second specified value, i.e., not 0x00, the target code block is a control code block.

In one possible implementation, 2 is based on ⁿ The control block and the data block of the group code stream block obtain a code block ID comprising: based on 2 ⁿ Control block of group code stream block gets 2 ⁿ The type of the data block of the group code stream block, and the code block ID of the target code block is obtained based on the type of the data block of each group code stream block and the order of each group code stream block. Illustratively, the code block ID includes m bits, m being a positive integer of 4 or more. For example, the structure of the target code block is as shown in fig. 5, the type corresponds to the 0 th bit, the code block ID corresponds to the m-1 st bit to the 1 st bit, and the code block content corresponds to the remaining bits. Illustratively, m=8 or m=12.

Illustratively, the code block IDs include a first ID for indicating the type of the data block of each group of code stream blocks and a second ID for indicating the position of the first encoded content of each group of code stream blocks in the code block content. For example, as shown in fig. 6, the target code block has a structure in which the type corresponds to the 0 th bit, the code block ID corresponds to the m-1 st bit to the 1 st bit, the code block content corresponds to the rest of bits, the m-1 st bit to the 1 st bit are divided into two parts, the former part of the lower bits is the first ID, and the latter part of the upper bits is the second ID. For example, the code block ID is 12 bits, the first 4 bits of the lower bits are the first ID, the last 8 bits of the upper bits are the second ID, the target code block has a structure as shown in fig. 7, the type corresponds to the 0 th bit, the first ID corresponds to the 4 th bit to the 1 st bit, the second ID corresponds to the 12 th bit to the 5 th bit, and the code block content corresponds to the rest 244 bits. Illustratively, the first ID includes four bits that respectively indicate the type of data blocks of the four groups of code stream blocks. For example, in the case where the data block of the code stream block is a MAC frame data block, the bit corresponding to the code stream block is 1; in the case where the data block of the code stream block is a control data block, the corresponding bit of the code stream block is 0.

In either case, the code block ID may be provided with hamming distance protection.

In one possible implementation manner, for a plurality of situations of the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first encoding in the code block content, the code block IDs corresponding to the situations are different. That is, the unique code block ID is indicated for various cases of the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first encoding in the code block content. Illustratively, four groups of code stream blocks are taken as an example for explanation, and the types of data blocks of the four groups of code stream blocks include, but are not limited to, the following cases A1 to A8.

In case A1, the data blocks of the four groups of code stream blocks include data blocks of the type error block.

Illustratively, for A1, for different numbers and different locations of data blocks of the type error blocks, the data blocks of the four groups of code stream blocks are shown in fig. 8, where C0 represents other types of control data blocks than the error blocks. For example, for case 1 in fig. 8, the type of data block of the first group of code stream blocks is an error block, and the types of data blocks of the remaining three groups of code stream blocks may be MAC frame data blocks or other types of control data blocks other than the error block. The other cases in fig. 8 are the same as the principle of case 1 described above, and will not be described here again.

In case A2, only one data block of the type starting block is included in the data blocks of the four groups of code stream blocks.

Illustratively, for A2, for different locations of data blocks of the type start block, data blocks of four groups of code stream blocks are shown in fig. 9, where C1 represents other types of control data blocks than start block, stop block, error block, and ordered set block. For example, for case 1 in fig. 9, the type of data block of the first group of code stream blocks is the start block, and the types of data blocks of the remaining three groups of code stream blocks are all MAC frame data blocks. For case 2 in fig. 9, the type of the data block of the first group of code stream blocks is C1, the type of the data block of the second group of code stream blocks is a start block, and the types of the data blocks of the remaining two groups of code stream blocks are MAC frame data blocks. For case 3 in fig. 9, the types of data blocks of the first and second groups of code stream blocks are C1, the type of data block of the third group of code stream blocks is a start block, and the type of data block of the fourth group of code stream blocks is a MAC frame data block. For case 4 in fig. 9, the types of the data blocks of the first to third groups of code stream blocks are C1, the type of the data block of the fourth group of code stream blocks is a start block, and the type of the data block of the fourth group of code stream blocks is a MAC frame data block.

In case A3, only one data block of the termination block type is included in the data blocks of the four groups of code stream blocks.

Illustratively, for A3, for different locations of data blocks of the type termination block, data blocks of four groups of code stream blocks are shown in fig. 10, where C2 represents other types of control data blocks than the start block, the termination block, the error block, and the ordered set block. For example, for case 1 in fig. 10, the type of data block of the first group of code stream blocks is a termination block, and the types of data blocks of the remaining three groups of code stream blocks are all C2. For case 2 in fig. 10, the type of data block of the first group of code stream blocks is MAC frame data block, the type of data block of the second group of code stream blocks is termination block, and the types of data blocks of the remaining two groups of code stream blocks are C2. For case 3 in fig. 10, the types of data blocks of the first group of code stream blocks and the second group of code stream blocks are both MAC frame data blocks, the type of data block of the third group of code stream blocks is a termination block, and the type of data block of the fourth group of code stream blocks is C2. For case 4 in fig. 10, the types of data blocks of the first to third groups of code stream blocks are all MAC frame data blocks, and the type of data block of the fourth group of code stream blocks is a termination block.

In one possible implementation, where the data block includes a termination control word (/ T /), the data block is of the type termination block. Illustratively, the different instances of the termination block are shown in FIG. 11, depending on the different locations of the termination control word. In fig. 11, the termination block is 64 bits, one byte every 8 bits; i denotes the i-th byte of the termination control word as termination block, i=0, 1,2,3,4,5,6 or 7; /C3/represents the remaining control words except the termination control word, the padding bit may be 0. The ordering of the/T/,/D/,/C3/and fill bits in this implementation may be referred to the ordering shown in fig. 11 and will not be described again.

In the case where only one data block of the termination block type is included in the data blocks of the four groups of code stream blocks, the code block IDs are different for the termination blocks corresponding to the termination control words at different positions. That is, in combination with cases 1 to 4 shown in fig. 10 and cases 1 to 8 shown in fig. 11, the code block IDs corresponding to these 32 cases are different.

In case A4, the data blocks of the four groups of code stream blocks include data blocks of which types are ordered blocks, and do not include data blocks of which types are start blocks or end blocks.

Illustratively, for A4, for different numbers and different locations of data blocks of the type of ordered set blocks, the data blocks of the four groups of code stream blocks are shown in fig. 12, where C4 represents other types of control data blocks than the start block, the end block, the error block, and the ordered set block. For example, for case 1 in fig. 12, the types of data blocks of the first group of code stream blocks are ordered-set blocks, and the types of data blocks of the second group of code stream blocks to the fourth group of code stream blocks are all C4. For case 2 in fig. 12, the type of data blocks of the second group of code stream blocks is an ordered set block, and the types of data blocks of the remaining three groups of code stream blocks other than the second group of code stream blocks are C4. The other cases of fig. 12 may refer to the types of the data blocks of each group of code stream blocks and the sequence thereof in fig. 12, and will not be described herein.

In case A5, the data blocks of the four groups of code stream blocks include data blocks of the type of ordered set blocks and data blocks of the type of start block, and do not include data blocks of the type of termination block.

Illustratively, for A5, for different numbers and different locations of data blocks of the type ordered set of blocks and different locations of data blocks of the type start block, the data blocks of the four groups of code stream blocks are shown in fig. 13, where C5 represents other types of control data blocks than start block, stop block, error block and ordered set of blocks. For example, for case 1 in fig. 13, the types of data blocks of the first group of code stream blocks are ordered blocks, the types of data blocks of the second group of code stream blocks are start blocks, and the types of data blocks of the remaining two groups of code stream blocks are MAC frame data blocks. For case 2, the data blocks of the first group of code stream blocks are of ordered set blocks, the data blocks of the second group of code stream blocks are of C5 type, the data blocks of the third group of code stream blocks are of starting block type, and the data blocks of the fourth group of code stream blocks are of MAC frame data block type. Other cases in fig. 13 may refer to the types of data blocks and the order of the data blocks in each group of code stream blocks in fig. 13, and will not be described herein.

In case A6, the data blocks of the four groups of code stream blocks include data blocks of which the type is a termination block and data blocks of which the type is an ordered set block, and do not include data blocks of which the type is a start block.

Illustratively, for A6, for different locations of data blocks of the type termination block and different numbers and different locations of data blocks of the type ordered set block, data blocks of four groups of code stream blocks are shown in fig. 14, where C6 represents other types of control data blocks than the start block, the termination block, the error block, and the ordered set block. For example, for case 1 in fig. 14, the type of data block of the first group of code stream blocks is a termination block, the type of data block of the second group of code stream blocks is an ordered set block, and the types of data blocks of the remaining two groups of code stream blocks are both C6. For case 2, the type of the data block of the first group of code stream blocks is a termination block, the type of the data block of the third group of code stream blocks is an ordered set block, and the types of the data blocks of the other two groups of code stream blocks are all C6. Other cases in fig. 14 may refer to the types of data blocks of each group of code stream blocks in fig. 14 and the order thereof, and will not be described herein.

In one possible implementation, where the data block includes a termination control word (/ T /), the data block is of the type termination block. The termination block is the same as the termination block in the case A3, that is, the termination block is shown in fig. 11, and will not be described here. Illustratively, in connection with cases 1 to 11 shown in fig. 14 and cases 1 to 8 shown in fig. 11, the code block IDs corresponding to the 88 cases are different.

In case A7, the data blocks of the four groups of code stream blocks include a data block of the type termination block and a data block of the type start block.

Illustratively, for A7, for different locations of the data block of type termination block and the data block of type start block, the data blocks of the four groups of code stream blocks are shown in fig. 15, where C7 represents other types of control data blocks than the start block, the termination block, the error block, and the ordered set block. For example, for case 1 in fig. 15, the type of data block of the first group of code stream blocks is a termination block, the type of data block of the second group of code stream blocks is a start block, and the types of data blocks of the remaining two groups of code stream blocks are MAC frame data blocks. For case 2, the type of data block of the first group of code stream blocks is a termination block, the type of data block of the second group of code stream blocks is C7, the type of data block of the third group of code stream blocks is a start block, and the type of data block of the fourth group of code stream blocks is a MAC frame data block. The other cases in fig. 15 may refer to the types of the data blocks of each group of code stream blocks in fig. 15 and the sequence thereof, and will not be described herein.

In one possible implementation, where the data block includes a termination control word (/ T /), the data block is of the type termination block. The termination block is the same as the termination block in the case A3, that is, the termination block is shown in fig. 11, and will not be described here. Illustratively, in the case where a data block of the type termination block precedes a data block of the type start block, the code block IDs corresponding to the 48 cases are different in combination with cases 1 to 6 shown in fig. 15 and cases 1 to 8 shown in fig. 11. In the case that the data block of the type start block precedes the data block of the type end block, this means that the four groups of code stream blocks correspond to a 32 byte packet, the end control word being the 7 th byte of the end block, i.e. case 8 shown in fig. 11.

In case A8, the data blocks of the four groups of code stream blocks include a data block of a type of a termination block, a data block of a type of an ordered set block, and a data block of a type of a start block.

Illustratively, for A8, for different locations of data blocks of type termination blocks, different locations of data blocks of type start blocks, and different numbers and different locations of data blocks of type ordered set blocks, data blocks of four groups of code stream blocks are shown in fig. 16, where C8 represents other types of control data blocks than start blocks, termination blocks, error blocks, and ordered set blocks. For example, for case 1 in fig. 16, the type of data blocks of the first group of code stream blocks is a termination block, the type of data blocks of the second group of code stream blocks is an ordered set block, the type of data blocks of the third group of code stream blocks is a start block, and the type of data blocks of the fourth group of code stream blocks is a MAC frame data block. For case 2, the type of data blocks of the first group of code stream blocks is a termination block, the type of data blocks of the second group of code stream blocks is an ordered set block, the type of data blocks of the third group of code stream blocks is C8, and the type of data blocks of the fourth group of code stream blocks is a start block. Other cases in fig. 16 may refer to the types of data blocks of each group of code stream blocks in fig. 16 and the order thereof, and will not be described herein.

In one possible implementation, where the data block includes a termination control word (/ T /), the data block is of the type termination block. The termination block is the same as the termination block in the case A3, that is, the termination block is shown in fig. 11, and will not be described here. Illustratively, the code block IDs corresponding to the 40 cases are different in combination with case 1 to case 5 shown in fig. 16 and case 1 to case 8 shown in fig. 11.

The code block IDs corresponding to the respective cases are different for the respective cases included in the case A1 to the case A8. The present embodiment is not limited to this regarding the value of the code block ID corresponding to each case.

Illustratively, for the case where the types of data blocks of three groups of code stream blocks among the four groups of code stream blocks in the case A1 to the case A8 are MAC frame data blocks, the code block IDs include, but are not limited to, two cases: in the first case, when the type of the data block of the first group of code stream blocks is the start block and the types of the data blocks of the other three groups of code stream blocks are all MAC frame data blocks, the code block ID is 0x5E, that is, bits 1 to 8 of the target code block are 01111010. In case two, in the case where the types of the data blocks of the first three groups of code stream blocks are all MAC frame data blocks and the type of the data block of the fourth group of code stream blocks is a termination block, the code block IDs are 0x07,0x17,0x27,0x37,0x47,0x57,0x67,0x77, respectively, corresponding to cases 1 to 8 in fig. 11. Whether the first or second case is described above, the LSB is the first transmitted bit.

For example, for the other cases other than the case one and the case two of the case A1 to the case A8, the code block ID is 12 bits, and the first 8 bits of the code block ID are different from the code block IDs of the case one and the case two.

In one possible implementation, the pair is based on 2 ⁿ Sequence pair 2 determined by control block and data block of group code stream block ⁿ Performing first coding on the data blocks of the group code stream blocks to obtain code block contents, wherein the first coding comprises the following steps: based on 2 ⁿ Sequence pair 2 determined by control block and data block of group code stream block ⁿ And compressing the data blocks of the group code stream blocks to obtain code block contents. Illustratively pair 2 ⁿ Compressing the data blocks of the group code stream block, comprising: pair 2 ⁿ And compressing each bit with 0 in the data block of the group code stream block. For example, each bit of the free block is 0, at 2 ⁿ And compressing each bit of the idle block under the condition that the type of the data block of the group code stream block is the idle block.

In summary, the target code block can be obtained based on the type, code block ID, and code block content.

In one possible implementation, the target code block is an error code block, and the error code block includes data for identifying an error. Illustratively, when 2 ⁿ When the group code stream blocks are not all data code stream blocks and do not belong to any of the cases A1 to A8, determining the target code block as an error code block, and acquiring the code block ID and the code block content of the target code block, wherein the type and the code block ID are used as data for identifying errors in the error code block. For example, bit 0 of the target code block corresponds to a class The 4 th bit to the 1 st bit correspond to the code block ID, the 0 th bit is assigned to 0, and the 4 th bit to the 1 st bit are all assigned to 1.

In one possible implementation, the data blocks of the four groups of code stream blocks are shown in fig. 17, where 0,1,2, and 3 represent the order of the four groups of code stream blocks, C represents the type of the data block of the code stream block as a control data block, and D represents the type of the data block of the code stream block as a MAC frame data block. For example, for combination 0, the data blocks of the four groups of code stream blocks are all of the control data blocks. For each combination in fig. 17, for example, when the type of the data block of the four groups of code stream blocks is not the MAC frame data code stream block, nor is it any of the cases A1 to A8 described above, the target code block is determined to be an error code block. For example, for two groups of code stream blocks, the types of the data blocks are all MAC frame data blocks, and when the type of the data block of a certain group of code stream blocks between the two groups of code stream blocks is any one of a starting block, an ordered set block, an idle block or a low-power idle block, the target code block is an error code block.

In one possible implementation, when the target code block is an error code block, the structure of the target code block is as shown in fig. 18. The 0 th bit of the target code block corresponds to the type, the 0 th bit is 0, the 4 th bit to the 1 st bit correspond to the code block ID, the 4 th bit to the 1 st bit are all 1, and the 256 th bit to the 5 th bit correspond to the code block content. For example, the first 4 bits of the code block content are 0xE, followed by 0x1E for every 8 bits. For another example, each bit of the code block content is 0.

In another possible implementation, when the target code block is an error code block, the length of the code block ID of the target code block is not limited to 4 bits as shown in fig. 18, for example, the length of the code block ID is 8 bits. The 0 th bit of the target code block corresponds to the type, the 0 th bit is 0, the 8 th bit to the 1 st bit correspond to the code block ID, the 8 th bit to the 1 st bit are all 1, and the 256 th bit to the 9 th bit correspond to the code block content. For example, every 8 bits of the code block content is 0x1E. For another example, each bit of the code block content is 0.

The encoding method provided by the embodiment of the application can perform the first encoding on the code stream blocks of different types to obtain the target code block, and has wider applicability.

In one possible implementation, pair 2 ⁿ Performing first coding on the group code stream block to obtain a target code block, wherein the first coding comprises the following steps: based on 2 ⁿ The control block and the data block of the group code stream block obtain an error detection result; based on error detection result pair 2 ⁿ Processing the group code stream block, and processing the processed 2 ⁿ And performing first coding on the group code stream block to obtain a target code block. That is, the target code block is based on the error detection result pair 2 ⁿ The group code stream block is processed to obtain an error detection result based on 2 ⁿ The control block and the data block of the group code stream block are obtained.

Illustratively, based on 2 ⁿ The control block and the data block of the group code stream block obtain an error detection result, comprising: based on 2 ⁿ The control block and the data block of the group code stream block are obtained 2 ⁿ Content and content order of group code stream blocks based on 2 ⁿ The content and the content sequence of the group code stream block obtain an error detection result. For example, when 2 ⁿ When the content sequence of the group code stream block is at least one of the first error condition set, the method comprises the steps of 2 ⁿ The content of the group code stream block is in error order, when 2 ⁿ When the content order of the group code stream blocks is not any of the first error condition set, the method 2 ⁿ The content order of the group code stream blocks is correct. Also for example, when 2 ⁿ When the content of the group code stream block is at least one of the second set of error conditions, the 2 ⁿ Content error of group code stream block, when 2 ⁿ When the content of the group code stream block is not any one of the second error condition set, the method 2 ⁿ The content of the group code stream block is correct.

In one possible implementation, two adjacent groups of code stream blocks are illustrated, and the first set of error conditions includes, but is not limited to, the following 4 conditions.

(1) In the case where the type of the data block of the former group of code stream blocks is the start block, the type of the data block of the latter group of code stream blocks is other types than the MAC frame data.

(2) In the case where the type of the data block of the former group of code stream blocks is MAC frame data, the type of the data block of the latter group of code stream blocks is other type than MAC frame data or termination block.

(3) In the case where the type of the data block of the former group of code stream blocks is the termination block, the type of the data block of the latter group of code stream blocks is other types than the free block or the ordered-set block.

(4) In the case that the type of the data block of the former group of code stream blocks is a free block or an ordered set block, the type of the data block of the latter group of code stream blocks is MAC frame data or a termination block.

In one possible implementation, illustrated as a group of code stream blocks, the second set of error conditions includes, but is not limited to, the following 4 conditions.

(1) For a code stream block in which the data block includes a start control word, the start control word is followed by other content than the data word.

(2) For a code stream block where the data block comprises data words, the data words are followed by other content than the data words or termination control words.

(3) For a code stream block where the data block includes a termination control word, the termination control word is followed by other content than an idle control word or an ordered set control word.

(4) For a code stream block in which the data block includes idle control words or ordered set control words, the idle control words or the ordered set control words are followed by data words or termination control words.

Illustratively, the error detection result includes 2 ⁿ Content order error or content error of group code stream block based on 2 ⁿ The code stream blocks with wrong content sequence or wrong content in the group code stream blocks obtain error blocks, for 2 ⁿ And performing first coding on the code stream blocks and error blocks with correct content sequence in the group code stream blocks to obtain target code blocks. That is, when the error detection result includes 2 ⁿ In case of a content order error or a content error of the group code stream block, the target code block is based on 2 ⁿ The code stream blocks with correct content sequence and correct content in the group code stream blocks and error blocks are obtained by first encoding, and the error blocks are based on 2 ⁿ The code stream blocks with wrong content sequence or wrong content in the group code stream blocks are obtained. Illustratively, the error block includes an error control word (error control character). Example(s)For example, for a code stream block with a content order error or a content error, the content of the code stream block is converted into an error control word to obtain an error block.

Illustratively pair 2 ⁿ Performing first coding on the code stream blocks and the error blocks with correct content sequence in the group code stream blocks to obtain target code blocks, wherein the first coding comprises the following steps: determining the type of the target code block as a control code block; based on 2 ⁿ The code stream blocks with correct content sequence and error blocks in the group code stream blocks obtain code block IDs; based on 2 ⁿ The order of determination of the control blocks and data blocks of the block code stream block is for error blocks and 2 ⁿ And performing first coding on the data blocks of the code stream blocks with correct content sequence and correct content in the group code stream blocks to obtain code block contents. In a possible implementation manner, the error block is an error block in the above case A1, and the manner of obtaining the code block ID and the code block content is the same as the related content principle of the above case A1, which is not described herein again.

Illustratively at 2 ⁿ When each of the group code stream blocks is a code stream block having a content order error or a content error, the method is based on 2 ⁿ Group code stream block gets 2 ⁿ Error blocks for the 2 ⁿ And performing first coding on the error blocks to obtain target code blocks, wherein the target code blocks are error code blocks.

By processing the code stream block with the error, the data with the error can be distinguished from the correct data when the data transmission is carried out later, and the reliability of the data is ensured.

Illustratively, after obtaining the target code block, the method further comprises: performing second coding on the target code block according to the FEC code pattern to obtain first data; the first data is transmitted. The embodiment of the present application is not limited with respect to the manner in which the target code block is second encoded according to the FEC code pattern. And performing second coding on the target code block according to the FEC code pattern to obtain first data, so that the receiving end can correct the received first data, and the accuracy of data transmission is ensured.

The encoding method provided by the embodiment of the application is applied to the 2 comprising a control block and a data block ⁿ The group code stream block is subjected to first encoding to obtain a target code block,without having to pair 2 ⁿ Each group of code stream blocks in the group of code stream blocks is subjected to 64B/66B coding to obtain 2 ⁿ 66 bit code blocks, 2 pairs ⁿ And transcoding the 66-bit code blocks to obtain target code blocks. Therefore, the coding efficiency is improved, and the time delay, the power consumption and the chip area occupation caused by the coding process are reduced.

The foregoing describes the encoding method provided by the embodiments of the present application, and the following describes the decoding method provided by the embodiments of the present application. In connection with the implementation scenario shown in fig. 1, the decoding method provided in the embodiment of the present application is shown in fig. 19. Illustratively, the decoding method provided by the embodiments of the present application is performed by the chip 104 of fig. 1, which includes, but is not limited to, step 1901 and step 1902.

In step 1901, a target code block is obtained, the target code block comprising a type and a data unit.

Illustratively, in connection with the implementation scenario of fig. 1, the chip 102 sends first data encoded in the FEC code pattern to the chip 104 via the channel 105, and during data transmission, errors may occur in the first data, and the data with errors is referred to as second data, and the chip 104 receives the second data via the channel 105.

In one possible implementation, the target code block is obtained, including but not limited to the following manner a and manner B.

Mode a, receiving second data, the second data being obtained based on the first data encoded with the FEC pattern; and performing second decoding on the second data to obtain a target code block, wherein the second decoding is error correction processing.

Illustratively, the target code block is an error code block obtained by error correcting the second data but not successfully error correcting. For example, performing the second decoding on the second data to obtain the target code block includes: and processing the second data according to the FEC code pattern to obtain a first codeword, performing error correction processing on the first codeword, and acquiring a target code block based on the error correction processing result.

Illustratively, the chip 104 has the function of an FEC decoder, and marks all code blocks in a first codeword as error code blocks when the FEC decoder determines that the number of error codes exceeds the error correction capability of the FEC decoder, that is, when the FEC decoder determines that the first codeword cannot be corrected. Thus, in the case where the error correction processing results in marking all the code blocks in the first codeword as error code blocks, the obtained target code block is an error code block.

Illustratively, when the error correction processing results in successful error correction of the first codeword, the code block obtained based on the first codeword after error correction is taken as the acquired target code block, and the code block obtained based on the first codeword after error correction is the code block that is successful in error correction.

Mode B, receiving second data, the second data being obtained based on the first data encoded with the FEC pattern; and performing second decoding on the second data to obtain a target code block, wherein the second decoding is error detection but no error correction processing.

Illustratively, the target code block is an error code block obtained by detecting an error from the second data without correcting the error. For example, performing the second decoding on the second data to obtain the target code block includes: processing the second data according to the FEC code pattern to obtain a first codeword, and performing error detection only but no error correction (bypass correction) on the first codeword; the target code block is acquired based on the result of the error detection but no error correction processing.

Illustratively, the chip 104 has the function of an FEC decoder, and when the FEC decoder detects that there is an error in a first codeword, marks all code blocks in the first codeword as error code blocks. Thus, in the case where the error detection but no error correction processing results in marking all code blocks in the first codeword as error code blocks, the acquired target code block is an error code block.

In an exemplary case where the first codeword is error-free as a result of the error detection but no error correction processing, the code block obtained based on the first codeword is taken as the acquired target code block, and the code block obtained based on the first codeword is an error-free code block.

Illustratively, the frame check sequence (frame check sequence, FCS) frame check performed based on the target code block fails. For example, the target code block is 257 bits, the first 5 bits are 01111, and the remaining 252 bits include, but are not limited to, the following four cases.

(1) The individual bits remain unchanged.

(2) The first 4 bits are 0x1 or 0xE, and every 8 bits in the remaining bits are 0x1E.

(3) Every 8 bits of the first 248 bits are 0x1E and the last 4 bits are 0x1 or 0xE.

(4) Each bit is 0.

Illustratively, the target code block is as shown in fig. 20, b representing a bit.

Step 1902, performing a first decoding on the target code block according to the type and the data unit of the target code block to obtain 2 ⁿ The system comprises a group of code stream blocks, wherein any group of code stream blocks comprises data blocks and control blocks obtained based on types and data units, the data blocks are obtained by performing first decoding on the data units based on decoding modes determined by the types and the data units, and n is an integer larger than 1.

The target code blocks are 257 bits, the control blocks of each group of code stream blocks are 8 bits, and the data blocks are 64 bits. Taking an example of first decoding one target code block to obtain four groups of code stream blocks (n=2) as an example, when a plurality of target code blocks are obtained, the first decoding process may be performed on each target code block to obtain 2 ⁿ And (5) assembling code stream blocks. For example, when two target code blocks are acquired, the two code blocks may be first decoded to obtain four groups of code stream blocks, that is, the two target code blocks may be first decoded to obtain eight groups of code stream blocks.

In one possible implementation, the target code block is first decoded according to the type and the data unit of the target code block to obtain 2 ⁿ The group code stream blocks include, but are not limited to, decoding mode one through decoding mode three as follows.

In the first decoding mode, the type of the target code block is determined to be a data code block based on the type of the target code block, and a data unit of the target code block comprises 2 ⁿ Content of 8t length, t is a positive integer; obtaining 2 based on the type of the target code block ⁿ Control block of group code stream block, 2 included in data unit ⁿ Respectively performing first decoding on 8 t-length content to obtain 2 ⁿ Data blocks of the group code stream block.

Exemplary, the type is used to indicate the number of target code blocksIn the case of the code block, a decoding mode is adopted to perform first decoding on the target code block to obtain 2 ⁿ And (5) assembling code stream blocks. The 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by first decoding the content with the length of 8t corresponding to the ith group of code stream blocks in the data unit, wherein i is more than or equal to 1 and less than or equal to 2 ⁿ Or i is an integer of 0 or more and 2 or less ⁿ -an integer of 1.

In one possible implementation, the type of the target code block is 1, which is used to indicate that the target code block is a data code block, and the data unit of the target code block includes four contents with lengths of 8t, where one content with a length of 8t corresponds to a group of code stream blocks. The 8t length is 64 bits, for example. The control blocks of the four groups of code stream blocks are all set to 0x00, and four 64-bit contents are respectively used as the contents of the data blocks of the four groups of code stream blocks.

Illustratively, j represents the sequence number of the four groups of code stream blocks, j=0, 1,2, or 3.RXC_j <7:0> represents a control block of a j-th group of code stream blocks, RXD_j <63:0> represents a data block of a j-th group of code stream blocks, rx_coded <256:0> represents a target code block, wherein rx_coded <0> represents a type of the target code block, rx_coded < (64j+64): (64j+1) > represents (64j+64) -th to (64j+1) -th bits of the target code block, and contents of RXC_j <7:0> and RXD_j <63:0> are expressed as follows in expression 3 and expression 4:

rxc_j <7:0> =0x00, j=0, 1,2 or 3 (expression 3)

RXD_j <63:0> = rx_coded < (64j+64): (64j+1) >, j=0, 1,2 or 3 (expression 4)

In expression 3, rxc_j <7:0> =0x00 indicates that the control blocks of each group of code stream blocks are all 0x00, and in expression 4, rxd_j <63:0> =rx_coded < (64j+64): (64j+1) > indicates that every 64 bits of a data unit are 64 bits of a data block of a group of code stream blocks.

For example, when j=0, rxd_0<63:0> =rx_coded <64:1>, indicating that the 64 th to 1 st bits of the target code block are respectively regarded as the 63 th to 0 th bits of the data block of the 0 th group of code stream blocks. When j=1, rxd_1<63:0> =rx_coded <128:65>, indicating that the 128 th bit to the 65 th bit of the target code block are respectively regarded as the 63 st bit to the 0 th bit of the data block of the 1 st group of code stream blocks. When j=2, rxd_2<63:0> =rx_coded <192:129>, meaning that the 192 th to 129 th bits of the target code block are respectively regarded as the 63 th to 0 th bits of the data block of the 2 nd group of code stream blocks. When j=3, rxd_3<63:0> =rx_coded <256:193>, meaning that the 256 th to 193 th bits of the target code block are respectively regarded as the 63 rd to 0 th bits of the data block of the 3 rd group of code stream blocks.

A second decoding mode, based on the type of the target code block, determining the type of the target code block as a control code block, wherein a data unit of the target code block comprises a code block ID and code block contents, and the code block ID is used for indicating the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding in the code block contents; obtaining 2 based on type and code block ID ⁿ A control block for the group code stream block, which performs a first decoding of the code block content based on the decoding mode determined by the type and the code block ID to obtain 2 ⁿ Data blocks of the group code stream block.

Illustratively, in the case where the type is used to indicate that the target code block is a control code block, the target code block is first decoded using the second decoding method to obtain 2 ⁿ And (5) assembling code stream blocks. The 2 ⁿ The control block included in the ith group of blocks of the group of blocks is obtained based on the type and the code block ID, 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by first decoding the code block contents based on a decoding mode determined by the type and the code block ID, wherein i is 1 or more and 2 or less ⁿ Or i is an integer of 0 or more and 2 or less ⁿ -an integer of 1.

In one possible implementation, the code block IDs include a first ID for indicating a type of the data block of each group of code stream blocks and a second ID for indicating a position of the first encoded content of each group of code stream blocks in the code block content. Obtaining 2 based on type and code block ID ⁿ A control block for the group code stream block, which performs a first decoding of the code block content based on the decoding mode determined by the type and the code block ID to obtain 2 ⁿ Data block and packet of group code stream blockThe method comprises the following steps: based on type, in first ID and 2 ⁿ Bits corresponding to the group code stream block and 2 in the second ID ⁿ Bits corresponding to the group code stream block are 2 ⁿ Control blocks included in the group code stream block are based on type, and 2 in the first ID ⁿ Bits corresponding to the group code stream block and 2 in the second ID ⁿ The code block content is subjected to first decoding in a decoding mode of bit determination corresponding to the group code stream block to obtain 2 ⁿ Data blocks of the group code stream block.

That is, the control block included in the i-th group of code stream blocks is obtained based on the type, the bit corresponding to the i-th group of code stream blocks in the first ID, and the bit corresponding to the i-th group in the second ID, and the data block included in the i-th group of code stream blocks is obtained by first decoding the content of the code block based on the type, the bit corresponding to the i-th group of code stream blocks in the first ID, and the decoding manner determined by the bit corresponding to the i-th group of code stream blocks in the second ID.

Illustratively, the type of the data block included in the i-th group of code stream blocks is determined based on the content of the control block included in the i-th group of code stream blocks and the content of the data block of the i-th group of code stream blocks.

The type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding are indicated by the unique code block ID, so that the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding are obtained based on the code block ID of the target code block, and the decoding mode of the target code block can be determined based on the type and the code block ID. Thereby being able to obtain 2 based on the type and code block ID ⁿ And the control block of the group code stream block performs first decoding on the code block based on the decoding mode determined by the type and the code block ID to obtain code block content.

A third decoding mode, based on the type of the target code block and the data unit, determining the type of the target code block as an error code block; will 2 ⁿ Setting a control block included in each group of code stream blocks as a first value, and setting 2 ⁿ And setting the data blocks included in each group of code stream blocks in the group of code stream blocks to be second values, wherein the first values and the second values are used for indicating that the code stream blocks are error code stream blocks.

Exemplary embodimentsThe data unit comprises a code block ID, a type and a code block ID, wherein the code block ID is used for indicating that a target code block is an error code block; 2 ⁿ Each group of code stream blocks comprises a control block with a first value of 2 ⁿ The data blocks included in each group of code stream blocks in the group of code stream blocks are second values, and the first values and the second values are used for indicating that the code stream blocks are error code stream blocks. For example, the type of the target code block is 0, the code block ID is 1111, the target code block is an error code block, and the first decoded 2 ⁿ Each group of code stream blocks in the group of code stream blocks comprises a control block of 0xFF,2 ⁿ Each group of code stream blocks includes a data block of 0 xFEFEFEFEFEFE.

Since the decoding method provided by the embodiment of the application can perform the first decoding on different types of target code blocks to obtain 2 ⁿ The method has wider applicability.

In one possible implementation, the target code block is first decoded according to the type and the data unit of the target code block to obtain 2 ⁿ A group code stream block comprising: obtaining an error detection result based on the type of the target code block and the data unit; performing first decoding on the target code block according to the error detection result, the type of the target code block and the data unit to obtain 2 ⁿ And (5) assembling code stream blocks. That is, 2 ⁿ The group code stream block is obtained by performing first decoding on the target code block according to an error detection result, which is obtained based on the type of the target code block and the data unit.

Illustratively, deriving the error detection result based on the type of the target code block and the data unit includes: and obtaining the content and the content sequence of the target code block based on the type of the target code block and the data unit, and obtaining an error detection result based on the content and the content sequence of the target code block. For example, when the content order of the target code block is at least one of the third error condition set, the content order of the target code block is wrong, and when the content order of the target code block is not any of the third error condition set, the content order of the target code block is correct. For another example, when the content of the target code block is at least one of the fourth set of error conditions, the content of the target code block is erroneous, and when the content of the target code block is not any of the fourth set of error conditions, the content of the target code block is correct.

In one possible implementation, taking a target code block as a control code block, the target code block is illustrated by taking four bit groups as an example, one bit group corresponds to a group of code stream blocks obtained through first decoding, and for two adjacent bit groups, the third set of error conditions includes, but is not limited to, the following 4 cases.

(1) In case the former bit group comprises a start control word (/ S /), the latter bit group comprises other contents than a data word (/ D /).

(2) In case the former group of bits comprises only data words, the latter group of bits comprises other content than data words or termination control words (/ T /).

(3) In case the former bit group comprises a termination control word, the latter bit group comprises other content than an idle control word (/ I /) or a sequential ordered set control word (/ O /).

(4) In case the previous bit group comprises an idle control word or a sequence ordered set control word, the latter bit group comprises a data word or a termination control word.

In one possible implementation, illustrated by way of example with one bit group, the fourth set of error conditions includes, but is not limited to, the following 4 conditions.

(1) For a group of bits comprising a start control word, the start control word is followed by other content than the data word.

(2) For a group of bits comprising a data word, the data word is followed by other content than the data word or a termination control word.

(3) For a group of bits comprising a termination control word, the termination control word is followed by other content than an idle control word or a sequence ordered set control word.

(4) For bit groups comprising idle control words or sequence ordered set control words, the idle control words or sequence ordered set control words are followed by data words or termination control words.

In one possible implementationIn the mode, the error detection result includes a content sequence error or a content error of the target code block, and the target code block is first decoded according to the error detection result, the type of the target code block and the data unit to obtain 2 ⁿ A group code stream block comprising: converting the target code block to obtain a second code block, and performing first decoding on the second code block according to the type of the second code block and the data unit to obtain 2 ⁿ And the second code block is obtained by converting the target code block and has the same bit number as the target code block. That is, 2 ⁿ The group code stream block is obtained by performing first decoding on a second code block according to the type and the data unit of the second code block, and the second code block is obtained by converting a target code block and is the same as the target code block in bit number.

Illustratively, converting the target code block to obtain a second code block includes: converting the bit group with the content sequence error or the content error into an error control word for the bit group with the content sequence error or the content error in the target code block; and obtaining a second code block based on the error control word and the bit group with correct content sequence and correct content in the target code block. In one possible implementation, the converted second code block is a control code block, and the second code block may be decoded in a decoding manner.

In another possible implementation, the error detection result includes a content order error or a content error of the target code block, and the first decoding is performed on the target code block according to the error detection result and the type and the data unit of the target code block to obtain 2 ⁿ A group code stream block comprising: performing first decoding on the target code block based on the type of the target code block and the data unit to obtain 2 ⁿ Group first code stream block, pair 2 ⁿ Converting the first code stream block to obtain 2 ⁿ And (5) assembling code stream blocks. That is, 2 ⁿ The group code stream block is based on pair 2 ⁿ 2 obtained by converting the first code stream block of the group ⁿ The group first code stream block is obtained by first decoding the target code block based on the type of the target code block and the data unit.

Illustratively pair 2 ⁿ Converting the first code stream blockTo 2 ⁿ A group code stream block comprising: for 2 ⁿ And converting the code stream block into an error code stream block based on the code stream block obtained by the bit group with the wrong content sequence or the wrong content in the first code stream block. For example, the control block of the error stream block is 0xFF, and the data block is 0 xfefefefefefe. The receiving end can distinguish error data and correct data by processing the target code block with error, so that the reliability of the data is ensured.

According to the decoding method provided by the embodiment of the application, the target code block is subjected to first decoding to obtain 2 comprising a control block and a data block ⁿ The code stream blocks are assembled without transcoding the target code blocks to obtain 2 ⁿ 66 bit code blocks, 2 pairs ⁿ Decoding the 66 bit code blocks to obtain 2 ⁿ And (5) assembling code stream blocks. Therefore, the decoding efficiency is improved, and the time delay, the power consumption and the chip area occupation caused by the decoding process are reduced.

The foregoing describes an encoding method provided by the embodiment of the present application, and corresponding to the foregoing method, the embodiment of the present application further provides an encoding apparatus. Fig. 21 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present application, where the encoding apparatus is applied to a first network device, and the first network device is the first network device in the embodiment shown in fig. 1. The encoding apparatus shown in fig. 21 is capable of performing all or part of the operations performed by the first network device based on the following modules shown in fig. 21. It should be understood that the apparatus may include additional modules than those shown or omit some of the modules shown therein, which is not limiting in this embodiment of the application. As shown in fig. 21, the apparatus includes:

An acquisition module 2201 for acquiring 2 ⁿ The code stream blocks comprise control blocks and data blocks, and n is an integer greater than 1;

a first encoding module 2202 for pair 2 ⁿ Performing first coding on the group code stream blocks to obtain target code blocks, wherein the target code blocks comprise data units and are based on 2 ⁿ The type of control block determination of the block of the group code stream, the data unit is based on 2 ⁿ Coding mode pair 2 determined by control block and data block of group code stream block ⁿ Group code stream blockThe data block is obtained by performing first encoding.

In one possible implementation, the type is used to indicate that the target code block is a data code block; the data unit is based on 2 ⁿ Sequential pair 2 of group code stream blocks ⁿ And performing first coding on the data blocks of the group code stream blocks to obtain the data blocks.

In one possible implementation, the type is used to indicate the target code block as a control code block; the data unit includes a code block identification ID and code block content, the code block content being based on 2 ⁿ Sequence pair 2 determined by control block and data block of group code stream block ⁿ The data block of the group code stream block is obtained by first encoding, and the code block ID is based on 2 ⁿ The control block and the data block of the group code stream block are obtained, and the code block ID is used for indicating the type of the data block of each group code stream block and the position of the content of each group code stream block after the first coding in the code block content.

In one possible implementation, the code block IDs include a first ID for indicating a type of the data block of each group of code stream blocks and a second ID for indicating a position of the first encoded content of each group of code stream blocks in the code block content.

In one possible implementation, the target code block is based on error detection result pair 2 ⁿ The group code stream block is processed to obtain an error detection result based on 2 ⁿ The control block and the data block of the group code stream block are obtained.

In one possible implementation, the error detection result includes 2 ⁿ Content order error or content error of group code stream block, target code block is based on 2 ⁿ The code stream blocks with correct content sequence and correct content in the group code stream blocks and error blocks are obtained by first encoding, and the error blocks are based on 2 ⁿ Content order error or content error in group code stream blockThe code stream block is obtained.

In one possible implementation, n has a value of 2, t has a value of 8, and the target code block has 257 bits.

In one possible implementation, 2 ⁿ The group code stream blocks are all from the media independent interface MII.

In one possible implementation, the apparatus further includes: a second encoding module 2203, configured to perform second encoding on the target code block according to the FEC code pattern to obtain first data; a transmitting module 2204, configured to transmit the first data.

The embodiment of the application provides a coding device, which comprises a control block and a data block 2 ⁿ First encoding the group code stream block to obtain a target code block without 2 ⁿ Each group of code stream blocks in the group of code stream blocks is subjected to 64B/66B coding to obtain 2 ⁿ 66 bit code blocks, 2 pairs ⁿ And transcoding the 66-bit code blocks to obtain target code blocks. Therefore, the coding efficiency is improved, and the time delay, the power consumption and the chip area occupation caused by the coding process are reduced.

The decoding method provided by the embodiment of the application is introduced above, and the embodiment of the application also provides a decoding device corresponding to the method. Fig. 22 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present application, where the apparatus may be applied to a second network device, and the second network device is the second network device in the embodiment shown in fig. 1. The decoding apparatus shown in fig. 22 is capable of performing all or part of the operations performed by the second network device based on the following modules shown in fig. 22. It should be understood that the apparatus may include additional modules than those shown or omit some of the modules shown therein, which is not limiting in this embodiment of the application. As shown in fig. 22, the apparatus includes:

An acquisition module 2301 configured to acquire a target code block, where the target code block includes a type and a data unit;

a decoding module 2302 for decoding the target code block according to the type and the type of the target code blockData unit, first decode target code block to obtain 2 ⁿ The system comprises a group of code stream blocks, wherein any group of code stream blocks comprises data blocks and control blocks obtained based on types and data units, the data blocks are obtained by performing first decoding on the data units based on decoding modes determined by the types and the data units, and n is an integer larger than 1.

In one possible implementation, the type is used to indicate that the target code block is a data code block; 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by first decoding the content with the length of 8t corresponding to the ith group of code stream blocks in the data unit, wherein t is a positive integer, and i is more than or equal to 1 and less than or equal to 2 ⁿ Or i is an integer of 0 or more and 2 or less ⁿ -an integer of 1.

In one possible implementation, the type is used to indicate the target code block as a control code block; the data unit comprises code block identification ID and code block content, wherein the code block ID is used for indicating the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after first coding in the code block content; 2 ⁿ The control block included in the ith group of blocks of the group of blocks is obtained based on the type and the code block ID, 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by first decoding the code block contents based on a decoding mode determined by the type and the code block ID, wherein i is 1 or more and 2 or less ⁿ Or i is an integer of 0 or more and 2 or less ⁿ -an integer of 1.

In one possible implementation, the code block IDs include a first ID for indicating a type of a data block of each group of code stream blocks and a second ID for indicating a position of a first encoded content of each group of code stream blocks in the code block content; the control block included in the ith group of code stream blocks is obtained based on the type, the bit corresponding to the ith group of code stream blocks in the first ID and the bit corresponding to the ith group of code stream blocks in the second ID, and the data block included in the ith group of code stream blocks is obtained by performing first decoding on the content of the code block based on the type, the bit corresponding to the ith group of code stream blocks in the first ID and the decoding mode determined by the bit corresponding to the ith group of code stream blocks in the second ID.

In one possible implementation, the data unit includes a code block identification ID, a type and a code block ID for indicating that the target code block is an error code block; 2 ⁿ Each group of code stream blocks comprises a control block with a first value of 2 ⁿ The data blocks included in each group of code stream blocks in the group of code stream blocks are second values, and the first values and the second values are used for indicating that the code stream blocks are error code stream blocks.

In one possible implementation, the acquiring module 2301 is configured to receive second data, where the second data is obtained based on the first data encoded with a forward error correction FEC pattern; and performing second decoding on the second data to obtain a target code block, wherein the second decoding is error correction processing.

In one possible implementation, the target code block is an error code block obtained by error correcting the second data but not successfully correcting the second data.

In one possible implementation, the acquiring module 2301 is configured to receive second data, where the second data is obtained based on the first data encoded with a forward error correction FEC pattern; and performing second decoding on the second data to obtain a target code block, wherein the second decoding is error detection but no error correction processing.

In one possible implementation, the target code block is an error code block obtained by detecting an error from the second data without correcting the error.

In one possible implementation, 2 ⁿ The group code stream block is obtained by performing first decoding on the target code block according to an error detection result, and the type and the data unit of the target code block, and the error detection result is obtained based on the type and the data unit of the target code block.

In one possible implementationWherein the error detection result includes a content order error or a content error of the target code block, 2 ⁿ The group code stream block is obtained by performing first decoding on a second code block according to the type and the data unit of the second code block, and the second code block is obtained by converting a target code block and has the same bit number as the target code block.

In one possible implementation, the error detection result includes a content order error or a content error of the target code block, 2 ⁿ The group code stream block is pair 2 ⁿ 2 obtained by converting the first code stream block of the group ⁿ The group of first code stream blocks is obtained by performing first decoding on the target code blocks according to the types and the data units of the target code blocks.

In one possible implementation, 2 ⁿ The group code stream blocks are all in the MII format of the media independent interface.

The decoding device provided by the embodiment of the application decodes the target code block to obtain 2 including a control block and a data block ⁿ The code stream blocks are assembled without transcoding the target code blocks to obtain 2 ⁿ 66 bit code blocks, 2 pairs ⁿ Decoding the 66 bit code blocks to obtain 2 ⁿ And (5) assembling code stream blocks. Therefore, the decoding efficiency is improved, and the time delay, the power consumption and the chip area occupation caused by the decoding process are reduced.

It should be understood that the apparatus provided in fig. 21 and fig. 22 is merely illustrative of the division of the functional modules when implementing the functions thereof, and in practical applications, the functional modules may be allocated to different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to implement all or part of the functions described above. In addition, the apparatus and the method embodiments provided in the foregoing embodiments belong to the same concept, and specific implementation processes of the apparatus and the method embodiments are detailed in the method embodiments and are not repeated herein.

The specific hardware structure of the device in the above embodiment is shown in fig. 23 as a network device 1500, which includes a transceiver 1501, a processor 1502 and a memory 1503. The transceiver 1501, the processor 1502 and the memory 1503 are connected by a bus 1504. The transceiver 1501 is configured to receive a message and send the message, the memory 1503 is configured to store instructions or program codes, and the processor 1502 is configured to invoke the instructions or program codes in the memory 1503 to cause the device to perform the relevant processing steps of the first network device or the second network device in the above-described method embodiment. In a specific embodiment, the network device 1500 of the embodiment of the present application may correspond to the first network device or the second network device in the foregoing method embodiments, where the processor 1502 in the network device 1500 reads the instructions or the program code in the memory 1503, so that the network device 1500 shown in fig. 23 can perform all or part of the operations performed by the first network device or the second network device.

The network device 1500 may also correspond to the apparatus shown in fig. 21 and 22 described above, for example, the acquisition module 2201 and the acquisition module 2301 referred to in fig. 21 and 22 correspond to the transceiver 1501, the first encoding module 2202 and the decoding module 2302 processor 1502.

Referring to fig. 24, fig. 24 shows a schematic structural diagram of a network device 2000 according to an exemplary embodiment of the present application. The network device 2000 shown in fig. 24 is configured to perform the operations related to the encoding method shown in fig. 2 and the operations related to the decoding method shown in fig. 19. The network device 2000 is, for example, a switch, a router, or the like.

As shown in fig. 24, the network device 2000 includes at least one processor 2001, a memory 2003, and at least one communication interface 2004.

The processor 2001 is, for example, a general central processing unit (central processing unit, CPU), a digital signal processor (digital signal processor, DSP), a network processor (network processer, NP), a graphics processor (graphics processing unit, GPU), a neural-network processor (neural-network processing units, NPU), a data processing unit (data processing unit, DPU), a microprocessor, or one or more integrated circuits for implementing the aspects of the present application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. PLDs are, for example, complex programmable logic devices (complex programmable logic device, CPLD), field-programmable gate arrays (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. Which may implement or perform the various logical blocks, modules, and circuits described in connection with the disclosure of embodiments of the invention. The processor may also be a combination that performs the function of a computation, e.g., including one or more microprocessors, a combination of a DSP and a microprocessor, and so forth.

Optionally, the network device 2000 also includes a bus. The bus is used to transfer information between the components of the network device 2000. The bus may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 24, but not only one bus or one type of bus. In fig. 24, the components of the network device 2000 may be connected by other manners besides bus connection, and the connection manner of the components is not limited in the embodiment of the present invention.

The Memory 2003 is, for example, but not limited to, a read-only Memory (ROM) or other type of static storage device that can store static information and instructions, as well as a random access Memory (random access Memory, RAM) or other type of dynamic storage device that can store information and instructions, as well as an electrically erasable programmable read-only Memory (electrically erasable programmable read-only Memory, EEPROM), compact disc read-only Memory (compact disc read-only Memory) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media, or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory 2003 is, for example, independent and is connected to the processor 2001 via a bus. Memory 2003 may also be integrated with processor 2001.

The communication interface 2004 uses any transceiver-like device for communicating with other devices or communication networks, which may be ethernet, radio Access Network (RAN) or wireless local area network (wireless local area networks, WLAN), etc. Communication interface 2004 may include a wired communication interface, and may also include a wireless communication interface. Specifically, the communication interface 2004 may be an ethernet (FE) interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an asynchronous transfer mode (asynchronous transfer mode, ATM) interface, a wireless local area network (wireless local area networks, WLAN) interface, a cellular network communication interface, or a combination thereof. The ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In the present embodiment, the communication interface 2004 may be used for the network device 2000 to communicate with other devices.

In a particular implementation, the processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 24, as an example. Each of these processors may be a single-core (single-CPU) processor or may be a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).

In a specific implementation, as an embodiment, the network device 2000 may include multiple processors, such as processor 2001 and processor 2005 shown in fig. 24. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).

In a specific implementation, the network device 2000 may also include output devices and input devices, as one embodiment. The output device communicates with the processor 2001, which can display information in a variety of ways. For example, the output device may be a liquid crystal display (liquid crystal display, LCD), a light emitting diode (light emitting diode, LED) display device, a Cathode Ray Tube (CRT) display device, or a projector (projector), or the like. The input device(s) and processor 2001 are in communication and may receive input from a user in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, a sensing device, or the like.

In some embodiments, memory 2003 is used to store program code 2010 for performing aspects of the present application, and processor 2001 may execute program code 2010 stored in memory 2003. That is, the network device 2000 can implement the encoding method or the decoding method provided by the method embodiment through the processor 2001 and the program code 2010 in the memory 2003. One or more software modules may be included in program code 2010. Optionally, the processor 2001 itself may also store program code or instructions for performing the present aspects.

In a specific embodiment, the network device 2000 of the embodiment of the present application may correspond to the first network device or the second network device in the above-described respective method embodiments, and the processor 2001 in the network device 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored by the processor 2001 itself, so that the network device 2000 shown in fig. 24 can perform all or part of the operations performed by the first network device or the second network device.

The network device 2000 may also correspond to the apparatus shown in fig. 21 and 22 described above, and each of the functional modules in the apparatus shown in fig. 21 and 22 is implemented in software of the network device 2000. In other words, the apparatus shown in fig. 21 and 22 includes functional modules generated after the processor 2001 of the network device 2000 reads the program code 2010 stored in the memory 2003. For example, the acquisition module 2201 and the acquisition module 2301 referred to in fig. 21 and 22 correspond to the communication interface 2004, and the first encoding module 2202 and the decoding module 2302 correspond to the processor 2001 and/or the processor 2005.

Wherein the steps of the methods shown in fig. 2 and 19 are performed by instructions in the form of integrated logic circuits of hardware or software in the processor of the network device 2000. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads information in the memory, and in combination with its hardware, performs the steps of the above method, which will not be described in detail here to avoid repetition.

Referring to fig. 25, fig. 25 illustrates a schematic structure of a network device 2100 provided in another exemplary embodiment of the present application. The network device 2100 shown in fig. 25 is configured to perform all or part of the operations involved in the methods shown in fig. 2 and 19 described above. The network device 2100 is, for example, a switch, router, etc., and the network device 2100 may be implemented by a general bus architecture.

As shown in fig. 25, the network device 2100 includes: a main control board 2110 and an interface board 2130.

The main control board is also called a main processing unit (main processing unit, MPU) or a routing processing card (route processor card), and the main control board 2110 is used for controlling and managing various components in the network device 2100, including routing computation, device management, device maintenance, and protocol processing functions. The main control board 2110 includes: a central processor 2111 and a memory 2112.

The interface board 2130 is also referred to as a line interface unit card (line processing unit, LPU), line card, or service board. The interface board 2130 is used to provide various service interfaces and to enable forwarding of data packets. The service interfaces include, but are not limited to, ethernet interfaces, such as flexible ethernet service interfaces (flexible ethernet Clients, flexE Clients), POS (packet over SONET/SDH) interfaces, etc. The interface board 2130 includes: central processor 2131 network processor 2132, forwarding table entry memory 2134, and physical interface cards (physical interface card, PIC) 2133.

The central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110.

The network processor 2132 is used to implement a message transmission process. The network processor 2132 may be in the form of a forwarding chip. The forwarding chip may be a network processor (network processor, NP). In some embodiments, the forwarding chip may be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (field programmable gate array, FPGA). Specifically, the network processor 2132 is configured to forward the received message based on the forwarding table stored in the forwarding table entry memory 2134, and if the destination address of the message is the address of the network device 2100, upload the message to the CPU (e.g. the central processor 2131) for processing; if the destination address of the message is not the address of the network device 2100, the next hop and the egress interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the egress interface corresponding to the destination address. The processing of the uplink message may include: processing a message input interface and searching a forwarding table; the processing of the downlink message may include: forwarding table lookup, etc. In some embodiments, the central processor may also perform the function of a forwarding chip, such as implementing software forwarding based on a general purpose CPU, so that no forwarding chip is needed in the interface board.

The physical interface card 2133 is used to implement the docking function of the physical layer, from which the original traffic enters the interface board 2130, and from which processed messages are sent out from the physical interface card 2133. The physical interface card 2133, also referred to as a daughter card, may be mounted on the interface board 2130 and is responsible for converting the photoelectric signals into messages and forwarding the messages to the network processor 2132 for processing after performing validity check on the messages. In some embodiments, the central processor 2131 may also perform the functions of the network processor 2132, such as implementing software forwarding based on a general purpose CPU, such that the network processor 2132 is not required in the physical interface card 2133.

Optionally, the network device 2100 includes a plurality of interface boards, for example, the network device 2100 further includes an interface board 2140, the interface board 2140 including: central processor 2141, network processor 2142, forwarding table entry store 2144, and physical interface card 2143. The function and implementation of the various components in interface board 2140 are the same or similar to interface board 2130 and are not described in detail herein.

Optionally, network device 2100 also includes a switch web 2120. Switch board 2120 may also be referred to as a switch board unit (switch fabric unit, SFU). In the case of a network device having multiple interface boards, switch web 2120 is used to accomplish the data exchange between the interface boards. For example, interface board 2130 and interface board 2140 may communicate with each other via switch web 2120.

The main control board 2110 is coupled to the interface board. For example. Main control board 2110, interface board 2130 and interface board 2140 are connected to the system backplane via a system bus to achieve interworking between the switch fabric 2120 and the system backplane. In one possible implementation, an inter-process communication protocol (inter-process communication, IPC) channel is established between the main control board 2110 and the interface boards 2130 and 2140, and communication is performed between the main control board 2110 and the interface boards 2130 and 2140 through the IPC channel.

Logically, network device 2100 includes a control plane that includes a main control board 2110 and a central processor 2111, and a forwarding plane that includes various components that perform forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs the functions of router, generating forwarding table, processing signaling and protocol messages, configuring and maintaining the state of the network device, etc., and the control plane issues the generated forwarding table to the forwarding plane, where the network processor 2132 forwards the message received by the physical interface card 2133 based on the forwarding table issued by the control plane. The forwarding table issued by the control plane may be stored in forwarding table entry memory 2134. In some embodiments, the control plane and the forwarding plane may be completely separate and not on the same network device.

It should be noted that the main control board may have one or more blocks, and the main control board and the standby main control board may be included when there are multiple blocks. The interface boards may have one or more, the more data processing capabilities the network device is, the more interface boards are provided. The physical interface card on the interface board may also have one or more pieces. The switching network board may not be provided, or may be provided with one or more blocks, and load sharing redundancy backup can be jointly realized when the switching network board is provided with the plurality of blocks. Under the centralized forwarding architecture, the network device may not need to exchange network boards, and the interface board bears the processing function of the service data of the whole system. Under the distributed forwarding architecture, the network device may have at least one switching fabric, through which data exchange between multiple interface boards is implemented, providing high-capacity data exchange and processing capabilities. Therefore, the data access and processing power of the network device of the distributed architecture is greater than that of the network device of the centralized architecture. Alternatively, the network device may have a configuration in which only one board card is provided, that is, there is no switching network board, the functions of the interface board and the main control board are integrated on the one board card, and the central processor on the interface board and the central processor on the main control board may be combined into one central processor on the one board card, so as to perform the functions after stacking the two, where the network device has low data exchange and processing capabilities (for example, network devices such as a low-end switch or a router). The specific architecture employed is not limited in any way herein, depending on the specific networking deployment scenario.

In a specific embodiment, the network device 2100 corresponds to the apparatus shown in fig. 21 and 22 described above. In some embodiments, the acquisition module 2201 and the acquisition module 2301 in the apparatus shown in fig. 21 and 22 correspond to the physical interface card 2133 or the physical interface card 2143 in the network device 2100. The first encoding module 2202 and the decoding module 2302 in the apparatus shown in fig. 21 and 22 correspond to at least one of the central processor 2111, the network processor 2132, and the network processor 2142 in the network device 2100.

Based on the network devices shown in fig. 23, fig. 24 and fig. 25, the embodiment of the application further provides a communication system, which includes: the first network device and the second network device. Alternatively, the first network device is the network device 1500 shown in fig. 23 or the network device 2000 shown in fig. 24 or the network device 2100 shown in fig. 25, and the second network device is the network device 1500 shown in fig. 23 or the network device 2000 shown in fig. 24 or the network device 2100 shown in fig. 25.

The methods performed by the first network device and the second network device may be referred to the above description of the embodiments shown in fig. 1, fig. 2, and fig. 19, and will not be repeated here.

It is to be appreciated that the processor described above can be a central processing unit (central processing unit, CPU), but also other general purpose processors, digital signal processors (digital signal processing, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), field-programmable gate arrays (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or any conventional processor or the like. It is noted that the processor may be a processor supporting an advanced reduced instruction set machine (advanced RISC machines, ARM) architecture.

Further, in an alternative embodiment, the memory may include read only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store information of the device type.

The memory may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available. For example, static RAM (SRAM), dynamic RAM (dynamic random access memory, DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM).

There is also provided a computer readable storage medium having stored therein at least one program instruction or code which when loaded and executed by a processor causes a computer to implement the encoding method of fig. 2 or the decoding method of fig. 19.

The present application provides a computer program (product) which, when executed by a computer, can cause a processor or computer to perform the respective steps and/or flows corresponding to the above-described method embodiments.

There is provided a chip comprising a processor for calling from a memory and executing instructions stored in said memory, to cause a communication device on which said chip is mounted to perform the method of the above aspects.

Providing another chip, comprising: the system comprises an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, the processor is used for executing codes in the memory, and when the codes are executed, the processor is used for executing the method in each aspect.

An apparatus is also provided, comprising the chip. Optionally, the device is a network device. The device is illustratively a router or a switch or a server.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The foregoing embodiments have been provided for the purpose of illustrating the technical solution and advantageous effects of the present application in further detail, and it should be understood that the foregoing embodiments are merely illustrative of the present application and are not intended to limit the scope of the present application, and any modifications, equivalents, improvements, etc. made on the basis of the technical solution of the present application should be included in the scope of the present application.

Those of ordinary skill in the art will appreciate that the various method steps and modules described in connection with the embodiments disclosed herein may be implemented as software, hardware, firmware, or any combination thereof, and that the steps and components of the various embodiments have been generally described in terms of functionality in the foregoing description to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Those of ordinary skill in the art may implement the described functionality using different approaches for each particular application, but such implementation is not to be considered as beyond the scope of the present application.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the above storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. By way of example, the methods of embodiments of the present application may be described in the context of machine-executable instructions, such as program modules, being included in devices on a real or virtual processor of a target. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or split between described program modules. Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed device, program modules may be located in both local and remote memory storage media.

Computer program code for carrying out methods of embodiments of the present application may be written in one or more programming languages. These computer program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the computer or other programmable data processing apparatus, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.

In the context of embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable an apparatus, device or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like.

Examples of signals may include electrical, optical, radio, acoustical or other form of propagated signals, such as carrier waves, infrared signals, etc.

A machine-readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a machine-readable storage medium include an electrical connection with one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and module may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or modules, or may be an electrical, mechanical, or other form of connection.

The modules illustrated as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purposes of the embodiments of the present application.

In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.

The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method in the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The terms "first," "second," and the like in this application are used to distinguish between identical or similar items that have substantially the same function and function, and it should be understood that there is no logical or chronological dependency between the "first," "second," and "nth" terms, nor is it limited to the number or order of execution. It will be further understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another element. For example, a first network device may be referred to as a second network device, and similarly, a second network device may be referred to as a first network device, without departing from the scope of the various described examples. The first network device and the second network device may both be any type of network device and, in some cases, may be separate and distinct network devices.

It should also be understood that, in the embodiments of the present application, the sequence number of each process does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not constitute any limitation on the implementation process of the embodiments of the present application.

The term "at least one" in this application means one or more, the term "plurality" in this application means two or more, for example, a plurality of second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

It is to be understood that the terminology used in the description of the various examples described herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various described examples and in the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the terms "if" and "if" may be interpreted to mean "when" ("white" or "upon") or "in response to a determination" or "in response to detection. Similarly, the phrase "if determined" or "if [ a stated condition or event ] is detected" may be interpreted to mean "upon determination" or "in response to determination" or "upon detection of [ a stated condition or event ] or" in response to detection of [ a stated condition or event ] "depending on the context.

It should be appreciated that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.

It should be further understood that reference throughout this specification to "one embodiment," "an embodiment," "one possible implementation," means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," "one possible implementation" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. A method of encoding, the method comprising:

acquisition 2 ⁿ The system comprises a group of code stream blocks, wherein any group of code stream blocks comprises a control block and a data block, and n is an integer greater than 1;

for said 2 ⁿ Performing first coding on the group code stream blocks to obtain target code blocks, wherein the target code blocks comprise data units and are based on the data units 2 ⁿ The type of the control block determination of the group code stream block, the data unit being based on the 2 ⁿ The control block of the group code stream block and the coding mode determined by the data block are used for the data block 2 ⁿ And the data blocks of the group code stream block are obtained by performing the first coding.

2. The method of claim 1, wherein the type is used to indicate that the target code block is a data code block;

the data unit is based on the 2 ⁿ The order of the group code stream blocks is to the 2 ⁿ And carrying out the first coding on the data blocks of the group code stream blocks.

3. The method of claim 1, wherein the type is used to indicate that the target code block is a control code block;

the data unit includes a code block identification ID and code block content, the code block content based on the 2 ⁿ The control block and the data block of the group code stream block are determined to be in the sequence of 2 ⁿ The data blocks of the group code stream block are obtained by the first coding, and the code block ID is based on the 2 ⁿ Control block and data block for group code stream blockThe obtained code block ID is used for indicating the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding in the code block content.

4. The method of claim 3, wherein the code block IDs comprise a first ID for indicating a type of data block of the respective group of code stream blocks and a second ID for indicating a position of the first encoded content of the respective group of code stream blocks in the code block content.

5. The method of claim 3 or 4, wherein the code block ID comprises m bits, the m being an integer of 4 or more.

6. The method of any of claims 3-5, wherein the code block ID is hamming distance protected.

7. The method according to any of claims 3-6, wherein the target code block is an error code block, and wherein the error code block includes data for identifying errors.

8. The method of any of claims 1-7, wherein the target code block pairs the 2 based on error detection results ⁿ Processing the group code stream block to obtain the error detection result based on the step 2 ⁿ The control block and the data block of the group code stream block are obtained.

9. The method of claim 8, wherein the error detection result comprises the 2 ⁿ Content order error or content error of group code stream block, the target code block is based on the 2 ⁿ The first coding is performed on the code stream blocks with correct content sequence and correct content and error blocks in the group code stream blocks, and the error blocks are based on the 2 ⁿ The code stream blocks with wrong content sequence or wrong content in the group code stream blocks are obtained.

10. The method according to any of claims 1-9, wherein the control block comprises t bits, the data block comprises 8t bits, and t is a positive integer.

11. The method of claim 10, wherein n has a value of 2, t has a value of 8, and the target code block has 257 bits.

12. The method according to any one of claims 1-11, wherein said 2 ⁿ The group code stream blocks are all from the media independent interface MII.

13. The method according to any one of claims 1-12, further comprising, after said obtaining the target code block:

performing second coding on the target code block according to a Forward Error Correction (FEC) code pattern to obtain first data;

and sending the first data.

14. A decoding method, the method comprising:

obtaining a target code block, wherein the target code block comprises a type and a data unit;

according to the type of the target code block and the data unit, performing first decoding on the target code block to obtain 2 ⁿ And the code stream blocks comprise data blocks and control blocks obtained based on the type and the data units, wherein the data blocks are obtained by performing first decoding on the data units based on the type and the decoding mode determined by the data units, and n is an integer greater than 1.

15. The method of claim 14, wherein the type is used to indicate that the target code block is a data code block;

Said 2 ⁿ The data blocks included in the ith group of code stream blocks are based on the data listThe content with the length of 8t corresponding to the ith group of code stream blocks in the element is obtained by first decoding, wherein t is a positive integer, and i is more than or equal to 1 and less than or equal to 2 ⁿ Or the integer of i is 0 or more and 2 or less ⁿ -an integer of 1.

16. The method of claim 14, wherein the type is used to indicate that the target code block is a control code block, and the data unit includes a code block identification ID and code block content, the code block ID is used to indicate a type of a data block of each group of code stream blocks and a position of the content of each group of code stream blocks after the first encoding in the code block content;

said 2 ⁿ The control block included in the ith group of code stream blocks among the group of code stream blocks is obtained based on the type and the code block ID, said 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by performing the first decoding on the code block contents based on the decoding mode determined by the type and the code block ID, wherein i is greater than or equal to 1 and less than or equal to 2 ⁿ Or the integer of i is 0 or more and 2 or less ⁿ -an integer of 1.

17. The method of claim 16, wherein the code block IDs comprise a first ID for indicating a type of data block of the respective group of code stream blocks and a second ID for indicating a position of the first encoded content of the respective group of code stream blocks in the code block content;

the control block included in the ith group of code stream blocks is obtained based on the type, the bit corresponding to the ith group of code stream blocks in the first ID and the bit corresponding to the ith group of code stream blocks in the second ID, and the data block included in the ith group of code stream blocks is obtained by performing the first decoding on the code block content based on a decoding mode determined by the type, the bit corresponding to the ith group of code stream blocks in the first ID and the bit corresponding to the ith group of code stream blocks in the second ID.

18. The method according to claim 16 or 17, wherein the type of data blocks comprised by the i-th group of code stream blocks is determined based on the content of the control blocks comprised by the i-th group of code stream blocks and the content of the data blocks comprised by the i-th group of code stream blocks.

19. The method according to any one of claims 16-18, wherein the code block ID comprises m bits, where m is an integer greater than or equal to 4.

20. The method according to any of claims 16-19, wherein the code block ID is hamming distance protected.

21. The method of claim 14, wherein the data unit includes a code block identification, ID, the type and the code block ID being used to indicate that the target code block is an error code block;

said 2 ⁿ Each group of code stream blocks comprises a control block with a first value, wherein 2 is as follows ⁿ And the data blocks included in each group of code stream blocks in the group of code stream blocks are second values, and the first values and the second values are used for indicating that the code stream blocks are error code stream blocks.

22. The method according to any one of claims 14-21, wherein the obtaining the target code block comprises:

receiving second data, the second data being obtained based on the first data encoded with forward error correction FEC;

and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error correction processing.

23. The method of claim 22, wherein the target code block is an error code block obtained by error correcting the second data but not successfully correcting the second data.

24. The method according to any one of claims 14-21, wherein the obtaining the target code block comprises:

and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error detection but no error correction processing.

25. The method of claim 24, wherein the target code block is an error code block obtained by detecting an error from the second data without correcting the error.

26. The method according to any one of claims 14-21, wherein said 2 ⁿ The group code stream block is obtained by performing the first decoding on the target code block according to an error detection result, and the type and the data unit of the target code block, and the error detection result is obtained based on the type and the data unit of the target code block.

27. The method of claim 26, wherein the error detection result comprises a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is obtained by performing the first decoding on the second code block according to the type and the data unit of the second code block, and the second code block is obtained by converting the target code block and has the same bit number as the target code block.

28. The method of claim 26, wherein the error detection result comprises a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is pair 2 ⁿ The first code stream block of the group is converted, the 2 ⁿ The group of first code stream blocks is obtained by performing the first decoding on the target code blocks according to the type of the target code blocks and the data unit.

29. The method according to any of claims 14-28, wherein the control block comprises t bits, the data block comprises 8t bits, and t is a positive integer.

30. The method of claim 29, wherein n has a value of 2, t has a value of 8, and the target code block has 257 bits.

31. The method according to any one of claims 14-30, wherein said 2 ⁿ The group code stream blocks are all in the MII format of the media independent interface.

32. An encoding apparatus, the apparatus comprising:

33. The apparatus of claim 32, wherein the type is used to indicate that the target code block is a data code block; the data unit is based on the 2 ⁿ The order of the group code stream blocks is to the 2 ⁿ And carrying out the first coding on the data blocks of the group code stream blocks.

34. The apparatus of claim 32, wherein the type is used to indicate that the target code block is a control code block; the data unit includes a code block identification ID and code block content, the code block content based on the 2 ⁿ The control block and the data block of the group code stream block are determined to be in the sequence of 2 ⁿ Group code stream blockThe data block is obtained by the first encoding, and the code block ID is based on the code block ID 2 ⁿ The code block ID is used for indicating the type of the data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding in the code block content.

35. The apparatus of claim 34, wherein the code block IDs comprise a first ID for indicating a type of data block of the respective group of code stream blocks and a second ID for indicating a position of the first encoded content of the respective group of code stream blocks in the code block content.

36. The apparatus of claim 34 or 35, wherein the code block ID comprises m bits, the m being an integer greater than or equal to 4.

37. The apparatus of any of claims 34-36, wherein the code block ID is hamming distance protected.

38. The apparatus of any of claims 34-37, wherein the target code block is an error code block, the error code block including data identifying an error.

39. The apparatus of any of claims 32-38, wherein the target code block is configured to encode the 2 based on an error detection result ⁿ Processing the group code stream block to obtain the error detection result based on the step 2 ⁿ The control block and the data block of the group code stream block are obtained.

40. The apparatus of claim 39, wherein the error detection result comprises the 2 ⁿ Content order error or content error of group code stream block, the target code block is based on the 2 ⁿ The first coding is carried out on the code stream blocks and error blocks with correct content sequence in the group code stream blocks, and the code stream blocks and the error blocks are obtainedThe error block is based on said 2 ⁿ The code stream blocks with wrong content sequence or wrong content in the group code stream blocks are obtained.

41. The apparatus of any of claims 32-40, wherein the control block comprises t bits, the data block comprises 8t bits, and t is a positive integer.

42. The apparatus of claim 41, wherein n has a value of 2, t has a value of 8, and the target code block has 257 bits.

43. The apparatus of any one of claims 32-42, wherein 2 ⁿ The group code stream blocks are all from the media independent interface MII.

44. The apparatus of any one of claims 32-43, wherein the apparatus further comprises:

the second coding module is used for carrying out second coding on the target code block according to the Forward Error Correction (FEC) code pattern to obtain first data;

and the sending module is used for sending the first data.

45. A decoding device, the device comprising:

a decoding module, configured to perform a first decoding on the target code block according to the type and the data unit of the target code block to obtain 2 ⁿ And the code stream blocks comprise data blocks and control blocks obtained based on the type and the data units, wherein the data blocks are obtained by performing first decoding on the data units based on the type and the decoding mode determined by the data units, and n is an integer greater than 1.

46. The apparatus of claim 45, wherein the type is used to indicate that the target code block is a data code block;

said 2 ⁿ The data blocks included in the ith group of code stream blocks in the group of code stream blocks are obtained by performing the first decoding on the content with the length of 8t corresponding to the ith group of code stream blocks in the data unit, wherein t is a positive integer, and i is greater than or equal to 1 and less than or equal to 2 ⁿ Or the integer of i is 0 or more and 2 or less ⁿ -an integer of 1.

47. The apparatus of claim 45, wherein the type is used to indicate the target code block is a control code block; the data unit comprises code block Identification (ID) and code block content, wherein the code block ID is used for indicating the type of a data block of each group of code stream blocks and the position of the content of each group of code stream blocks after the first coding in the code block content;

48. The apparatus of claim 47, wherein the code block ID includes a first ID for indicating a type of the data block of each group of code stream blocks and a second ID for indicating a position of the first encoded content of each group of code stream blocks in the code block content; the control block included in the ith group of code stream blocks is obtained based on the type, the bit corresponding to the ith group of code stream blocks in the first ID and the bit corresponding to the ith group of code stream blocks in the second ID, and the data block included in the ith group of code stream blocks is obtained by performing the first decoding on the code block content based on a decoding mode determined by the type, the bit corresponding to the ith group of code stream blocks in the first ID and the bit corresponding to the ith group of code stream blocks in the second ID.

49. The apparatus of claim 47 or 48, wherein the type of data blocks included in the i-th group of code stream blocks is determined based on contents of a control block included in the i-th group of code stream blocks and contents of the data blocks included in the i-th group of code stream blocks.

50. The apparatus of any of claims 47-49, wherein the code block ID comprises m bits, the m being an integer greater than or equal to 4.

51. The apparatus of any of claims 47-50, wherein the code block ID is hamming distance protected.

52. The apparatus of claim 45, wherein the data unit includes a code block identification, ID, the type and the code block ID to indicate that the target code block is an error code block; said 2 ⁿ Each group of code stream blocks comprises a control block with a first value, wherein 2 is as follows ⁿ And the data blocks included in each group of code stream blocks in the group of code stream blocks are second values, and the first values and the second values are used for indicating that the code stream blocks are error code stream blocks.

53. The apparatus of any of claims 45-52, wherein the means for obtaining is configured to receive second data obtained based on first data encoded with a forward error correction, FEC, pattern; and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error correction processing.

54. The apparatus of claim 53, wherein the target code block is an error code block obtained by error correcting the second data but not successfully correcting the second data.

55. The apparatus of any of claims 45-52, wherein the means for obtaining is configured to receive second data obtained based on first data encoded with a forward error correction, FEC, pattern; and performing second decoding on the second data to obtain the target code block, wherein the second decoding is error detection but no error correction processing.

56. The apparatus of claim 55, wherein the target code block is an error code block obtained by detecting an error from the second data but not correcting the error.

57. The apparatus of any one of claims 45-52, wherein said 2 ⁿ The group code stream block is obtained by performing the first decoding on the target code block according to an error detection result, and the type and the data unit of the target code block, and the error detection result is obtained based on the type and the data unit of the target code block.

58. The apparatus of claim 57, wherein the error detection result comprises a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is obtained by performing the first decoding on the second code block according to the type and the data unit of the second code block, and the second code block is obtained by converting the target code block and has the same bit number as the target code block.

59. The apparatus of claim 57, wherein the error detection result comprises a content order error or a content error of the target code block, the 2 ⁿ The group code stream block is pair 2 ⁿ The first code stream block of the group is converted, the 2 ⁿ The group of first code stream blocks is obtained by performing the first decoding on the target code blocks according to the type of the target code blocks and the data unit.

60. The apparatus of any of claims 45-59, wherein the control block comprises t bits, the data block comprises 8t bits, and t is a positive integer.

61. The apparatus of claim 60, wherein n has a value of 2, t has a value of 8, and the target code block has 257 bits.

62. The device of any one of claims 45-61, wherein said 2 ⁿ The group code stream blocks are all in the MII format of the media independent interface.

63. A network device, the network device comprising: a processor coupled to a memory having stored therein at least one program instruction or code that is loaded and executed by the processor to cause the network device to implement the method of any of claims 1-31.

64. A communication system, characterized in that the system comprises a first network device for performing the method according to any of claims 1-13 and a second network device for performing the method according to any of claims 14-31.

65. A computer readable storage medium having stored therein at least one program instruction or code which when loaded and executed by a processor causes a computer to implement the method of any of claims 1-31.

66. A computer program product, characterized in that the computer program product comprises computer program code which, when run by a computer, causes the computer to implement the method as claimed in any one of claims 1-31.

67. A chip comprising a processor for calling from a memory and executing instructions stored in the memory, to cause a communication device on which the chip is mounted to perform the method of any of claims 1-31.

68. A chip, the chip comprising: the device comprises an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, the processor is used for executing codes in the memory, and when the codes are executed, the processor is used for executing the method of any one of claims 1-31.