CN116455292A - Busbar current sampling circuit and permanent magnet synchronous motor - Google Patents

Busbar current sampling circuit and permanent magnet synchronous motor Download PDF

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Publication number
CN116455292A
CN116455292A CN202310485792.5A CN202310485792A CN116455292A CN 116455292 A CN116455292 A CN 116455292A CN 202310485792 A CN202310485792 A CN 202310485792A CN 116455292 A CN116455292 A CN 116455292A
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CN
China
Prior art keywords
circuit
resistor
operational amplifier
bus current
bias
Prior art date
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Pending
Application number
CN202310485792.5A
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Chinese (zh)
Inventor
陈毅东
陈晓东
栗俊杰
杨日阳
赵洵
付晓燕
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Shenzhen Zhaowei Machinery and Electronics Co Ltd
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Shenzhen Zhaowei Machinery and Electronics Co Ltd
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Application filed by Shenzhen Zhaowei Machinery and Electronics Co Ltd filed Critical Shenzhen Zhaowei Machinery and Electronics Co Ltd
Priority to CN202310485792.5A priority Critical patent/CN116455292A/en
Publication of CN116455292A publication Critical patent/CN116455292A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/14—Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
    • H02P21/14—Estimation or adaptation of machine parameters, e.g. flux, current or voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
    • H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
    • H02P25/022—Synchronous motors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
    • H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
    • H02P25/022—Synchronous motors
    • H02P25/024—Synchronous motors controlled by supply frequency
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
    • H02P27/12—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation pulsing by guiding the flux vector, current vector or voltage vector on a circle or a closed curve, e.g. for direct torque control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P2207/00—Indexing scheme relating to controlling arrangements characterised by the type of motor
    • H02P2207/05—Synchronous machines, e.g. with permanent magnets or DC excitation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Ac Motors In General (AREA)

Abstract

The application relates to the field of motor circuits, in particular to a bus current sampling circuit and a permanent magnet synchronous motor, wherein the circuit is applied to a driving circuit of the permanent magnet synchronous motor, and the bus current sampling circuit comprises: the circuit comprises an operational amplifier, a balance circuit, a bias circuit, an amplification regulating circuit and a filtering integrating circuit; the bus of the driving circuit is provided with a sampling resistor connected in series, and one end of the sampling resistor, which is close to the bridge arm, is connected with the balance circuit; the operational amplifier is respectively connected with the amplifying and adjusting circuit, the filtering and integrating circuit, the balancing circuit and the biasing circuit; the balance circuit is also connected with a bias circuit; the amplifying and adjusting circuit is also connected with a filtering and integrating circuit; the balance circuit is used for collecting phase current of the driving circuit; the amplification adjusting circuit is used for adjusting the amplification factor of the operational amplifier; the filtering integration circuit is used for filtering and integrating the current output by the operational amplifier and outputting bus current. The bus current accuracy control circuit reduces the circuit volume on the premise of ensuring the bus current accuracy.

Description

Busbar current sampling circuit and permanent magnet synchronous motor
Technical Field
The application relates to the field of motor circuits, in particular to a bus current sampling circuit and a permanent magnet synchronous motor.
Background
In the prior art, for a single-resistance sampling circuit, bus current is obtained in two general modes, wherein the first mode is to estimate the bus current by detecting phase current through a Hall sensor; the second is to estimate the bus current based on the three-phase current and its time of action in one pulse width modulated wave period. The first mode is high in accuracy, but high in circuit complexity, large in size and high in cost. The second approach, while low cost, is not accurate.
Disclosure of Invention
In view of the above problems, the present application proposes a bus current sampling circuit and a permanent magnet synchronous motor.
The embodiment of the application provides a busbar current sampling circuit, is applied to permanent magnet synchronous motor's drive circuit, busbar current sampling circuit includes: the circuit comprises an operational amplifier, a balance circuit, a bias circuit, an amplification regulating circuit and a filtering integrating circuit;
the bus of the driving circuit is provided with a sampling resistor connected in series, and one end, close to the bridge arm, of the sampling resistor is connected with the balance circuit;
the operational amplifier is respectively connected with the amplifying and adjusting circuit, the filtering and integrating circuit, the balancing circuit and the biasing circuit; the balance circuit is also connected with the bias circuit; the amplifying and adjusting circuit is also connected with the filtering and integrating circuit;
the balance circuit is used for collecting phase currents of the driving circuit;
the bias circuit is used for stabilizing the input voltage of the operational amplifier;
the amplification adjusting circuit is used for adjusting the amplification factor of the operational amplifier;
and the filter integration circuit is used for carrying out filter integration on the current output by the operational amplifier and outputting bus current.
Further, in the bus current sampling circuit, the amplifying and adjusting circuit includes an impedance matching resistor and a feedback resistor;
one end of the impedance matching resistor is respectively connected with one end of the feedback resistor and the inverting input end of the operational amplifier, and the other end of the impedance matching resistor is grounded;
the other end of the feedback resistor is respectively connected with the output end of the operational amplifier and the filter integrating circuit.
Further, in the bus current sampling circuit, the bus current sampling circuit further comprises a first capacitor, and the first capacitor is connected to two ends of the feedback resistor in parallel.
Further, in the bus current sampling circuit, the bias circuit includes a first bias resistor and a second bias resistor;
one end of the first bias resistor is respectively connected with the balance circuit, the second bias resistor and the non-inverting input end of the operational amplifier, and the other end of the first bias resistor is connected with a second level;
one end of the second bias resistor is respectively connected with one end of the first bias resistor, the balance circuit and the non-inverting input end of the operational amplifier, and the other end of the second bias resistor is grounded.
Further, in the bus current sampling circuit, the bus current sampling circuit further comprises a second capacitor, and the second capacitor is connected to two ends of the second bias resistor in parallel.
Further, in the bus current sampling circuit, the balancing circuit includes a balancing resistor, one end of the balancing resistor is used for collecting phase current, and the other end of the balancing resistor is connected with the non-inverting input end of the operational amplifier and the biasing circuit respectively.
Further, in the bus current sampling circuit, the impedance matching resistor and the balance resistor have equal resistance values; the resistance values of the first bias resistor and the second bias resistor are equal; the resistance of the first bias resistor is twice the resistance of the feedback resistor.
Further, in the bus current sampling circuit, the filter integrating circuit includes a filter resistor and a filter capacitor;
one end of the filter resistor is respectively connected with the output end of the operational amplifier and the amplification regulating circuit, the other end of the filter resistor is connected with one end of the filter capacitor, the other end of the filter resistor is also used for outputting the bus current, and the other end of the filter capacitor is grounded.
Further, in the above bus current sampling circuit, the bus current sampling circuit further includes a third capacitor, one end of the third capacitor is connected to the output end of the operational amplifier and the amplification adjusting circuit, respectively, and the other end of the third capacitor is grounded.
The other embodiment of the application also provides a permanent magnet synchronous motor, which comprises the bus current sampling circuit.
The embodiment of the application has the following beneficial effects:
according to the embodiment of the application, the novel circuit is constructed to directly collect the bus current in the permanent magnet synchronous motor, so that the complexity of the bus current sampling circuit is reduced, the size of the bus current sampling circuit is reduced, and the cost is increased on the premise of ensuring the accuracy of the bus current.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are required for the embodiments will be briefly described, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of protection of the present application. Like elements are numbered alike in the various figures.
FIG. 1 illustrates a first schematic diagram of a bus current sampling circuit according to some embodiments of the present application;
fig. 2 shows a schematic structural diagram of a driving circuit of a permanent magnet synchronous motor according to some embodiments of the present application;
FIG. 3 illustrates an inverter space voltage vector schematic diagram of a permanent magnet synchronous motor according to some embodiments of the present application;
FIG. 4 illustrates a first current flow schematic diagram of a drive circuit of a permanent magnet synchronous motor according to some embodiments of the present application;
FIG. 5 illustrates a second current flow schematic diagram of a drive circuit of a permanent magnet synchronous motor according to some embodiments of the present application;
fig. 6 illustrates a second structural schematic diagram of a bus current sampling circuit according to some embodiments of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.
The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
In the following, the terms "comprises", "comprising", "having" and their cognate terms may be used in various embodiments of the present application are intended only to refer to a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be interpreted as first excluding the existence of or increasing the likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of this application belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is identical to the meaning of the context in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The embodiments described below and features of the embodiments may be combined with each other without conflict.
In general, a circuit for precisely calculating the bus current by additionally increasing the circuit volume of the hall sensor is complex, has a large volume and is costly. And bus current error obtained by multiplying each phase of current in the single-resistance sampling circuit by corresponding action time is larger. Therefore, there is a need for a solution that satisfies both the accuracy of the bus current and the lower cost.
Therefore, the application provides a bus current sampling circuit and a permanent magnet synchronous motor to solve the problems.
Referring to fig. 1, a schematic diagram of a bus current sampling circuit according to an embodiment of the present application is shown. The bus current sampling circuit is exemplarily applied to a permanent magnet synchronous motor.
In some embodiments, a bus current sampling circuit is applied to a driving circuit of a permanent magnet synchronous motor, the bus current sampling circuit includes: an operational amplifier 110, a balancing circuit 120, a biasing circuit 130, an amplification adjustment circuit, and a filter integration circuit 150;
the bus of the driving circuit is provided with a sampling resistor connected in series, and one end of the sampling resistor, which is close to the bridge arm, is connected with the balance circuit 120; the operational amplifier 110 is respectively connected with the amplifying and adjusting circuit 140, the filtering integrating circuit 150, the balancing circuit 120 and the biasing circuit 130; the balance circuit 120 is also connected with a bias circuit 130; the amplification adjustment circuit 140 is also connected to a filter integration circuit 150.
The balance circuit 120 is used for collecting phase currents of the driving circuit; the bias circuit 130 is used for stabilizing the input voltage of the operational amplifier 110; the amplification adjusting circuit is used for adjusting the amplification factor of the operational amplifier 110; the filter integration circuit 150 is used for filtering and integrating the current output by the operational amplifier 110 and outputting bus current.
Specifically, the non-inverting input terminal of the operational amplifier 110 is connected to the balancing circuit 120 and the biasing circuit 130, the inverting input terminal of the operational amplifier 110 is connected to the amplifying and adjusting circuit, the output terminal of the operational amplifier 110 is connected to the filter integrating circuit 150, the power supply terminal of the operational amplifier 110 is connected to the first level, and the ground terminal of the operational amplifier 110 is grounded.
In general, for a single-resistance sampling circuit, as shown in fig. 2 to 3, when the space voltage vector Uref is distributed in the first sector, the space voltage vector Uref is mainly synthesized by the basic voltage vectors U1 and U2. When the basic vector U1 (100) acts, the corresponding bridge arm switch states are that the Q1, Q4 and Q6 switch tubes are on, and the rest switch tubes are off, so that a current path loop shown in fig. 4 is formed. As can be seen from fig. 4, the bus current Idc corresponds to the phase current ia, that is, idc=ia. When the basic vector U2 (110) acts, the corresponding switching tubes of the bridge arm switch states Q1, Q3 and Q6 are turned on, and the rest of the switching tubes are turned off, so that a current path loop shown in fig. 5 is formed. As can be seen from fig. 5, there is a correspondence between the bus current Idc and the phase current ic, that is idc= -ic (the current flowing through the center point is positive and the current flowing out the center point is negative). At this time, if the current sampling is performed twice in one PWM period, two-phase current values ia and ic can be obtained, and if the kirchhoff's law is passed, ib can also be obtained. The other sectors are the same as the first sector, each sector only collecting two-phase current. The estimated bus current can be obtained through the two-phase current and the corresponding action time.
The balancing circuit 120 of the BUS current sampling circuit is connected to one end (as shown in the position of ISEN_BUS) of the sampling resistor Rs near the bridge arm in FIG. 2 to collect the average current of the BUS in one PWM period (the BUS current output by the BUS collecting circuit in the application is the required average current of the BUS in one PWM period).
It should be noted that, in order to prevent the voltages at two ends of the sampling resistor from being too large and the power of the sampling resistor from being limited, the resistance value of the sampling resistor is generally small, so that the pressure difference at two ends of the sampling resistor is also small, and if the sampling resistor is directly input into the ADC of the singlechip for collection, the singlechip is difficult to distinguish. Therefore, in order to improve the resolution, the voltage needs to be amplified, and thus, the present application amplifies by the operational amplifier 110.
In some embodiments, as shown in fig. 6, the amplification adjustment circuit in the bus current sampling circuit includes an impedance matching resistor R1 and a feedback resistor R2;
one end of the impedance matching resistor R1 is respectively connected with one end of the feedback resistor R2 and the inverting input end of the operational amplifier 110, and the other end of the impedance matching resistor R1 is grounded; the other end of the feedback resistor R2 is connected to the output terminal of the operational amplifier 110 and the filter integrating circuit 150, respectively.
Specifically, the amplification factor of the electrical signal output from the operational amplifier 110 can be adjusted by adjusting the magnitudes of the resistance values of the impedance matching resistor R1 and the feedback resistor R2. The impedance matching resistor R1 is used for impedance matching. It is conceivable that the magnification may be set arbitrarily for different application scenarios, without limitation.
In some embodiments, as shown in fig. 6, the bus current sampling circuit further includes a first capacitor C1, where the first capacitor C1 is connected in parallel to two ends of the feedback resistor R2. The first capacitor C1 is used for high-power amplification, and plays a role in slowing down the change of the output signal, so that the output signal is stable. Alternatively, the capacitance of the first capacitor C1 ranges from 50 to 200pf, preferably the capacitance of the first capacitor C1 is 100pf.
In some embodiments, as shown in fig. 6, the bias circuit 130 of the bus current sampling circuit includes a first bias resistor R3 and a second bias resistor R4;
one end of the first bias resistor R3 is connected to the balancing circuit 120, the second bias resistor R4 and the non-inverting input end of the operational amplifier 110, respectively, and the other end of the first bias resistor R3 is connected to the second level.
One end of the second bias resistor R4 is connected to one end of the first bias resistor R3, the balance circuit 120 and the non-inverting input end of the operational amplifier 110, respectively, and the other end of the second bias resistor R4 is grounded.
Specifically, since the voltage input at the positive input end of the operational amplifier 110 may be positive or negative, if a negative voltage is input, the output of the operational amplifier 110 is also negative, and finally the voltage output by the operational amplifier 110 is collected by the chip MCU, and the MCU cannot recognize the negative voltage. Therefore, in order to solve this problem, a bias circuit 130 is added to provide a bias voltage so that the input voltage is boosted by the bias circuit 130 to obtain a positive voltage. In addition, the bias circuit 130 can also improve the anti-interference capability of the output voltage of the operational amplifier 110, and obtain a more stable signal.
In some embodiments, as shown in fig. 6, the bus current sampling circuit further includes a second capacitor C2, and the second capacitor C2 is connected in parallel to both ends of the second bias resistor R4. The second capacitor C2 is used to filter out high-frequency noise waves (filter out waves of bias voltage) of the input signal. In the experimental process, it is found that, preferably, the second capacitor C2 selects the pf level, so that the effect of fast response can be achieved, and if a capacitor of uf or nf level is used, the response is slower, so that the purpose of instantaneous detection cannot be achieved.
In some embodiments, as shown in fig. 6, the balancing circuit 120 of the bus current sampling circuit includes a balancing resistor R5, where one end of the balancing resistor R5 is used to collect phase current, and the other end of the balancing resistor R5 is connected to the non-phase input end of the operational amplifier 110 and the bias circuit 130, respectively. Wherein the balancing resistor R5 is used to match the input impedance.
Preferably, the resistance of the balancing resistor R5 is the same as that of the impedance matching resistor R1, so that the offset current and the offset current of the operational amplifier 110 have the least influence, and the output bus current is more accurate.
In some embodiments, during the calculation, the superposition theorem for the circuit and the weak-to-weak and weak-to-weak characteristics of the operational amplifier 110 are available:
where Vo is the output voltage of the operational amplifier 110; v1 is the input voltage of the balance resistor R5; v2 is the endpoint voltage between the feedback resistor R2 and the impedance matching resistor R1; r1 is the resistance value of the impedance matching resistor; r2 is the resistance of the feedback resistor; r3 is the resistance value of the first bias resistor; r4 is the resistance value of the second bias resistor; r5 is the resistance of the balance resistor; 3.3 is the voltage of the second level, namely the voltage connected to one end of the first bias resistor R3.
Therefore, the impedance matching resistor R1 and the balance resistor R5 in the bus current sampling circuit can be equal in resistance value; the resistance values of the first bias resistor R3 and the second bias resistor R4 are equal; the resistance of the first bias resistor R3 is twice the resistance of the feedback resistor R2.
If the first level and the second level select a 3.3V voltage, the bias voltage is 1.65V. The negative pressure of the input signal is maximally-1.65V. It should be noted that, the resistance of the impedance matching resistor R1 and the resistance of the feedback resistor R2 are matched with the resistance of the sampling resistor Rs, if the current flowing through the current sampling resistor is I, i×rs×r2/R1 is less than 1.65.
In addition, on the premise that the parallel resistance of the first bias resistor R3 and the second bias resistor R4 is equal to the resistance of the feedback resistor R2, the resistance of the feedback resistor R2 and the impedance matching resistor R1 is the amplification factor of the circuit. For example, by a factor of 10, the resistance of the feedback resistor R2 is 10 times that of the impedance matching resistor R1.
It should be noted that, when the resistance values of the first bias resistor R3 and the second bias resistor R4 are both set to 500kΩ, the first bias resistor R3 and the second bias resistor R4 form a series loop with a resistance value of 1mΩ, the current resistance value is very small and the anti-interference capability is very weak, and according to practical experimental data, the channel current can ensure anti-interference about 1mA, that is, the resistance values of the first bias resistor R3 and the second bias resistor R4 are selected to ensure that the current of the series loop formed by the two is kept about 1 mA.
In some embodiments, as shown in fig. 6, the filter integration circuit 150 in the bus current sampling circuit includes a filter resistor R6 and a filter capacitor C3;
one end of the filter resistor R6 is respectively connected with the output end of the operational amplifier 110 and the amplifying and regulating circuit, the other end of the filter resistor R6 is connected with one end of the filter capacitor C3, the other end of the filter resistor R6 is also used for outputting bus current, and the other end of the filter capacitor C3 is grounded.
Specifically, because the bus current is provided with the cultural waves, in order to eliminate the cultural waves in the circuit, the low-pass filter circuit consisting of the filter resistor R6 and the filter capacitor C3 is adopted, and high-frequency components in the bus current are filtered after low-pass filtering, so that signals output by the circuit are more stable. Optionally, the value of the filter resistor R6 is in the range of 50-200Ω, and preferably, the filter resistor R6 is in the range of 100deg.Ω.
In some embodiments, as shown in fig. 6, the bus current sampling circuit further includes a third capacitor C4, one end of the third capacitor C4 is connected to the output end of the operational amplifier 110 and the amplification adjusting circuit, and the other end of the third capacitor C4 is grounded.
Alternatively, both the third capacitor C4 and the filter capacitor C3 take 2.2UF or, when only the filter capacitor C3 is present, the filter capacitor C3 takes 4.7UF.
According to experimental data, when the third capacitor C4 is not provided, only the filter capacitor C3 is provided, and the filter capacitor C3 takes 4.7UF, the current output by the operational amplifier 110 has no ripple and small delay.
According to the embodiment of the application, the novel circuit is constructed to directly collect the bus current in the permanent magnet synchronous motor, so that the complexity of the bus current sampling circuit is reduced, the size of the bus current sampling circuit is reduced, and the cost is increased on the premise of ensuring the accuracy of the bus current. According to actual calculation, the bus current sampling circuit is far lower in cost than a Hall sensor utilized in the prior art. In addition, the error of the bus current obtained by sampling is about 8% lower than that of the bus current obtained by multiplying the two-phase current in a single carrier period and the action time in the bus current in the prior art.
Another embodiment of the present application further provides a permanent magnet synchronous motor, including the bus current sampling circuit.
In particular, the permanent magnet synchronous circuit can be applied to electric vehicles (two-wheel, multi-wheel and the like), industrial robots and other electronic equipment.
It will be appreciated that the circuit in this embodiment corresponds to the bus current sampling circuit in the above embodiment, and that the options of the bus current sampling circuit described above are equally applicable to this embodiment, and will not be repeated here.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, of the flow diagrams and block diagrams in the figures, which illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules or units in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application.

Claims (10)

1. A bus current sampling circuit, characterized in that it is applied to a driving circuit of a permanent magnet synchronous motor, said bus current sampling circuit comprising: the circuit comprises an operational amplifier, a balance circuit, a bias circuit, an amplification regulating circuit and a filtering integrating circuit;
the bus of the driving circuit is provided with a sampling resistor connected in series, and one end, close to the bridge arm, of the sampling resistor is connected with the balance circuit;
the operational amplifier is respectively connected with the amplifying and adjusting circuit, the filtering and integrating circuit, the balancing circuit and the biasing circuit; the balance circuit is also connected with the bias circuit; the amplifying and adjusting circuit is also connected with the filtering and integrating circuit;
the balance circuit is used for collecting phase currents of the driving circuit;
the bias circuit is used for stabilizing the input voltage of the operational amplifier;
the amplification adjusting circuit is used for adjusting the amplification factor of the operational amplifier;
and the filter integration circuit is used for carrying out filter integration on the current output by the operational amplifier and outputting bus current.
2. The bus current sampling circuit of claim 1, wherein the amplification adjustment circuit comprises an impedance matching resistor and a feedback resistor;
one end of the impedance matching resistor is respectively connected with one end of the feedback resistor and the inverting input end of the operational amplifier, and the other end of the impedance matching resistor is grounded;
the other end of the feedback resistor is respectively connected with the output end of the operational amplifier and the filter integrating circuit.
3. The bus current sampling circuit of claim 2, further comprising a first capacitor connected in parallel across the feedback resistor.
4. The bus current sampling circuit of claim 2, wherein the bias circuit comprises a first bias resistor and a second bias resistor;
one end of the first bias resistor is respectively connected with the balance circuit, the second bias resistor and the non-inverting input end of the operational amplifier, and the other end of the first bias resistor is connected with a second level;
one end of the second bias resistor is respectively connected with one end of the first bias resistor, the balance circuit and the non-inverting input end of the operational amplifier, and the other end of the second bias resistor is grounded.
5. The bus current sampling circuit of claim 4, further comprising a second capacitor connected in parallel across the second bias resistor.
6. The bus current sampling circuit according to claim 4, wherein the balancing circuit comprises a balancing resistor, one end of the balancing resistor is used for collecting phase current, and the other end of the balancing resistor is respectively connected with the non-phase input end of the operational amplifier and the biasing circuit.
7. The bus current sampling circuit of claim 6, wherein the impedance matching resistor and the balancing resistor have equal resistance values; the resistance values of the first bias resistor and the second bias resistor are equal; the resistance of the first bias resistor is twice the resistance of the feedback resistor.
8. The bus current sampling circuit of claim 1, wherein the filter integrating circuit comprises a filter resistor and a filter capacitor;
one end of the filter resistor is respectively connected with the output end of the operational amplifier and the amplification regulating circuit, the other end of the filter resistor is connected with one end of the filter capacitor, the other end of the filter resistor is also used for outputting the bus current, and the other end of the filter capacitor is grounded.
9. The bus current sampling circuit according to any one of claims 1 to 8, further comprising a third capacitor, wherein one end of the third capacitor is connected to the output end of the operational amplifier and the amplification adjusting circuit, respectively, and the other end of the third capacitor is grounded.
10. A permanent magnet synchronous motor comprising a bus current sampling circuit according to any one of claims 1 to 9.
CN202310485792.5A 2023-04-28 2023-04-28 Busbar current sampling circuit and permanent magnet synchronous motor Pending CN116455292A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310485792.5A CN116455292A (en) 2023-04-28 2023-04-28 Busbar current sampling circuit and permanent magnet synchronous motor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310485792.5A CN116455292A (en) 2023-04-28 2023-04-28 Busbar current sampling circuit and permanent magnet synchronous motor

Publications (1)

Publication Number Publication Date
CN116455292A true CN116455292A (en) 2023-07-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310485792.5A Pending CN116455292A (en) 2023-04-28 2023-04-28 Busbar current sampling circuit and permanent magnet synchronous motor

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