CN116455187A - Ramp signal generating circuit, multiphase converter and control circuit thereof - Google Patents

Ramp signal generating circuit, multiphase converter and control circuit thereof Download PDF

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Publication number
CN116455187A
CN116455187A CN202310341028.0A CN202310341028A CN116455187A CN 116455187 A CN116455187 A CN 116455187A CN 202310341028 A CN202310341028 A CN 202310341028A CN 116455187 A CN116455187 A CN 116455187A
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China
Prior art keywords
signal
ramp
circuit
pwm control
signal generating
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CN202310341028.0A
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Chinese (zh)
Inventor
张珅华
邓建
沈志远
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Nanjing Sili Microelectronics Technology Co ltd
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Nanjing Sili Microelectronics Technology Co ltd
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Priority to CN202310341028.0A priority Critical patent/CN116455187A/en
Publication of CN116455187A publication Critical patent/CN116455187A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H02M3/1586—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel switched with a phase shift, i.e. interleaved
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

According to an embodiment of the present invention, a ramp signal generating circuit and a multiphase converter and a control circuit thereof are disclosed, the ramp signal generating circuit is applied to the multiphase converter, the multiphase converter includes N first circuits and control circuits coupled in parallel, the control circuit is configured to generate N PWM control signals with sequentially staggered phases to respectively control main switching tubes in the N first circuits, the ramp signal generating circuit includes: n ramp signal generating units configured to generate N ramp unit signals corresponding to the N PWM control signals one by one, respectively; the superposition circuit is configured to superpose the N ramp unit signals to obtain ramp signals; wherein the first current ramp signal generating unit is configured to generate the first current ramp unit signal based on the pulse rising edge of the first current PWM control signal and one PWM control signal following the first current PWM control signal. The use of the ramp signal generating circuit improves the anti-interference performance of an actual system.

Description

Ramp signal generating circuit, multiphase converter and control circuit thereof
Technical Field
The present invention relates to the field of power electronics, and more particularly, to a ramp signal generating circuit, a multiphase converter, and a control circuit thereof.
Background
The switching power supply is used for converting an unregulated ac or dc input voltage into a regulated ac or dc output voltage. Along with the development of the power supply requirement of the high-performance processor towards low voltage and high current, the multiphase Buck converter gradually becomes a mainstream topological structure due to the advantages of high power density, small output voltage ripple and the like. And comparing a modulation signal obtained by weighted addition of the output voltage of the multiphase buck converter and the total inductance current of a plurality of buck circuits coupled in parallel in the multiphase buck converter with two input ends of a slope signal input comparator to obtain a total pulse signal T1, and sequentially distributing high pulses of the total pulse signal T1 to the plurality of buck circuits in the multiphase buck converter to generate corresponding PWM signals, wherein each time when the modulation signal and the slope compensation signal intersect, one high pulse of the total pulse signal T1 is output.
The prior art generates a ramp signal using a ramp signal generating circuit shown in fig. 1, which includes a current source I as shown in fig. 1 ISC Capacitance C ISC And switch S ISC Current source I ISC And capacitor C ISC A switch S coupled in series between the power supply Vcc and ground potential ISC Is coupled in series to a current source I ISC And capacitor C ISC The ramp signal is configured as a current source I between the common terminal and the ground potential ISC And capacitor C ISC The voltage at the common terminal. In the prior art, the switch S is turned on by using the total pulse signal T1 ISC Control is performed by a switch S during a low level of the total pulse signal T1 ISC Switch off, current source I ISC Counter capacitor C ISC Charging, during the high level (i.e., high pulse) of the total pulse signal T1, the switch S ISC Conduction and capacitance C ISC Through switch S ISC And (5) discharging. In an ideal case, the discharge is instantaneously completed, and the capacitor C is arranged after the discharge ISC And is rapidly charged, and the ramp signal approaches the triangular wave infinitely. In practice, however, the capacitance C ISC The higher the number of buck circuits connected in parallel or the higher the switching frequency, the higher the frequency of the total pulse signal, resulting in the capacitance C ISC Is charged after discharging, so that the actual ramp signal is severely distorted and is not saw-toothed triangle wave, and the amplitude and the central value of the ramp signal deviate from the designAnd the anti-interference performance of an actual system is greatly reduced.
Disclosure of Invention
In view of this, the present invention provides a ramp signal generating circuit, a multiphase converter and a control circuit thereof, so as to solve the technical problem that the ramp signal is severely distorted when the number of parallel buck circuits is increased or the switching frequency is increased in the prior art.
An embodiment of the present invention provides a ramp signal generating circuit applied to a multiphase converter, where the multiphase converter includes N first circuits and a control circuit coupled in parallel, and the control circuit is configured to generate N PWM control signals with sequentially staggered phases to control main switching tubes in the N first circuits, and the ramp signal generating circuit is characterized by including: n ramp signal generating units configured to generate N ramp unit signals corresponding to the N PWM control signals one by one, respectively; a superimposing circuit configured to superimpose the N ramp unit signals to obtain a ramp signal; wherein the first current ramp signal generating unit is configured to generate the first current ramp unit signal in accordance with a time interval between pulse rising edges of the first current PWM control signal and one PWM control signal following the first current ramp signal.
In one embodiment, the first ramp unit signal is configured to temporarily start rising from zero from the pulse rising edge of the first PWM control signal until the pulse rising edge of the subsequent one of the PWM control signals temporarily stops rising and quickly drops to zero.
In one embodiment, each ramp signal generating unit comprises a first capacitor, the first capacitor in a first current ramp signal generating unit being charged during the time interval to generate a first current ramp unit signal, wherein the ramp unit signal is configured as a voltage on the first capacitor.
In one embodiment, the i-th ramp signal generating unit is configured to generate the i-th ramp unit signal according to the i-th PWM control signal and the pulse rising edge of the i+1th PWM control signal, i being greater than zero and less than N; the nth ramp signal generating unit is configured to generate an nth ramp unit signal according to pulse rising edges of the nth PWM control signal and the 1 st PWM control signal.
In one embodiment, each ramp signal generating unit comprises a first constant current source and a first capacitance, the ramp unit signal being configured as a voltage on the first capacitance; in the ith ramp signal generating unit, at the pulse rising edge of the ith PWM control signal, the first constant current source charges the first capacitor, and at the pulse rising edge of the (i+1) th PWM control signal, the first capacitor discharges, i is greater than zero and less than N; in the nth ramp signal generating unit, the first constant current source charges the first capacitor at a pulse rising edge of the nth PWM control signal, and the first capacitor discharges at a pulse rising edge of the 1 st PWM control signal.
In one embodiment, the ramp signal generating unit further includes a first switch, the first constant current source and the first capacitor being coupled in series between a power supply and a ground potential, the first switch being coupled between a common terminal of the first constant current source and the first capacitor and the ground potential.
In one embodiment, in the ith ramp signal generating unit, at the pulse rising edge of the ith PWM control signal, the first switch is turned off, the first constant current source charges the first capacitor, at the pulse rising edge of the (i+1) th PWM control signal, the first switch is turned on, and the first capacitor discharges, i is greater than zero and less than N; in the nth ramp signal generating unit, at the pulse rising edge of the nth PWM control signal, the first switch is turned off, the first constant current source charges the first capacitor, at the pulse rising edge of the 1 st PWM control signal, the first switch is turned on, and the first capacitor discharges.
In one embodiment, the ramp signal generating unit further includes: the first signal generator comprises a first one-shot circuit, a second one-shot circuit and a first RS trigger, wherein the reset end of the first RS trigger is coupled with the output end of the first one-shot circuit, the set end of the first RS trigger is coupled with the output end of the second one-shot circuit, and the output end of the first RS trigger generates a first signal for controlling the on and off of the first switch.
In one embodiment, in the ith ramp signal generating unit, the input end of the first one-shot circuit receives the ith PWM control signal, and the input end of the second one-shot circuit receives the (i+1) th PWM control signal; in the nth ramp signal generating unit, the input end of the first one-shot circuit receives the nth PWM control signal, and the input end of the second one-shot circuit receives the 1 st PWM control signal.
In one embodiment, the superimposing circuit includes: the output ends of the N voltage-controlled current sources are coupled to the first end of the first resistor, the second end of the first resistor is grounded, and the control ends of the N voltage-controlled current sources respectively receive the N slope unit signals; wherein the ramp signal is configured to be the voltage at the first end of the first resistor.
The embodiment of the invention also provides a control circuit applied to a multiphase converter, wherein the multiphase converter comprises N first circuits coupled in parallel, and the control circuit is characterized by comprising: the ramp signal generating circuit described above to generate a ramp signal; the control circuit is configured to generate N PWM control signals which are sequentially misphased according to the ramp signals so as to respectively control the main switching tubes in the N first circuits.
In one embodiment, the control circuit further comprises: and the conduction time control circuit is configured to generate first control signals according to the output voltage of the multiphase converter, the sum of the inductance currents of the N first circuits and the ramp signals, wherein high pulses in the first control signals sequentially and respectively control the N PWM control signals to be changed from low level to high level so as to control the conduction time of the main switching tubes in the N first circuits.
In one embodiment, the control circuit further comprises: n PWM control signal generating circuits configured to generate N PWM control signals, respectively, to control switching states of the main switching transistors in the N first circuits, respectively; each PWM control signal generating circuit comprises a second RS trigger and a turn-off moment control circuit, in the j-th PWM control signal generating circuit, a setting end of the second RS trigger receives an Nth high pulse in the first control signal, a reset end of the second RS trigger receives an output signal of the turn-off moment control circuit, and an output end of the second RS trigger generates a control signal of the j-th PWM, wherein k is greater than or equal to zero, and j is greater than zero and less than or equal to N.
In one embodiment, the off-time control circuit includes a timer circuit configured to output a pulse signal after delaying a first time to control the j-th PWM control signal to change from a high level to a low level, starting at a time when the j-th PWM control signal changes from a low level to a high level, in the j-th PWM control signal generation circuit.
In one embodiment, the off-time control circuit further comprises: an on-time adjustment circuit configured to control the first time in accordance with an input voltage of the multiphase converter; wherein the first time is reduced when the input voltage becomes large; when the input voltage becomes smaller, the first time is increased.
In one embodiment, the off-time control circuit further comprises: an on-time adjustment circuit configured to control the first time according to an output voltage or a reference voltage signal of the multiphase converter; wherein the first time is increased when the output voltage or reference voltage signal becomes large; the first time is reduced when the output voltage or reference voltage signal becomes smaller.
In one embodiment, the on-time control circuit includes: a modulation voltage signal generation circuit configured to generate a modulation voltage signal from a sum of an output voltage of the multiphase converter and inductor currents of the N first circuits; a slope compensation signal generation circuit configured to generate a slope compensation signal from the slope signal; a first comparator configured to receive the modulated voltage signal at a first input, the ramp compensation signal at a second input, and the first control signal at an output.
In one embodiment, the ramp compensation signal generating circuit is configured to superimpose a bias voltage on the ramp signal to generate a ramp compensation signal.
In one embodiment, the PWM control signals corresponding to the two adjacent first circuits are out of phase by 360/N degrees.
The embodiment of the invention also provides a multiphase converter, which comprises: the control circuit comprises N first circuits coupled in parallel and any one of the control circuits, wherein the N first circuits are configured to generate N PWM control signals which are sequentially in a phase-staggered mode so as to respectively control a main switching tube in the N first circuits.
In one embodiment, the first circuit is one of a buck circuit, a boost circuit, and a buck-boost circuit.
Compared with the prior art, the technical scheme of the invention has the following advantages: the ramp signal generating circuit in the embodiment of the invention is applied to a multiphase converter, the multiphase converter comprises N first circuits and a control circuit which are coupled in parallel, the control circuit is configured to generate N PWM control signals which are sequentially in phase-staggered mode so as to respectively control main switching tubes in the N first circuits, and the ramp signal generating circuit comprises: n ramp signal generating units for generating N ramp unit signals corresponding to the N PWM control signals one by one, respectively; the superposition circuit is used for superposing the N ramp unit signals to obtain ramp signals; wherein the first current ramp signal generating unit is configured to generate the first current ramp unit signal based on the pulse rising edge of the first current PWM control signal and one PWM control signal following the first current PWM control signal. The ramp signal generating circuit does not use the total pulse signal T1 output by the comparator in the prior art, the frequency of the total pulse signal T1 is up to tens of megahertz, the corresponding PWM control signals of each first circuit are used for generating the respective ramp unit signals, and then the ramp unit signals are overlapped to obtain the ramp signals, the frequency of the PWM control signals is below 3-5 megahertz, so that sufficient time is provided for discharging of the capacitor, the technical problems that the ramp signals are severely distorted and deviate from a design point due to insufficient discharging of the capacitor in the prior art are solved, the actual effect of the ramp signals is close to the design point, the jitter of the PWM control signals is reduced, the anti-interference performance of an actual system is improved, and the ramp signal generating circuit can be applied to scenes with more parallel phases and higher switching frequency.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a circuit schematic diagram of a prior art ramp signal generation circuit;
FIG. 2 is a waveform diagram illustrating operation of the ramp signal generating circuit according to the present invention;
FIG. 3 is a schematic diagram of a ramp signal generating circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of an embodiment of the superposition circuit of the present invention;
FIG. 5 is a waveform diagram illustrating operation of an embodiment of a ramp signal generating circuit according to the present invention;
FIG. 6 is a schematic circuit diagram of an embodiment of the multiphase converter and control circuit of the present invention;
fig. 7 is a circuit diagram of a PWM control signal generation circuit according to a first embodiment of the present invention;
fig. 8 is a circuit diagram of a PWM control signal generation circuit according to a second embodiment of the present invention;
FIG. 9 is a waveform diagram illustrating operation of an embodiment of the PWM control signal generation circuit of the present invention;
fig. 10 is a waveform diagram illustrating an embodiment of the control circuit of the present invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Meanwhile, it should be understood that in the following description, "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
The ramp signal generating circuit and the control circuit according to the present invention are applied to any type of multiphase converter, and the multiphase buck converter will be described hereinafter as an example, but the present invention is not limited thereto, and the ramp signal generating circuit and the control circuit are also applicable to multiphase converters of other topology types.
The invention discloses a ramp signal generating circuit which is applied to a multiphase buck converter, wherein the multiphase buck converter comprises N buck circuits and a control circuit which are coupled in parallel, the control circuit is configured to generate N PWM control signals which are sequentially in a staggered phase to respectively control a main switch tube in the N buck circuits, the ramp signal generating circuit comprises N ramp signal generating units and a superposition circuit, the N ramp signal generating units are used for respectively generating N ramp unit signals which are in one-to-one correspondence with the N PWM control signals, and the superposition circuit is used for superposing the N ramp unit signals to obtain ramp signals, wherein a first ramp signal generating unit is configured to generate a first ramp unit signal according to the pulse rising edge of a first PWM control signal and a subsequent PWM control signal. Here, one PWM control signal subsequent to the nth PWM control signal is the first PWM control signal. Further, the first current ramp signal generating unit is configured to generate the first current ramp unit signal according to a time interval between pulse rising edges of the first current PWM control signal and one PWM control signal following the first current ramp signal. Further, each ramp signal generating unit comprises a first capacitor, and the first capacitor in the first current ramp signal generating unit is charged in the time interval to generate a first current ramp unit signal, and the ramp unit signal is configured to be a voltage on the first capacitor.
Specifically, the i-th ramp signal generating unit is configured to generate the i-th ramp unit signal from the pulse rising edges of the i-th PWM control signal and the i+1th PWM control signal, more specifically, the i-th ramp unit signal temporarily rises from zero until the pulse rising edge of the i+1th PWM control signal temporarily stops rising and rapidly drops to zero, where i is greater than zero and less than N; the nth ramp signal generating unit is configured to generate the nth ramp unit signal from the pulse rising edges of the nth PWM control signal and the 1 st PWM control signal, more specifically, the nth ramp unit signal temporarily starts rising from zero until the pulse rising edge of the 1 st PWM control signal temporarily stops rising and quickly drops to zero.
Further, each ramp signal generating unit in the current period is generated according to each PWM signal in the current period.
Further, each ramp signal generating unit comprises a first constant current source and a first capacitor, the ramp unit signal being configured as a voltage on the first capacitor; in the ith ramp signal generating unit, at the pulse rising edge of the ith PWM control signal, a first constant current source charges the first capacitor, the ith ramp unit signal increases from zero, at the pulse rising edge of the (i+1) th PWM control signal, the first capacitor discharges, the ith ramp unit signal rapidly decreases to 0, and i is greater than zero and less than N; in the nth ramp signal generating unit, at the pulse rising edge of the nth PWM control signal, the nth ramp unit signal increases from zero, the first constant current source charges the first capacitor, and at the pulse rising edge of the 1 st PWM control signal, the first capacitor discharges, and the nth ramp unit signal rapidly decreases to 0.
When n=4, the operation waveform diagram of the ramp signal generating circuit is as shown in fig. 2, in the 1 st ramp signal generating unit: on the pulse rising edge of the 1 st PWM control signal PWM1, the first constant current source charges the first capacitor, the 1 st ramp unit signal V ISC1 Increasing from zero, discharging the first capacitor at the rising edge of the pulse of the 2 nd PWM control signal PWM2, the 1 st ramp unit signal V ISC1 Rapidly decreasing to 0. In the 2 nd ramp signal generating unit: on the rising edge of the pulse of the 2 nd PWM control signal PWM2, the first constant current source charges the first capacitor, and the 2 nd ramp unit signal V ISC2 Increasing from zero, discharging the first capacitor at the rising edge of the pulse of the 3 rd PWM control signal PWM3, and the 2 nd ramp unit signal V ISC2 Rapidly decreasing to 0. In the 3 rd ramp signal generating unit: on the rising edge of the pulse of the 3 rd PWM control signal PWM3, the first constant current source charges the first capacitor, and the 3 rd ramp unit signal V ISC3 Increasing from zero, discharging the first capacitor at the rising edge of the pulse of the 4 th PWM control signal PWM4, the 3 rd ramp unit signal V ISC3 Rapidly decreasing to 0. In the 4 th ramp signal generating unit: at the pulse rising edge of the 4 th PWM control signal PWM4, the first constant current source charges the first capacitor, the 4 th ramp unit signal V ISC4 Increasing from zero, discharging the first capacitor at the pulse rising edge of the 1 st PWM control signal PWM1, and the 4 th ramp unit signal V ISC4 Fast reductionTo 0. As shown in fig. 2, adjacent two ramp unit signals are out of phase, and only one ramp unit signal is generated at any time, for the ramp unit signal V ISC1 ～V ISC4 Is superimposed to obtain a ramp signal V ISC 。
Fig. 3 is a circuit diagram of an embodiment of a ramp signal generating circuit according to the present invention. The ramp signal generating circuit is applied to a multiphase buck converter, and the multiphase buck converter comprises N buck circuits and a control circuit which are coupled in parallel, wherein the control circuit is configured to generate N PWM control signals which are sequentially in a staggered phase to respectively control a main switch tube in the N buck circuits. As shown in fig. 3, the ramp signal generating circuit includes N ramp signal generating units 11 to 1N configured to generate N ramp unit signals V in one-to-one correspondence with the N PWM control signals PWM1 to PWMN, respectively, and a superimposing circuit 2 ISC1 ～V ISCN The method comprises the steps of carrying out a first treatment on the surface of the The superimposing circuit 2 is configured to receive N ramp unit signals V ISC1 ～V ISCN And for N ramp unit signals V ISC1 ～V ISCN Superposition is carried out to obtain a ramp signal V ISC The method comprises the steps of carrying out a first treatment on the surface of the Wherein the first current ramp signal generating unit is configured to generate the first current ramp unit signal based on the pulse rising edge of the first current PWM control signal and one PWM control signal following the first current PWM control signal. It should be noted that, one PWM control signal subsequent to the nth PWM control signal PWMN is the first PWM control signal PWM1. That is, the i-th ramp signal generating unit is configured to generate the i-th ramp unit signal according to the i-th PWM control signal and the pulse rising edge of the i+1th PWM control signal, i being greater than zero and less than N; the nth ramp signal generating unit is configured to generate an nth ramp unit signal according to pulse rising edges of the nth PWM control signal and the 1 st PWM control signal.
In the present embodiment, the ramp signal generating units 1j each include a first constant current source I ISCj First capacitor C ISCj And a first switch Qj, a first constant current source I ISCj And a first capacitor C ISCj A first switch Qj coupled in series between the power supply Vcc and ground potential and a first constant current source I ISCj And firstCapacitor C ISCj Ramp unit signal V between the common terminal of (a) and ground potential ISCj Is configured as the first capacitance C ISCj At a voltage (i.e. a first constant current source I ISCj And a first capacitor C ISCj And the voltage of the common terminal of (c), wherein j is greater than zero and equal to or less than N.
In the I-th ramp signal generating unit 1I, at the pulse rising edge of the I-th PWM control signal PWMi, the first switch Qi is turned off, and the first constant current source I ISCi For the first capacitor C ISCi Charging, i-th ramp unit signal V ISCi Increase from zero; on the pulse rising edge of the (i+1) th PWM control signal PMW (i+1), the first switch Qi is turned on, and the first capacitor C ISCi Discharging, i-th ramp unit signal V ISCi Rapidly decreasing to 0, i being greater than zero and less than N. In the nth ramp signal generating unit 1N, at the pulse rising edge of the nth PWM control signal PWMN, the first switch QN is turned off, and the first constant current source I ISCN For the first capacitor C ISCN Charging, nth ramp unit signal V ISCN Increasing from zero, on the pulse rising edge of the 1 st PWM control signal PWM1, the first switch QN is turned on, the first capacitor C ISCi Discharging, N-th ramp unit signal V ISCN Rapidly decreasing to 0.
In this embodiment, the ramp signal generating unit 1j further includes a first one-shot circuit 1j1, a second one-shot circuit 1j2, and a first RS flip-flop 1j3, the reset terminal R of the first RS flip-flop 1j3 is coupled to the output terminal of the first one-shot circuit 1j1, the set terminal of the first RS flip-flop 1j3 is coupled to the output terminal of the second one-shot circuit 1j2, and the output terminal of the first RS flip-flop 1j3 is coupled to the control terminal of the first switch, that is, the first signal Gj output by the first RS flip-flop 1j3 is used to control the on and off of the first switch Qj, where j is greater than zero and less than or equal to N. The first one-shot circuit 1j1 and the second one-shot circuit 1j2 are configured to output a pulse signal on a rising edge of the input corresponding PWM control signal to trigger the subsequent first RS flip-flop 1j3.
In the ith ramp signal generating unit 1i, the input end of the first one-shot circuit 1i1 receives the ith PWM control signal PWMi, and the input end of the second one-shot circuit 1i2 receives the (i+1) th PWM control signal PWM (i+1), i being greater than zero and less than N; in the nth ramp signal generating unit 1N, the input terminal of the first one-shot circuit 1N1 receives the nth PWM control signal PWMN, and the input terminal of the second one-shot circuit 1N2 receives the 1 st PWM control signal PWM1.
It should be noted that, this embodiment is only given as an example, and an embodiment of the ramp signal generating unit is given, but the ramp signal generating unit of the present invention may also have other structures, for example, the first switch is coupled between the first constant current source and the first capacitor, and the on and off of the first switch are opposite to those of the first switch in this embodiment, which is not limited in this aspect, and any ramp signal generating unit that generates the signal of the first ramp unit according to the pulse rising edge of the first PWM control signal and the subsequent PWM control signal is within the scope of the present invention.
Fig. 4 is a schematic circuit diagram of an embodiment of the superposition circuit of the present invention. As shown in fig. 4, the superimposing circuit 2 includes N voltage-controlled current sources V21 to V2N and a first resistor R1, wherein the output ends of the N voltage-controlled current sources V21 to V2N are coupled to the first end of the first resistor R1, the second end of the first resistor R1 is grounded, and the control ends of the N voltage-controlled current sources V21 to V2N respectively receive N ramp unit signals V ISC1 ～V ISCN The method comprises the steps of carrying out a first treatment on the surface of the Ramp signal V ISC Is configured as a voltage at a first end of the first resistor R1.
It should be noted that, this embodiment only shows a specific structure of a superimposing circuit by way of example, and the present invention is not limited thereto, and any superimposing circuit that superimposes N ramp unit signals to obtain a ramp signal is within the scope of the present invention.
Fig. 5 is a waveform diagram illustrating an operation of the ramp signal generating circuit according to an embodiment of the present invention. When N is equal to 4 in the ramp signal generating circuit shown in fig. 3, the operation waveforms thereof are as shown in fig. 5.
In the 1 st ramp signal generating unit 11, as shown in fig. 5, on the pulse rising edge of the 1 st PWM control signal PWM1, the first signal G1 transitions from high level to low level, the first switch Q1 is turned off, and the first constant current source I ISC1 To the firstCapacitor C ISC1 Charging, 1 st ramp unit signal V ISC1 Increase from zero; on the rising edge of the pulse of the 2 nd PWM control signal PWM2, the first signal G1 jumps from low level to high level, the first switch Q1 is turned on, and the first capacitor C ISC1 Discharging, 1 st ramp unit signal V ISC1 Rapidly drops to 0. In the 2 nd ramp signal generating unit 12, as shown in fig. 5, on the pulse rising edge of the 2 nd PWM control signal PWM2, the first signal G2 transitions from high level to low level, the first switch Q2 is turned off, and the first constant current source I ISC2 For the first capacitor C ISC2 Charging, the 2 nd ramp unit signal V ISC2 Increase from zero; on the rising edge of the pulse of the 3 rd PWM control signal PWM3, the first signal G2 jumps from low level to high level, the first switch Q2 is turned on, and the first capacitor C ISC2 Discharging, the 2 nd ramp unit signal V ISC2 Rapidly drops to 0. In the 3 rd ramp signal generating unit 13, as shown in fig. 5, on the pulse rising edge of the 3 rd PWM control signal PWM3, the first signal G3 transitions from high level to low level, the first switch Q3 is turned off, and the first constant current source I ISC3 For the first capacitor C ISC3 Charging, 3 rd ramp unit signal V ISC3 Increase from zero; on the rising edge of the pulse of the 4 th PWM control signal PWM4, the first signal G3 jumps from low level to high level, the first switch Q3 is turned on, and the first capacitor C ISC3 Discharging, 3 rd ramp unit signal V ISC3 Rapidly drops to 0. In the 4 th ramp signal generating unit 14, as shown in fig. 5, on the pulse rising edge of the 4 th PWM control signal PWM4, the first signal G4 transitions from high level to low level, the first switch Q4 is turned off, and the first constant current source I ISC4 For the first capacitor C ISC4 Charging, 4 th ramp unit signal V ISC4 Increase from zero; on the pulse rising edge of the 1 st PWM control signal PWM1, the first signal G4 jumps from low level to high level, the first switch Q4 is turned on, and the first capacitor C ISC4 Discharging, 4 th ramp unit signal V ISC4 Rapidly drops to 0. Ramp unit signal V ISC1 ～V ISC4 Superposition is carried out to obtain a ramp signal V ISC 。
Fig. 6 is a circuit schematic of an embodiment of the multiphase converter and control circuit of the present invention. In fig. 6, the multiphase converter is a multiphase buck converter, and the multiphase buck converter includes N buck circuits and a control circuit coupled in parallel, wherein the input ends of the N buck circuits are connected in parallel to receive an input voltage Vin, the output ends of the N buck circuits are connected in parallel to generate an output voltage Vout, and the control circuit is configured to generate N PWM control signals PWM1 to PWMN of sequentially misphase to respectively control main switching tubes in the N buck circuits. Fig. 10 is a waveform diagram illustrating an embodiment of the control circuit of the present invention. When N is equal to 4 in the control circuit shown in fig. 6, the operation waveforms thereof are as shown in fig. 10. The control circuit of the present embodiment will be described later with reference to fig. 6 and 10.
The control circuit includes a ramp signal generating circuit, a turn-on timing control circuit, and N PWM control signal generating circuits T1 to TN. The ramp signal generating circuit is configured to generate the ramp signal V in the manner described above ISC And will not be described in detail herein.
The turn-on time control circuit is configured to control the turn-on time according to the output voltage Vout, the sum of the inductance currents of the N buck circuits, and the ramp signal V ISC And generating a first control signal TRIG, wherein high pulses in the first control signal TRIG are sequentially distributed to N PWM control signal generating circuits T1-TN, and respectively control N PWM control signals to change from low level to high level so as to control the conduction time of a main switching tube in N buck circuits and realize natural phase interleaving of each PWM control signal. The on-time control circuit includes a modulated voltage signal generation circuit, a slope compensation signal generation circuit, and a first comparator C1.
The modulation voltage signal generating circuit is configured to generate a modulation voltage signal V according to the sum of the output voltage Vout and the inductance current of the N buck circuits MOD . The output voltage Vout and the inductance currents of the N buck circuits are weighted respectively and added to obtain a voltage control signal V MOD . In this embodiment, the inductor Ls in each buck circuit is serially coupled with a resistor DCR, and the inductor current in each buck circuit is sampled by the resistor DCR, and in other embodiments, the inductor current may be sampled by any other partyThe inductance current information in each buck circuit is obtained, and the invention is not limited to this. The modulation voltage signal generating circuit is configured to sample the inductance currents in the N buck circuits respectively to obtain N inductance current sampling signals, and the N inductance current sampling signals are superimposed to obtain the sum V of the inductance currents of the N buck circuits isum And sum of inductor currents V isum And the first coefficient Ki to obtain the second signal V2. The modulation voltage signal generating circuit is also used for sampling the output voltage Vout, and for the output voltage Vout and the reference voltage signal V REF The difference is taken to obtain a first error signal Ve and the second coefficient Kv are multiplied to obtain a third signal V3. Modulating voltage signal V MOD Configured to be equal to the sum of the second signal V2 and the third signal V3, i.e.: v (V) MOD ＝V2+V3＝Ki*V isum +kv Ve. The embodiment exemplarily shows a specific implementation manner of the modulated voltage signal generating circuit, but the invention is not limited thereto, and the modulated voltage signal V is generated by using other arbitrary modification manners of the specific implementation manner in the embodiment MOD The modulation voltage signal generation circuit of the voltage regulator is within the protection scope of the invention.
The control circuit further includes a ramp compensation signal generation circuit configured to generate a ramp signal V ISC A slope compensation signal V1 is generated. Further, in the ramp signal V ISC And superposing a bias voltage to obtain the slope compensation signal V1, wherein the bias voltage can be 0. In the present embodiment, the slope compensation signal generation circuit includes an operational amplifier EA having two input terminals for receiving an output voltage Vout and a reference voltage signal V, respectively REF The output end of the first compensation signal generates a first compensation signal V COMP The ramp compensation signal V1 is configured to be equal to the ramp signal V ISC And a first compensation signal V COMP The sum is that: v1=v ISC +V COMP . In the present embodiment, the first compensation signal V COMP Is the bias voltage. In further embodiments, the bias voltage is a fixed voltage (e.g., 5V).
In the present embodiment, the first comparator C1 is the firstOne input terminal (i.e. inverting input terminal) and the second input terminal (i.e. non-inverting input terminal) respectively receive the modulated voltage signal V MOD And the slope compensation signal V1, the output terminal of the first comparator C1 generates the first control signal TRIG. When the slope compensation signal V1 is greater than the modulation voltage signal V MOD The first control signal TRIG is high, and when the slope compensation signal V1 is smaller than the modulation voltage signal V MOD The first control signal TRIG is low so that, as shown in fig. 10, a plurality of high pulses p1, p2, p3 … occur in the first signal TRIG (the pulse width of the high pulses is small in practice, and the high pulses are subjected to widening processing here for convenience of illustration).
It should be understood that any other modification of the first control signal TRIG generated by the specific implementation manner in this embodiment is within the scope of the present invention. In the present embodiment, the voltage signal V is modulated MOD In the order of combination of the individual components of the voltage signal V MOD Ramp signal V ISC And a first compensation signal V COMP The order of combination of (c) is not limited to the order illustrated in the present embodiment, and the present invention is not limited thereto. The combination and order of the signals input to the positive terminal or the negative terminal of the comparator or the operational amplifier are not limited to those shown in the present embodiment, and the present invention is not limited thereto.
In this embodiment, the on-time control circuit further includes a phase distribution unit configured to sequentially distribute the high pulses p1, p2, p3 in the first control signal TRIG to the N PWM control signal generating circuits T1 to TN, so as to control the N PWM control signals to change from low level to high level, and control the on-time of the main switching tubes in the N buck circuits. Specifically, the high pulse p1 is allocated to the PWM control signal generating circuit T1, and as shown in fig. 10, the PWM control signal PWM1 changes from low level to high level at the pulse rising edge of the high pulse p1, that is, the main switching tube in the first buck circuit is turned on. The high level p2 is allocated to the PWM control signal generation circuit T2, and as shown in fig. 10, the PWM control signal PWM2 changes from the low level to the high level at the pulse rising edge of the high pulse p2, that is, the main switching tube in the second buck circuit is turned on. Similar high pulses p3, p4, p5 … are assigned and will not be described in detail herein. The nth+jth high pulse in the first control signal is distributed to the PWM control signal generating circuit Tj to control the jth PWM control signal PWMj to change from low level to high level, at this time, the jth buck circuit main switch is turned on, k is greater than or equal to 0, and j is greater than zero and less than or equal to N.
The N PWM control signal generation circuits T1 to TN are configured to generate N PWM control signals PWM1 to PWMN, respectively, to control the switching states of the main switching transistors in the N buck circuits, respectively.
Specifically, each PWM control signal generation circuit includes a second RS flip-flop and a turn-off timing control circuit. In the jth PWM control signal generating circuit Tj, the set end of the second RS flip-flop receives the nth high pulse of the first control signal, the reset end of the second RS flip-flop receives the output signal of the turn-off time control circuit, and the output end of the second RS flip-flop generates the control signal PWMj of the jth PWM, where k is greater than or equal to 0, and j is greater than 0 and less than or equal to N.
The ramp signal generating circuit of the invention does not use the total pulse signal T1 output by the comparator in the prior art to control the charge and discharge of one capacitor to obtain a ramp signal (the frequency of the total pulse signal T1 is up to tens of megahertz, which can lead to the capacitor to be discharged or charged again), but uses PWM control signals corresponding to each buck circuit to respectively charge and discharge different capacitors to generate respective ramp unit signals, and then stacks the ramp unit signals to obtain the ramp signal, wherein the frequency of the PWM control signal is below 3-5 megahertz, thereby providing sufficient time for the discharge of each capacitor. The ramp signal generating circuit solves the technical problems that in the prior art, the ramp signal is severely distorted and deviates from a design point due to insufficient capacitor discharge, so that the actual effect of the ramp signal is close to the design point, the anti-interference performance of an actual system is improved, and the ramp signal generating circuit can be applied to scenes with more parallel phases and higher switching frequency.
Fig. 7 is a circuit diagram of a PWM control signal generation circuit according to a first embodiment of the present invention. The off-time control circuit in this embodiment includes a timer circuit. As shown in fig. 7, the jth PWM control signal circuit Tj includes a second RS flip-flop 7j1 and a timing circuit 7j2, the set terminal of the second RS flip-flop 7j1 receives the second control signal TRIGj, the reset terminal of the second RS flip-flop 7j1 is coupled to the output terminal of the timing circuit 7j2, and the output terminal of the second RS flip-flop 7j1 outputs the control signal PWMj of the jth PWM. The second control signal TRIGj is a signal formed by an nth pulse and a j pulse in the first control signal.
Fig. 9 is a waveform diagram illustrating the operation of the PWM control signal generation circuit according to an embodiment of the present invention. As shown in fig. 9, the second control signal TRIGj is used for controlling the moment when the j-th PWM control signal changes from low level to high level, and after delaying the first time T1, the timing circuit outputs a pulse signal to control the j-th PWM control signal to change from high level to low level from moment when the j-th PWM control signal changes from low level to high level. The plurality of pulse signals output from the timer circuit in the jth PWM control signal generation circuit constitute an output signal VAj of the timer circuit.
In this embodiment, the first time T1 is a fixed time, and the control method is Constant On Time (COT) control, which is not limited in the present invention. In other embodiments, the first time T1 may be adjusted according to the input voltage Vin and the output voltage Vout, where the control method is adaptive on-time (AOT) control. For example, fig. 8 is a circuit diagram of a PWM control signal generation circuit according to a second embodiment of the present invention. In this embodiment, the off-time control circuit includes a timer circuit and an on-time adjustment circuit. As shown in fig. 8, on the basis of the first embodiment, an on-time adjusting circuit 7j3 is added, and the on-time adjusting circuit 7j3 is configured to adjust the input voltage Vin and/or the output voltage Vout (or the reference voltage signal V) REF ) Controlling a first time T1; when the input voltage Vin becomes larger, reducing a first time T1; when the input voltage Vin becomes smaller, the first time T1 is increased. When the output voltage Vout or the reference voltage signal V REF When the time is increased, the first time T1 is increased; when the output voltage Vout or the reference voltage signal V REF When decreasing, decrease the first timeT1. The on-time (i.e., the first time T1) in AOT control is varied in real time with the input voltage Vin and/or the output voltage Vout, and thus has certain advantages over COT control in that a relatively fixed switching frequency can be achieved.
Further, as shown in fig. 6, the jth PWM control signal circuit Tj is further configured to generate a PWM control signal PWMj' complementary to the control signal PWMj of the jth PWM circuit, so as to respectively control the auxiliary switching transistors of the jth buck circuit.
Further, PWM control signals corresponding to two adjacent buck circuits are out of phase by 360/N degrees.
It should be noted that, in the above embodiments of the present invention, the multiphase buck converter is taken as an example, but the present invention is not limited thereto, and any topology structure of interleaving and parallel connection is within the protection scope of the present invention, for example, but not limited to, multiphase boost converter, multiphase buck-boost converter, multiphase PFC controlled AC-DC circuit, and the like. In the present invention, the horizontal axis of each operation waveform chart is time, and this will be described.
Although the embodiments have been described and illustrated separately above, and with respect to a partially common technique, it will be apparent to those skilled in the art that alternate and integration may be made between embodiments, with reference to one embodiment not explicitly described, and reference may be made to another embodiment described.
In accordance with embodiments of the present invention, as described above, these embodiments are not exhaustive of all details, nor are they intended to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (21)

1. A ramp signal generating circuit for use in a multiphase converter comprising N first circuits coupled in parallel and a control circuit configured to generate N sequentially phase-staggered PWM control signals to control main switching tubes of the N first circuits, respectively, comprising:
n ramp signal generating units configured to generate N ramp unit signals corresponding to the N PWM control signals one by one, respectively; and
a superimposing circuit configured to superimpose the N ramp unit signals to obtain a ramp signal;
wherein the first current ramp signal generating unit is configured to generate the first current ramp unit signal in accordance with a time interval between pulse rising edges of the first current PWM control signal and one PWM control signal following the first current ramp signal.
2. The ramp signal generating circuit according to claim 1, wherein: the first ramp unit signal is configured to temporarily start rising from zero from the pulse rising edge of the first PWM control signal until the pulse rising edge of the subsequent one of the PWM control signals temporarily stops rising and quickly drops to zero.
3. The ramp signal generating circuit according to claim 1, wherein: each ramp signal generating unit comprises a first capacitor, and the first capacitor in a first current ramp signal generating unit is charged in the time interval to generate a first current ramp unit signal, wherein the ramp unit signal is configured as a voltage on the first capacitor.
4. The ramp signal generating circuit according to claim 1, wherein:
the i-th ramp signal generating unit is configured to generate an i-th ramp unit signal according to pulse rising edges of the i-th PWM control signal and the i+1th PWM control signal, i being greater than zero and less than N;
the nth ramp signal generating unit is configured to generate an nth ramp unit signal according to pulse rising edges of the nth PWM control signal and the 1 st PWM control signal.
5. The ramp signal generating circuit according to claim 1, wherein: each ramp signal generating unit comprises a first constant current source and a first capacitor, the ramp unit signal being configured as a voltage on the first capacitor;
in the ith ramp signal generating unit, at the pulse rising edge of the ith PWM control signal, the first constant current source charges the first capacitor, and at the pulse rising edge of the (i+1) th PWM control signal, the first capacitor discharges, i is greater than zero and less than N;
In the nth ramp signal generating unit, the first constant current source charges the first capacitor at a pulse rising edge of the nth PWM control signal, and the first capacitor discharges at a pulse rising edge of the 1 st PWM control signal.
6. The ramp signal generating circuit according to claim 5, wherein: the ramp signal generating unit further includes a first switch, the first constant current source and the first capacitor being coupled in series between a power supply and a ground potential, the first switch being coupled between a common terminal of the first constant current source and the first capacitor and the ground potential.
7. The ramp signal generating circuit according to claim 6, wherein:
in the ith ramp signal generating unit, at the pulse rising edge of the ith PWM control signal, the first switch is turned off, the first constant current source charges the first capacitor, at the pulse rising edge of the (i+1) th PWM control signal, the first switch is turned on, and the first capacitor is discharged, wherein i is greater than zero and less than N;
in the nth ramp signal generating unit, at the pulse rising edge of the nth PWM control signal, the first switch is turned off, the first constant current source charges the first capacitor, at the pulse rising edge of the 1 st PWM control signal, the first switch is turned on, and the first capacitor discharges.
8. The ramp signal generating circuit according to claim 6, wherein: the ramp signal generating unit further includes: the first signal generator comprises a first one-shot circuit, a second one-shot circuit and a first RS trigger, wherein the reset end of the first RS trigger is coupled with the output end of the first one-shot circuit, the set end of the first RS trigger is coupled with the output end of the second one-shot circuit, and the output end of the first RS trigger generates a first signal for controlling the on and off of the first switch.
9. The ramp signal generating circuit according to claim 8, wherein:
in the ith ramp signal generating unit, the input end of the first one-shot circuit receives the ith PWM control signal, and the input end of the second one-shot circuit receives the (i+1) th PWM control signal;
in the nth ramp signal generating unit, the input end of the first one-shot circuit receives the nth PWM control signal, and the input end of the second one-shot circuit receives the 1 st PWM control signal.
10. The ramp signal generating circuit according to claim 1, wherein: the superimposing circuit includes: the output ends of the N voltage-controlled current sources are coupled to the first end of the first resistor, the second end of the first resistor is grounded, and the control ends of the N voltage-controlled current sources respectively receive the N slope unit signals;
Wherein the ramp signal is configured to be the voltage at the first end of the first resistor.
11. A control circuit for use in a multiphase converter comprising N first circuits coupled in parallel, comprising:
the ramp signal generating circuit of any one of claims 1-10, to generate a ramp signal;
the control circuit is configured to generate N PWM control signals which are sequentially misphased according to the ramp signals so as to respectively control the main switching tubes in the N first circuits.
12. The control circuit of claim 11, further comprising:
and the conduction time control circuit is configured to generate first control signals according to the output voltage of the multiphase converter, the sum of the inductance currents of the N first circuits and the ramp signals, wherein high pulses in the first control signals sequentially and respectively control the N PWM control signals to be changed from low level to high level so as to control the conduction time of the main switching tubes in the N first circuits.
13. The control circuit of claim 11, further comprising: n PWM control signal generating circuits configured to generate N PWM control signals, respectively, to control switching states of the main switching transistors in the N first circuits, respectively;
Each PWM control signal generation circuit includes a second RS flip-flop and a turn-off timing control circuit,
in the jth PWM control signal generating circuit, the set end of the second RS flip-flop receives the nth high pulse of the first control signal, the reset end of the second RS flip-flop receives the output signal of the turn-off time control circuit, and the output end of the second RS flip-flop generates the jth PWM control signal, where k is greater than or equal to zero, and j is greater than zero and less than or equal to N.
14. The control circuit of claim 13, wherein: the off-time control circuit comprises a timer circuit,
in the jth PWM control signal generation circuit, the timer circuit is configured to output a pulse signal after a delay for a first time from a time point when the jth PWM control signal changes from a low level to a high level, to control the jth PWM control signal to change from the high level to the low level.
15. The control circuit of claim 14, wherein: the off-time control circuit further includes: an on-time adjustment circuit configured to control the first time in accordance with an input voltage of the multiphase converter;
wherein the first time is reduced when the input voltage becomes large; when the input voltage becomes smaller, the first time is increased.
16. The control circuit according to claim 14 or 15, characterized in that: the off-time control circuit further includes: an on-time adjustment circuit configured to control the first time according to an output voltage or a reference voltage signal of the multiphase converter;
wherein the first time is increased when the output voltage or reference voltage signal becomes large; the first time is reduced when the output voltage or reference voltage signal becomes smaller.
17. The control circuit of claim 12, wherein the on-time control circuit comprises:
a modulation voltage signal generation circuit configured to generate a modulation voltage signal from a sum of an output voltage of the multiphase converter and inductor currents of the N first circuits;
a slope compensation signal generation circuit configured to generate a slope compensation signal from the slope signal;
a first comparator configured to receive the modulated voltage signal at a first input, the ramp compensation signal at a second input, and the first control signal at an output.
18. The control circuit of claim 17, wherein: the slope compensation signal generation circuit is configured to superimpose a bias voltage on the slope signal to generate a slope compensation signal.
19. The control circuit of claim 11, wherein: PWM control signals corresponding to the two adjacent first circuits are out of phase by 360/N degrees.
20. A multiphase converter, comprising:
n first circuits coupled in parallel, and
the control circuit of any of claims 11-19, configured to generate N sequentially misphased PWM control signals to control a main switching tube of the N first circuits, respectively.
21. The multiphase converter of claim 20, wherein: the first circuit is one of a buck circuit, a boost circuit and a buck-boost circuit.
CN202310341028.0A 2023-03-31 2023-03-31 Ramp signal generating circuit, multiphase converter and control circuit thereof Pending CN116455187A (en)

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