CN116435266A

CN116435266A - Chip packaging structure and electronic equipment

Info

Publication number: CN116435266A
Application number: CN202310489524.0A
Authority: CN
Inventors: 张国艺
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-07-14

Abstract

The application discloses a chip packaging structure and electronic equipment, belongs to electronic equipment technical field. The chip packaging structure comprises: the chip and the adapter block assembly are packaged by the plurality of rewiring layers, the plurality of plastic sealing layers, the chip, the connecting terminal assembly and the adapter block assembly; the plurality of rewiring layers are arranged in a stacked mode along a first direction, a plastic sealing layer is clamped between every two adjacent rewiring layers, the wafer and the transfer block assembly are embedded in the same plastic sealing layer, the transfer block assembly is arranged on the periphery of the wafer in a surrounding mode, the connecting terminal assembly is connected to the rewiring layer farthest from the wafer along the first direction in the plurality of rewiring layers, and the connecting terminal assembly is arranged on one surface, away from the plastic sealing layer, of the rewiring layer; the first direction is a direction perpendicular to the wafer, and one surface of the rewiring layer, on which the connecting terminal assembly is arranged, is a chip active surface.

Description

Chip packaging structure and electronic equipment

Technical Field

The application belongs to the technical field of electronic equipment, and particularly relates to a chip packaging structure and electronic equipment.

Background

The main board device is one of core components in the electronic equipment, and with the gradual increase of functions of the electronic equipment, the integration level of the main board device is also higher and higher. In the related art, the motherboard device is mostly packaged in a stacked manner (Package on Packaged, POP) to save area.

In the prior art, the POP technology encapsulates a target wafer between an upper substrate and a lower substrate. The lower substrate can be used for bearing a target wafer, the upper substrate can be used for bearing a top chip, and the stack of the multi-layer chip packaging structure in the vertical direction can be realized through the supporting function of the upper substrate and the lower substrate, so that the three-dimensional packaging is realized. The upper substrate may be an interposer substrate, the lower substrate may be a common organic substrate, a Molding Compound (MC) may be filled between the target wafer and the substrate, and copper core solder balls or solder balls may be used in the MC to realize electrical interconnection between the upper and lower substrates.

However, the above-mentioned packaging structure packages the target wafer through the upper and lower substrates, so that the thickness of the whole packaging structure (including the upper substrate, the plastic packaging material, the target wafer and the lower substrate) is relatively large, which is not beneficial to heat dissipation of the target chip. And the packaging structure simultaneously uses a substrate, plastic packaging materials and the like, and the materials have different thermal expansion coefficients, when the whole packaging structure is subjected to temperature change, the expansion is inconsistent due to the different thermal expansion coefficients of various materials, when the temperature of the local position of the chip is overhigh, the chip generates warpage, the serious empty welding or short-circuit abnormality is finally caused in the chip mounting process, the temperature of the local area of the chip is overhigh, and a solder ball or a bump possibly causes cracking abnormality under the action of long-term thermal stress, so that the chip is invalid.

Disclosure of Invention

An object of the embodiment of the application is to provide a chip packaging structure and electronic equipment, which can solve the problems of concentrated thermal stress effect and chip warpage caused by thermal stress of the chip packaging structure in the prior art.

In order to solve the technical problems, the application is realized as follows:

in a first aspect, embodiments of the present application provide a chip package structure, including: the chip and the adapter block assembly are packaged by the plurality of rewiring layers, the plurality of plastic sealing layers and the plurality of plastic sealing layers; the plurality of rewiring layers are arranged in a stacked mode along a first direction, the plastic sealing layers are clamped between two adjacent rewiring layers, the wafer and the adapter block assembly are embedded in the same plastic sealing layer, the adapter block assembly is arranged on the periphery of the wafer in a surrounding mode, the connecting terminal assembly is arranged on the rewiring layer farthest from the wafer along the first direction, and the connecting terminal assembly is arranged on one surface, away from the plastic sealing layer, of the rewiring layer; the first direction is a direction perpendicular to the wafer, and one surface of the rewiring layer, on which the connecting terminal assembly is arranged, is the chip active surface.

In this application embodiment, the setting of a plurality of rewiring layers is used for realizing electrical apparatus extension and interconnection effect in a certain plane, and the setting of rewiring layer can realize evenly distributed to whole active surface with the connecting terminal in the connecting terminal subassembly, and then provides the condition for reducing thermal stress's gathering. The plastic layer wraps the wafer and the adapter assembly, the adapter assembly is also arranged around the wafer, a certain supporting force can be provided for the wafer in a first direction by the arrangement of the plastic layer and the silicon adapter assembly, the strength of the structural support of the wafer is enhanced, the wafer can bear more stress load without deformation in use, and the warping degree of the chip can be controlled within an acceptable range. The connecting terminal assembly is connected to the rewiring layer farthest from the wafer along the first direction, and it can be understood that the outermost rewiring layer is also arranged on one surface of the outermost rewiring layer, which is away from the plastic sealing layer, and one surface of the connecting terminal assembly, which is connected to the rewiring layer, is the chip active surface. The connection terminal assembly provided on the active surface is used to achieve interconnection between the chip and the motherboard or other chips. In this application is implemented, the rewiring layer has the effect of dispersing thermal stress to whole active surface, and then makes the holistic relatively even that is heated of chip packaging structure, can reduce local thermal stress concentration, more is favorable to the whole heat dissipation of chip, has reduced the possibility of the warpage problem that the chip leads to because of thermal stress gathers. In addition, the same plastic layer wraps the wafer and the adapter block assembly in, so that the strength of the wafer body structure is improved, the stress load borne by the chip packaging structure is increased, and the possibility of warping of the chip due to thermal stress is further reduced.

In a second aspect, embodiments of the present application provide an electronic device including a chip package structure as described above.

Drawings

FIG. 1 is a schematic cross-sectional view of a chip package structure in an embodiment of the present application;

FIG. 2 is a schematic illustration of a molding compound layer with a wafer and interposer assembly in an embodiment of the present application;

fig. 3 is a schematic structural view of a connection terminal assembly in an embodiment of the present application;

FIG. 4 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 5 is a second schematic diagram of a manufacturing process of the chip package structure according to the embodiment of the present application;

FIG. 6 is a third schematic diagram of a manufacturing process of the chip package structure according to the embodiment of the present application;

FIG. 7 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 12 is a schematic illustration of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 13 is a schematic view of a manufacturing process of a chip package structure according to an embodiment of the present application;

FIG. 14 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application;

fig. 15 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application.

Reference numerals illustrate:

10. a wafer; 11. a through wafer via; 20. an adapter assembly; 21. a transfer block; 211. a through hole; 212. an electric conductor; 30. a first rewiring layer; 31. a second rewiring layer; 32. a third wiring layer; 33. a fourth rewiring layer; 40. a first plastic layer; 41. a second plastic layer; 42. a third plastic layer; 50. a first connector post assembly; 51. a second connector post assembly; 511. a first connection post; 512. a second connection post; 60. a connection terminal assembly; 61. a first connection terminal; 62. a second connection terminal; 70. chip active surface.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

The chip packaging structure and the electronic device provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings by specific embodiments and application scenarios thereof.

Referring to fig. 1 to 3, embodiments of the present application provide a chip package structure, including: a plurality of rewiring layers, a plurality of plastic sealing layers, a wafer 10 and a transfer block assembly 20, wherein the wafer 10 and the transfer block assembly 20 are packaged by the plurality of rewiring layers and the plurality of plastic sealing layers; the plurality of rewiring layers and the plurality of plastic sealing layers are alternately arranged in sequence along a first direction, the plastic sealing layers are clamped between the two adjacent rewiring layers, the wafer 10 and the adapter block assembly 20 are embedded in the same plastic sealing layer, the adapter block assembly 20 is arranged on the periphery of the wafer 10 in a surrounding mode, the terminal assembly 60 is arranged on the rewiring layer farthest from the wafer along the first direction in the plurality of rewiring layers, and the terminal assembly 60 is arranged on one surface, away from the plastic sealing layer, of the rewiring layer; the first direction is a direction perpendicular to the wafer 10, and the surface of the redistribution layer on which the connection terminal assembly 60 is disposed is the chip active surface 70.

In this application embodiment, the setting of a plurality of rewiring layers is used for realizing electrical apparatus extension and interconnection effect in a certain plane, and the setting of rewiring layer can realize evenly distributed to whole active surface with the connecting terminal in the connecting terminal subassembly, and then provides the condition for reducing thermal stress's gathering. The plastic layer wraps the wafer 10 and the adapter block assembly 20, the adapter block assembly 20 is also surrounded around the wafer 10, and the arrangement of the plastic layer and the adapter block assembly 20 can also provide a certain supporting force for the wafer 10 in the first direction, so that the strength of the structural support of the wafer 10 is enhanced, the wafer 10 can bear more stress load without deformation in use, and the degree of chip warpage can be controlled within an acceptable range. The connection terminal assembly 60 is connected to the rewiring layer farthest from the wafer along the first direction, and it is understood that the outermost rewiring layer is the outermost rewiring layer, and the connection terminal assembly 60 is disposed on the surface of the outermost rewiring layer away from the plastic sealing layer, and the surface of the connection terminal assembly 60 connected to the rewiring layer is the chip active surface 70. The connection terminal assembly 60 provided on the active surface is used to achieve interconnection between the chip and the motherboard or other chip. The connection terminal assembly 60 is disposed on the active surface of the chip, one end of the connection terminal assembly 60 is connected to the second connection post assembly 51, and the other end of the connection terminal assembly 60 is connected to the motherboard or other chip. In this application is implemented, the rewiring layer has the effect of dispersing thermal stress to whole active surface, and then makes the holistic relatively even that is heated of chip packaging structure, can reduce local thermal stress concentration, more is favorable to the whole heat dissipation of chip, has reduced the possibility of the warpage problem that the chip leads to because of thermal stress gathers. In addition, the same plastic layer wraps the wafer 10 and the adapter block assembly 20, so that the strength of the body structure of the wafer 10 is improved, the stress load borne by the chip packaging structure is increased, and the possibility of warping of the chip due to thermal stress is further reduced.

Optionally, in the embodiment of the present application, the plurality of redistribution layers includes a first redistribution layer 30, a second redistribution layer 31, a third redistribution layer 32, and a fourth redistribution layer 33, and the plurality of molding layers includes a first molding layer 40, a second molding layer 41, and a third molding layer 42; the first redistribution layer 30, the first molding layer 40, the second redistribution layer 31, the second molding layer 41, the third redistribution layer 32, the third molding layer 42, and the fourth redistribution layer 33 are sequentially and alternately arranged, and the wafer 10 and the interposer assembly 20 are embedded in the second molding layer 41.

In the embodiment of the application, a plurality of rewiring layers and a plurality of plastic sealing layers are sequentially and alternately overlapped. It will be appreciated that the first redistribution layer 30, the first molding layer 40, the second redistribution layer 31, the second molding layer 41, the third redistribution layer 32, the third molding layer 42, and the fourth redistribution layer 33 are sequentially and alternately arranged, and the die 10 and the interposer assembly 20 are embedded in the second molding layer 41. The plurality of molding layers and the interposer assembly 20 disposed within the second molding layer 41 provide strength support for the die 10 embedded within the second molding layer 41.

It should be noted that, the plastic package materials of a plurality of plastic package layers are the same, and the thermal stress coefficient of the same plastic package material is the same, and under the condition that the same thermal stress coefficient is generated and deformed by heat, so that the deformation quantity is the same, and the method has the beneficial effect of reducing the warpage of the chip caused by overlarge deformation generated by different deformation quantities of materials.

It should be noted that, after the plastic sealing layer is filled with the plastic sealing material, the first surface of the plastic sealing material needs to be ground. Specifically, the plastic sealing material is filled on the first surface of the carrier plate and surrounds the wafer 10 and the side surfaces and the bottom surfaces of the plurality of transfer blocks 21, so that the back surface and the side surfaces of the wafer 10 are isolated from the outside, and in addition, the filling height of the plastic sealing material is at least higher than the upper surfaces of the wafer 10 and the transfer blocks 21. The molding material may then be ground to thin as needed to enable the through holes 211 of the wafer 10 and the transfer block 21 to be exposed from the upper surface.

Further, a thin film material, for example, an adhesive layer thin film, a sacrificial layer thin film or a buffer layer thin film, is selectively coated on the first surface of the molding material, and then a plurality of re-wiring layers are prepared on the thin film. The method mainly comprises the steps of sputtering a seed layer, coating a dielectric layer, photoetching, developing, curing at high temperature, electroplating, removing the seed layer and the like. Wherein, a plurality of bonding pads are prepared on the first surface of the rewiring layer.

Optionally, in the embodiment of the present application, the chip package structure further includes a first connection post assembly 50 and a second connection post assembly 51, where the first connection post assembly 50 is embedded in the first plastic sealing layer 40 along the first direction, and the second connection post assembly 51 is embedded in the third plastic sealing layer 42 along the first direction; the first connection post assembly 50 is connected to the first and second re-wiring layers 30 and 31 at both ends thereof in the first direction, and the second connection post assembly 51 is connected to the third and fourth re-wiring layers 32 and 33 at both ends thereof in the first direction; the wafer 10 is connected through the second redistribution layer 31, the first connection pillar assembly 50, and the first redistribution layer 30 to achieve electrical interconnection with pins disposed at the first redistribution layer 30; the wafer 10 is connected through the third re-wiring layer 32, the second connection post assembly 51, and the fourth re-wiring layer 33 to realize electrical interconnection with pins provided at the fourth re-wiring layer 33.

In the embodiment of the present application, the first connection post assembly 50 and the second connection post assembly 51 are used to implement electrical interconnection between pins. The first connecting post assembly 50 is embedded in the first plastic layer 40 along the first direction, and the second connecting post assembly 51 is embedded in the third plastic layer 42 along the first direction. Specifically, both ends of the first connection post assembly 50 in the first direction are connected to the first and second re-wiring layers 30 and 31, respectively, both ends of the second connection post assembly 51 in the first direction are connected to the third and fourth re-wiring layers 32 and 33, respectively, the wafer 10 is connected through the second re-wiring layer 31, the first connection post assembly 50 and the first re-wiring layer 30, and the wafer 10 is connected through the third and second re-wiring layers 32, 51 and 33 to realize electrical interconnection between pins. That is, the metal wiring in the fourth re-wiring layer 33 is connected to the first re-wiring layer 30 through the fourth re-wiring layer 33, the second connection post assembly 51, the third re-wiring layer 32, the interposer assembly 20, the second re-wiring layer 31, and the first connection post assembly 50 to achieve electrical interconnection between the upper and lower pins.

The material of the connection post may be copper, or may be another material for realizing electrical interconnection, which is not limited in this embodiment. In addition, the shape of the connecting post may be spherical, cylindrical or square. The shape of the connecting posts may be the same or different. The present embodiment is not limited in any way.

Alternatively, in the embodiment of the present application, the connection terminal assembly 60 includes a plurality of first connection terminals 61 and a plurality of second connection terminals 62, and the plurality of first connection terminals 61 form a first connection terminal 61 array and are arranged on the chip active surface 70; the first connection terminals 61 are arranged in a plurality of rows and columns, gaps are formed between any two adjacent columns or any two adjacent rows of the second connection terminals 62, a plurality of second connection terminals 62 are arranged in at least two gaps, and the plurality of second connection terminals 62 are uniformly distributed at intervals in the gaps along the extending direction of the gaps.

In the present embodiment, the connection terminal assembly 60 includes a plurality of first connection terminals 61 and a plurality of second connection terminals 62, wherein the first connection terminals 61 are larger in size than the second connection terminals 62. The plurality of first connection terminals 61 form a first connection terminal 61 array and are arranged on the chip active surface 70, specifically, as shown in fig. 3, the first connection terminal 61 array is a plurality of rows and a plurality of columns, it can be understood that the plurality of first connection terminals 61 are uniformly arranged at intervals along two directions perpendicular to each other, and gaps are formed between the first connection terminals 61 of any two adjacent columns or any two adjacent rows. The plurality of second connection terminals 62 are each disposed in the gap between the adjacent two first connection terminals 61, and the second connection terminals 62 disposed in the gap are uniformly spaced apart. In this embodiment of the application, carry out special size through the connecting terminal of rewiring layer with wafer 10 thermal stress concentration region and strengthen the processing to evenly disperse to the whole active surface of chip, thereby effectively reduce the assembly of thermal stress, have the beneficial effect that promotes the whole radiating effect of chip, in addition, size strengthens connecting terminal and can strengthen the welding strength between chip and the mainboard, has the beneficial effect of avoiding welding crack unusual.

It should be noted that, one second connection terminal 62 may be disposed between two first connection terminals 61, or a plurality of second connection terminals 62 may be disposed, and the number of the second connection terminals may be determined according to the actual situation, which is not limited in this embodiment.

Alternatively, in the embodiment of the present application, the projection of the first connection terminal 61 on the chip active surface 70 is a first cross section, the projection of the second connection terminal 62 on the chip active surface 70 is a second cross section, and the area of the first cross section is larger than the cross section of the second cross section.

In the embodiment of the present application, the first cross section is a projection of the first connection terminal 61 on the active surface of the chip, and the second cross section is a projection of the second connection terminal 62 on the active surface of the chip, and the area of the first cross section is larger than the area of the second cross section, that is, the size of the first connection terminal 61 is larger than the size of the second connection terminal 62. Further, the first connection terminal 61 and the second connection terminal 62 may have a spherical shape, a cylindrical shape, or a square shape. The first connection terminal 61 and the second connection terminal 62 may have the same shape or may have different shapes. The present embodiment is not limited in any way.

It should be noted that the specifications of the connection terminals in the connection terminal assembly 60 may be various, and are not limited to the two specifications, and the present embodiment is not limited to this, and may be specific according to the actual situation.

Note that, the first connection terminal 61 and the second connection terminal 62 may be solder balls or bumps, which are not limited in this embodiment.

Alternatively, in the embodiment of the present application, the second connection post assembly 51 includes a first connection post 511 and a second connection post 512, the first connection post 511 is connected to the first connection terminal 61, and the second connection post 512 is connected to the second connection terminal 62; wherein the diameter of the first connection post 511 is larger than the diameter of the second connection post 512.

In the embodiment of the present application, the second connection post assembly 51 is connected to the connection terminal assembly 60, the second connection post assembly 51 includes a first connection post 511 and a second connection post 512, wherein the diameter of the first connection post 511 is larger than that of the second connection post 512, the first connection post 511 is connected to the first connection terminal 61, and the second connection post 512 is connected to the second connection terminal 62. The connection post of a large size and the connection terminal of a large size are connected, and the connection post of a small size and the connection terminal of a small size are connected. In this application implementation, the first connecting column 511 with enlarged size and the second connecting column 512 with smaller size than the first connecting column 511 are respectively and correspondingly connected with the connecting terminals with different sizes, which further reduces the concentration of thermal stress, evenly distributes the thermal stress on the active surface, and is more beneficial to improving the overall heat dissipation effect of the chip, in addition, the first connecting column 511 with the size can enhance the welding strength between the target chip and the connecting terminals.

Optionally, in the embodiment of the present application, the adapter block assembly 20 includes a plurality of adapter blocks 21, the plurality of adapter blocks 21 are enclosed on the periphery of the wafer 10, the wafer 10 and the plurality of adapter blocks 21 are disposed at intervals, and the plurality of adapter blocks 21 are disposed at intervals.

In the embodiment of the present application, the plurality of the transfer blocks 21 are enclosed on the periphery of the wafer 10, and it can be understood that the plurality of transfer blocks 21 enclose the wafer 10 along the periphery, and the wafer 10 and the plurality of transfer blocks 21 are disposed at intervals, and the plurality of transfer blocks 21 are disposed at intervals. The gap at the interval is filled with plastic sealing material of the plastic sealing layer. In the embodiment of the application, the strength of the chip packaging structure is enhanced through the arrangement of the plastic packaging material and the plurality of the adapter blocks 21, so that the wafer packaging structure can bear more stress load, and the warping deformation degree of the chip can be better controlled within an acceptable range. In addition, the transfer block 21 can obtain better heat dissipation effect for the chip 10 compared with the completely filled plastic package material.

The number of the plurality of the adapter blocks 21 may be four, six, or eight, and may be specific according to the actual situation. The present embodiment is not limited in any way.

It should be noted that the material of the adapter block 21 may be silicon, and in practical applications, the adapter block assembly 20 may include a plurality of silicon adapter blocks.

Alternatively, in the embodiment of the present application, the transfer block 21 includes a through hole 211 and an electrical conductor 212, the through hole 211 is opened in the transfer block 21 along the first direction, the electrical conductor 212 is filled in the through hole 211, and the electrical conductor 212 is connected to the second redistribution layer 31 and the third redistribution layer 32, respectively.

In the present embodiment, the via 211 is configured to provide a mounting space for the conductor 212, and the conductor 212 is configured to electrically interconnect with an adjacent redistribution layer. The through hole 211 is opened in the first direction in the adapter block 21, the conductor 212 is filled in the through hole 211, and the conductor 212 is connected to the second redistribution layer 31 and the third redistribution layer 32, respectively.

Note that, when the number of the through holes 211 may be greater than that of the conductive body 212, the same as that of the conductive body 212 may be used. When the number of through holes 211 is greater than that of the conductors 212, the through holes 211 without the conductors 212 may further improve the heat radiation capability of the joint block 21.

Specifically, the through holes 211 (Through Silicon Via, abbreviated as "TSVs") are formed by punching holes in the silicon body and filling the holes with the conductive bodies 212, thereby performing vertical interconnection between chips. In practical applications, the main steps of TSV include photoresist marking, deep reactive ion etching, vapor deposition of seed layer, filling electroplated copper, chemical mechanical polishing, and fabricating circuit layer.

In addition, etching is performed on the upper and lower surfaces of the interposer block 21, respectively, to make corresponding related metal wirings (including a plurality of pads), and in particular, silicon etching is a process of selectively removing unwanted materials from the surface of the silicon wafer using a chemical or physical method, which is a generic term for stripping and removing materials by a solution, a reactive ion or other mechanical means. The present embodiment is not limited to a silicon etching process.

Optionally, in the embodiment of the present application, the wafer 10 further includes a plurality of through-wafer vias 11, and the plurality of through-wafer vias 11 are disposed on the wafer 10 along the first direction.

In this embodiment, the wafer 10 further includes a plurality of through-wafer vias 11, and the plurality of through-wafer vias 11 are disposed on the wafer 10 along the first direction. The provision of the through-wafer vias 11 serves to enhance the heat dissipation of the wafer 10.

In practical applications, the wafer 10 and the plurality of transfer blocks 21 are sequentially mounted on the carrier. Specifically, a layer of heat release film is first attached to the upper surface of the carrier, and then the wafer 10 and the plurality of transfer blocks 21 are sequentially attached to the heat release film in accordance with the chip layout design, respectively.

In particular, the adapter 21 can enhance the strength of the body structure of the wafer 10, and can share the body stress load of the wafer 10, so that the degree of warpage deformation of the chip can be better controlled within an acceptable range.

Optionally, in an embodiment of the present application, there is further provided an electronic device including the chip packaging structure as described above.

In the embodiment of the application, the electronic equipment comprises the chip packaging structure, and the electronic equipment provided with the chip packaging structure has the advantages of reducing local thermal stress concentration, being more beneficial to the overall heat dissipation of the chip and reducing the possibility of warping problem of the chip caused by thermal stress concentration. In addition, the same plastic layer wraps the wafer 10 and the adapter block assembly 20, so that the strength of the body structure of the wafer 10 is improved, the stress load borne by the chip packaging structure is increased, and the possibility of warping of the chip due to thermal stress is further reduced.

Referring to fig. 4 to 15, a process for manufacturing a chip package structure is shown. In the actual manufacturing process, referring to fig. 4, the interposer is prepared on the carrier board, including the through holes 211 and the surface circuit of the interposer, and the manufacturing process of the plurality of interposer blocks 21 in the interposer block assembly 20 is consistent. Specifically, since the material of the transfer block is silicon, it is understood that the through hole 211 may be a through silicon via (Through Silicon Via, abbreviated as "TSV"), that is, the hole is perforated by a silicon body layer and then filled with a conductive metal, so as to perform vertical interconnection between chips, and the main steps of TSV fabrication include photoresist marking, deep reactive ion etching, vapor deposition of a seed layer, filling with electroplated copper, chemical mechanical polishing, and fabrication of a circuit layer.

It should be noted that the carrier may be understood as a carrier that plays a supporting role in the chip packaging process, and is not a chip packaging structure, but is only used in the packaging process, where the carrier may be glass, ceramic, metal or other materials with similar functions and compatible with the wafer level packaging process, and the embodiment is not limited in this respect, and in addition, a plurality of different carrier may be used in the packaging process of the present application.

Referring to fig. 5, etching is performed on upper and lower surfaces of the silicon transfer block, respectively, to fabricate corresponding related metal wirings including a plurality of pads. Specifically, silicon etching is a process of selectively removing unwanted materials from the surface of a silicon wafer using chemical or physical methods, which is a generic term for stripping and removing materials by solution, reactive ions or other mechanical means. The present application is not limited to silicon etching processes.

Referring to fig. 6, the wafer 10 and the transfer block group 20 are sequentially attached to another carrier plate, respectively. Specifically, a layer of thermal stripping film is firstly stuck on the upper surface of the carrier plate, and then the wafer 10 and the transfer block group 20 are respectively stuck on the thermal stripping film in sequence according to the chip layout design. In particular, the adaptor 21 can enhance the strength of the chip body structure, and can share the stress load of the multi-chip body, so that the warpage deformation degree of the chip can be better controlled within an acceptable range.

Referring to fig. 7, a molding material is filled as a second molding layer 41, and a first surface of the second molding layer 41 facing away from the wafer 10 is ground. Specifically, the plastic packaging material is filled on the first surface of the carrier plate and surrounds the wafer 10 and the side surfaces and the bottom surfaces of the plurality of transfer blocks 21, so that the back surface and the side surfaces of the wafer 10 are isolated from the outside, and in addition, the filling height of the plastic packaging material is at least higher than the upper surfaces of the wafer 10 and the transfer blocks 21. The molding material may then be ground to thin as needed to enable the through holes 211 of the wafer 10 and the transfer block 21 to be exposed from the upper surface.

Referring to fig. 8, the second redistribution layer 31 (RDL, redistribution Layer) is prepared. Specifically, the first surface of the second plastic layer 41 is selectively coated with a thin film material, for example, an adhesive layer thin film, a sacrificial layer thin film, or a buffer layer thin film. A second redistribution layer 31 is then prepared on the film. The method mainly comprises the steps of sputtering a seed layer, coating a dielectric layer, photoetching, developing, curing at high temperature, electroplating, removing the seed layer and the like. Wherein a number of pads are prepared on the first surface of the second redistribution layer 31.

Referring to fig. 9, a first molding layer 40 and a first connection post assembly 50 are prepared on a first surface of the second redistribution layer 31. Specifically, the first connection post assembly 50 may be prepared by sputtering a seed layer, performing photolithography with a dry film (dry film lamination), developing, curing, electroplating, photoresist removing, seed layer removing, plastic packaging, and the like. That is, the first connection post assembly 50 may be plated on the exposed position of the first surface metal wiring of the second re-wiring layer 31, and both ends of the first connection post assembly 50 may be connected to the lines of the second re-wiring layer 31 and the first re-wiring layer 30 of the subsequent process, respectively, to form a channel for line communication. The molding material is filled as the first molding layer 40, and the first surface of the first molding layer 40 is ground. Specifically, the plastic sealing material is filled in the first surface of the second redistribution layer 31 and surrounds the side surfaces and the bottom surface of the first connection pillar assembly 50, so that the back surface and the side surfaces are isolated from the outside, and in addition, the filling height of the plastic sealing material is at least higher than the upper surface of the first connection pillar assembly 50. The molding compound may then be ground as needed to thin down so that the first connector post assembly 50 can be exposed from the first surface of the molding compound.

Referring to fig. 10, a first re-wiring layer 30 is prepared. Specifically, a film material, for example, an adhesive layer film, a sacrificial layer film, or a buffer layer film, may be selectively coated on the first surface of the first molding layer 40. A first redistribution layer 30 is then prepared on the film. The method mainly comprises the steps of sputtering a seed layer, coating a dielectric layer, photoetching, developing, curing at high temperature, electroplating, removing the seed layer and the like. Wherein a number of pads are prepared on the first surface of the first redistribution layer 30.

The steps shown in fig. 4 to 10 can be performed to obtain the package structure shown in fig. 10, which can be a reconstituted wafer.

Referring to fig. 11, a third re-wiring layer 32 is prepared on the second surface of the second molding layer 41. In particular, fig. 4 to 10 and 11 to 15 use different carrier plates. Before the third redistribution layer 32 is prepared, the reconstituted wafer obtained in the above steps is flipped over in the vertical direction as shown in fig. 10, the other side of the reconstituted wafer is attached to another carrier, and then the previous carrier is removed. And begins to prepare the third re-wiring layer 32 on the second surface of the second molding layer 41. Specifically, a film material, for example, an adhesive layer film, a sacrificial layer film, or a buffer layer film, may be selectively coated on the second surface of the second molding layer 41. A third re-wiring layer 32 is then prepared on the film. The method mainly comprises the steps of sputtering a seed layer, coating a dielectric layer, photoetching, developing, curing at high temperature, electroplating, removing the seed layer and the like. Wherein a number of pads are prepared on the first surface of the third re-wiring layer 32.

Referring to fig. 12, a second connection post assembly 51 is prepared on the first surface of the third re-wiring layer 32. Specifically, the connecting column can be prepared by adopting the technological methods of sputtering a seed layer, photoetching a dry film (dry film lamination), developing, solidifying, electroplating, photoresist removing, seed layer removing, plastic packaging and the like. That is, the second connection post assembly 51 may be plated on the exposed position of the first surface metal wiring of the third re-wiring layer 32, and both ends of the connection post may be respectively connected to the third re-wiring layer 32 of the chip and the fourth re-wiring layer 33 of the subsequent process to form a channel for line communication.

Referring to fig. 13, a molding material is filled as the third molding layer 42, and the first surface of the third molding layer 42 is ground. Specifically, the first surface of the third wiring layer 32 is filled with a molding material, and the side and bottom surfaces of the second connection post assembly 51 are sealed and surrounded, so that the back surface and the side surfaces are isolated from the outside, in addition, the filling height of the molding material is at least higher than the upper surface of the second connection post assembly 51, and then the molding material can be ground to be thinned as required, so that the second connection post assembly 51 can be exposed from the first surface of the third molding layer 42.

Referring to fig. 14, a fourth re-wiring layer 33 is prepared. Specifically, the first surface of the third plastic layer 42 is selectively coated with a thin film material, for example, an adhesive layer thin film, a sacrificial layer thin film, or a buffer layer thin film. A third plastic layer 42 is then prepared on the film. The method mainly comprises the steps of sputtering a seed layer, coating a dielectric layer, photoetching, developing, curing at high temperature, electroplating, removing the seed layer and the like. An under bump metal (Under Bump Metallization, abbreviated as "UBM") may be formed on the first surface of the fourth redistribution layer 33 to improve bonding strength and mechanical reliability, and the UBM may be used for subsequent solder ball or bump fabrication. The material, structure and process of the UBM are not limited in this application.

Referring to fig. 15, a connection terminal assembly 61 is prepared on the UBM of the first surface of the fourth re-wiring layer 33. Specifically, the connection terminal assembly 61 may be prepared by electroplating, printing, ball plating, etc., and the connection terminal may be a solder ball, a solder bump, or other equivalent structure having an electrical interconnection function. In particular, the present application may include two or more sets of connection terminals of different sizes, which is not limited in any way. For ease of understanding, the present application will be described with reference to fig. 3 by taking two sets of examples, including a first connection terminal 61 and a second connection terminal 62.

By way of example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), and the like, and the non-mobile electronic device may be a personal computer (personal computer, PC), a Television (TV), a teller machine, a self-service machine, and the like, and the embodiments of the present application are not limited in particular.

It should be noted that, the electronic device in the embodiment of the present invention includes the mobile electronic device and the non-mobile electronic device described above.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.

Claims

1. A chip package structure, comprising: a plurality of rewiring layers, a plurality of plastic sealing layers, a wafer (10), a connecting terminal assembly (60) and a transfer block assembly (20), wherein the wafer (10) and the transfer block assembly (20) are packaged by the plurality of rewiring layers and the plurality of plastic sealing layers;

the plurality of rewiring layers are stacked along a first direction, the plastic sealing layers are clamped between two adjacent rewiring layers, the wafer (10) and the adapter block assembly (20) are embedded in the same plastic sealing layer, the adapter block assembly (20) is arranged on the periphery of the wafer (10) in a surrounding mode, the connecting terminal assembly (60) is connected to the rewiring layer farthest from the wafer along the first direction in the plurality of rewiring layers, and the connecting terminal assembly (60) is arranged on one surface, deviating from the plastic sealing layer, of the rewiring layer;

wherein the first direction is a direction perpendicular to the wafer (10), and a surface of the rewiring layer, on which the connection terminal assembly (60) is arranged, is the chip active surface (70).

2. The chip package structure according to claim 1, wherein the plurality of redistribution layers includes a first redistribution layer (30), a second redistribution layer (31), a third redistribution layer (32), and a fourth redistribution layer (33), and the plurality of molding layers includes a first molding layer (40), a second molding layer (41), and a third molding layer (42);

the first rewiring layer (30), the first plastic sealing layer (40), the second plastic sealing layer (31), the second plastic sealing layer (41), the third plastic sealing layer (32), the third plastic sealing layer (42) and the fourth plastic sealing layer (33) are sequentially and alternately arranged, and the wafer (10) and the adapter component (20) are embedded in the second plastic sealing layer (41).

3. The chip package structure according to claim 2, further comprising a first connection post assembly (50) and a second connection post assembly (51), the first connection post assembly (50) being embedded in the first molding layer (40) along the first direction, the second connection post assembly (51) being embedded in the third molding layer (42) along the first direction;

the first connecting column assembly (50) is connected with the first rewiring layer (30) and the second rewiring layer (31) along the two ends of the first direction respectively, and the second connecting column assembly (51) is connected with the third rewiring layer (32) and the fourth rewiring layer (33) along the two ends of the first direction respectively;

the wafer (10) is connected through the second redistribution layer (31), the first connection stud assembly (50) and the first redistribution layer (30) to enable electrical interconnection with pins disposed on the first redistribution layer (30);

the wafer (10) is connected through the third re-wiring layer (32), the second connection stud assembly (51) and the fourth re-wiring layer (33) to realize and provide electrical interconnection of pins at the fourth re-wiring layer (33).

4. The chip package structure according to claim 1, wherein the connection terminal assembly (60) includes a plurality of first connection terminals (61) and a plurality of second connection terminals (62), and the plurality of first connection terminals (61) form a first connection terminal array and are arranged on the chip active surface (70);

the first connecting terminal array is multi-row and multi-column, gaps are formed between any two adjacent columns or any two adjacent rows of the first connecting terminals (61), a plurality of second connecting terminals (62) are arranged in any one gap, and the second connecting terminals (62) are uniformly distributed at intervals in the gap along the extending direction of the gap.

5. The chip package structure according to claim 4, wherein a projection of the first connection terminal (61) onto the chip active surface (70) is a first cross-section, and a projection of the second connection terminal (62) onto the chip active surface (70) is a second cross-section, and an area of the first cross-section is larger than an area of the second cross-section.

6. The chip package structure according to claim 5, wherein the second connection post assembly (51) includes a first connection post (511) and a second connection post (512), the first connection post (511) being connected to the first connection terminal (61), the second connection post (512) being connected to the second connection terminal (62);

wherein the diameter of the first connecting post (511) is larger than the diameter of the second connecting post (512).

7. The chip packaging structure according to claim 6, wherein the adapter assembly (20) comprises a plurality of adapter blocks (21), the plurality of adapter blocks (21) are arranged around the periphery of the wafer (10), the wafer (10) and the plurality of adapter blocks (21) are arranged at intervals, and the plurality of adapter blocks (21) are arranged at intervals.

8. The chip packaging structure according to claim 7, wherein the via (21) includes a through hole (211) and a conductor (212), the through hole (211) is opened in the via (21) along the first direction, the conductor (212) is filled in the through hole (211), and the conductor (212) is connected to the second redistribution layer (31) and the third redistribution layer (32), respectively.

9. The chip packaging structure according to claim 8, wherein the wafer (10) further comprises a plurality of through wafer vias (11), the plurality of through wafer vias (11) being open to the wafer (10) along the first direction.

10. An electronic device comprising the chip package structure according to any one of claims 1 to 9.