CN116435203A - IC packaging technology of conducting resin and copper column double-sided fan-out - Google Patents
IC packaging technology of conducting resin and copper column double-sided fan-out Download PDFInfo
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- CN116435203A CN116435203A CN202310203885.4A CN202310203885A CN116435203A CN 116435203 A CN116435203 A CN 116435203A CN 202310203885 A CN202310203885 A CN 202310203885A CN 116435203 A CN116435203 A CN 116435203A
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 45
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 31
- 239000010949 copper Substances 0.000 title claims abstract description 31
- 239000011347 resin Substances 0.000 title claims abstract description 5
- 229920005989 resin Polymers 0.000 title claims abstract description 5
- 238000012536 packaging technology Methods 0.000 title description 2
- 238000005553 drilling Methods 0.000 claims abstract description 28
- 239000003292 glue Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000012545 processing Methods 0.000 claims abstract description 17
- 239000011889 copper foil Substances 0.000 claims abstract description 14
- 238000003825 pressing Methods 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 238000012858 packaging process Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000012546 transfer Methods 0.000 claims abstract description 4
- 229910000679 solder Inorganic materials 0.000 claims description 16
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 238000007639 printing Methods 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000003801 milling Methods 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 abstract description 3
- 229910010271 silicon carbide Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 11
- 238000004806 packaging method and process Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 239000012467 final product Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83024—Applying flux to the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model discloses an IC packaging process of conducting resin and copper column double-sided fan-out, which comprises the steps of etching a first core plate, a second core plate and a third core plate, and dispensing glue on the first core plate by a glue dispenser; mounting each component on the first core board; after the glue is solidified, slotting the second core plate, the first PP and the second PP; arranging the plates sequentially from bottom to top according to the order of the first core plate, the first PP, the second core plate, the second PP and the third core plate, and pressing to form an L2/5 layer core plate; performing laser drilling pretreatment, processing laser drilling blind holes, and electroplating and filling the blind holes on the laser drilling blind holes; the L2/5 layer core board is subjected to pattern transfer to form an L2/5 layer circuit pattern, PP and copper foil are respectively arranged on the L2/5 layer core board, and the L1/6 layer board is formed by high-temperature pressing of a press; and (3) performing laser drilling pretreatment, processing laser drilling blind holes, performing blind hole electroplating filling, and transferring the patterns on the L1/6 layer plates to form L1/6 layer circuit patterns. The parasitic inductance is low, and the method is suitable for new generation silicon carbide and gallium nitride high-frequency chips, and reduces the energy loss of the circuit.
Description
Technical Field
The utility model relates to the field of semiconductors, in particular to an IC packaging process of double-sided fan-out of conductive adhesive and copper columns.
Background
At present, along with development of cloud computing application, informatization gradually covers various fields of society. The daily work and life of people increasingly use networks, so that the network data volume is continuously increased, and the performance requirement on a server is higher. In the server, the PCB (Printed Circuit Board ) is an important component, the number of devices and the routing density are also continuously improved along with the improvement of the server performance, the single board is larger, the layout and the routing are denser, and finally the workload is larger. With the development of moore's law, the rate is doubled, the capacity is doubled, and the chip is also bigger and bigger, so that the power consumption is suddenly increased and the signal rate is doubled continuously. The number of the board layers is higher and higher, the required board grade is continuously improved, the cost is higher and higher, and the processing challenges are larger and larger.
Components used in the electronic circuit industry are divided into Active components (generally referred to as chips) and passive components (Passive Component, including various capacitive and resistive-inductive components), and the processing steps of the conventional Component package structure are as follows:
1. a solder paste printer was used to screen-print a solder paste on the Top surface of a package Substrate (Substrate) in cooperation with a printing steel mesh.
2. Various active elements and passive elements are mounted on the Top surface of the substrate by using a chip mounter, the solder paste is solidified after lead-free reflow soldering, and a pin of the Bottom surface of the element is interconnected with the packaging substrate by the solder paste, so that signal fan-out of the Bottom surface of the element is realized
3. Connecting chip Top surface with substrate Top surface network by Wire bonding (Wire bonding) to realize chip Top surface signal fanout, and making resistor-capacitor element not Wire bonded, wherein two electrodes fan out signal through solder paste single face
4. Plastic packaging (Molding) is carried out by adding plastic packaging glue to protect the semiconductor chip and the bonding aluminum wire
5. Tin ball is planted on the Bottom surface of the packaging substrate to finish the processing and manufacturing of the plastic packaging module
6. And (3) printing solder paste on the PCB, and attaching the plastic package module and various other passive elements to the surface of the PCB to form a final product.
The patent document with the application number of CN201721719338.8 discloses a high-frequency mixed pressure blind hole plate, and relates to the technical field of PCB plates; the high-frequency ROGERS comprises a high-frequency ROGERS core board, a first PP layer, a first copper foil layer, a second PP layer, an FR-4 core board, a third PP layer and a second copper foil layer; the first PP layer is arranged between the high-frequency ROGERS core plate and the first copper foil layer, the second PP layer is arranged between the first copper foil layer and the FR-4 core plate, and the third PP layer is arranged between the FR-4 core plate and the second copper foil layer; the high-frequency ROGERS core board, the first PP layer, the first copper foil layer, the second PP layer, the FR-4 core board, the third PP layer and the second copper foil layer are all provided with through conductive through holes, and the conductive through holes are used for conducting the high-frequency ROGERS core board, the first copper foil layer and the second copper foil layer electrically; the high-frequency ROGERS core board is formed by laminating copper foil and high-frequency thermosetting ceramic hydrocarbon material; the beneficial effects of the utility model are as follows: the high-frequency signal can be output more quickly, so that the energy consumption is reduced, and the mutual interference and conduction between copper layers are avoided.
Patent document application number "CN202111438916.1" discloses a method, system, apparatus and storage medium for manufacturing a printed circuit board, the method comprising: calculating the total thickness of the copper sheet and the position and the size of the hollowed-out area according to the power consumption requirement and the layout wiring space; determining the thickness of the copper sheet to be added according to the total thickness, and hollowing out the prepreg according to the size widening preset value; manufacturing a copper sheet according to the thickness of the copper sheet to be added and the size, bonding the copper sheet to a core plate, placing the copper sheet into a hollowed-out area, and comparing whether the copper sheet and the hollowed-out area are properly aligned or not; and in response to proper alignment of the copper sheet and the hollowed-out area, laminating, punching and curing the prepreg and the core board to obtain the printed circuit board. According to the utility model, the copper sheet with a small area is arranged at the corresponding position of the core plate to realize the high-power supply requirement of the printed circuit board, so that the cost is greatly reduced, the lamination is flexibly designed, the limitation of conventional requirements such as thickness is reduced, and the yield and the product competitiveness are improved.
The above patent documents disclose, in combination with the prior art, that the existing IC packaging process of double-sided fan-out of conductive glue and copper pillars has the following drawbacks:
1. the parasitic inductance of the aluminum wire is too high to be suitable for the new generation of high-frequency silicon carbide (SiC) and gallium nitride (GaN) chips.
2. The aluminum wire is used for conduction, the transmission path is long, the on-resistance is large, and the conversion efficiency (output power/input power) of the module is reduced
3. The stacked structure of the element, the packaging substrate and the PCB base plate has large plate thickness, and does not accord with the development trend of thinning of electronic products.
4. The components are all mounted on the surfaces of the packaging substrate and the PCB bottom plate, and limited by the surface areas of the substrate and the PCB, the number of the components which can be mounted is limited, and more complex electronic circuit performance can not be realized.
Disclosure of Invention
In order to overcome the defects of the prior art, one of the purposes of the utility model is to provide an IC packaging process with double-sided fan-out of conductive adhesive and copper columns, which can solve the problems of low applicability and low conversion efficiency.
One of the purposes of the utility model is realized by adopting the following technical scheme:
an IC packaging process of conducting resin and copper column double-sided fan-out comprises the following steps:
s10, step: etching the first core plate, the second core plate and the third core plate, and dispensing glue on the first core plate by using a glue dispenser;
s20, step: mounting each component on the first core board;
s30, step: after the glue is solidified, slotting the second core plate, the first PP and the second PP;
s40, step: arranging the plates from bottom to top in sequence according to the first core plate, the first PP, the second core plate, the second PP and the third core plate, and pressing at high temperature by a press to form an L2/5 layer core plate;
s50, step: performing laser drilling pretreatment on the L2/5 layer core plate, processing laser drilling blind holes, and electroplating and leveling the blind holes on the L2/5 layer core plate;
s60, step: the L2/5 layer core board is subjected to pattern transfer to form an L2/5 layer circuit pattern, PP and copper foil are respectively arranged on the L2/5 layer core board, and the L1/6 layer board is formed by high-temperature pressing of a press;
s70, step: and performing laser drilling pretreatment on the L1/6 laminate, processing laser drilling blind holes, electroplating and filling the blind holes, and transferring the patterns of the L1/6 laminate to form L1/6 layers of circuit patterns.
Further, in the step S10, conductive paste including sintered silver paste or solder paste is used when the first core board, the second core board and the third core board are etched and dispensed on the first core board by a dispenser.
Further, in the step S20, when the components are mounted on the first core board, the conductive adhesive is used to conduct the network of the component and the first core board, so as to realize the fan-out signal of the Bottom surface of the component.
Further, in the step S30, after the glue is cured, when the second core board and the grooves of the first PP and the second PP are grooved, if the glue is sintered silver paste, a programmable oven is used for baking and curing.
Further, in the step S30, after the glue is cured, when the second core board and the grooves of the first PP and the second PP are grooved, if the glue is solder paste, the lead-free reflow soldering wire is cured.
Further, in the step S30, when the second core board, the first PP and the second PP are grooved after the glue is cured, the grooving processing mode is die cutting or CNC numerical control milling.
Further, in the step S50, when the L2/5 layer core board is subjected to laser drilling pretreatment and laser drilling blind holes are processed, and the blind holes on the laser drilling blind holes are electroplated and filled, the chip Top surface pins are interconnected with the PCB network through the laser drilling blind holes and fan out signals.
Further, in the step S50, the circuit pattern is designed on the second core board by designing the buried holes of the L2/5 layer and the through holes of the L1/6 layer, and then the build-up layer is further designed to realize more complex electrical functions.
Further, the method further comprises the step of S80: and (5) performing the processing of the rest PCB flow.
Further, the method further comprises the step of S90: and (3) printing solder paste on the PCB, and attaching the plastic-packaged module to the surface of the PCB as a plastic-packaged module or attaching the plastic-packaged module and a passive element to the Top surface of the PCB as the PCB.
Compared with the prior art, the utility model has the beneficial effects that:
(1) The embedded chip directly fans out signals through the blind hole copper column, has low parasitic inductance, is suitable for the new generation of silicon carbide and gallium nitride high-frequency chips, and solves the problems of low applicability and low conversion efficiency.
(2) The embedded element transmits electric signals through the blind hole copper column, the resistivity is low, the transmission path is short, the conversion efficiency (output power/input power) of the module is greatly improved, and the energy loss of the circuit is reduced.
(3) The product structure of the element and the pure PCB has no package substrate design, greatly reduces the thickness of the final product, and caters to the development trend of thinning of electronic products.
(4) The module has high integration level, more compact and dense wiring, and is beneficial to realizing more complex electronic circuit functions.
(5) Part of the elements are embedded into the PCB, so that a large amount of surface area of the PCB is vacated for mounting more surface elements, and more complex electronic circuit functions are realized.
The foregoing description is only an overview of the present utility model, and is intended to be implemented in accordance with the teachings of the present utility model, as well as the preferred embodiments thereof, together with the following detailed description of the utility model, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 is a flow chart of a preferred embodiment of the IC packaging process of the double-sided fan-out of the conductive paste and copper pillars of the present utility model;
FIG. 2 is a schematic illustration of a core plate structure;
fig. 3 is a schematic view of another core structure.
Detailed Description
The present utility model will be further described with reference to the accompanying drawings and detailed description, wherein it is to be understood that, on the premise of no conflict, the following embodiments or technical features may be arbitrarily combined to form new embodiments.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When a component is considered to be "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, an IC package process of double-sided fanout of a conductive paste and a copper pillar includes the following steps:
s10, step: etching the first core plate, the second core plate and the third core plate, and dispensing glue on the first core plate by using a glue dispenser; preferably, in the step S10, a conductive paste including sintered silver paste or solder paste is used when the first core board, the second core board and the third core board are etched and dispensed on the first core board by a dispenser.
S20, step: mounting each component on the first core board; preferably, in the step S20, when the components are mounted on the first core board, the conductive adhesive is used to conduct the network of the component and the first core board, so as to realize the fan-out signal of the Bottom surface of the component.
S30, step: after the glue is solidified, slotting the second core plate, the first PP and the second PP; preferably, in the step S30, after the glue is cured, when the second core board and the grooves of the first PP and the second PP are grooved, if the glue is sintered silver paste, a programmable oven is used for baking and curing. If the glue is solder paste, the solder paste is cured by lead-free reflow soldering. The grooving processing mode is die cutting or CNC numerical control milling.
S40, step: arranging the plates from bottom to top in sequence according to the first core plate, the first PP, the second core plate, the second PP and the third core plate, and pressing at high temperature by a press to form an L2/5 layer core plate;
s50, step: performing laser drilling pretreatment on the L2/5 layer core plate, processing laser drilling blind holes, and electroplating and leveling the blind holes on the L2/5 layer core plate; preferably, in the step S50, when the L2/5 layer core board is subjected to laser drilling pretreatment and processing of laser drilling blind holes, and the blind holes on the laser drilling blind holes are electroplated and filled, the chip Top surface pins are interconnected with the PCB network through the laser drilling blind holes and fan out signals. Through designing L2/5 layer buried holes and L1/6 layer through holes, and designing circuit patterns on the second core board, and continuing to design build-up layers to realize more complex electrical functions.
S60, step: the L2/5 layer core board is subjected to pattern transfer to form an L2/5 layer circuit pattern, PP and copper foil are respectively arranged on the L2/5 layer core board, and the L1/6 layer board is formed by high-temperature pressing of a press;
s70, step: the L1/6 layer plate is subjected to laser drilling pretreatment, laser drilling blind holes are processed, blind holes are electroplated and filled, and the L1/6 layer plate pattern is transferred to form an L1/6 layer circuit pattern, wherein the specific schematic diagram is shown in FIG. 2.
S80, step: and (5) performing the processing of the rest PCB flow.
S90, step: and (3) printing solder paste on the PCB, and attaching the plastic-packaged module to the surface of the PCB as a plastic-packaged module or attaching the plastic-packaged module and a passive element to the Top surface of the PCB as the PCB. The method has the following technical effects:
(1) The embedded chip directly fans out signals through the blind hole copper column, has low parasitic inductance, is suitable for the new generation of silicon carbide and gallium nitride high-frequency chips, and solves the problems of low applicability and low conversion efficiency.
(2) The embedded element transmits electric signals through the blind hole copper column, the resistivity is low, the transmission path is short, the conversion efficiency (output power/input power) of the module is greatly improved, and the energy loss of the circuit is reduced.
(3) The product structure of the element and the pure PCB has no package substrate design, greatly reduces the thickness of the final product, and caters to the development trend of thinning of electronic products.
(4) The module has high integration level, more compact and dense wiring, and is beneficial to realizing more complex electronic circuit functions.
(5) Part of the elements are embedded into the PCB, so that a large amount of surface area of the PCB is vacated for mounting more surface elements, and more complex electronic circuit functions are realized.
It should be noted that: referring to fig. 3 specifically, the above-mentioned basic process flow is that more complex electrical functions can be realized by designing L2/5 layer buried holes and L1/6 layer through holes, designing circuit patterns on the second core board, and continuing to design build-up layers.
The above embodiments are only preferred embodiments of the present utility model, and the scope of the present utility model is not limited thereto, but any insubstantial changes and substitutions made by those skilled in the art on the basis of the present utility model are intended to be within the scope of the present utility model as claimed.
Claims (10)
1. The IC packaging process of conducting resin and copper column double-sided fan-out is characterized by comprising the following steps:
s10, step: etching the first core plate, the second core plate and the third core plate, and dispensing glue on the first core plate by using a glue dispenser;
s20, step: mounting each component on the first core board;
s30, step: after the glue is solidified, slotting the second core plate, the first PP and the second PP;
s40, step: arranging the plates from bottom to top in sequence according to the first core plate, the first PP, the second core plate, the second PP and the third core plate, and pressing at high temperature by a press to form an L2/5 layer core plate;
s50, step: performing laser drilling pretreatment on the L2/5 layer core plate, processing laser drilling blind holes, and electroplating and leveling the blind holes on the L2/5 layer core plate;
s60, step: the L2/5 layer core board is subjected to pattern transfer to form an L2/5 layer circuit pattern, PP and copper foil are respectively arranged on the L2/5 layer core board, and the L1/6 layer board is formed by high-temperature pressing of a press;
s70, step: and performing laser drilling pretreatment on the L1/6 laminate, processing laser drilling blind holes, electroplating and filling the blind holes, and transferring the patterns of the L1/6 laminate to form L1/6 layers of circuit patterns.
2. The IC package process for double sided fanout of conductive paste and copper pillar according to claim 1, wherein: in the step S10, conductive paste including sintered silver paste or solder paste is used when the first core board, the second core board and the third core board are etched and dispensed on the first core board by a dispenser.
3. The IC package process for double sided fanout of conductive paste and copper pillar according to claim 1, wherein: in the step S20, when the components are mounted on the first core board, the conductive adhesive is used to conduct the network of the component and the first core board, so as to realize the fan-out signal of the Bottom surface of the component.
4. The IC package process for double sided fanout of conductive paste and copper pillar according to claim 1, wherein: in the step S30, after the glue is cured, when the second core board and the grooves of the first PP and the second PP are grooved, if the glue is sintered silver paste, the programmable oven is used for baking and curing.
5. The IC package process for double sided fanout of conductive paste and copper pillar according to claim 1, wherein: in the step S30, after the glue is cured, when the second core board and the grooves of the first PP and the second PP are grooved, if the glue is solder paste, the lead-free reflow soldering wire is cured.
6. The IC package process for double sided fanout of conductive paste and copper pillar according to claim 1, wherein: in the step S30, after the glue is cured, the second core board, the first PP and the second PP are grooved, and the grooving processing mode is die cutting or CNC numerical control milling.
7. The IC package process for double sided fanout of conductive paste and copper pillar according to claim 1, wherein: in the step S50, when the L2/5 layer core board is subjected to laser drilling pretreatment and laser drilling blind holes are processed, and the blind holes on the L2/5 layer core board are electroplated and filled, chip Top surface pins are interconnected with a PCB network through the laser drilling blind holes and fan out signals.
8. The IC package process for double sided fanout of conductive paste and copper pillar according to claim 1, wherein: in the step S50, the L2/5 layer buried holes and the L1/6 layer through holes are designed, the circuit patterns are designed on the second core board, and the layer adding is further designed to realize more complex electrical functions.
9. The IC package process of claim 1, further comprising the step of S80: and (5) performing the processing of the rest PCB flow.
10. The IC package process of claim 1, further comprising the step of S90: and (3) printing solder paste on the PCB, and attaching the plastic-packaged module to the surface of the PCB as a plastic-packaged module or attaching the plastic-packaged module and a passive element to the Top surface of the PCB as the PCB.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310203885.4A CN116435203A (en) | 2023-03-03 | 2023-03-03 | IC packaging technology of conducting resin and copper column double-sided fan-out |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310203885.4A CN116435203A (en) | 2023-03-03 | 2023-03-03 | IC packaging technology of conducting resin and copper column double-sided fan-out |
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