CN116431416B

CN116431416B - Processor, debugging method, computing device, and computer-readable storage medium

Info

Publication number: CN116431416B
Application number: CN202310653489.1A
Authority: CN
Inventors: 徐凯; 方奇; 闫欣
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2023-06-05
Filing date: 2023-06-05
Publication date: 2023-08-11
Anticipated expiration: 2043-06-05
Also published as: CN116431416A

Abstract

The application provides a processor, a debugging method, a computing device and a computer readable storage medium, wherein the processor comprises: one or more cores; the first debugging port is used for receiving and/or sending debugging commands; the second debugging port is used for sending tracking data; and the first data channel comprises one or more routing nodes, and is connected with the one or more cores, the first debugging port and the second debugging port through the one or more routing nodes. The embodiment of the application is beneficial to reducing the number of buses used for on-chip debugging in a processor by adopting the same data channel to transmit the debugging command and the tracking data. In addition, the data channel comprises a routing node, and the forwarding mechanism of the routing node can be used for reducing difficulty and cost of top-level connection and physical implementation of a debugging system in a processor while guaranteeing data accuracy.

Description

Processor, debugging method, computing device, and computer-readable storage medium

Technical Field

The present application relates to the field of computer technology, and more particularly, to a processor, a debugging method, a computing device, and a computer readable storage medium.

Background

When on-chip debugging a processor based on debug commands and trace data (trace), the debug commands and trace data are typically transmitted using different buses. With the greatly increased demands on processor performance, dominant frequency, and number of cores, the number of buses transmitting debug commands and trace data may increase exponentially.

Disclosure of Invention

The application provides a processor, a debugging method, a computing device and a computer readable storage medium. Various aspects of embodiments of the application are described below.

In a first aspect, there is provided a processor comprising: one or more cores; a first debug port for receiving and/or sending debug commands for on-chip debugging of the one or more cores; the second debugging port is used for sending tracking data; the first data channel is used for transmitting the debugging command and the tracking data, and comprises one or more routing nodes, and the first data channel is connected with the one or more cores, the first debugging port and the second debugging port through the one or more routing nodes, wherein the one or more routing nodes are used for forwarding the debugging command and the tracking data transmitted by the first data channel.

As a possible implementation manner, the processor further includes: the first conversion module is connected with a first routing node in the one or more routing nodes, and is connected with the first debugging port, and the first conversion module is used for converting a data format between the first debugging port and the first routing node.

As a possible implementation manner, the first conversion module is connected to the second debug port, and the first conversion module is further configured to: and converting the data format supported by the first routing node into the data format supported by the second debugging port.

As a possible implementation manner, the processor further includes: and the second conversion module is connected with one core of the one or more cores, is connected with a second routing node and is used for converting the data format between the core and the second routing node.

As a possible implementation manner, the second conversion module is further configured to: receiving the debug command sent by the second routing node; judging whether the debugging command meets the requirement or not; and returning a response message corresponding to the debugging command according to the judging result.

As a possible implementation manner, the first conversion module is further configured to: receiving the debug command through a first debug port; determining, based on the debug command, a core of the one or more cores associated with the debug command; and determining a routing node connected with the core in the one or more routing nodes according to the core.

As a possible implementation manner, the first conversion module is further configured to: receiving the debug command and/or the trace data sent by the first routing node; judging whether the debug command and/or the trace data meet the requirements; and returning a response message corresponding to the debugging command and/or the tracking data according to the judging result.

In a second aspect, a debug method is provided, the method being applied to a processor, the processor comprising: one or more cores; a first debug port for receiving and/or sending debug commands for on-chip debugging of the one or more cores; the second debugging port is used for sending tracking data; a first data channel for transmitting the debug command and the trace data, the first data channel including one or more routing nodes, the first data channel being connected to the one or more cores, the first debug port, the second debug port by the one or more routing nodes; the method comprises the following steps: on-chip debugging of the one or more cores is performed based on the debug command and/or the trace data.

As a possible implementation manner, the processor further includes a first conversion module, where the first conversion module is connected to a first routing node of the one or more routing nodes, and the first conversion module is connected to the first debug port, and the method includes: and converting the data format between the first debugging port and the first routing node through the first conversion module.

As a possible implementation manner, the first conversion module is connected to the second debug port, and the method includes: and converting the data format supported by the first routing node into the data format supported by the second debugging port through the first conversion module.

As one possible implementation, the processor includes a second conversion module, the second conversion module being connected to one of the one or more cores, and the second conversion module being connected to a second routing node, the method comprising: and converting the data format between the core and the second routing node through the second conversion module.

As a possible implementation manner, the method further includes: receiving the debug command sent by the second routing node; judging whether the debugging command meets the requirement or not; and returning a response message corresponding to the debugging command according to the judging result.

As a possible implementation manner, the method further includes: receiving the debug command through a first debug port; determining, based on the debug command, a core of the one or more cores associated with the debug command; and determining a routing node connected with the core in the one or more routing nodes according to the core.

As a possible implementation manner, the method further includes: receiving the debug command and/or the trace data sent by the first routing node; judging whether the debug command and/or the trace data meet the requirements; and returning a response message corresponding to the debugging command and/or the tracking data according to the judging result.

In a third aspect, a computing device is provided, the computing device comprising a processor as described in the first aspect or any one of the possible implementations of the first aspect.

In a fourth aspect, a chip is provided, the chip comprising a processor as described in the first aspect or any one of the possible implementation manners of the first aspect.

In a fifth aspect, a computer readable storage medium is provided, on which code for performing the method according to the second aspect or any one of the possible implementations of the second aspect is stored.

The embodiment of the application is beneficial to reducing the number of buses used for on-chip debugging in a processor by adopting the same data channel (namely the first data channel) to transmit the debugging command and the trace data. In addition, the data channel comprises a routing node, and the forwarding mechanism of the routing node can be used for reducing difficulty and cost of top-level connection and physical implementation of a debugging system in a processor while guaranteeing data accuracy.

Drawings

FIG. 1 is a logic diagram of an on-chip debug system.

FIG. 2 is a topology diagram of one physical implementation of the debug system of FIG. 1.

Fig. 3 is a schematic structural diagram of a processor according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of another processor according to an embodiment of the present application.

Fig. 5 is a schematic diagram showing a connection relationship of the first conversion module in fig. 4.

Fig. 6 is a schematic diagram showing a connection relationship of the second conversion module in fig. 4.

Fig. 7 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Fig. 8 is a flow chart of a debugging method according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.

The debugging method of the processor can comprise two major categories of software debugging and hardware debugging. The software debugging method can realize the monitoring and control of the processor to be debugged, such as the checking of the value of a register and the setting of a breakpoint, through the system call by running the software on an operating system. Methods of debugging hardware typically require adding components for debugging to the processor to enable monitoring and control of the processor to be debugged.

As one implementation, the hardware debug method may configure and access registers through debug commands to enable monitoring and control of the processor. For example, the hardware debugging method can realize control of the processor by debugging command configuration registers. For another example, the hardware debug method may read the value in the register by a debug command and determine the state of the processor based on the value in the register to enable monitoring of the processor.

As another implementation mode, the hardware debugging method can also acquire the running state of the processor by tracking data, so that the monitoring of the processor is realized. For example, a hardware debug method may obtain trace data of a processor core (core) to determine the operating state of a processor. The trace data may be the behavior of some or all of the high-speed bus nodes acquired based on bus monitoring technology.

To transmit the debug commands and trace data described above, a debug component in the processor may include a debug interface, such as a joint test workgroup (joint test action group, JTAG) interface or a serial line debug (serial wire debug, SWD) interface. JTAG is an International Standard test protocol (IEEE 1149.1 compliant) that is primarily used for on-chip testing. SWD is another debug interface proposed by ARM corporation, and fewer signals can be used relative to JTAG interface. For example, the processor may receive debug commands through the debug interface, and may also send register values through the debug interface. As another example, the processor may send trace data through the debug interface.

When the debugging interface is communicated with the processor, the debugging interface can be connected with different modules according to different functions. For example, the debug interface may be electrically connected to a debug access port (debug access port, DAP) to enable transmission of debug commands. As another example, the debug interface may be electrically connected to a trace port interface unit (trace port interface unit, TPIU) to enable the transfer of trace data.

One commonly used on-chip debug system is CoreSight, coreSight, which is an on-chip debug system based on an ARM architecture, and can realize two functions of debug and trace. debug is the aforementioned debug command-based debug method.

The following describes a CoreSight on-chip debug system using a multi-core processor as an example. FIG. 1 is a logic diagram of an on-chip debug system.

The processor to be debugged may include one or more cores, such as the processor shown in FIG. 1 includes cores 0 through core n+1 (core 0 through core n) for a total of n+1 cores.

Referring to FIG. 1, the on-chip bus may include a variety of buses that are typically used to transmit debug commands and trace data. For example, an APB bus may be employed to transmit debug commands, such as transmitting configuration information received from debug port 1 (DAP) to the relevant registers in the core, and transmitting the value of phase Guan Jicun to the debug port over the bus. The transmission path of the debug command may be as shown by the solid line in fig. 1. For another example, the ATB bus may be used to transfer trace data, such as trace data of a core run to debug port 2 (TPIU). Debug port 2 may transmit trace data to pins of the processor, or input/output (I/O) ports of the processor, the trace data transmission path may be as shown by the dashed lines in fig. 1.

Since debug systems often differ from the data format of the on-chip bus, preprocessing such as format conversion may be performed on debug commands and/or trace data. For example, the DAP may interconvert debug commands into JTAG or SWD bus protocol format and APB bus format. For another example, the TPIU can compress and package the trace data in the ATB bus protocol format and output the trace data to the outside of the chip through the on-chip pins, so that a debugger can record and analyze the running condition of the chip conveniently.

Transmitting debug commands and trace data over different buses may result in an increase in the number of buses. As the number of processor cores increases, the number of buses required increases. As such, this may increase the cost and implementation of the processor.

In actual use, the processor is typically physically designed based on the logic of the debug system. FIG. 2 shows a topology diagram of one physical implementation of the debug system of FIG. 1.

In the physical design, for convenience in realization and division, each module is often integrated and analyzed according to functions, frequencies and physical placement positions. For example, referring to FIG. 2, the less frequent DAP, TPIU may be combined with PAD (PAD) correlations to one module, which may be referred to as physical design 0 (physical design 0); the frequency of the cores is often relatively high, so that the cores are independently integrated into a module, such as physical design 1 (physical design 1) to physical design n+1 (physical design n +1).

Therefore, referring to fig. 2, in the physical implementation process of the processor, multiple buses, such as APB 0-APB n, are required between the physical design 0 and each core (i.e. physical design 1-physical design n+1) to realize transmission of the debug command; multiple buses, such as ATB 0-ATB n, are required between physical design 0 and each core (i.e., physical design 1-physical design n+1) to achieve the transfer of trace data.

With the greatly increased demands on the performance, the main frequency and the number of cores of the processor, the number of APB and ATB buses can be increased in multiple, and further the difficulty and the cost of top-level connection and physical implementation can be greatly increased.

On the one hand, when the number of buses increases greatly, a large amount of chip area may be required for wiring, thereby increasing the processor cost. In practical use, the space between buses can be reduced to save the chip area, but in this way, the reliability of the data may be affected, other measures need to be taken to ensure the reliability of the data, and the realization cost is increased.

On the other hand, as the number of cores increases, the number of ports on the bus also increases greatly. Taking the example of 8 processor cores in the processor, the data bit width of the APB bus for configuring each processor core is 32 bits, the address bit width is 12 bits, and the data bit width of the ATB bus for transmitting trace data to the physical design 0 module is 32 bits, the APB bus number of the physical design 0 is approximately (32×2+12×8=608 ports, and the ATB bus to the physical design 0 module is approximately 32×8=256 ports).

In yet another aspect, as the number of cores increases, the physical design module where the DAP and TPIU are located is farther from the physical design module where a portion of the cores are located in the physical implementation topology of the processor. For example, in FIG. 2, physical design 0 is farther from physical design n, the accuracy of the data transferred between physical design 0 and physical design n may be affected, and there may be a clock offset. As the width and spacing of the interconnect lines continue to decrease, the line-to-line coupling capacitance increases accordingly, and the long global parallel bus may cause greater crosstalk noise, thereby affecting signal integrity and signal transmission accuracy. At the same time, the delay on the interconnect will be a major factor affecting the signal delay, and the delay on the global interconnect of the bus structure will be greater than one clock cycle, making the clock skew difficult to manage. A large number of registers may be inserted in the bus between physical design 0 and physical design n to solve the above problem. However, as such, the implementation cost of the processor on-chip debug system is greatly increased, and risks and uncontrollability may be increased.

To solve the above-mentioned problems, embodiments of the present application provide a processor in which an integrated on-chip debug system transmits debug commands and trace data through the same data channel (i.e. a first data channel), which helps to reduce the number of buses used for on-chip debugging in the processor. In addition, the data channel comprises a routing node, and the forwarding mechanism of the routing node can be used for reducing difficulty and cost of top-level connection and physical implementation of a debugging system in a processor while guaranteeing data accuracy.

Fig. 3 is a schematic structural diagram of a processor according to an embodiment of the present application. One or more cores 310, a first debug port 320, a second debug port 330, and a first data channel 340 may be included in processor 300. The on-chip debug system in processor 300 may include a first debug port 320, a second debug port 330, and a first data channel 340. The first debug port 320, the second debug port 330, and the first data channel 340 may also be referred to as on-chip debug components of the processor 300.

Computations, accept/store commands, process data, etc. in processor 300 may be performed by one or more cores 310. Each of the one or more cores 310 may operate alone or in combination with a plurality of cores.

An on-chip debug system may be included in processor 300 to facilitate debugging of the processor.

As one implementation, a first debug port 320 may be included in processor 300, and first debug port 320 may be used to receive and/or transmit the debug commands described previously, which may be used to debug one or more cores on-chip. For example, the control of one or more cores is provided by a debug command to configure a register component, or the monitoring of the operating state of one or more cores is provided by a debug command to read a value in a register. Wherein the value of the register is associated with the operating state of the core. As one example, the first debug port may be a DAP.

As another implementation, a second debug port 330 may be included in processor 300, and second debug port 330 may be used to send trace data. For example, trace data of the core may be transferred to the second debug port 330 to enable monitoring of the core's operation and status. As one example, the second debug port 330 may be a TPIU.

As previously described, if cores in a processor are to be debugged, one or more cores 310 need to be monitored and controlled, and thus one or more cores may be connected to a first debug port and one or more cores may also be connected to a second debug port.

As one implementation, the processor 300 may include a first data channel 340, where the first data channel 340 may be coupled to some or all of the one or more cores 310. The first data channel 340 may be used to send trace data or register values for one or more cores 310, as well as to receive debug commands for on-chip debugging of the cores. The core connected to the first data channel 340 may implement communication with the debug interface through the first data channel 340, and the core not directly connected to the first data channel 340 may be indirectly connected to the first data channel 340 through other manners. For example, a core that is not directly connected to the first data channel 340 may implement an indirect connection to the first data channel 340 through a core that is directly connected to the first data channel 340.

The first data channel 340 may be used to transmit the debug command as well as the trace data. To enable transmission of debug commands, first data channel 340 may be connected to one or more cores 310 and first debug port 320. To enable the transfer of trace data, a first data channel 340 may be connected to one or more cores 310 and a second debug port 330. For example, the first data channel 340 may be a ring-shaped data channel on which one or more cores 310, first debug port 320, and second debug port 330 may be located. As another example, the first data channel 340 may be a mesh data channel, and the one or more cores 310, the first debug port 320, and the second debug port 330 may be located on the mesh data channel, such as at the intersection of the mesh data channel.

The embodiment of the application is beneficial to reducing the number of buses used for on-chip debugging in the processor by adopting the first data channel to transmit the debugging command and the tracking data, thereby reducing the cost of the processor and the physical realization cost.

The first data path 340 may include one or more routing nodes that may forward data transmitted in the first data path. In this way, the problem of data correctness caused by remote transmission through the bus can be avoided.

One or more routing nodes may be coupled to one or more cores 310, first debug port 320, second debug port 330. For example, each of the one or more cores 310 is connected to a routing node. As an example, each core may be connected to a routing node, respectively. As another example, each routing node may be coupled to multiple cores, which may help reduce the length or size of the first data channel to reduce the cost of the processor.

The first debug port 320 may be connected to a first routing node of the one or more routing nodes. The first routing node may or may not be connected to the core at the same time.

The second debug port 330 may be connected to a first routing node of the one or more routing nodes, or may be connected to other routing nodes of the one or more routing nodes other than the first routing node. The first debug port 320 and the second debug port 330 are connected to the same routing node, which can reduce complexity of data transmission. The routing node connected to the second debug port 330 may or may not be connected to the core at the same time.

As mentioned above, the first data channel 340 may be a ring data channel or a mesh data channel. One or more routing nodes may be located on the first data path 340 as data receiving and/or transmitting nodes of the first data path 340. For example, one or more routing nodes may be located on the first data path 340 in a ring shape, such as evenly distributed across the ring-shaped data path. As another example, one or more routing nodes may be located on a mesh data channel, such as at intersections or vertices of a mesh in a mesh data channel.

Based on the first data channel 340 including one or more routing nodes, the problem of data transmission accuracy caused by a long distance in the process of transmitting a debug command or tracking data by a bus is solved. For a data transmission node with a far distance, such as a core, a debugging command or tracking data can be forwarded through one or more routing nodes instead of being directly transmitted to the data transmission node, so that the accuracy and reliability of the data can be improved. The distance referred to herein refers to the distance of the node from the debug interface.

Taking the data transmission between the target data transmission node and the debug interface as an example through a routing node forwarding implementation, the processor provided by the embodiment of the application can perform the forwarding transmission through a routing node instead of the direct point-to-point transmission when the data transmission is performed between the debug interface and the target data transmission node, so that the distance of single transmission can be reduced, thereby being beneficial to improving the accuracy of the data transmission and reducing the cost of physical implementation of the processor.

As the number of processor cores increases, the data traffic between the units of the processor increases rapidly, and thus, more and more processors employ Network On Chip (NOC) architecture. While network-on-chip is a concept employing parallel distributed computers and conventional computer networks, switching nodes, i.e. routers, are introduced between the different processor cores, rather than bus structures. This has the advantage of avoiding communication collision of the shared bus and improving chip communication efficiency and communication traffic.

Based on the above, the processor provided by the embodiment of the application can realize communication between the core and the debugging interface and transfer of tracking data by means of a bus routing mode of the network on chip. That is, a first data channel in the processor may be connected to the first debug port, the second debug port, and one or more cores in a network-on-chip manner to enable data transfer between the cores and the debug interfaces in the processor. In this way, the first data channel may have good scalability and reliable data transmission capability.

In the related art, the core transmits the debug command in the APB bus protocol format, the transmission trace data in the ATB bus protocol format, and the debug interface may be in a JTAG or SWD bus protocol format, for example. In order to reduce the implementation complexity of the processor provided by the embodiment of the application, the original data formats of the core and the debugging interface are generally reserved.

However, in one aspect, the data format of the first data channel in the processor provided by the embodiment of the present application may be, for example, a network-on-chip channel bus protocol format, which is different from the data format of the debug interface in the related art.

Thus, to enable transmission of debug commands, the processor may further comprise a first conversion module for enabling data format conversion of debug commands. For example, the first translation module is coupled to a first routing node of the one or more routing nodes, and the first translation module is coupled to the first debug port, that is, the first debug port may be coupled to the first routing node through the first translation module. The first conversion module may be configured to convert a data format between the first debug port and the first routing node. For example, the first conversion module may convert the data format supported by the first debug port into the data format supported by the first routing node, or may convert the data format supported by the first routing node into the data format supported by the first debug port.

In some implementations, the first debug port and the second debug port may each be connected to the same routing node. Based on this, the first conversion module may be further connected to the second debug port, where the first conversion module may be further configured to convert a data format supported by the first routing node into a data format supported by the second debug port, so as to implement transmission of trace data.

On the other hand, the data format of the first data channel in the processor provided by the embodiment of the application is different from the data format of the core in the related art.

Thus, the processor may further comprise a second conversion module. For example, a second conversion module may be coupled to one of the one or more cores and coupled to the second routing node, the second conversion module may be configured to convert a data format between the core and the second routing node.

One or more second conversion modules may be included in the processor. For example, the number of second conversion modules may be the same as the number of one or more cores, that is, each second conversion module corresponds to each core.

When a debug command or trace data is transmitted in the first data channel, a target module, such as a first debug port, a second debug port, one or more cores, that receives the debug command or trace data needs to be determined for data transmission. Because the first debug port, the second debug port and one or more cores are all connected with the routing node, as an implementation manner, data transmission can be performed based on the target routing node corresponding to the target module. For example, each of the one or more routing nodes may have a different identity, and data may be transmitted based on the identity of the destination routing node to which the destination module is connected. The second conversion modules are in one-to-one correspondence with the cores, and the first conversion modules are in correspondence with the first debugging ports and the second debugging ports, so that as another implementation mode, data transmission can be performed based on the identifiers of the first conversion modules and the second conversion modules connected with the target modules.

Typically, the debug command may include information of the core corresponding to the debug command, such as an address of the core. A possible method of determining a target routing node comprises: firstly, a debugging command can be received through a first debugging port; second, based on the debug command, such as based on the address of the core contained in the debug command, a core of the one or more cores associated with the debug command, i.e. the target module, may be determined; finally, from the core, a routing node of the one or more routing nodes that is connected to the core, i.e., a target routing node, may be determined. Wherein determining the target routing node may refer to determining an identity of the target routing node. The method of determining a target routing node described above may be performed by a first translation module.

Typically, trace information is sent by the core to the second debug port. Because the position of the second debug port is fixed, the target modules are the second debug port in the process of transmitting the tracking information, and the identification of the corresponding target routing nodes is also fixed.

Similarly to the transmission of the trace information, when the value of the register corresponding to the debug command is transmitted from the core to the first debug port, the target modules are all the first debug ports, and the identification of the corresponding target routing nodes is also fixed.

To ensure reliability of data transmission, when a target module receives a debug command or trace data, a response message may be sent to the module (which may also be referred to as a source module) that sent the debug command or trace data. If the target module is the core, a response message may be sent by the second conversion module to the source module. If the target module is the first debug port or the second debug port, a response message may be sent by the first translation module to the source module.

As one implementation, the response message may include a transmission completion response message, and a transmission error response message. It may be determined whether the debug command or trace data is satisfactory before sending the response message. For example, if the debug command or trace data meets the requirements, a transmission completion response message corresponding to the debug command or trace data is returned. For another example, if the debug command or the trace data does not meet the requirements, a transmission error response message corresponding to the debug command or the trace data is returned. In addition, if the debug command or trace data is not satisfactory, the debug command or trace data may be discarded while a transmission error response message is returned.

Whether the debug command or the trace data meets the requirements or not can be judged through various conditions. For example, the receiving module may determine whether the target module corresponding identifier of the debug command or trace data is consistent with its own identifier. As another example, it may be determined whether the identity of the module that sent the debug command or trace data is the identity of an assigned module, such as the second translation module. For example, it may be determined whether the bus address of the core to be debugged corresponds to the identification of the target module.

As an implementation manner, in the process of receiving the debug command by the processor, determining whether the debug command meets the requirement and returning a response message may be performed by the second conversion module. For example, the second conversion module is configured to: receiving a debugging command sent by a second routing node; judging whether the debugging command meets the requirement; and returning a response message corresponding to the debugging command according to the judging result.

As another implementation manner, in the process that the debug interface receives the debug command (such as the value of the register) and the trace data sent by the processor, determining whether the debug command or the trace data meets the requirement and returning a response message can be executed by the first conversion module. For example, the first conversion module is to: receiving a debugging command and/or tracking data sent by a first routing node; judging whether the debug command and/or the trace data meet the requirements; and returning a response message corresponding to the debugging command and/or the tracking data according to the judging result.

Fig. 4 is a schematic structural diagram of another processor according to an embodiment of the present application. The processor shown in fig. 4 may include 8 cores 410,8 second conversion modules 420, a first conversion module 430, a first debug port 440, a second debug port 450, 4 routing nodes (routing node 0-routing node 3), and a first data path 460 including the 4 routing nodes.

Wherein each routing node is connected to two cores. A second conversion module 420 may be included between the core and the routing node. The first debug port 440 and the second debug port 450 may be connected to the same routing node (e.g. routing node 0 in fig. 4). A first translation module 430 may be included between a first debug port 440 (i.e., DAP), a second debug port 450 (i.e., TPIU), and routing node 0.

Fig. 5 is a schematic diagram showing a connection relationship of the first conversion module in fig. 4. The processor provided by the embodiment of the application can be added with a first conversion module before the DAP component and the TPIU component in the on-chip debugging system, and is used for bridging communication between the routing node and the DAP component and between the routing node and the TPIU component. The first conversion module may also be referred to as DTN (debug to NOC). The DTN may be a component responsible for transmitting DAP messages to and receiving messages from the first data channel.

Fig. 6 is a schematic diagram showing a connection relationship of the second conversion module in fig. 4. The processor provided by the embodiment of the application adds a second conversion module for each core component to be used for bridging the communication between the routing node and the core. The second conversion module may also be referred to as CTN (coreto NOC). The CTN may be responsible for receiving and transmitting messages from routing nodes in the first data channel. For example, the CTN may receive trace information of the core, a debug command, or may send a debug command to the core.

It should be noted that, when the first data channel transmits data, any routing algorithm may be used, which is not limited in the present application.

The processor provided by the embodiment of the application can change the structure of the on-chip debugging system from a simple point-to-point (bus) structure to a network structure, is beneficial to optimizing the debugAPB access path from the DAP to the core and the data transmission path from the ATB to the TPIU, and reduces the connection of a large number of APB and ATB buses at the top layer and the number of module ports. Meanwhile, the processor provided by the embodiment of the application is beneficial to solving the problem of difficult realization caused by too far physical distance, thereby being beneficial to reducing the difficulty, cost and uncontrollable risk of physical synthesis. Finally, the processor provided by the embodiment of the application is convenient for the design and iteration of the system.

The transmission flow of the debug command and the trace data provided by the embodiment of the application will be described in detail below by taking the first data channel as an on-chip network channel as an example.

A transmission flow of a debug command may include steps 1 to 5.

In step 1, when there is a debug command (e.g. a debug command received through a JTAG interface) to communicate with the debug logic of the core, the DTN component may first convert the APB transaction (which may also be referred to as an APB read/write request) of the DAP component into a NOC bus protocol format; then determining which core the transaction is to be sent to according to the target address included in the APB transaction, and determining the route Identification (ID) of the target based on the core; finally, the DAP component transmits the converted transactions in the NOC bus protocol format to the NOC channel.

In step 2, a routing node connected to the DAP component may route the debug command transaction, e.g. to a corresponding CTN component interface, according to a target ID included in the debug command transaction.

In step 3, the CTN component may receive a debug command transaction from the routing node and check if the transaction is satisfactory. If so, the debug transaction may be transmitted to the core and a transaction complete response may be returned; if not, the debug transaction may be discarded and an error response returned.

In step 4, the routing node returns the response in step 3 to the DTN component, which checks the response and responds to the DAP component that the transaction is complete.

In step 5, the DAP makes the next transmission of the debug transaction.

A transmission flow of trace data may include steps 6 to 10.

In step 6, when the core has trace transactions to send, the CTN converts the ATB transaction to a bus protocol format of the NOC channel, with the routing ID fixed to the DTN node ID.

In step 7, the routing node performs transaction routing according to the ID, for example, the routing of the transaction to the node where the DTN is located.

In step 8, the DTN receives the transaction from the routing node and checks the transaction to determine whether the transaction meets the requirements. If so, the corresponding ATB transaction for the transaction translation may be sent to the component TPIU and a routing node transaction complete response is replied. If not, the transaction is discarded and a routing node transaction error response is replied.

In step 9, the CTN receives the response in step 3 and issues a response to the core based on the response.

In step 10, the core continues to send trace transactions.

Still with 8 processor cores in the aforementioned processor, the APB bus for configuring each processor core has a write/read data bit width of 32 bits and an address bit width of 12 bits, and each core transmits the data bit width 32 bits of the ATB bus of the trace data to the physical design 0 module, for example, the APB bus number of physical design 0 is approximately (32×2+12) ×8=608 ports, and the ATB bus to the physical design 0 module is approximately 32×8=256 ports.

The paths that need to be at great expense to ensure the transmission correctness are: physical design 0 transmits the bus to routing node 3. When the processor provided by the embodiment of the application is adopted, ATB and ATB buses of a physical design 0 module can be removed, and meanwhile, the paths which need to be greatly spent to ensure the transmission accuracy can be optimized by only adding a group of channels (first data channels) which are communicated with the routing nodes.

The more processor cores, the more significant the benefits of the processor provided by embodiments of the present application. For example, when the number of processor cores reaches more than 32, the benefit of the processor structure provided by the embodiment of the application is particularly remarkable.

Fig. 7 is a schematic structural diagram of a computing device according to an embodiment of the present application. The computing device 700 shown in fig. 7 includes a processor 710, and the processor 710 may be any of the processors mentioned above.

An embodiment of the apparatus of the present application is described above in detail in connection with fig. 1 to 7, and an embodiment of the method of the present application is described below in detail in connection with fig. 8. It is to be understood that the description of the method embodiments corresponds to the description of the device embodiments, and that parts not described in detail can therefore be seen in the preceding device embodiments.

Fig. 8 is a flow chart of a debugging method according to an embodiment of the present application. The debugging method is applied to a processor, and the processor comprises: one or more cores; a first debug port for receiving and/or sending debug commands for on-chip debugging of the one or more cores; the second debugging port is used for sending tracking data; and the first data channel is used for transmitting the debugging command and the tracking data, comprises one or more routing nodes, and is connected with the one or more cores, the first debugging port and the second debugging port through the one or more routing nodes.

Referring to fig. 8, the method 800 may include step S810.

In step S810, on-chip debugging is performed on one or more cores based on the debug command and/or trace data.

It should be understood that in embodiments of the present application, "B corresponding to a" means that B is associated with a, from which B may be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be read by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disk (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A processor, comprising:

one or more cores;

a first debug port for receiving and/or sending debug commands for on-chip debugging of the one or more cores;

the second debugging port is used for sending tracking data;

the first data channel is used for transmitting the debugging command and the tracking data, and comprises one or more routing nodes, and the first data channel is connected with the one or more cores, the first debugging port and the second debugging port through the one or more routing nodes, wherein the one or more routing nodes are used for forwarding the debugging command and the tracking data transmitted by the first data channel.

2. The processor of claim 1, wherein the processor further comprises:

the first conversion module is connected with a first routing node in the one or more routing nodes, and is connected with the first debugging port, and the first conversion module is used for converting a data format between the first debugging port and the first routing node.

3. The processor of claim 2, wherein the first translation module is coupled to the second debug port, the first translation module further configured to:

and converting the data format supported by the first routing node into the data format supported by the second debugging port.

4. A processor according to claim 3, wherein the processor further comprises:

and the second conversion module is connected with one core of the one or more cores, is connected with a second routing node and is used for converting the data format between the core and the second routing node.

5. The processor of claim 4, wherein the second conversion module is further configured to:

Receiving the debug command sent by the second routing node;

judging whether the debugging command meets the requirement or not;

and returning a response message corresponding to the debugging command according to the judging result.

6. A processor according to claim 3, wherein the first conversion module is further configured to:

receiving the debug command through a first debug port;

determining, based on the debug command, a core of the one or more cores associated with the debug command;

and determining a routing node connected with the core in the one or more routing nodes according to the core.

7. A processor according to claim 3, wherein the first conversion module is further configured to:

receiving the debug command and/or the trace data sent by the first routing node;

judging whether the debug command and/or the trace data meet the requirements;

and returning a response message corresponding to the debugging command and/or the tracking data according to the judging result.

8. A method of debugging, the method being applied to a processor, the processor comprising:

one or more cores;

The second debugging port is used for sending tracking data;

a first data channel for transmitting the debug command and the trace data, the first data channel including one or more routing nodes, the first data channel being connected to the one or more cores, the first debug port, the second debug port by the one or more routing nodes;

the method comprises the following steps:

on-chip debugging of the one or more cores is performed based on the debug command and/or the trace data.

9. The method of claim 8, wherein the processor further comprises a first translation module coupled to a first routing node of the one or more routing nodes and coupled to the first debug port, the method comprising:

and converting the data format between the first debugging port and the first routing node through the first conversion module.

10. The method of claim 9, wherein the first translation module is coupled to the second debug port, the method comprising:

and converting the data format supported by the first routing node into the data format supported by the second debugging port through the first conversion module.

11. The method of claim 10, wherein the processor comprises a second translation module coupled to one of the one or more cores and coupled to a second routing node, the method comprising:

and converting the data format between the core and the second routing node through the second conversion module.

12. The method of claim 11, wherein the method further comprises:

receiving the debug command sent by the second routing node;

judging whether the debugging command meets the requirement or not;

13. The method according to claim 10, wherein the method further comprises:

receiving the debug command through a first debug port;

14. The method according to claim 10, wherein the method further comprises:

judging whether the debug command and/or the trace data meet the requirements;

15. A computing device comprising the processor of any of claims 1-7.

16. A computer readable storage medium having stored thereon code for performing the method of any of claims 8-14.