CN109194430B - SRIO-based C6678 distributed system time synchronization method and system - Google Patents
SRIO-based C6678 distributed system time synchronization method and system Download PDFInfo
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- CN109194430B CN109194430B CN201810876929.9A CN201810876929A CN109194430B CN 109194430 B CN109194430 B CN 109194430B CN 201810876929 A CN201810876929 A CN 201810876929A CN 109194430 B CN109194430 B CN 109194430B
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- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
Abstract
The invention provides a time synchronization method and a time synchronization system for a C6678 distributed system based on SRIO, and belongs to the technical field of information processing. The invention carries on the time synchronization to each C6678 processor by controlling SRIO, the synchronization method includes launching the time synchronization request by any C6678 processor at first, and carry on SRIO enumerations to the system, discern all C6678 processors under the multistage SRIO switched network, and distribute the broadcast ID for it; and then, performing broadcast interruption on all the C6678 processors including the C6678 processor initiating the time synchronization request, sending the calculated time difference reaching each stage of the SRIO switching network to each C6678 processor, and finally unifying system time according to the time of receiving the broadcast interruption and the time difference by each C6678 processor, wherein the system comprises modules for realizing the functions. The invention is based on SRIO broadcast interruption, has high transmission speed, can not influence the aspects of the program time sequence and the like of the existing system software, and has higher system time synchronization precision.
Description
Technical Field
The invention relates to the technical field of information processing, in particular to a method and a system for synchronizing the time of a C6678 distributed system based on SRIO.
Background
RapidIO is an interconnection communication technology mainly applied to a high-performance embedded system, data transmission is carried out in an exchange interconnection mode, namely a traditional single point-to-point connection mode is not adopted, an exchange mechanism is added, and flexibility of the system is enhanced. Serial RapidIO (SRIO) can adopt modes of 1X, 4X and the like, and the transmission rate can reach dozens of gigabits. RapidIO technology has a complete consideration for routing, switching, and fault tolerance and error correction, and is therefore being applied to more and more high-performance reliable data transmission systems.
TMS320C6678 (abbreviated as C6678) of Texas Instruments (abbreviated as TI) of America is a multi-core Digital Signal Processor (DSP) chip widely used in the field of embedded high-performance computing in China at present. TI provides a plurality of C6678 loading modes, and software can be loaded through JTAG (test interface for debug), Ethernet (ETH for short), PCIe (PCI Express bus), SRIO (high speed serial bus), SPI (serial peripheral interface), I2C (two-wire serial bus), and other interfaces. The TI company integrates an RBL (ROM Boot Loader, built-in load core) in a C6678, and may selectively enter a corresponding load mode according to an external input, receive and execute an application software code.
In a distributed real-time system, each node processor has an independent hardware clock, two counting registers TSCH and TSCL in C6678 have the same frequency with a CPU and represent a 64-bit number together, the CPU runs a cycle, and the register is added with 1 to record the time of DSP operation or event occurrence. However, the phenomenon that the loading time of each DSP is inconsistent commonly exists in a distributed system adopting loading modes such as ETH, PCIe, JTAG, and the like, which may cause that the time of each DSP cannot be synchronized, and bring difficulties to data observation and debugging. For example: two DSPs respond to a certain interrupt at the same time, and the interrupt does not appear to respond at the same time due to inconsistent loading time and inconsistent recorded DSP time. It is therefore desirable to have a globally acknowledged system time for these distributed independent processors.
Disclosure of Invention
Aiming at the problems, the invention provides a SRIO-based C6678 distributed system time synchronization method, so that each piece of C6678 has a globally acknowledged system time under the condition that the subsystem time cannot be synchronized due to inconsistent loading time.
The invention firstly provides a SRIO-based C6678 distributed system time synchronization method, which carries out time synchronization on each C6678 processor through SRIO and mainly comprises the following steps:
step one, any C6678 processor initiates a time synchronization request;
step two, the C6678 processor initiating the time synchronization request carries out SRIO enumeration on the system, identifies all the C6678 processors under the multi-stage SRIO switching network, and distributes broadcast IDs for the C6678 processors;
step three, the C6678 processor initiating the time synchronization request carries out broadcast interruption to all the C6678 processors including the C6678 processor, and each C6678 processor records the time of receiving the interruption;
step four, the C6678 processor initiating the time synchronization request calculates the time difference of reaching each stage of SRIO switching network, and sends to each C6678 processor;
and step five, unifying the system time by each C6678 processor according to the time recorded in the step three and the time difference received in the step four.
Preferably, in the second step, performing SRIO enumeration on the system includes determining a shortest path from the C6678 processor initiating the time synchronization request to each stage of SRIO switch according to a breadth-first search principle.
Preferably, in the fifth step, unifying the system time includes:
and subtracting the time difference received in the step four from the time recorded in the step three to obtain the common system time as the current reference time 0.
In another aspect, the present invention provides a SRIO-based time synchronization system for a C6678 distributed system, where any of the C6678 processors includes:
the enumeration module is used for performing SRIO enumeration on the system, identifying all C6678 processors under a multi-stage SRIO switching network, and distributing broadcast IDs for the processors;
the error processing module is used for calculating the time difference of the C6678 processor which initiates the time synchronization request reaching each stage of the SRIO switching network;
a sending module, configured to send a broadcast interrupt to all C6678 processors, and send the time difference calculated by the error processing module to each C6678 processor;
a receiving module for receiving the broadcast interruption and receiving the time difference;
and the synchronization module is used for unifying the system time according to the time of receiving the broadcast interruption and the time difference.
Preferably, the enumeration module includes a search unit, and the search unit determines the shortest path from the C6678 processor initiating the time synchronization request to each stage of SRIO switch according to a breadth-first search principle.
The invention has the advantages that:
(1) the method has the advantages of light weight, low system overhead, SRIO broadcast interruption based, high transmission speed and no influence on the aspects of the existing system software program time sequence and the like.
(2) The method is suitable for a multi-DSP distributed system under a multi-stage SRIO switching complex network.
(3) And the system level time synchronization is convenient for software developers to observe and debug the system level software program time sequence.
The invention can be applied to embedded information processing systems using TMS320C6678DSP, such as aviation, aerospace, ships, communication, software radio, artificial intelligence and other fields.
Drawings
Fig. 1 is a flowchart of a preferred embodiment of a SRIO-based C6678 distributed system time synchronization method according to the present invention.
Fig. 2 is a schematic diagram of a system architecture of a preferred embodiment of the SRIO-based C6678 distributed system time synchronization system according to the present invention.
Detailed Description
In order to make the implementation objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in more detail below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are only some, but not all embodiments of the invention. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The SRIO interconnection system structure is divided into three layers, namely a logic layer, a transmission layer and a physical layer. The logic layer specification is positioned at the highest layer, defines all operation protocols and packet formats and provides necessary information for initiating and completing transactions by an end device; the transport layer specification is in the middle layer of the protocol layer, and the layer defines the address space, the addressing mechanism and the routing information for packet switching of the SRIO; the physical layer specification is at the bottom level and includes details of the device level interface such as packet transport mechanisms, flow control, electrical parameters, and low level error management. Based on the reasons, the invention synchronizes the system time through the SRIO broadcast interruption, has high transmission speed and does not influence the aspects of the program time sequence and the like of the existing system software.
It should be noted that the C6678 processor according to the present invention is one of the most widely used multi-core Digital Signal Processor (DSP) chips, and those skilled in the art will understand that the following description using "DSP" is equivalent to the description of "C6678 processor". The invention carries out time synchronization on the system, and under the general condition, the system can comprise a plurality of board cards, each board card is provided with an SRIO switch, and a plurality of DSP chips are connected through the SRIO switch.
Fig. 1 shows a time synchronization method for a multi-chip C6678 loading system based on SRIO, which specifically comprises the following working processes:
step 1, based on the power-on operation of the SRIO switching network system, each DSP performs initialization work.
And 2, initiating a synchronous request by any terminal DSP in the system.
And 3, initiating a synchronous DSP to perform SRIO enumeration on the system, and distributing the same broadcast ID to all terminal DSP ports.
And 4, initiating the synchronous DSP to send SRIO interruption to all the terminal DSPs.
And 5, recording the system time tISR of receiving the interrupt by each DSP.
Step 6, the DSP (switching level 0) that initiates the time synchronization request calculates the interrupt delay tn from switching level 0 to level n according to the switching level n in which the other DSPs are located (t0 is 0).
And 7, recording the tISR-tn by each DSP, and taking the recorded tISR-tn as the reference time 0 to obtain the common system time.
In this embodiment, the SRIO enumeration method in step 3 is initiated by any DSP in the system, and accesses switches at different levels by using a method for maintaining data packets. In the enumeration process, the system architecture can be regarded as an unweighted graph, the shortest path from the initiating device to each level of switch is determined by adopting a width-first search principle, and broadcast IDs are distributed to the connecting ports (outlets) passing through the switches and the ports of the articulated terminal devices.
Fig. 2 is a structure diagram of a multi-stage SRIO switching system suitable for the method, as shown in the figure, a plurality of SRIO switches are interconnected in the whole system, and a terminal device DSP can be connected to each switch. In this embodiment, the DSP controls SRIO transmission by loading the following modules, which include:
the enumeration module is used for performing SRIO enumeration on the system, identifying all C6678 processors under a multi-stage SRIO switching network, and distributing broadcast IDs for the processors;
the error processing module is used for calculating the time difference of the C6678 processor which initiates the time synchronization request reaching each stage of the SRIO switching network;
a sending module, configured to send a broadcast interrupt to all C6678 processors, and send the time difference calculated by the error processing module to each C6678 processor;
a receiving module for receiving the broadcast interruption and receiving the time difference;
and the synchronization module is used for unifying the system time according to the time of receiving the broadcast interruption and the time difference.
The method is suitable for a complex SRIO switching network system architecture, does not limit the number and interconnection mode of SRIO switches in principle, is particularly suitable for a multi-board card array, is based on SRIO broadcast interruption, has high transmission speed, and does not influence the aspects of the existing system software program time sequence and the like. On the other hand, in the invention, the interrupt delay time tn is slightly different according to the configuration of each switch, the switching interrupt delay difference of each stage is generally in the order of microseconds, and the tISR visually reflects the order of magnitude of the loading time difference and is generally in the order of seconds. The combination of the two makes the system time synchronization more accurate.
Finally, it should be pointed out that: the above examples are only for illustrating the technical solutions of the present invention, and are not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (5)
1. A SRIO-based C6678 distributed system time synchronization method is used for synchronizing the time of a plurality of C6678 processors, and is characterized in that the time synchronization of each C6678 processor is performed through SRIO, and the time synchronization of each C6678 processor through SRIO comprises the following steps:
step one, any C6678 processor initiates a time synchronization request;
step two, the C6678 processor initiating the time synchronization request carries out SRIO enumeration on the system, identifies all the C6678 processors under the multi-stage SRIO switching network, and distributes broadcast IDs for the C6678 processors;
step three, the C6678 processor initiating the time synchronization request carries out broadcast interruption to all the C6678 processors including the C6678 processor, and each C6678 processor records the time of receiving the interruption;
step four, the C6678 processor initiating the time synchronization request calculates the time difference of reaching each stage of SRIO switching network, and sends to each C6678 processor;
and step five, unifying the system time by each C6678 processor according to the time recorded in the step three and the time difference received in the step four.
2. The SRIO-based C6678 distributed system time synchronization method of claim 1, wherein in said step two, performing SRIO enumeration on the system comprises determining a shortest path from the C6678 processor initiating the time synchronization request to the SRIO switches of each stage according to a breadth-first search principle.
3. The SRIO-based C6678 distributed system time synchronization method of claim 1, wherein in step five, unifying system time comprises:
and subtracting the time difference received in the step four from the time recorded in the step three to obtain the common system time as the current reference time 0.
4. A SRIO-based C6678 distributed system time synchronization system is characterized in that any C6678 processor comprises:
the enumeration module is used for performing SRIO enumeration on the system, identifying all C6678 processors under a multi-stage SRIO switching network, and distributing broadcast IDs for the processors;
the error processing module is used for calculating the time difference of the C6678 processor which initiates the time synchronization request reaching each stage of the SRIO switching network;
a sending module, configured to send a broadcast interrupt to all C6678 processors, and send the time difference calculated by the error processing module to each C6678 processor;
a receiving module for receiving the broadcast interruption and receiving the time difference;
and the synchronization module is used for unifying the system time according to the time of receiving the broadcast interruption and the time difference.
5. The SRIO-based C6678 distributed system time synchronization system of claim 4 wherein said enumeration module comprises a search unit, said search unit determining the shortest path from the C6678 processor initiating the time synchronization request to the SRIO switches of each stage according to a breadth-first search principle.
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| CN110830137B (en) * | 2019-10-24 | 2021-06-01 | 广东安朴电力技术有限公司 | Multi-node time synchronization control system based on SRIO and synchronization control method thereof |
| CN110865969B (en) * | 2019-11-05 | 2022-05-31 | 中国人民解放军国防科技大学 | Method and device for supporting inter-processor interrupt communication of extensible processor |
| CN111506156B (en) * | 2020-06-17 | 2020-12-04 | 北京机电工程研究所 | Time service method and system of processor array |
| CN113392065A (en) * | 2021-07-14 | 2021-09-14 | 中科晶锐(苏州)科技有限公司 | Heterogeneous computing system and computing method |
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