CN116431228A

CN116431228A - Method and device for configuring chip address, energy storage device and readable storage medium

Info

Publication number: CN116431228A
Application number: CN202310359351.0A
Authority: CN
Inventors: 王亚雄; 吴东; 陈熙; 王雷
Original assignee: Ecoflow Technology Ltd
Current assignee: Ecoflow Technology Ltd
Priority date: 2023-03-31
Filing date: 2023-03-31
Publication date: 2023-07-14

Abstract

The application is applicable to the technical field of battery management, and provides a method, a device, energy storage equipment and a readable storage medium for configuring a chip address, wherein first data of a target AFE chip are read based on a preset initial address by sequentially waking up all AFE chips; checking the first data to obtain a first checking result of the first data; when the first verification result is that the first verification result is passed, configuring the address of the target AFE chip as a target address corresponding to the target AFE chip; on the premise of not increasing the resource cost of the controller and the production procedure, the communication addresses of the AFE chips can be rapidly configured, the address configuration efficiency under the scene of the AFE chips is improved, and meanwhile, the data of the AFE chips can be accurately and reliably read respectively; has stronger usability and practicability.

Description

Method and device for configuring chip address, energy storage device and readable storage medium

Technical Field

The application belongs to the technical field of battery management, and particularly relates to a method and device for configuring a chip address, energy storage equipment and a computer readable storage medium.

Background

During charge and discharge control of the battery module by the battery management system (Battery Management System, BMS), much data is read from an Analog Front End (AFE) chip. For a general AFE analog front-end chip, the number of channels for data acquisition is limited; for battery modules with a large number of battery strings, one BMS board may use a plurality of AFE chips at the same time.

At present, when data in the AFE chips are read, a plurality of controllers are generally adopted to establish a plurality of communication links with different AFE chips for communication, or corresponding communication addresses are set for the plurality of AFE chips in each energy storage device through upper computer software provided by a manufacturer; however, the former requires more controller resources, and the latter requires an increased production process, resulting in higher implementation costs and low address configuration efficiency.

Disclosure of Invention

The embodiment of the application provides a method, a device, energy storage equipment and a computer readable storage medium for configuring a chip address, which can reduce the implementation cost and improve the address configuration efficiency.

In a first aspect, the present application provides a method for configuring a chip address, applied to a processor, where the processor is connected to a plurality of analog front end AFE chips, the method may include:

Sequentially waking up all AFE chips;

each time an AFE chip is awakened, reading first data of a target AFE chip based on a preset initial address; the target AFE chip is a currently awakened AFE chip;

checking the first data to obtain a first check result of the first data;

and when the first verification result is that the first verification result is passed, configuring the address of the target AFE chip as a target address corresponding to the target AFE chip.

In a possible implementation manner of the first aspect, after the verifying the first data to obtain a first verification result of the first data, the method further includes:

when the first check result is that the first data does not pass, reading the second data of the target AFE chip based on the target address;

checking the second data to obtain a second checking result of the second data;

and when the second check result is passing, determining that the address of the target AFE chip is configured as the target address.

In a possible implementation manner of the first aspect, when the second check result is a pass, the method further includes:

initializing the target AFE chip based on a cell parameter associated with the target AFE chip.

In a possible implementation manner of the first aspect, after the verifying the second data, obtaining a second verification result of the second data, the method further includes:

and when the second checking result is that the power-on abnormality information is not passed, ending the operation of configuring the chip address and reporting the power-on abnormality information.

In a possible implementation manner of the first aspect, after the configuring the address of the target AFE chip to be the target address corresponding to the target AFE chip, the method further includes:

In a possible implementation manner of the first aspect, after the initializing the target AFE chip, the method further includes:

judging whether the wake-up sequence number of the target AFE chip reaches the total number of the AFE chips;

if the wake-up sequence number reaches the total number, ending the operation of configuring the chip address;

and if the wake-up sequence number does not reach the total number, returning to execute the step of waking up the AFE chips in sequence.

In a possible implementation manner of the first aspect, the sequentially waking up each AFE chip includes:

And sending the wake-up instruction to the target AFE chip based on a wake-up pin connected with the target AFE chip.

In a second aspect, an embodiment of the present application provides an apparatus for configuring a chip address, where the apparatus may include:

the wake-up unit is used for sequentially waking up the AFE chips;

the reading unit is used for reading first data of the target AFE chip based on a preset initial address after each AFE chip is awakened; the target AFE chip is a currently awakened AFE chip;

the processing unit is used for checking the first data to obtain a first checking result of the first data;

and the configuration unit is used for configuring the address of the target AFE chip as the target address corresponding to the target AFE chip when the first check result is passed.

In a third aspect, the present application provides an energy storage device, including a battery module, a memory, a processor, and a plurality of analog front end AFE chips, where the plurality of analog front end AFE chips are connected to the battery module; the memory stores a computer program which when executed by the processor implements the method of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium storing a computer program which, when executed by a processor, implements the method of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer program product for causing a terminal device to perform the method of the first aspect described above when the computer program product is run on the terminal device.

It will be appreciated that the advantages of the second to fifth aspects described above may be referred to in the description related to the first aspect, and will not be described here again.

Compared with the related art, the application has the beneficial effects that:

according to the method, each AFE chip is awakened in sequence, and first data of a target AFE chip are read based on a preset initial address every time one AFE chip is awakened; checking the first data to obtain a first checking result of the first data; and when the first verification result is that the first verification result passes, the address of the target AFE chip is configured as the target address corresponding to the target AFE chip.

By the scheme provided by the embodiment of the application, the communication addresses of a plurality of AFE chips can be rapidly configured on the premise of not increasing the resource cost of the controller. Moreover, the scheme provided by the embodiment of the application can be executed by the processor of the energy storage device, so that the energy storage device can automatically execute the scheme after being electrified, corresponding addresses are configured for a plurality of AFE chips in the energy storage device, a worker does not need to configure through upper computer software provided by a manufacturer, production procedures do not need to be increased, address configuration efficiency under a scene of the plurality of AFE chips is improved, and the method has high usability and practicability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an application scenario of a method for configuring a chip address according to an embodiment of the present application;

FIG. 2 is a flow chart of a method for configuring a chip address according to an embodiment of the present application;

FIG. 3 is a flowchart of a second check result for obtaining second data according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart for determining whether the chip serial number reaches the total number according to the embodiment of the present application;

FIG. 5 is a flow chart of a method for configuring a chip address according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an apparatus for configuring a chip address according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of an energy storage device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The battery management system (Battery Management System, BMS) is a management system that monitors the operating state of the battery module and controls the charge and discharge of the battery module. The BMS acquires dynamic data of the battery pack in the working period, communicates with the upper computer, transmits the dynamic data to the upper computer, and the upper computer analyzes the dynamic data and feeds back the running state of the battery.

During the charge and discharge control of the battery module by the battery management system, many data are read from an Analog Front End (AFE) chip. For a general AFE analog front end chip, the number of channels for data acquisition is limited, and currently, the number of voltage acquisition channels of most of the AFE analog front end chips is not more than 16, which cannot meet the requirement for a battery module with a large number of battery strings, so that when the number of battery strings is large, one BMS board can use a plurality of AFE chips at the same time.

For the same AFE chip, the default communication addresses are the same. At present, when data in an AFE chip is read, a plurality of controllers are generally adopted to establish a plurality of communication links with different AFE chips for communication, or communication addresses of the AFE chips are set through upper computer software provided by manufacturers; however, the former requires more controller resources, and the latter requires an increased production process, resulting in higher implementation costs and lower address configuration efficiency.

In view of the above drawbacks, an embodiment of the present application provides a method for configuring a chip address, where the method sequentially wakes up each AFE chip, and reads first data of a target AFE chip based on a preset initial address after waking up one AFE chip; checking the first data to obtain a first checking result of the first data; when the first verification result is that the first verification result is passed, configuring the address of the target AFE chip as a target address corresponding to the target AFE chip; on the premise of not increasing the resource cost of the controller and the production procedure, the communication addresses of the AFE chips can be rapidly configured, the address configuration efficiency under the scene of the AFE chips is improved, and meanwhile, the data of the AFE chips can be accurately and reliably read respectively; has stronger usability and practicability.

Referring to fig. 1, fig. 1 is a schematic diagram of an application scenario of a method for configuring a chip address according to an embodiment of the present application.

In some embodiments, the method for configuring a chip address provided in the embodiments of the present application is applied to a processor in a battery management system, where the processor is connected to a plurality of analog front end AFE chips. As shown in fig. 1, the battery management system 100 includes: processor 110, analog front end AFE chip set 120, driver chip 130, and switching circuit 140.

In some embodiments, the set of analog front end AFE chips 120 includes a plurality of analog front end AFE chips. As shown in fig. 1, the processor 110 is connected to the AFE chip set 120 and the driver chip 130, and the processor 110 is configured to control operations of the AFE chip set 120 and the driver chip 130. Each analog front end AFE chip in the analog front end AFE chip set 120 is configured to collect various data (such as the total voltage of the battery, the voltage, the current, and the temperature of the battery cell) in the battery module 200, and the processor 110 reads the collected data and performs corresponding protection or charge/discharge control on the battery module 200 according to the read data.

In one embodiment, a register may be provided in the AFE chipset 120, and data collected by the AFE chipset for the battery module 200 may be stored in the register.

The driving chip 130 is used for driving and controlling the switching circuit 140. In practical applications, the driver chip 130 may be directly integrated on the processor 110.

In some embodiments, as shown in fig. 1, the switch circuit 140 is used to control the charge and discharge of the battery module 200. The switching circuit 140 may include a charge switch S1 and a discharge switch S2. When the charging switch S1 and the discharging switch S2 are both turned on, the battery module 200 may be charged or discharged; when both the charge switch S1 and the discharge switch S2 are turned off, the battery module 200 prohibits charging and prohibits discharging; when the charge switch S1 is turned on and the discharge switch S2 is turned off, the battery module 200 allows charging and prohibits discharging; when the charge switch S1 is turned off and the discharge switch S2 is turned on, the battery module 200 allows discharge, prohibiting charge.

The battery module 200 includes a plurality of battery cells, and the plurality of battery cells may be connected in parallel or in series, or connected in series and parallel to obtain a required battery voltage, and stacked or arranged in a certain order.

The following describes a specific procedure implemented by the method for configuring a chip address according to the embodiment of the present application.

Referring to fig. 2, fig. 2 is a flowchart illustrating implementation of a method for configuring a chip address according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:

S201, waking up each AFE chip in turn.

In some embodiments, the processor, when configuring the address of the AFE chip, first wakes up each AFE chip in turn, wakes up one AFE chip at a time, and then performs an operation of configuring the address on the waked-up AFE chip in a subsequent step. When the AFE chip is awakened, the AFE chip and the battery cell in the battery module can be sequentially awakened according to the corresponding relation, and the corresponding awakening sequence can be configured for awakening.

For example, when the AFE chip is awakened, the wake-up can be performed according to a one-to-one correspondence relationship between the AFE chip and the battery cell string. The battery module can comprise a plurality of battery cell groups, each battery cell group consists of a plurality of battery cells, the connection relation of different battery cell groups can be parallel connection, and the battery cell groups are stacked or arranged according to a certain sequence, and one AFE chip corresponds to one battery cell group, so that when the AFE chip is awakened, the corresponding AFE chip can be awakened according to the stacking or arrangement sequence of the battery cell groups.

It should be noted that, the processor is respectively connected to different AFE chips through the wake-up lines connected to the wake-up pins, and then wakes up the AFE chips through the wake-up lines, and a specific wake-up process is described in the following embodiments. When the AFE chip is awakened, the address of the awakened AFE chip is not required to be known, but when the processor reads data from the awakened AFE chip after the AFE chip is awakened, the processor needs to read according to the address of the AFE chip.

When the AFE chip is awakened, if different awakening pins/awakening lines are configured with corresponding awakening sequences, the processor can sequentially awaken the corresponding AFE chip according to the awakening sequences corresponding to the awakening pins/the awakening lines, and only one AFE chip is awakened at a time, so that an address is configured for the awakened AFE chip.

S202, each time an AFE chip is awakened, first data of a target AFE chip is read based on a preset initial address.

In some embodiments, the target AFE chip is a currently awake AFE chip, and after sequentially waking up the AFE chips, the first data of the currently awake AFE chip is read each time one AFE chip is awake. When the first data is read, the first data is read according to a preset initial address, and then the read data is checked in a subsequent step to obtain a corresponding check result. The first data may be any data that may be supported by the target AFE chip, for example, data such as voltage, current, or temperature of the battery cell collected by the target AFE.

In some embodiments, for the same type of AFE chip, default addresses are the same when leaving the factory, if multiple AFE chips are awakened at the same time, when data is read according to the default addresses of the AFE chips, the data of the multiple AFE chips are read at the same time, and interference is caused. If only one AFE chip is woken up at a time, when data is read according to a default address, only the data of one AFE chip can be read, but the data of other AFE chips cannot be read, and interference cannot be caused, so that only one AFE chip is woken up at a time in the embodiment.

Accordingly, since only one AFE chip is awakened at a time, when the AFE chip is awakened, whether the AFE chip is reconfigured or not is not required to be known, the default awakened AFE chip is an AFE chip with an address which is not reconfigured, the preset initial address is a default address when the factory is shipped, and the data of the current awakened AFE chip is read according to the default address.

It should be noted that, the processor is connected to a plurality of AFE chips through a communication line, and performs data reading and writing (i.e. configuration of initialization parameters) on the AFE chips through the communication line. In battery management systems, a large amount of data is read by the processor from the AFE chip, such as actual current data. When the battery is charged, the battery management system sends request current data to the charger, the magnitude of the request current is required to be determined according to the magnitude of the actual current read by the AFE chip, the battery management system compares the required current with the actual current, and the magnitude of the required current is enabled to be approximately equal to the magnitude of the actual current by adjusting the magnitude of the request current.

S203, checking the first data to obtain a first check result of the first data.

In some embodiments, after reading the first data of the currently awakened AFE chip based on the preset initial address, the first data is checked to obtain a first check result of the first data. The checking mode may be to determine whether the first data is empty, where the first checking result includes two types of data: one is that the first data is not empty, and the verification result is passed; the other is that the first data is empty, and the check result is not passed.

It should be noted that, when the first data of the currently awakened AFE chip is read based on the preset initial address, it is possible that the address of the currently awakened AFE chip is reconfigured, and after the address of the AFE chip is reconfigured, when the data is read from the AFE chip based on the preset initial address, the read first data is empty. If the address of the currently awake AFE chip is not reconfigured, the first data with contents may be read, i.e., the read first data is not empty.

S204, when the first check result is that the first check result is passed, the address of the target AFE chip is configured as the target address corresponding to the target AFE chip.

In some embodiments, when the first data of the target AFE chip read based on the preset initial address is verified, and the obtained first verification result is that the first data passes, that is, when the read first data is not empty, the address is configured for the target AFE chip, the address of the target AFE chip is configured as the target address corresponding to the address, and the target AFE chip can communicate with the processor based on the new address.

In some embodiments, the target address corresponding to the target AFE chip may be related to the wake-up sequence corresponding to the target AFE chip. For example, the processor may configure the 1 st target address for the 1 st wake-up target AFE chip and the 2 nd target address for the 2 nd wake-up target AFE chip.

In some embodiments, the AFE chip is characterized by being unable to maintain normal communication with the processor when not awake and being able to communicate with the processor when awake. When the target address is configured for the AFE chips, only one AFE chip is woken up at a time, and the target address is configured for the currently woken up AFE chip. Since the rest of the AFE chips are not woken up and cannot communicate with the processor, the processor cannot read its data, so the addresses of the rest of the AFE chips are not configured.

In some embodiments, when initializing the AFE chip, wake up the AFE chip sequentially, and each wake up one AFE chip configures a corresponding target address for the AFE chip until the address configuration of the last AFE chip is completed. At this time, the addresses of all the AFE chips are different, so that the normal communication function can be realized, namely, the processor communicates with different AFE chips according to different addresses, and reads the data acquired by the AFE.

In some embodiments, the processor is in a powered state while the energy storage device is in a standby state or a sleep state. When the energy storage equipment is in a power-off state, the processor is in a power-off state, all the AFE chips in the battery module are powered off, and the addresses of the AFE chips can be restored to default addresses when leaving a factory, so that when the energy storage equipment is powered on again, the target addresses need to be reconfigured for all the AFE chips.

In other embodiments, the AFE chip may also store the address of the AFE chip via a non-volatile storage medium. When the AFE chip stores the address through the nonvolatile storage medium, the address of the AFE chip cannot be restored to a default address when leaving a factory due to shutdown of the energy storage device.

In the scheme provided by the embodiment, the processor sequentially wakes up each AFE chip, and reads the first data of the target AFE chip based on a preset initial address every time one AFE chip is waken up; checking the first data to obtain a first checking result of the first data; when the first verification result is that the first verification result is passed, configuring the address of the target AFE chip as a target address corresponding to the target AFE chip; on the premise of not increasing the resource cost of the controller and the production procedure, the communication addresses of the AFE chips can be rapidly configured, the address configuration efficiency under the scene of the AFE chips is improved, and meanwhile, the data of the AFE chips can be accurately and reliably read respectively; has stronger usability and practicability.

In step S201, each AFE chip is sequentially awakened, specifically: and sending a wake-up instruction to the target AFE chip based on a wake-up pin connected with the target AFE chip.

In some embodiments, the processor may wake up when sequentially waking up each AFE chip by sending a wake-up instruction to the target AFE chip based on a wake-up pin connected to the target AFE chip. Different wake-up pins of the processor are connected with different wake-up lines, the different wake-up lines are connected with different target AFE chips, the processor sends wake-up instructions to the different target AFE chips through the different wake-up lines, and the AFE chips can be woken up after receiving the wake-up instructions.

After step S204, the method for configuring a chip address provided in the embodiment of the present application further includes: the target AFE chip is initialized based on the cell parameters associated with the target AFE chip.

In some embodiments, after the first data of the target AFE chip read based on the preset initial address is verified, and the obtained first verification result is that the first data passes, after the address of the target AFE chip is configured as the target address corresponding to the target AFE chip, the target AFE chip may be initialized, and when the initialization is performed, the initialization may be performed according to the cell parameter associated with the target AFE chip.

By way of example, the cell parameters associated with the target AFE chip may include: overvoltage protection value, overcurrent protection value, undervoltage protection value or temperature protection value and other parameters. After the target AFE chip is configured with the target address, the target AFE chip may be initialized according to these cell parameters. After initializing the target AFE chip, the processor can control the charge and discharge of the battery module according to the battery cell parameters and the voltage, current or temperature data of the battery cell collected by the target AFE chip, and the battery module is prevented from overvoltage, overcurrent, undervoltage, overhigh temperature or overlow temperature and the like.

Referring to fig. 3, fig. 3 is a flowchart illustrating a second check result of obtaining second data according to an embodiment of the present application. As shown in fig. 3, the process may include the steps of:

s301, when the first check result is that the first data does not pass, the second data of the target AFE chip is read based on the target address.

In some embodiments, when the first data of the target AFE chip read based on the preset initial address is verified, and the obtained first verification result is failed, that is, when the read first data is empty, the second data of the target AFE chip may be read based on the target address, and then the second data is verified in a subsequent step to obtain a corresponding verification result, and whether the AFE chip has been configured with the target address before is determined according to the verification result. The second data may be any data that may be supported by the target AFE chip, for example, data such as voltage, current, or temperature of the battery cell collected by the target AFE.

S302, checking the second data to obtain a second checking result of the second data.

In some embodiments, after the second data of the target AFE chip is read based on the target address, the second data is verified, resulting in a second verification result of the second data. The checking may be performed by determining whether the second data is empty, where the second checking result includes two types: one is that the second data is not empty, and the second check result is passed; the other is that the second data is empty, the second check result is not passed.

It should be noted that, when the second check result is failed, that is, when the read second data is empty, it indicates that the address of the target AFE chip may be configured as the target address, so the second data of the target AFE chip may be read directly based on the target address. If the address of the target AFE chip is configured as the target address, when the second data is read based on the target address, the second data with content can be read, namely the second data is not null; if the address of the target AFE chip is not configured with the target address, when the second data is read based on the target address, the read second data is empty.

S303, when the second check result is that the address of the target AFE chip is passed, determining that the address of the target AFE chip is configured as the target address, and initializing the target AFE chip based on the cell parameter associated with the target AFE chip.

In some embodiments, when the second data of the target AFE chip read based on the target address is verified, and the obtained second verification result is passing, that is, when the read second data is not empty, it may be determined that the address of the target AFE chip is configured as the target address, so that the target address is not configured any more, the target AFE chip may be initialized directly based on the cell parameter associated with the target AFE chip, and a specific process of the initialization is described in the foregoing embodiments and is not repeated herein.

It should be noted that, when the energy storage device is started up each time, the processor returns to the power-on state from the power-down state and starts up, and reconfigures the target addresses of all AFE chips. In an actual application scenario, after the processor is powered down each time, the address of the AFE chip may be restored to a default address when shipped, but the AFE chip may also reserve the address configuration of the AFE chip, that is, the configured target address.

Therefore, when the first check result is that the first data fails, the processor may read the second data of the target AFE chip based on the target address, and determine whether the address of the target AFE chip is configured as the target address.

S304, when the second checking result is that the second checking result is not passed, the operation of configuring the chip address is finished, and the abnormal information of the starting is reported.

In some embodiments, when the second data of the target AFE chip read based on the target address is verified, and the obtained second verification result is that the second data does not pass, that is, when the read second data is empty, it may be determined that the address of the target AFE chip is not configured with the target address.

Accordingly, since the second data of the target AFE chip is read based on the target address on the premise that the first check result is not passed, that is, the first data of the target AFE chip read based on the preset initial address is empty. When the first check result is not passed, there is a possibility that the address of the target AFE chip has been configured as the target address. However, when the second check result is failed, it may be determined that the address of the target AFE chip is not configured as the target address, and this possibility is excluded. At this time, the energy storage device may fail, resulting in abnormal power-on, and the processor cannot configure the target address for the target AFE chip and cannot read data from the target AFE chip, so that the operation of configuring the chip address may be ended at this time, and information about abnormal power-on is reported, which also indicates that the initialization of the target AFE chip fails.

Referring to fig. 4, fig. 4 is a flowchart illustrating a process of determining whether the chip numbers reach the total number after initializing the target AFE chip according to an embodiment of the present application. As shown in fig. 4, the judging process may include the steps of:

s401, judging whether the wake-up sequence number of the target AFE chips reaches the total number of the AFE chips.

In some embodiments, after initializing the target AFE chip, it may be determined whether the wake-up sequence number of the target AFE chip reaches the total number of AFE chips, and then a corresponding operation is performed according to the determination result in a subsequent step.

In some embodiments, when configuring the target address for the target AFE chip, the wake-up sequence may be set for the AFE chip according to a pre-configured wake-up sequence, where the wake-up sequence may be sequentially incremented from 1, and the maximum wake-up sequence is the total number of AFE chips. When the AFE chips are awakened, the AFE chips can be sequentially awakened according to the awakening sequence number of the AFE chips, namely, the AFE chips are sequentially awakened from the AFE chip with the awakening sequence number of 1 according to the ascending sequence of the awakening sequence number. Each time one AFE chip is awakened, the address of the target AFE chip is configured as the target address corresponding thereto by performing a corresponding operation.

For example, the total number of the AFE chips is 10, wake-up serial numbers are set for the AFE chips according to the stacking sequence of the battery cells, the wake-up serial numbers are sequentially increased from 1, and the maximum wake-up serial number is 10. When the AFE chip is awakened, the AFE chip with the awakening sequence number of 1 is awakened in sequence until the AFE chip with the awakening sequence number of 10 is awakened.

In some embodiments, after the target AFE chip is configured with the target address, the target AFE chip may be initialized, and after the target AFE chip is initialized, it is determined whether the wake-up sequence number of the target AFE chip reaches the total number of AFE chips, that is, it is determined whether all the AFE chips have been initialized.

It should be noted that, multiple groups of battery cells may be configured in the battery module of the energy storage device. For a plurality of AFE chips of the same model, data such as voltage, current or temperature of a plurality of groups of battery cells can be collected at the same time, so that the total number of the AFE chips can be determined according to the number of the battery cells actually adopted in the energy storage equipment.

S402, if the wake-up sequence number reaches the total number, the operation of configuring the chip address is ended.

In some embodiments, after initializing the target AFE chip, when determining whether the wake-up sequence number of the target AFE chip reaches the total number of AFE chips, if the wake-up sequence number of the target AFE chip reaches the total number of AFE chips, that is, the target addresses have been configured for all the AFE chips, and performing corresponding initialization, the operation of configuring the chip addresses may be ended, which indicates that the initialization of the AFE chip is successful.

S403, if the wake-up sequence number does not reach the total number, returning to execute the step of waking up each AFE chip in sequence.

In some embodiments, after initializing the target AFE chip, when determining whether the wake-up sequence number of the target AFE chip reaches the total number of AFE chips, if the wake-up sequence number of the target AFE chip does not reach the total number of AFE chips, it indicates that there are more AFE chips not configured with the target address and is initialized, so the steps of sequentially waking up the AFE chips and subsequent steps are performed, and the target addresses are configured and initialized for the remaining AFE chips.

Referring to fig. 5, fig. 5 is a flowchart illustrating an overall implementation of a method for configuring a chip address according to an embodiment of the present application. As shown in fig. 5, the method comprises the steps of:

s501, waking up each AFE chip in turn.

In some embodiments, the processor, when configuring the address of the AFE chip, first wakes up each AFE chip in turn, one AFE chip at a time. The wake-up AFE chip is then subjected to an address configuration operation in a subsequent step.

When the AFE chip is awakened, the AFE chip and the battery cell in the battery module can be sequentially awakened according to the corresponding relation, and the corresponding awakening sequence can be configured for awakening.

When the AFE chip is awakened, an awakening instruction can be sent to the AFE chip based on an awakening pin connected with the AFE chip.

S502, each time an AFE chip is awakened, first data of a target AFE chip is read based on a preset initial address.

In some embodiments, the target AFE chip is a currently awakened AFE chip, after each AFE chip is sequentially awakened, each time when one AFE chip is awakened, first data of the currently awakened AFE chip is read, when the first data is read, the first data can be read according to a preset initial address, then in a subsequent step, whether the processor normally reads the first data is judged, that is, the read data is checked, and a corresponding check result is obtained. The first data may be any data that may be supported by the target AFE chip, for example, data such as voltage, current, or temperature of the battery cell collected by the target AFE.

It should be noted that, the preset initial address is a default address when the AFE chip leaves the factory, and the data of the currently awakened AFE chip can be read according to the default address. Upon waking up the AFE chip, the default wake-up AFE chip is an AFE chip that is not address reconfigured without knowing whether the AFE chip is address reconfigured. In the subsequent step, the processor reads the address of the target AFE chip based on the default address, and judges whether the data can be read normally.

Correspondingly, if the processor can read the data normally, the address of the target AFE chip is not reconfigured and is still the default address, and the address of the target AFE chip can be configured at the moment; if the processor is unable to read the data normally, it indicates that the address of the target AFE chip may have been reconfigured as the target address, at which time the data of the target AFE chip may be read based on the target address, thereby determining whether the address of the target AFE chip has been reconfigured as the target address.

S503, checking the first data to determine whether the processor reads the first data normally.

In some embodiments, after reading the first data of the currently awakened AFE chip based on the preset initial address, the first data is checked to determine whether the processor reads the first data normally, i.e. whether the first data is empty.

The step S503 may include the steps of:

s5031, if the processor can read the first data normally, the address of the target AFE chip is configured as the target address corresponding to the target AFE chip.

In some embodiments, when determining whether the processor reads the first data normally, if the processor can read the first data normally, that is, when the first data read is not empty, the address is configured for the target AFE chip, the address of the target AFE chip is configured as the target address corresponding to the address, and the target AFE chip can communicate with the processor by using the new address.

It should be noted that, the target address is a new communication address configured for the target AFE chip and different from a default address when shipped, and the target AFE chip may communicate with the processor according to the new communication address.

In the actual application process, the processor can generate a plurality of target addresses capable of being used for address configuration in advance, and different target addresses correspond to different wake-up sequence numbers/wake-up pins. Subsequently, when each AFE chip is awakened one by one, the corresponding target address can be determined according to the awakening sequence number/awakening pin of the awakened target AFE chip.

S5032, if the processor can not read the first data normally, reading the second data of the target AFE chip based on the target address.

In some embodiments, when determining whether the processor can normally read the first data, if the processor cannot normally read the first data, that is, when the read first data is empty, the second data of the target AFE chip may be read based on the target address, whether the AFE chip has been configured with the target address before, and then the second data is checked in a subsequent step to determine whether the processor can normally read the second data. The second data may be any data that may be supported by the target AFE chip, for example, data such as voltage, current, or temperature of the battery cell collected by the target AFE.

The following steps may be included after step S5031:

s50311 initializes the target AFE chip based on the cell parameters associated with the target AFE chip.

In some embodiments, after the address of the target AFE chip is configured as the target address corresponding to the target AFE chip, an initialization operation may be performed on the target AFE chip. When initialized, the target AFE chip may be initialized according to its cell parameters associated with it.

S50312, judging whether the wake-up sequence number of the target AFE chip reaches the total number of AFE chips.

The step S50312 may include the steps of:

if the wake-up sequence number reaches the total number, the operation of configuring the chip address is ended.

If the number of wake-up sequences does not reach the total number, the process returns to step S501 and the following steps.

The following steps may be included after step S5032:

s50321, it is determined whether the processor can normally read the second data.

In some embodiments, after the second data of the target AFE chip is read based on the target address, the second data is checked to determine whether the processor can read the second data normally, i.e., whether the second data is empty.

The step S50321 may include the steps of:

if the processor can read the second data normally, it is determined that the address of the target AFE chip is configured as the target address, and step S50311 is performed.

In some embodiments, when determining whether the processor reads the second data normally, if the processor can read the second data normally, that is, when the read second data is not empty, it may be determined that the address of the target AFE chip is configured as the target address, so the target address is not configured any more, and the target AFE chip may be initialized directly based on the cell parameter associated with the target AFE chip.

If the processor can not read the second data normally, the operation of configuring the chip address is finished, and the abnormal information of the starting is reported.

In some embodiments, when determining whether the processor normally reads the second data, if the processor cannot normally read the second data, that is, when the read second data is empty, it may be determined that the address of the target AFE chip is not configured with the target address. The energy storage device may fail, resulting in abnormal power-on, and the processor cannot configure the target address for the target AFE chip, so that the operation of configuring the chip address may be ended, and the information of abnormal power-on may be reported, which also indicates that the initialization of the target AFE chip fails.

According to the method provided by the embodiment of the application, the processor can wake up all the AFE chips in sequence, and each time one AFE chip is waken up, the first data of the target AFE chip is read based on the preset initial address; checking the first data to obtain a first checking result of the first data; and when the first verification result is that the first verification result passes, the address of the target AFE chip is configured as the target address corresponding to the target AFE chip. By the method, on the premise of not increasing the resource cost of the controller and the production procedure, the communication addresses of the AFE chips can be rapidly configured, the address configuration efficiency under the scene of the AFE chips is improved, and meanwhile, the data of the AFE chips can be accurately and reliably read respectively; has stronger usability and practicability.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.

Corresponding to the method described in the above embodiments, fig. 6 shows a schematic structural diagram of an apparatus for configuring a chip address according to an embodiment of the present application, and for convenience of explanation, only a portion related to the embodiment of the present application is shown.

Referring to fig. 6, the apparatus includes:

a wake-up unit 601, configured to wake up the AFE chips in sequence;

a reading unit 602, configured to read first data of a target AFE chip based on a preset initial address every time an AFE chip is awakened; the target AFE chip is a currently awakened AFE chip;

the processing unit 603 is configured to verify the first data to obtain a first verification result of the first data;

and a configuration unit 604, configured to configure the address of the target AFE chip as the target address corresponding to the target AFE chip when the first check result is passed.

It should be noted that, because the content of information interaction and execution process between the above devices/units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein again.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

Fig. 7 is a schematic structural diagram of an energy storage device 7 according to an embodiment of the present application. As shown in fig. 7, the energy storage device 7 of this embodiment includes: at least one processor 701 (only one is shown in fig. 7), a memory 703, a battery module 704, a plurality of analog front end AFE chips 705 and a computer program 702 stored in the memory 703 and executable on the at least one processor 701, the plurality of analog front end AFE chips 705 being connected to the battery module 704, the steps in the above method embodiments being implemented by the processor 701 when executing the computer program 702.

The energy storage device 7 may be a battery device such as a power battery, a lead-acid battery, a lithium ion battery, etc. The energy storage device 7 may include, but is not limited to, a processor 701, a memory 703, a battery module 704, and a plurality of analog front end AFE chips 705. It will be appreciated by those skilled in the art that fig. 7 is merely an example of the energy storage device 7 and is not meant to be limiting as the energy storage device 7, and may include more or fewer components than shown, or may combine certain components, or different components, such as may also include input-output devices, network access devices, etc.

The processor 701 may be a central processing unit (Central Processing Unit, CPU), and the processor 701 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 703 may in some embodiments be an internal storage unit of the energy storage device 7, such as a hard disk or a memory of the energy storage device 7. The memory 703 may also be an external storage device of the energy storage device 7 in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital Card (SD), a Flash memory Card (Flash Card) or the like, which are provided on the energy storage device 7. Further, the memory 703 may also include both an internal storage unit and an external storage device of the energy storage device 7. The memory 703 is used to store an operating system, application programs, boot Loader (Boot Loader), data, and other programs, such as program code for the computer program. The memory 703 may also be used to temporarily store data that has been output or is to be output.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may accomplish all or part of the flow of the method of the above-described embodiment by instructing the relevant hardware through a computer program, where the computer program may be stored in a computer readable storage medium, and the computer program may be executed by a processor to implement the steps of the method embodiment as described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable storage medium may include at least: any entity or device capable of carrying computer program code to computing device/electronics, recording medium, computer Memory, read-Only Memory (ROM), random-access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media such as U-discs, removable hard-discs, magnetic or optical disks, and so forth. In some jurisdictions, computer-readable storage media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

Embodiments of the present application also provide a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the respective method embodiments described above.

The embodiments of the present application also provide a computer program product which, when run on a mobile terminal, causes the mobile terminal to perform steps that may be implemented in the various method embodiments described above.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/electronic device and method may be implemented in other manners. The above-described apparatus/electronic device embodiments are merely illustrative, the division of the modules or units is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units, components may be combined or integrated into another system, and some features may be omitted from execution. Alternatively, the indirect coupling, direct coupling, or communication connection between the illustrated and discussed may be through some interfaces, devices, or units, which may be electrical, mechanical, or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. A method of configuring a chip address for a processor, the processor coupled to a plurality of analog front end AFE chips, the method comprising:

sequentially waking up all AFE chips;

checking the first data to obtain a first check result of the first data;

2. The method of claim 1, wherein after the verifying the first data, obtaining a first verification result of the first data, the method further comprises:

checking the second data to obtain a second checking result of the second data;

3. The method of claim 2, wherein when the second test result is pass, the method further comprises:

4. The method of claim 2, wherein after said verifying said second data, obtaining a second verification result of said second data, said method further comprises:

5. The method of claim 1, wherein after said configuring the initial address of the target AFE chip to a target address corresponding to the target AFE chip, the method further comprises:

6. The method of claim 3 or 5, wherein after said initializing the target AFE chip, the method further comprises:

7. The method of claim 6, wherein waking each AFE chip in turn comprises:

8. An apparatus for configuring a chip address, the apparatus comprising:

the wake-up unit is used for sequentially waking up the AFE chips;

9. The energy storage device comprises a battery module, a memory, a processor and a plurality of analog front end AFE chips, wherein the analog front end AFE chips are connected with the battery module; the memory stores a computer program, characterized in that the processor implements the steps of the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.