CN116431217A - High-speed 3DES algorithm based on 51-series singlechip special register - Google Patents
High-speed 3DES algorithm based on 51-series singlechip special register Download PDFInfo
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Abstract
The invention discloses a high-speed 3DES algorithm based on a 51-series singlechip special register, which is applied to a 51-series singlechip with at least 16 special function registers, and utilizes BIT variable operation of the special register to finish data BIT operation of the algorithm in a replacement link, namely, BIT variables of the special register are used for establishing corresponding relation with BIT positions of data to be replaced according to a replacement rule. The invention replaces byte array variables in the traditional programming form with bit variables of the special register, so that the memory occupied by the variables is reduced; the bit variable is adopted, and the transposition operation is directly carried out during calculation, so that the cyclic calculation is avoided, and the operation time is shortened; the operation resource is saved, and the code operation efficiency is high, so that the encryption and decryption operations can be completed rapidly.
Description
Technical Field
The invention relates to the technical field of encryption algorithms, in particular to a high-speed 3DES algorithm based on a special register of a 51-series singlechip.
Background
In cryptography, the triple data encryption algorithm, or 3DES, is a symmetric key encryption block cipher, which is equivalent to applying a triple Data Encryption Standard (DES) algorithm to each data block. Due to the enhancement of the computing capability of the computer, the key length of the original edition DES password becomes easy to be cracked by violence; rather than designing a completely new block cipher algorithm, 3DES is designed to provide a relatively simple method of avoiding similar attacks by increasing the key length of DES.
The 3DES uses a 56-bit key and a block encryption method, and in the block encryption method, plaintext to be encrypted is divided into text blocks with a size of 64 bits and then substitution and related operations are performed according to a specified rule. By adopting the programming of the traditional method, byte type array variables are needed in the replacement link and are used for defining the replacement rule of data bits in different calculation links, the number of the array variables is 4, and 208 bytes of memory are occupied in total. Wherein:
(1) The array variable used for defining the 1 st permutation rule, namely the IP permutation rule occupies 64 bytes, and the variable name is defined as bpTimes_1 in the invention;
(2) The array variable used for defining the 2 nd substitution rule, namely expanding the substitution rule occupies 48 bytes, and the variable name is defined as bpExp32_48 in the invention;
(3) The array variable used for defining the 3 rd permutation rule occupies 32 bytes, and the variable name is defined as bpTimes_3 in the invention;
(4) The array variable used to define the 4 th permutation rule, i.e., the final permutation rule, takes 64 bytes, and the variable name is defined as bpTimes_4 in the present invention.
When the traditional programming mode is used, byte type array variables are called, more instructions are called during compiling, the number of instruction periods is large, and the algorithm flow is as follows:
the 1 st replacement of the plaintext data to be encrypted is firstly completed, then 16 rounds of operation are needed, each round of operation is needed to be completed according to the 2 nd and 3 rd replacement rules, and after the 16 rounds of operation are completed, the 4 th replacement operation is needed to be performed finally.
Each replacement operation needs to call a corresponding byte array variable, and the data position information in the replacement rule is obtained by calling elements in the array, so that the operation flow and the operation data are as follows:
(1) 1 st permutation (i.e. IP permutation)
In IP permutation, 64 cycles are required, elements of bpTimes_1 are called according to a permutation rule, 56 instructions are generated after each data transposition compilation, 83 machine cycles correspond to the 56 instructions, and the total instruction number is 3584, and 5312 machine cycles are all achieved.
(2) The 2 nd permutation (i.e. extension permutation)
In the expansion replacement, 16 rounds of circulation are needed, elements of bpExp32_48 are called according to a replacement rule, 48 circulation operation is carried out on each round, each time of data transposition is carried out, 60 instructions are generated after compiling, 89 machine cycles are corresponding, the total instruction number is 46080, and 68352 machine cycles are all needed.
(3) 3 rd substitution
In the 3 rd permutation, 16 rounds of loops are needed, elements of bpTimes_3 are called according to a permutation rule, 32 loops are operated for each round, each time of data transposition is performed, 56 instructions are generated after compiling, the total instruction number is 28672 corresponding to 83 machine cycles, and 42496 machine cycles are all needed.
(4) 4 th substitution (i.e., final substitution)
In the final permutation, elements of bpTimes_4 are called according to a permutation rule, 64 times of cyclic operation are carried out, each time of data transposition is carried out, 61 instructions are generated after compiling, 86 machine cycles are corresponding, the total instruction number is 3904, and the total instruction number is 5504 machine cycles.
In each encryption and decryption operation, 82240 instructions, 121664 machine cycles, are consumed in the computation of the correlation with the permutation. Therefore, the whole encryption and decryption process needs to occupy a large amount of memory and has low efficiency.
In each encryption and decryption operation, 82240 instructions, 121664 machine cycles, are consumed in the computation of the correlation with the permutation. Therefore, the whole encryption and decryption process needs to occupy a large amount of memory and has low efficiency.
Disclosure of Invention
In order to solve the problems, the invention provides a high-speed 3DES algorithm based on a 51-series singlechip special register, and the special register bit variable operation is adopted to replace the traditional array operation in the replacement link, so that the variable occupies smaller memory and the operation efficiency is higher.
For this purpose, the technical scheme of the invention is as follows: a high-speed 3DES algorithm based on 51 series SCM special registers is applied to 51 series SCM with at least 16 special function registers, and comprises the following steps:
1) Defining a permutation rule variable, wherein the variable name is g_bpBits, and the variable name is an array with the length of 8 bytes and is used for establishing the mapping between the special function register bit variable and the permutation rule;
2) Defining an operation data variable, wherein the length of the operation data variable is an array of 8 bytes, the variable name is g_bpHex, and the operation data variable is used for establishing the mapping between the special function register bit variable and the operation data;
3) And (3) performing a replacement flow, completing 4 rounds of replacement according to a replacement rule, and directly performing the replacement operation by using bit variable assignment of a special register during the replacement.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: in the step 3), in the 1 st replacement, according to the replacement rule, the replacement operation is directly completed; in the 2 nd permutation, the transposition operation of the data is completed through 16 times of circulation; in the 3 rd permutation, the transposition operation of the data is completed through 16 times of circulation; in the 4 th replacement, the replacement operation is directly completed according to the replacement rule.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: in the step 1), 64 bits correspond to a substitution rule, the variable type is sbit, and the variable type is named as b_bpBit0_0-b_bpBit7_7, and the variable type is respectively corresponding to g_bpBits [0] to g_bpBits [7].
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: in the step 2), 64 bits correspond to the data position to be operated, the variable type is sbit, the names are b_bpHex0_0-b_bpHex7_7, and g_bpHex [0] to g_bpHex [7] are respectively corresponding.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: the transposition flow of the step 3) specifically comprises the following steps:
3.1 In IP replacement, the grouped 8 bytes of plaintext data to be operated can be assigned to a replacement rule variable array g_bpBits, so that the one-to-one correspondence between the special register bit variables b_bpBit0_0-b_bpBit7 and the bits of operation data can be completed, and then the special register bit variables b_bpBit0_0-b_bpBit7 are sequentially assigned to the special register bit variables b_bpHex0_0-b_bpHex7 according to the replacement rule, so that the assignment of the operation data variable array g_bpHex can be completed;
3.2 In the expansion permutation, 16 rounds of operations are carried out, in each round of operation, the bit variable of a special register is assigned according to the permutation rule, and the bit variables b_bpBit0_0-b_bpBit3_7 of the special register are used for assigning the bit variables b_bpHex0-b_bpHex5_7, so that the expansion of 32 bits to 48 bits is completed; then using b_bpBit0_0-b_bpBit5_7 to finish assignment of operational data variable elements g_bpHex [0] -g_bpHex [3 ];
3.3 In the 3 rd permutation, 16 rounds of operation are carried out, bit variables of a special register are assigned according to a permutation rule, and the bit variables b_bpBit0_0-b_bpBit3_7 of the special register are used for assigning values of b_bpHex0_0-b_bpHex3_7;
3.4 In the final permutation, the bit variables b_bpBit0_0 to b_bpHex7_7 of the special register are used for assigning values according to the permutation rule by using the bit variables b_bpBit0_0 to b_bpBit7_7 of the special register, and only one operation is performed.
In 3DES operation, the data replacement process corresponding to the encryption and decryption flow is the same, so that the corresponding replacement rule is written as a function, and in the operation process, the replacement of the data can be completed by directly calling the function.
The 51 series single chip microcomputer is internally provided with 21 special function registers (SFRs for short), each SFR occupies 1 byte, namely 8 bits, each bit can be directly operated and operated during programming, and the instruction period for executing one bit operation is usually only one instruction period, so that the bit operation function of the 51 single chip microcomputer is used for replacing the traditional function operation, the calculation process of an algorithm can be simplified, the code amount of the program is reduced by 15%, the calculation time is shortened to one tenth, the operation speed is greatly improved, and the hardware cost is reduced.
Compared with the prior art, the invention has the beneficial effects that:
1. the BIT variable operation of the special register is utilized to complete the data BIT operation of the algorithm in the replacement link, namely, the BIT variable of the special register is used to establish the corresponding relation with each BIT position of the data to be replaced according to the replacement rule;
2. bit variables of a special register are used for replacing byte array variables in a traditional programming form, so that the memory occupied by the variables is reduced;
3. the special register bit variable is adopted, and the transposition operation is directly carried out during calculation, so that the cyclic calculation is avoided, and the operation time is shortened;
4. the compiling instruction of the bit variable operation is usually one clock period, the occupied machine period is less, the operation resource is saved, the code operation efficiency is high, and therefore the encryption and decryption operation can be completed rapidly.
Drawings
The following is a further detailed description of embodiments of the invention with reference to the drawings
FIG. 1 is a diagram of the overall replacement logic of the present invention;
FIG. 2 is a schematic diagram of the data exchange of the IP replacement process according to the present invention;
FIG. 3 is a schematic diagram of an extended replacement process according to the present invention;
FIG. 4 is a schematic diagram of the 3 rd displacement process of the present invention;
FIG. 5 is a schematic diagram of the 4 th replacement process according to the present invention.
Detailed Description
The high-speed 3DES algorithm described in this embodiment is applied to a 51-series single-chip microcomputer with at least 16 special function registers. The 51 series single chip microcomputer is internally provided with a special function register (SFR for short), each SFR occupies 1 byte, namely 8 bits, each bit can be directly operated and operated during programming, and the instruction period for executing one bit operation usually has only one instruction period, so that the bit operation function of the 51 single chip microcomputer is used for replacing the traditional function operation, the calculation process of an algorithm can be simplified, the code quantity of a program is reduced by 15%, the calculation time is shortened to one tenth, the operation speed is greatly improved, and the hardware cost is reduced.
The algorithm is specifically as follows:
1. the bit variable of the special register is utilized to replace the byte type array variable, and the bit variable of the special register occupies 16 bytes, namely 128 bits of the memory, and corresponds to the data bit information in the exchange rule respectively, as shown in fig. 1, wherein:
1.1 A permutation rule variable is defined, the variable name is g_bpBits, and the variable name is used for establishing the mapping between the special function register bit variable and the permutation rule; the 64 bits correspond to a replacement rule, the variable types are sbit, the names are b_bpBit0_0-b_bpBit7_7, and g_bpBits [0] to g_bpBits [7] are respectively corresponding;
1.2 Defining an arithmetic data variable with the length of 8 bytes, wherein the variable name is g_bpHex, and the arithmetic data variable is used for establishing the mapping between the special function register bit variable and the arithmetic data;
the 64 bits correspond to the data position to be operated, the variable type is sbit, the names are b_bpHex0_0-b_bpHex7_7, and g_bpHex [0] to g_bpHex [7] are respectively corresponding.
2. With bit variables, the transposition operation is directly performed during calculation, the compiling instruction is usually one clock cycle,
2.1 In IP replacement, the grouped 8 bytes of plaintext data to be operated can be assigned to the replacement rule variable array g_bpBits, so that the one-to-one correspondence between the special register bit variables b_bpBit0_0-b_bpBit7 and the bits of operation data can be completed, and then the special register bit variables b_bpBit0_0-b_bpBit7 are sequentially assigned to the special register bit variables b_bpHex0_0-b_bpHex7 according to the replacement rule, so that the assignment of the operation data variable array g_bpHex can be completed. And only one operation is performed, transposition of the data is completed, 128 instructions are generated after compiling, and 254 machine cycles are corresponding.
The data exchange flow of the replacement rule of this round is shown in fig. 2, and specifically is as follows:
b_bpHex0_7＝b_bpBit7_6；b_bpHex0_6＝b_bpBit6_6；
b_bpHex0_5＝b_bpBit5_6；b_bpHex0_4＝b_bpBit4_6；
b_bpHex0_3＝b_bpBit3_6；b_bpHex0_2＝b_bpBit2_6；
b_bpHex0_1＝b_bpBit1_6；b_bpHex0_0＝b_bpBit0_6；
b_bpHex1_7＝b_bpBit7_4；b_bpHex1_6＝b_bpBit6_4；
b_bpHex1_5＝b_bpBit5_4；b_bpHex1_4＝b_bpBit4_4；
b_bpHex1_3＝b_bpBit3_4；b_bpHex1_2＝b_bpBit2_4；
b_bpHex1_1＝b_bpBit1_4；b_bpHex1_0＝b_bpBit0_4；
b_bpHex2_7＝b_bpBit7_2；b_bpHex2_6＝b_bpBit6_2；
b_bpHex2_5＝b_bpBit5_2；b_bpHex2_4＝b_bpBit4_2；
b_bpHex2_3＝b_bpBit3_2；b_bpHex2_2＝b_bpBit2_2；
b_bpHex2_1＝b_bpBit1_2；b_bpHex2_0＝b_bpBit0_2；
b_bpHex3_7＝b_bpBit7_0；b_bpHex3_6＝b_bpBit6_0；
b_bpHex3_5＝b_bpBit5_0；b_bpHex3_4＝b_bpBit4_0；
b_bpHex3_3＝b_bpBit3_0；b_bpHex3_2＝b_bpBit2_0；
b_bpHex3_1＝b_bpBit1_0；b_bpHex3_0＝b_bpBit0_0；
b_bpHex4_7＝b_bpBit7_7；b_bpHex4_6＝b_bpBit6_7；
b_bpHex4_5＝b_bpBit5_7；b_bpHex4_4＝b_bpBit4_7；
b_bpHex4_3＝b_bpBit3_7；b_bpHex4_2＝b_bpBit2_7；
b_bpHex4_1＝b_bpBit1_7；b_bpHex4_0＝b_bpBit0_7；
b_bpHex5_7＝b_bpBit7_5；b_bpHex5_6＝b_bpBit6_5；
b_bpHex5_5＝b_bpBit5_5；b_bpHex5_4＝b_bpBit4_5；
b_bpHex5_3＝b_bpBit3_5；b_bpHex5_2＝b_bpBit2_5；
b_bpHex5_1＝b_bpBit1_5；b_bpHex5_0＝b_bpBit0_5；
b_bpHex6_7＝b_bpBit7_3；b_bpHex6_6＝b_bpBit6_3；
b_bpHex6_5＝b_bpBit5_3；b_bpHex6_4＝b_bpBit4_3；
b_bpHex6_3＝b_bpBit3_3；b_bpHex6_2＝b_bpBit2_3；
b_bpHex6_1＝b_bpBit1_3；b_bpHex6_0＝b_bpBit0_3；
b_bpHex7_7＝b_bpBit7_1；b_bpHex7_6＝b_bpBit6_1；
b_bpHex7_5＝b_bpBit5_1；b_bpHex7_4＝b_bpBit4_1；
b_bpHex7_3＝b_bpBit3_1；b_bpHex7_2＝b_bpBit2_1；
b_bpHex7_1＝b_bpBit1_1；b_bpHex7_0＝b_bpBit0_1。
2.2 In the expansion permutation, 16 rounds of operations are carried out, in each round of operation, the bit variable of a special register is assigned according to the permutation rule, and the bit variables b_bpBit0_0-b_bpBit3_7 of the special register are used for assigning the bit variables b_bpHex0-b_bpHex5_7, so that the expansion of 32 bits to 48 bits is completed; and then carrying out operation, merging 48 bits into 32 bits according to a replacement rule, carrying out assignment on b_bpHex0_0-b_bpHex5_7 by using the bit variables b_bpBit0_0-b_bpBit5_7 of the special register through bit variable assignment of the special register, and completing assignment on the operation data variable elements g_bpHex0-g_bpHex5.
The 32 bits are expanded to 48 bits, 96 instructions are generated after compiling, the total instruction number is 1536 corresponding to 191 machine cycles, and the total instruction number is 3056 machine cycles.
The data exchange flow corresponding to the round of replacement is shown in fig. 3, and specifically is as follows:
b_bpHex0_7＝b_bpBit3_0；b_bpHex0_6＝b_bpBit0_7；
b_bpHex0_5＝b_bpBit0_6；b_bpHex0_4＝b_bpBit0_5；
b_bpHex0_3＝b_bpBit0_4；b_bpHex0_2＝b_bpBit0_3；
b_bpHex0_1＝b_bpBit0_4；b_bpHex0_0＝b_bpBit0_3；
b_bpHex1_7＝b_bpBit0_2；b_bpHex1_6＝b_bpBit0_1；
b_bpHex1_5＝b_bpBit0_0；b_bpHex1_4＝b_bpBit1_7；
b_bpHex1_3＝b_bpBit0_0；b_bpHex1_2＝b_bpBit1_7；
b_bpHex1_1＝b_bpBit1_6；b_bpHex1_0＝b_bpBit1_5；
b_bpHex2_7＝b_bpBit1_4；b_bpHex2_6＝b_bpBit1_3；
b_bpHex2_5＝b_bpBit1_4；b_bpHex2_4＝b_bpBit1_3；
b_bpHex2_3＝b_bpBit1_2；b_bpHex2_2＝b_bpBit1_1；
b_bpHex2_1＝b_bpBit1_0；b_bpHex2_0＝b_bpBit2_7；
b_bpHex3_7＝b_bpBit1_0；b_bpHex3_6＝b_bpBit2_7；
b_bpHex3_5＝b_bpBit2_6；b_bpHex3_4＝b_bpBit2_5；
b_bpHex3_3＝b_bpBit2_4；b_bpHex3_2＝b_bpBit2_3；
b_bpHex3_1＝b_bpBit2_4；b_bpHex3_0＝b_bpBit2_3；
b_bpHex4_7＝b_bpBit2_2；b_bpHex4_6＝b_bpBit2_1；
b_bpHex4_5＝b_bpBit2_0；b_bpHex4_4＝b_bpBit3_7；
b_bpHex4_3＝b_bpBit2_0；b_bpHex4_2＝b_bpBit3_7；
b_bpHex4_1＝b_bpBit3_6；b_bpHex4_0＝b_bpBit3_5；
b_bpHex5_7＝b_bpBit3_4；b_bpHex5_6＝b_bpBit3_3；
b_bpHex5_5＝b_bpBit3_4；b_bpHex5_4＝b_bpBit3_3；
b_bpHex5_3＝b_bpBit3_2；b_bpHex5_2＝b_bpBit3_1；
b_bpHex5_1＝b_bpBit3_0；b_bpHex5_0＝b_bpBit0_7。
the calculation formula of the rule converting 48 bits into 32 bits is: calculating a data position bM in the BOX; every 6 bits of units, (first bit is 2+last bit) multiplied by 16+ (bit 1-bit 5), 312 instructions are generated after compiling, corresponding to 452 machine cycles, the total instruction number is 4992, and 7232 machine cycles are all generated.
2.3 In the 3 rd permutation, 16 rounds of operation are carried out, bit variables of a special register are assigned according to a permutation rule, and the bit variables b_bpBit0_0-b_bpBit3_7 of the special register are used for assigning values of b_bpHex0_0-b_bpHex3_7; after compiling, 64 instructions are generated, corresponding to 127 machine cycles, the total instruction number is 1024, and the total instruction number is 2032 machine cycles.
The data exchange flow corresponding to the replacement rule of this round is shown in fig. 4, and specifically is as follows:
b_bpHex0_7＝b_bpBit1_0；b_bpHex0_6＝b_bpBit0_1；
b_bpHex0_5＝b_bpBit2_4；b_bpHex0_4＝b_bpBit2_3；
b_bpHex0_3＝b_bpBit3_3；b_bpHex0_2＝b_bpBit1_4；
b_bpHex0_1＝b_bpBit3_4；b_bpHex0_0＝b_bpBit2_7；
b_bpHex1_7＝b_bpBit0_7；b_bpHex1_6＝b_bpBit1_1；
b_bpHex1_5＝b_bpBit2_1；b_bpHex1_4＝b_bpBit3_6；
b_bpHex1_3＝b_bpBit0_3；b_bpHex1_2＝b_bpBit2_6；
b_bpHex1_1＝b_bpBit3_1；b_bpHex1_0＝b_bpBit1_6；
b_bpHex2_7＝b_bpBit0_6；b_bpHex2_6＝b_bpBit0_0；
b_bpHex2_5＝b_bpBit2_0；b_bpHex2_4＝b_bpBit1_2；
b_bpHex2_3＝b_bpBit3_0；b_bpHex2_2＝b_bpBit3_5；
b_bpHex2_1＝b_bpBit0_5；b_bpHex2_0＝b_bpBit1_7；
b_bpHex3_7＝b_bpBit2_5；b_bpHex3_6＝b_bpBit1_3；
b_bpHex3_5＝b_bpBit3_2；b_bpHex3_4＝b_bpBit0_2；
b_bpHex3_3＝b_bpBit2_2；b_bpHex3_2＝b_bpBit1_5；
b_bpHex3_1＝b_bpBit0_4；b_bpHex3_0＝b_bpBit3_7。
2.4 In the 4 th permutation, the bit variables b_bpBit0_0 to b_bpHex7_7 of the special register are used for assigning values according to the permutation rule by using the bit variables b_bpBit0_0 to b_bpBit7_7 of the special register, and only one operation is performed. 128 instructions are generated after compiling, corresponding to 255 machine cycles.
The data exchange flow corresponding to the replacement rule of this round is shown in fig. 5, and specifically is as follows:
b_bpHex0_7＝b_bpBit4_0；b_bpHex0_6＝b_bpBit0_0；
b_bpHex0_5＝b_bpBit5_0；b_bpHex0_4＝b_bpBit1_0；
b_bpHex0_3＝b_bpBit6_0；b_bpHex0_2＝b_bpBit2_0；
b_bpHex0_1＝b_bpBit7_0；b_bpHex0_0＝b_bpBit3_0；
b_bpHex1_7＝b_bpBit4_1；b_bpHex1_6＝b_bpBit0_1；
b_bpHex1_5＝b_bpBit5_1；b_bpHex1_4＝b_bpBit1_1；
b_bpHex1_3＝b_bpBit6_1；b_bpHex1_2＝b_bpBit2_1；
b_bpHex1_1＝b_bpBit7_1；b_bpHex1_0＝b_bpBit3_1；
b_bpHex2_7＝b_bpBit4_2；b_bpHex2_6＝b_bpBit0_2；
b_bpHex2_5＝b_bpBit5_2；b_bpHex2_4＝b_bpBit1_2；
b_bpHex2_3＝b_bpBit6_2；b_bpHex2_2＝b_bpBit2_2；
b_bpHex2_1＝b_bpBit7_2；b_bpHex2_0＝b_bpBit3_2；
b_bpHex3_7＝b_bpBit4_3；b_bpHex3_6＝b_bpBit0_3；
b_bpHex3_5＝b_bpBit5_3；b_bpHex3_4＝b_bpBit1_3；
b_bpHex3_3＝b_bpBit6_3；b_bpHex3_2＝b_bpBit2_3；
b_bpHex3_1＝b_bpBit7_3；b_bpHex3_0＝b_bpBit3_3；
b_bpHex4_7＝b_bpBit4_4；b_bpHex4_6＝b_bpBit0_4；
b_bpHex4_5＝b_bpBit5_4；b_bpHex4_4＝b_bpBit1_4；
b_bpHex4_3＝b_bpBit6_4；b_bpHex4_2＝b_bpBit2_4；
b_bpHex4_1＝b_bpBit7_4；b_bpHex4_0＝b_bpBit3_4；
b_bpHex5_7＝b_bpBit4_5；b_bpHex5_6＝b_bpBit0_5；
b_bpHex5_5＝b_bpBit5_5；b_bpHex5_4＝b_bpBit1_5；
b_bpHex5_3＝b_bpBit6_5；b_bpHex5_2＝b_bpBit2_5；
b_bpHex5_1＝b_bpBit7_5；b_bpHex5_0＝b_bpBit3_5；
b_bpHex6_7＝b_bpBit4_6；b_bpHex6_6＝b_bpBit0_6；
b_bpHex6_5＝b_bpBit5_6；b_bpHex6_4＝b_bpBit1_6；
b_bpHex6_3＝b_bpBit6_6；b_bpHex6_2＝b_bpBit2_6；
b_bpHex6_1＝b_bpBit7_6；b_bpHex6_0＝b_bpBit3_6；
b_bpHex7_7＝b_bpBit4_7；b_bpHex7_6＝b_bpBit0_7；
b_bpHex7_5＝b_bpBit5_7；b_bpHex7_4＝b_bpBit1_7；
b_bpHex7_3＝b_bpBit6_7；b_bpHex7_2＝b_bpBit2_7；
b_bpHex7_1＝b_bpBit7_7；b_bpHex7_0＝b_bpBit3_7。
3. comparison of results
Table 1 shows that this embodiment calls 7808 instructions in the calculation, requiring 12829 machine cycles; table 2 shows the number of machine cycles consumed in the conventional algorithm, and in each encryption process, 82240 instructions are called, 121664 machine cycles, in the computation associated with the permutation.
Table 1 uses bit variables to directly perform the transposition operation (using special registers)
| Calculation link | Instruction number | Cycle number of machine | Number of cycles | Number of wheels | Total instruction number | Total number of machine cycles |
| IP substitution | 128 | 254 | 1 | 1 | 128 | 254 |
| 32-bit extension to 48-bit rule | 96 | 191 | 1 | 16 | 1536 | 3056 |
| Conversion of 48 bits into 32 bit rules | 312 | 452 | 1 | 16 | 4992 | 7232 |
| 3 |
64 | 127 | 1 | 16 | 1024 | 2032 |
| Final replacement | 128 | 255 | 1 | 1 | 128 | 255 |
| Totals to | 7808 | 12829 |
Table 2 operates with byte-type variables (traditional algorithm)
| Calculation link | Instruction number | Cycle number of machine | Number of cycles | Number of wheels | Total instruction number | Total number of machine |
| IP substitution | ||||||
| 56 | 83 | 64 | 1 | 3584 | 5312 | |
| Expansion of | 60 | 89 | 48 | 16 | 46080 | 68352 |
| 3 |
56 | 83 | 32 | 16 | 28672 | 42496 |
| |
61 | 86 | 64 | 1 | 3904 | 5504 |
| Totals to | 82240 | 121664 |
For the same key and data, the same 51 series singlechip device is used, and the same group of 8 byte data is encrypted and decrypted according to the same data processing flow, and the results are compared as follows:
programming in a traditional mode, wherein the occupied memory resource is 746 bytes, the code space is 5764 bytes, the time for completing one-time encryption is 178ms, and the total time for completing one-time encryption and decryption is 355ms;
the bit operation mode is adopted for programming, the occupied memory resource is 698 bytes, the code space is 4863 bytes, the time for completing one encryption is 18ms, and the total time for completing one encryption and decryption is 36ms.
Therefore, the bit operation mode is adopted for programming, the variable occupies small memory, the transposition operation is directly carried out during calculation, the compiling instruction is usually one clock period, and the code operation efficiency is high. In 3DES operation, the data replacement process corresponding to the encryption and decryption flow is the same, so that the corresponding replacement rule is written as a function, and in the operation process, the replacement of the data can be completed by directly calling the function.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (5)
1. A high-speed 3DES algorithm based on 51 series SCM special registers is applied to 51 series SCM with at least 16 special function registers, and is characterized in that: the method comprises the following steps:
1) Defining a permutation rule variable, wherein the variable name is g_bpBits, and the variable name is an array with the length of 8 bytes and is used for establishing the mapping between the special function register bit variable and the permutation rule;
2) Defining an operation data variable, wherein the length of the operation data variable is an array of 8 bytes, the variable name is g_bpHex, and the operation data variable is used for establishing the mapping between the special function register bit variable and the operation data;
3) And (3) performing a replacement flow, completing 4 rounds of replacement according to a replacement rule, and directly performing the replacement operation by using bit variable assignment of a special register during the replacement.
2. The high-speed 3DES algorithm based on the 51-series singlechip special register as set forth in claim 1, wherein the high-speed 3DES algorithm is characterized in that: in the step 3), in the 1 st replacement, according to the replacement rule, the replacement operation is directly completed; in the 2 nd permutation, the transposition operation of the data is completed through 16 times of circulation; in the 3 rd permutation, the transposition operation of the data is completed through 16 times of circulation; in the 4 th replacement, the replacement operation is directly completed according to the replacement rule.
3. The high-speed 3DES algorithm based on the 51-series singlechip special register as set forth in claim 1, wherein the high-speed 3DES algorithm is characterized in that: in the step 1), 64 bits correspond to a substitution rule, the variable type is sbit, and the variable type is named as b_bpBit0_0-b_bpBit7_7, and the variable type is respectively corresponding to g_bpBits [0] to g_bpBits [7].
4. A high-speed 3DES algorithm based on a special register of a 51-series single chip microcomputer as claimed in claim 3, wherein: in the step 2), 64 bits correspond to the data position to be operated, the variable type is sbit, the names are b_bpHex0_0-b_bpHex7_7, and g_bpHex [0] to g_bpHex [7] are respectively corresponding.
5. The high-speed 3DES algorithm based on the 51-series singlechip special register as set forth in claim 4, wherein the high-speed 3DES algorithm is characterized in that: the transposition flow of the step 3) specifically comprises the following steps:
3.1 In IP replacement, the grouped 8 bytes of plaintext data to be operated can be assigned to a replacement rule variable array g_bpBits, so that the one-to-one correspondence between the special register bit variables b_bpBit0_0-b_bpBit7 and the bits of operation data can be completed, and then the special register bit variables b_bpBit0_0-b_bpBit7 are sequentially assigned to the special register bit variables b_bpHex0_0-b_bpHex7 according to the replacement rule, so that the assignment of the operation data variable array g_bpHex can be completed;
3.2 In the expansion permutation, 16 rounds of operations are carried out, in each round of operation, the bit variable of a special register is assigned according to the permutation rule, and the bit variables b_bpBit0_0-b_bpBit3_7 of the special register are used for assigning the bit variables b_bpHex0-b_bpHex5_7, so that the expansion of 32 bits to 48 bits is completed; then using b_bpBit0_0-b_bpBit5_7 to finish assignment of operational data variable elements g_bpHex [0] -g_bpHex [3 ];
3.3 In the 3 rd permutation, 16 rounds of operation are carried out, bit variables of a special register are assigned according to a permutation rule, and the bit variables b_bpBit0_0-b_bpBit3_7 of the special register are used for assigning values of b_bpHex0_0-b_bpHex3_7;
3.4 In the final permutation, the bit variables b_bpBit0_0 to b_bpHex7_7 of the special register are used for assigning values according to the permutation rule by using the bit variables b_bpBit0_0 to b_bpBit7_7 of the special register, and only one operation is performed.
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