CN116420190A - Semiconductor memory device and method for operating semiconductor memory device - Google Patents
Semiconductor memory device and method for operating semiconductor memory device Download PDFInfo
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Abstract
A semiconductor memory device includes a plurality of memory cells to which voltages are applied between a bit line and a source line, the memory cells each including: a memory element electrically connected to the bit line at the 1 st terminal, the memory element storing data according to a change in resistance value; and a selection transistor electrically connected to a 2 nd terminal of the memory element at a drain and electrically connected to the source line at a source, wherein in the memory element, a resistance value when a current is caused to flow in a 1 st direction from the 1 st terminal toward the 2 nd terminal is less likely to change than a resistance value when a current is caused to flow in a 2 nd direction from the 2 nd terminal toward the 1 st terminal.
Description
Technical Field
The present disclosure relates to a semiconductor memory device and an operation method of the semiconductor memory device.
Background
In recent years, as a nonvolatile memory of the next generation, an STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory ) using a spin injection write method has been attracting attention. STT-MRAM, which stores data according to the magnetization direction of a magnetic substance, can write data almost infinitely and at high speed, and therefore is expected to expand into a code storage device, a working memory, or the like.
Specifically, the STT-MRAM includes an MTJ (Magnetic Tunnel Junction ) element as a storage element. The STT-MRAM can store data of "0" or "1" by controlling the magnetization directions of the magnetic bodies facing each other in the MTJ element to be parallel or antiparallel.
In such an STT-MRAM, write current is passed through the MTJ element, and data is rewritten. In the STT-MRAM, since a write failure of data to the MTJ element occurs according to the magnitude of the write current, suppression of the write failure is studied (for example, patent document 1).
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open publication No. 2014-146414
Disclosure of Invention
On the other hand, in a nonvolatile memory such as an STT-MRAM, further reduction in power consumption is desired. Therefore, in the STT-MRAM, it is desirable to more efficiently flow a write current in the MTJ element.
Accordingly, it is desirable to provide a semiconductor memory device capable of writing data into a memory element more efficiently and an operation method of the semiconductor memory device.
One embodiment of the present disclosure provides a semiconductor memory device including a memory cell to which a voltage is applied between a bit line and a source line, the memory cell including: a memory element electrically connected to the bit line at the 1 st terminal, the memory element storing data according to a change in resistance value; and a selection transistor electrically connected to a 2 nd terminal of the memory element at a drain and electrically connected to the source line at a source, wherein in the memory element, a resistance value when a current is caused to flow in a 1 st direction from the 1 st terminal toward the 2 nd terminal is less likely to change than a resistance value when a current is caused to flow in a 2 nd direction from the 2 nd terminal toward the 1 st terminal.
In addition, another embodiment of the present disclosure provides an operation method of a semiconductor memory device, including: for a plurality of memory cells each including a memory element electrically connected to a bit line at the 1 st terminal and electrically connected to a drain of a selection transistor at the 2 nd terminal, the plurality of memory cells each including a memory element having a lower easiness of change in resistance value when a current is caused to flow in the 1 st direction from the 1 st terminal toward the 2 nd terminal than a memory element having a lower easiness of change in resistance value when a current is caused to flow in the 2 nd direction from the 2 nd terminal toward the 1 st terminal, the plurality of memory cells being arranged in a plurality of columns in a matrix, the memory elements each having data reset by causing a current to flow in the 1 st direction; and writing data by individually flowing a current from the 2 nd direction in the memory element of the predetermined memory cell.
In the semiconductor memory device and the operating method of the semiconductor memory device according to the embodiments of the present disclosure, the memory element is provided to be electrically connected to the bit line at the 1 st terminal and to be electrically connected to the drain of the selection transistor at the 2 nd terminal, and the resistance value when the current is caused to flow in the 1 st direction from the 1 st terminal toward the 2 nd terminal is made to be less likely to change than the resistance value when the current is caused to flow in the 2 nd direction from the 2 nd terminal toward the 1 st terminal. Thus, the semiconductor memory device can cancel the asymmetry of the ease of current flow to the memory element, which is generated in the circuit configuration due to the direction in which the current flows, with the asymmetry of the ease of change in the resistance state of the memory element.
Drawings
Fig. 1 is a schematic circuit diagram showing a structure of a memory cell of one specific example of a semiconductor memory device.
Fig. 2 is a graph showing a change in resistance value of a memory element with respect to a voltage applied to the memory element.
Fig. 3 is a schematic circuit diagram showing a structure of a memory cell array of one specific example of the semiconductor memory device.
Fig. 4 is a circuit diagram showing the flow of current when data is written to memory cells of the memory cell array individually.
Fig. 5 is a circuit diagram showing the flow of current when data is written collectively to a plurality of memory cells of the memory cell array.
Fig. 6 is a flowchart showing a flow of a data writing operation to a memory cell array of one specific example of the semiconductor memory device.
Detailed Description
Hereinafter, embodiments in the present disclosure will be described in detail with reference to the accompanying drawings. The embodiment described below is a specific example of the present disclosure, and the technology of the present disclosure is not limited to the following embodiments. The arrangement, dimensions, and dimensional ratios of the components of the present disclosure are not limited to those shown in the drawings.
The following procedure is described.
1. Structural example of memory cell
2. Structural example of memory cell array
3. Example of write operation to memory cell array
<1. Structural example of memory cell >
First, a memory cell which is one specific example of a semiconductor memory device according to an embodiment of the present disclosure is described with reference to fig. 1. Fig. 1 is a schematic circuit diagram showing the structure of a memory cell 1 of this specific example.
As shown in fig. 1, the memory cell 1 includes a memory element 10 and a selection transistor NT. The memory cell 1 is capable of writing and reading data by applying a voltage between the source line SL and the bit line BL.
The memory element 10 includes a 1 st terminal n1 and a 2 nd terminal n2, and is electrically connected to the bit line BL at the 1 st terminal n1 and to the drain of the selection transistor NT at the 2 nd terminal n 2. The memory element 10 can store data according to the level of the resistance value between the 1 st terminal n1 and the 2 nd terminal n 2. For example, the memory element 10 may store data of "0" by being in a high resistance state, and may store data of "1" by being in a low resistance state.
Specifically, the memory element 10 may be a MTJ (Magnetic Tunnel Junction) element including a fixed layer P whose magnetization direction is fixed, a free layer F whose magnetization direction is variable, and an extremely thin tunnel insulating layer B interposed between the fixed layer and the free layer.
The resistance value of the MTJ element varies depending on which of the parallel state or the antiparallel state the magnetization direction of the free layer F and the magnetization direction of the fixed layer P are. Thus, the memory element 10 can change the resistance value (i.e., the stored data) by changing the magnetization direction of the free layer F. For example, in the MTJ element, a current flows in a predetermined direction, and electrons having a spin direction matching the spin direction of electrons of the free layer F are injected into the free layer F in a reverse direction. Accordingly, the spin of electrons in the free layer F is inverted by the spin torque of injected electrons, and thus the magnetization direction of the free layer F is inverted. Thus, the memory element 10 including the MTJ element can change the resistance value (i.e., the stored data) according to the direction in which the current flows. That is, the memory cell 1 including the memory element 10 may be configured as an STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory).
The selection transistor NT is, for example, an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) that controls an on state and an off state according to a voltage applied to a gate via a word line WL. The selection transistor NT is electrically connected to the 2 nd terminal n2 of the memory element 10 at the drain and to the source line SL at the source.
The source line SL and the bit line BL are provided so as to extend in the same direction and parallel to each other. The word line WL is provided so as to extend in a direction perpendicular to the source line SL and the bit line BL.
In this embodiment, the memory element 10 is provided with asymmetry in which the easiness of writing data of one of "0" and "1" is higher (that is, the easiness of writing is higher) than the data of the other of "0" and "1". Specifically, the memory element 10 is provided so that the ease of change in resistance when a current flows in the 2 nd direction d2 from the 2 nd terminal n2 to the 1 st terminal n1 is higher than the ease of change in resistance when a current flows in the 1 st direction d1 from the 1 st terminal n1 to the 2 nd terminal n 2.
For example, in the MTJ element, a current flowing when changing the magnetization directions of the free layer F and the fixed layer P from the parallel state to the antiparallel state is larger than a current flowing when changing the magnetization directions of the free layer F and the fixed layer P from the antiparallel state to the parallel state. Accordingly, the memory element 10 including the MTJ element is provided such that the magnetization direction of the free layer F becomes antiparallel to the magnetization direction of the fixed layer P when a current is caused to flow in the 1 st direction d1, and the magnetization direction of the free layer F becomes parallel to the magnetization direction of the fixed layer P when a current is caused to flow in the 2 nd direction d2, whereby the asymmetry can be achieved. The asymmetry in the MTJ element can be controlled according to the magnetization direction of the fixed layer P and the magnetic characteristics of the free layer F.
In this case, the electrical characteristics of the memory element 10 are as shown in fig. 2. Fig. 2 is a graph showing a change in the resistance value TMR of the memory element 10 with respect to the voltage Vmtj applied to the memory element 10. In fig. 2, the negative side region shows a change in resistance value when a current flows in the 1 st direction d1 with respect to the memory element 10, and the positive side region shows a change in resistance value when a current flows in the 2 nd direction d2 with respect to the memory element 10.
As shown in fig. 2, in the memory element 10, the absolute value of the applied voltage when the region on the positive side (i.e., when the current flows in the 2 nd direction d 2) is changed from the high-resistance state to the low-resistance state is smaller than the absolute value of the applied voltage when the region on the negative side (i.e., when the current flows in the 1 st direction d 1) is changed from the low-resistance state to the high-resistance state. Thus, in the memory element 10, the resistance state can be changed more easily by passing the current in the 2 nd direction d2 than by passing the current in the 1 st direction d 1.
In the present embodiment, the 2 nd terminal n2 of the memory element 10 is electrically connected to the drain of the selection transistor NT. Therefore, when a current flows in the memory element 10 from the 2 nd terminal n2 toward the 1 st terminal n1 (i.e., toward the 2 nd direction d 2), a current flows in the memory element 10 through the selection transistor NT, so that the amount of current flowing in the memory element 10 due to the source follower effect of the selection transistor NT decreases. On the other hand, in the case where a current flows in the memory element 10 from the 1 st terminal n1 toward the 2 nd terminal n2 (i.e., toward the 1 st direction d 1), the source follower effect of the selection transistor NT does not occur, so the amount of current flowing in the memory element 10 does not decrease.
In the present embodiment, the memory element 10 is provided so that the resistance state is easily changed more easily when a current is caused to flow in the 2 nd direction d2 in which the voltage applied to the memory element 10 is relatively low. That is, the memory element 10 is provided so that the resistance state is less likely to change when a current is caused to flow in the 1 st direction d1 in which the voltage applied to the memory element 10 is relatively high than when a current is caused to flow in the 2 nd direction d 2.
Accordingly, the memory cell 1 can cancel the asymmetry of the ease of current flow to the memory element 10, which is generated in the circuit configuration due to the direction in which the current flows, with the asymmetry of the ease of change in the resistance state of the memory element 10. Thus, the memory cell 1 can rewrite the data stored in the memory element 10 more efficiently.
In addition, the memory cell 1 can avoid the size of the selection transistor NT from being increased in order to increase the current flowing through the memory element 10, and thus can reduce the cell size. Further, since the memory cell 1 can rewrite the data stored in the memory element 10 more efficiently, occurrence of defective writing of the data into the memory element 10 can be further suppressed.
<2 > structural example of memory cell array
Next, a memory cell array which is one specific example of the semiconductor memory device according to the present embodiment will be described with reference to fig. 3 to 5. Fig. 3 is a schematic circuit diagram showing the structure of the memory cell array 100 of this specific example. Fig. 4 is a circuit diagram showing the flow of current when data is written to the memory cells 1 of the memory cell array 100 individually. Fig. 5 is a circuit diagram showing the flow of current when data is written collectively to the plurality of memory cells 1 of the memory cell array 100.
As shown in fig. 4, the memory cell array 100 has an array structure in which a plurality of memory cells 1 shown in fig. 1 are arranged in a matrix. Specifically, the memory cells 1 are repeatedly arranged in the Y direction to constitute 1 unit of columns CL, and the columns CL are repeatedly arranged in the X direction to constitute the memory cell array 100.
The source lines SL electrically connected to the memory cells 1 of 1 unit column CL are electrically connected to the column switches CS of the p-type MOSFETs provided for each column CL. The bit lines BL electrically connected to the memory cells 1 of 1 unit column CL are electrically connected to the reset transistor RST which is a p-type MOSFET together with the bit lines of the other columns CL. The word line WL extends in the Y direction and is electrically connected to the memory cells 1 of the plurality of columns CL.
The source line SL is electrically connected to a reset transistor RST' of an n-type MOSFET provided for each of the plurality of columns CL in correspondence with the reset transistor RST. The bit line BL is electrically connected to a column switch CS' of an n-type MOSFET provided for each column CL in correspondence with the column switch CS.
Next, a writing operation of data into the memory cell array 100 shown in fig. 3 will be described with reference to fig. 4 and 5. Further, the voltage L represents an applied voltage lower than the voltage H.
First, in the memory cell array 100 in the standby state, a voltage L is applied to the word line WL. In addition, since the well potential is the voltage H with respect to the reset transistor RST and the column switch CS, the voltage H is controlled to be in the off state by being applied to the gate, and the voltage L is controlled to be in the off state by being applied to the gate with respect to the reset transistor RST 'and the column switch CS'.
As shown in fig. 4, when the resistance state of the memory element 10 is changed from the high resistance state to the low resistance state, the memory cell array 100 causes a current to flow from the 2 nd terminal n2 toward the 1 st terminal n1 (toward the 2 nd direction d 2) in the memory element 10 in the memory cell CL. Specifically, a voltage H is applied to the word line WL, a voltage L is applied to the gate to be controlled to be in an on state with respect to the column switch CS of the selected column CL, and a voltage H is applied to the gate to be controlled to be in an on state with respect to the column switch CS'.
Thus, in the memory cell array 100, a current can flow along the path Write0 in the 2 nd direction d2 in the memory element 10 of the selected 1 memory cell 1. Since the magnetization directions of the fixed layer P and the free layer F in the memory element 10 are changed from the antiparallel state to the parallel state by flowing a current in the 2 nd direction d2, the resistance state of the memory element 10 can be changed from the high resistance state to the low resistance state.
As shown in fig. 5, when the resistance state of the memory element 10 is changed from the low resistance state to the high resistance state, the memory cell array 100 causes a current to flow from the 1 st terminal n1 toward the 2 nd terminal n2 (toward the 1 st direction d 1) in the memory element 10 in the memory cell CL. Specifically, a voltage H is applied to the word line WL, and with respect to the reset transistor RST, a voltage L is applied to the gate so as to be controlled to be in an on state, and with respect to the reset transistor RST', a voltage H is applied to the gate so as to be controlled to be in an on state. The column switches CS and CS' are controlled to be turned off in the same manner as in the standby state.
As a result, in the memory cell array 100, a current can flow along the path Write1 in the 1 st direction d1 in the memory elements 10 of all the memory cells 1 of the plurality of columns CL. Since the magnetization directions of the fixed layer P and the free layer F in the memory element 10 are changed from the parallel state to the antiparallel state by the current flowing in the 1 st direction d1, the resistance state of the memory element 10 can be changed from the low resistance state to the high resistance state.
As described above, in the memory cell array 100, the column switches CS and CS 'are provided for each column of the columns CL in the path through which the current flows from the source line SL to the memory element 10, and the reset transistors RST and RST' are provided for each column of the plurality of columns CL in the path through which the current flows from the bit line BL to the memory element 10. Accordingly, the memory cell array 100 can reduce the number of switches in a path through which current flows from the bit line BL to the memory element 10, and thus can be made smaller in size.
Further, by providing the reset transistors RST and RST 'in a larger size than the column switches CS and CS', the memory cell array 100 can flow a larger current from the reset transistor RST when a current flows from the 1 st direction d1 to the memory element 10. Accordingly, the memory cell array 100 can suppress occurrence of a write failure to the memory element 10 in the 1 st direction d1 in which it is difficult to write data to the memory element 10. In addition, the memory cell array 100 can cancel the influence of the source follower effect of the selection transistor NT with ease of writing to the memory element 10 in the 2 nd direction d2 in which data is easily written to the memory element 10. Thus, the memory cell array 100 can also suppress occurrence of defective writing to the memory element 10 in the 2 nd direction d 2.
<3 > write operation example to memory cell array
Next, writing of data into a memory cell array, which is one specific example of the semiconductor memory device according to the present embodiment, will be described with reference to fig. 6. Fig. 6 is a flowchart showing a flow of a data writing operation to the memory cell array 100 of this specific example.
As shown in fig. 6, when data is written into the memory cell array 100, first, the reset transistor RST is turned on according to a predetermined address, and a current flows from the 1 st direction d1 to all the memory elements 10 in the plurality of columns CL. Thus, all the memory elements 10 of the plurality of columns CL of the predetermined address change to the high resistance state, so that data of, for example, "0" is written to these memory elements 10 (S201).
Next, the reset transistor RST is turned off, the column switch CS of the selected column CL is turned on, and a current flows from the 2 nd direction d2 to the memory element 10 of the selected memory cell 1. Thus, the memory element 10 of the selected memory cell 1 changes to the low resistance state, so that, for example, data of "1" is written to the memory element 10 (S202).
The memory cell array 100 performs the operation of step S202 individually for each memory element 10 of the memory cell 1 to which the data of "1" is written. Thereafter, the memory cell array 100 shifts to the next address (S203), and the operations of step S201 and step S202 are repeatedly performed. Thereby, data is written to the memory cell array 100.
Thus, the memory cell array 100 can perform data writing (i.e., writing of "1") by individually accessing the memory elements 10 of the plurality of columns CL after collectively resetting (i.e., writing of "0") the memory elements 10 of the plurality of columns CL using the reset transistor RST.
Accordingly, the memory cell array 100 can access each memory cell 1 by the column switch CS in the 2 nd direction d2 in which data is easy to write. In addition, the memory cell array 100 can collectively reset the plurality of columns CL by flowing a large current in the 1 st direction d1 in which data is difficult to write. Thus, the memory cell array 100 can suppress occurrence of defective writing of data while maintaining a reduced area of the entire array.
The technology of the present disclosure has been described above with reference to the embodiments and specific examples. However, the technology of the present disclosure is not limited to the above embodiment and the like, and various modifications are possible.
For example, the structure of the MTJ element included in the memory element 10 is not limited to the laminated structure of the fixed layer P, the tunnel insulating layer B, and the free layer F. The MTJ element included in the memory element 10 may be either a bottom pin structure or a top pin structure. The fixed layer P and the free layer F may also include multiple layers.
The memory cell 1 may include a semiconductor memory device other than the STT-MRAM as long as it includes a memory element 10 that stores data in a resistance state and has asymmetry in easiness of change of a resistance value. For example, the memory cell 1 may include a ReRAM (Resistive Random Access Memory ) having a CER film having an electric field induced large resistance change (CER effect) as the memory element 10.
Further, the structures and operations described in the embodiments are not necessarily all necessary as the structures and operations of the present disclosure. For example, the components of the independent claims not described in the above-described embodiments are to be understood as arbitrary components.
The terms used throughout this specification and the appended patent claims should be construed as "non-limiting" terms. For example, the terms "comprising" or "including" should be interpreted as "not limited to the arrangement described as being included. The term "having" is to be construed as "not limited to the means described as having".
The term used in the present specification includes terms used for convenience of description only, and is not used for the purpose of limiting the structure and operation. For example, terms such as "right", "left", "upper", "lower", and the like merely refer to directions on the drawings to which reference is made. The terms "inner" and "outer" refer to only a direction toward the center of the target element and a direction away from the center of the target element, respectively. The same applies to similar expressions and expressions with the same gist.
In addition, the technology of the present disclosure can also take the following structure. According to the technology of the present disclosure having the following structure, the asymmetry of the ease of change in the resistance state of the memory element can be used to cancel the asymmetry of the ease of flow of current to the memory element, which is generated in the circuit structure due to the direction in which the current is caused to flow. Thus, the semiconductor memory device can write data to the memory element more efficiently. The effects achieved by the technology of the present disclosure are not necessarily limited to those described herein, and may be any of those described in the present disclosure.
(1) A semiconductor memory device, wherein,
the semiconductor memory device includes a memory cell to which a voltage is applied between a bit line and a source line,
the memory cell includes:
a memory element electrically connected to the bit line at the 1 st terminal, the memory element storing data according to a change in resistance value; and
a selection transistor electrically connected to the 2 nd terminal of the memory element at a drain electrode and to the source line at a source electrode,
in the memory element, the ease of change in the resistance value when a current is passed from the 1 st terminal toward the 1 st terminal is lower than the ease of change in the resistance value when a current is passed from the 2 nd terminal toward the 2 nd terminal in the 1 st direction.
(2) The semiconductor memory device according to the above (1), wherein,
the memory element includes a fixed layer whose magnetization orientation is fixed, a free layer whose magnetization orientation is variable, and a tunnel insulating layer sandwiched between the fixed layer and the free layer.
(3) The semiconductor memory device according to the above (2), wherein,
in the memory element, the direction of magnetization of the free layer is antiparallel to the direction of magnetization of the fixed layer by flowing a current in the 1 st direction, and the direction of magnetization of the fixed layer is parallel to the direction of magnetization of the fixed layer by flowing a current in the 2 nd direction.
(4) The semiconductor memory device according to any one of the above (1) to (3), wherein,
a plurality of the memory cells are provided,
the plurality of memory cells are arranged in a matrix.
(5) The semiconductor memory device according to the above (4), wherein,
the semiconductor memory device further includes a column switch provided for each column of the memory cells,
current flows from the 2 nd direction in the storage element of the memory cell via the column switch.
(6) The semiconductor memory device according to the above (4) or (5), wherein,
the semiconductor memory device further includes a reset transistor provided for each of a plurality of columns of the memory cells,
current flows from the 1 st direction in the storage elements of all the memory cells of the plurality of columns via the reset transistor.
(7) The semiconductor memory device according to any one of the above (1) to (6), wherein,
the semiconductor memory device further includes the bit line extending in the same direction and a word line extending in a direction orthogonal to the source line,
the word line is electrically connected to a gate of the select transistor.
(8) An operation method of a semiconductor memory device, comprising:
for a plurality of memory cells each including a memory element having a lower easiness of change in resistance value when a current is passed in a 1 st direction from a 1 st terminal toward a 2 nd terminal than in a 2 nd direction from the 2 nd terminal toward the 1 st terminal, the memory element being electrically connected to a bit line at the 1 st terminal and to a drain of a selection transistor at the 2 nd terminal,
passing a current from the 1 st direction through the memory elements of all the memory cells arranged in a plurality of columns in a matrix, and resetting data; and
and writing data by individually flowing a current from the 2 nd direction in the memory element of the predetermined memory cell.
The present application is based on japanese patent application No. 2020-169451 filed in the japanese patent office at 6/10/2020, which is hereby incorporated by reference in its entirety for all purposes.
It should be understood that various modifications, combinations, sub-combinations and alterations will occur to those skilled in the art from a design point and other reasons, but are included within the scope of the appended claims and their equivalents.
Claims (8)
1. A semiconductor memory device, wherein,
the semiconductor memory device includes a memory cell to which a voltage is applied between a bit line and a source line,
the memory cell includes:
a memory element electrically connected to the bit line at the 1 st terminal, the memory element storing data according to a change in resistance value; and
a selection transistor electrically connected to the 2 nd terminal of the memory element at a drain electrode and to the source line at a source electrode,
in the memory element, the ease of change in the resistance value when a current is passed from the 1 st terminal toward the 1 st terminal is lower than the ease of change in the resistance value when a current is passed from the 2 nd terminal toward the 2 nd terminal in the 1 st direction.
2. The semiconductor memory device according to claim 1, wherein,
the memory element includes a fixed layer whose magnetization orientation is fixed, a free layer whose magnetization orientation is variable, and a tunnel insulating layer sandwiched between the fixed layer and the free layer.
3. The semiconductor memory device according to claim 2, wherein,
in the memory element, the direction of magnetization of the free layer is antiparallel to the direction of magnetization of the fixed layer by flowing a current in the 1 st direction, and the direction of magnetization of the fixed layer is parallel to the direction of magnetization of the fixed layer by flowing a current in the 2 nd direction.
4. The semiconductor memory device according to claim 1, wherein,
a plurality of the memory cells are provided,
the plurality of memory cells are arranged in a matrix.
5. The semiconductor memory device according to claim 4, wherein,
the semiconductor memory device further includes a column switch provided for each column of the memory cells,
current flows from the 2 nd direction in the storage element of the memory cell via the column switch.
6. The semiconductor memory device according to claim 4, wherein,
the semiconductor memory device further includes a reset transistor provided for each of a plurality of columns of the memory cells,
current flows from the 1 st direction in the storage elements of all the memory cells of the plurality of columns via the reset transistor.
7. The semiconductor memory device according to claim 1, wherein,
the semiconductor memory device further includes the bit line extending in the same direction and a word line extending in a direction orthogonal to the source line,
the word line is electrically connected to a gate of the select transistor.
8. An operation method of a semiconductor memory device, comprising:
for a plurality of memory cells each including a memory element having a lower easiness of change in resistance value when a current is passed in a 1 st direction from a 1 st terminal toward a 2 nd terminal than in a 2 nd direction from the 2 nd terminal toward the 1 st terminal, the memory element being electrically connected to a bit line at the 1 st terminal and to a drain of a selection transistor at the 2 nd terminal,
resetting data by flowing a current from the 1 st direction in the memory elements of all the memory cells arranged in a plurality of columns in a matrix; and
data is written by flowing a current from the 2 nd direction alone in the memory element of the predetermined memory cell.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020169451A JP2022061436A (en) | 2020-10-06 | 2020-10-06 | Semiconductor storage device, and operating method of semiconductor storage device |
| JP2020-169451 | 2020-10-06 | ||
| PCT/JP2021/030067 WO2022074941A1 (en) | 2020-10-06 | 2021-08-17 | Semiconductor storage device and method for operating semiconductor storage device |
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| JP2010177256A (en) * | 2009-01-27 | 2010-08-12 | Fujitsu Ltd | Magnetic memory device |
| JP4922374B2 (en) * | 2009-09-17 | 2012-04-25 | 株式会社東芝 | Magnetic memory |
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2020
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