CN116418341A - High-precision on-chip clock circuit - Google Patents
High-precision on-chip clock circuit Download PDFInfo
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- CN116418341A CN116418341A CN202111668686.8A CN202111668686A CN116418341A CN 116418341 A CN116418341 A CN 116418341A CN 202111668686 A CN202111668686 A CN 202111668686A CN 116418341 A CN116418341 A CN 116418341A
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- 239000003990 capacitor Substances 0.000 claims abstract description 39
- 230000006698 induction Effects 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005070 sampling Methods 0.000 claims description 21
- 230000010355 oscillation Effects 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 235000003642 hunger Nutrition 0.000 claims description 6
- 230000037351 starvation Effects 0.000 claims description 5
- 230000000087 stabilizing effect Effects 0.000 claims description 3
- 230000001276 controlling effect Effects 0.000 claims description 2
- 230000001105 regulatory effect Effects 0.000 claims description 2
- 230000007774 longterm Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 239000013078 crystal Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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Abstract
The invention provides a high-precision on-chip clock circuit, which is based on a negative feedback loop to realize a frequency-locked oscillator so as to provide an accurate and stable clock. The whole circuit is divided into three continuous steps which are not mutually interfered: and charging the induction capacitor by adopting a reference current in the output signal period of the single oscillator, and comparing the voltage across the induction capacitor with the reference voltage to adjust the output frequency of the oscillator and discharge the induction capacitor. The three steps are repeatedly and circularly operated, and finally the working frequency of the oscillator is locked in a state that the voltage at two ends of the induction capacitor is equal to the reference voltage, so that the working frequency of the oscillator is clamped to be the ratio of the reference current to the product of the capacitance value of the induction capacitor and the reference voltage. The invention avoids the influence of the delay of the comparator in the traditional relaxation oscillator on the frequency, and each module runs separately in the whole working process, thereby greatly improving the precision and stability of the clock, and the circuit has better long-term frequency stability and temperature stability.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a high-precision on-chip clock circuit.
Background
With the increasing complexity of integrated circuits and the development of system on a chip (SOC), clocks are densely distributed in each circuit module of the SOC, which becomes an important module in a chip. Under the condition of meeting the integration level, the existing on-chip clock often suffers from various non-ideal factors, so that long-term stability is difficult to achieve, and the clock precision is poor.
There are three types of existing on-chip clock generation circuits:
(1) The first method utilizes an off-chip crystal oscillator to generate a precise on-chip clock [ D.Yoon, et al, "" A5.58nW 32.768kHz DLL-Assisted XO for Real-Time Clocks in Wireless Sensing Applications "" IEEE ISSCC Dig.Tech.papers,2012, pp.366-368 "], and an off-chip quartz oscillator is needed, so that the clock frequency is accurate and stable, deviation can not occur when the surrounding external environment (such as temperature and the like) changes, the disadvantage is that the required off-chip quartz oscillator is high in price and cost, high in power consumption, low in frequency and in the range of tens of kHz-tens of MHz, and cannot meet the requirement of high frequency, and the method is commonly used for a low-frequency circuit at present;
(2) The second on-chip clock improves the problem of too low frequency in the first method, and is composed of a phase-locked loop (PLL) and an off-chip crystal oscillator, so that a higher frequency can be realized to reach a high frequency of tens of GHz, but the disadvantage is obvious, the power consumption is high firstly, and the cost is high because the off-chip crystal oscillator is required to provide a stable standard input, so that the on-chip clock is required to provide enough carrier frequency in a digital circuit or a radio frequency circuit which is commonly used for the high frequency at present, such as a CPU, wiFi,5G technology and the like.
(3) The third is the research focus of the invention, namely, a high-precision on-chip clock, and both methods are not applicable to the requirement. The on-chip clock is powered by an active power supply such as a battery, and the like, but generates induction current as a power supply by means of electromagnetic field static field coupling, and can be applied to the Internet of things (NBlot, low-power wide area network), passive radio frequency electronic tags (passive RFID, which are commonly applied to tracking or monitoring goods, guaranteeing goods information, transportation state and the like). Especially for passive RFID, no built-in battery is supported, the price is required to be controlled at a low level and the service life is long, and the control of the high-precision on-chip clock is not separated from the internal circuit.
For the third on-Chip clock, the existing scheme is often difficult to ensure high precision of the clock, the clock output signal is easy to generate ripple wave [ M.Choi, T.Jang, S.Bang, Y.Shi, D.Blaauw and D.Sylveste. "A110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3.3 ppm/. Degree.C Temperature Stability for System-on-Chip Designs" [ IEEE J.solid-State Circuits, vol.51, no.9, pp.2106-2118, sep.2016 ] ] in the stabilizing process, the clock output signal is used as an ideal clock source, the clock source has long-term frequency stability and temperature stability, the clock precision is required to be high, the clock frequency is less disturbed, the influence of the non-ideal source on the clock frequency is avoided as much as possible, and the output clock signal waveform is as smooth as possible, so that the occurrence of the ripple wave is avoided. The invention introduces a brand new working thought of the on-chip clock source circuit based on the existing problems and application requirements, greatly avoids the influence of non-ideal factors on a clock, reduces the generation of clock waveform ripple waves and improves the clock precision.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a high-precision on-chip clock circuit, in which the circuit structure implements a frequency-locked oscillator based on a negative feedback loop.
In order to achieve the above purpose, the present invention adopts the following scheme:
an object of the present invention is to provide a high-precision on-chip clock circuit composed of a sampling charge pump circuit, an amplifying circuit, a comparison charge pump circuit, a low-pass filter circuit, an oscillator circuit, a divide-by-three circuit, a reference voltage generating circuit and a reference current generating circuit.
Further, the oscillator circuit is composed of a voltage-current conversion circuit and a current starvation type ring oscillator circuit, wherein the voltage-current conversion circuit linearly converts an input voltage into an output current, and the output current is input into the current starvation type ring oscillator circuit to obtain an oscillation frequency linearly changing with the input voltage.
The second object of the present invention is to provide a high-precision on-chip clock circuit working method, comprising the following steps:
the output signal of the oscillator circuit passes through the frequency dividing circuit to obtain a control signal with a pulse width of one oscillation period, and the control signal is used for controlling the reference current generated by the reference current generating circuit to charge a sensing capacitor in the sampling charge pump circuit;
the voltage at two ends of the induction capacitor is compared with the reference voltage generated by the reference voltage generating circuit through the amplifying circuit, the current output by the amplifying circuit charges the comparison charge pump circuit, the voltage output by the comparison charge pump circuit is input into the oscillator circuit after passing through the low-pass filter circuit, and the oscillation frequency of the oscillator is further regulated, so that the voltage at two ends of the induction capacitor is more approximate to the reference voltage;
the sampling charge pump circuit discharges;
and repeating the steps, and finally stabilizing the circuit in a state that the voltage at two ends of the induction capacitor in the sampling charge pump circuit is equal to the reference voltage, wherein the corresponding oscillation frequency is also stabilized in the ratio of the reference current to the product of the capacitance value of the induction capacitor in the sampling charge pump circuit and the reference voltage.
The circuit structure realizes the frequency-locked oscillator based on the negative feedback loop, and introduces a brand new clock source circuit working thought to provide accurate and stable clocks. The whole circuit is divided into three continuous steps which are not mutually interfered: the reference current is adopted to charge the induction capacitor in the output signal period of the single oscillator, the voltage across the induction capacitor is compared with the reference voltage to adjust the output frequency of the oscillator, and the induction capacitor discharges. The sampling charge pump circuit induction capacitor charging, the comparison of the amplifying circuit, the frequency adjustment of the oscillator circuit and the induction capacitor discharging of the sampling charge pump circuit are respectively independent, three different phase control signals output by the three frequency dividing circuits are sequentially controlled to be carried out, the frequency of the whole circuit is not influenced by the delay time of the amplifier, the charging and discharging time of the induction capacitor in the sampling charge pump is sufficient, the frequency deviation caused by charge accumulation in the parasitic capacitor is avoided, the clock oscillation frequency is only related to the reference voltage, the reference current and the capacitance value of the induction capacitor, and the stable supply of the chip clock is realized.
The beneficial effects of the invention are as follows:
according to the high-precision on-chip clock circuit, the frequency locking oscillator is realized based on the feedback loop, the influence of the delay of the comparator in the traditional relaxation oscillator on the frequency is avoided, each module operates separately in the whole working process, the precision and the stability of the clock are greatly improved, and the circuit has good long-term frequency stability and temperature stability.
The following describes the specific embodiments of the present invention in further detail with reference to examples, so that the technical solution of the present invention is easier to understand and grasp.
Drawings
FIG. 1 is a diagram of a high-precision on-chip clock circuit complete circuit in accordance with an embodiment of the present invention;
FIG. 2 is a waveform diagram of a theoretical circuit output clock during a settling process;
FIG. 3a is a circuit diagram of a reference voltage generation circuit used in a high precision on-chip clock circuit according to an embodiment of the present invention;
FIG. 3b is a circuit diagram of a reference current generation circuit used in a high precision on-chip clock circuit in accordance with an embodiment of the present invention;
FIG. 4 is an enlarged circuit diagram of a high precision on-chip clock circuit used in accordance with an embodiment of the present invention;
FIG. 5 is a circuit diagram of a voltage conversion current used in a high precision on-chip clock circuit according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a current starved ring oscillator used in a high precision on-chip clock circuit according to an embodiment of the present invention;
FIG. 7 is a circuit diagram of a divide-by-three circuit used in a high precision on-chip clock circuit in accordance with an embodiment of the present invention;
fig. 8 is a simulated waveform diagram of a high-precision on-chip clock circuit in accordance with an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Examples
The embodiment of the invention comprises a sampling charge pump circuit, an amplifying circuit, a comparison charge pump circuit, a low-pass filter circuit, an oscillator circuit, a frequency dividing circuit, a reference voltage generating circuit and a reference current generating circuit, wherein a schematic diagram of the embodiment of the invention is shown in fig. 1.
The waveform of the output clock of the circuit in the process of tending to stabilize is similar to that of fig. 2, and when the frequency of the output clock is lower than the target frequency, the reference current in the first step sampling charge pump charges the sensing capacitor for a longer time, so that the voltage across the capacitor is larger than the reference voltage. In the second step, since the voltage at two ends of the sensing capacitor in the sampling charge pump is larger than the reference voltage, the output current of the amplifying circuit is injected into the sensing capacitor in the comparison charge pump circuit to increase the voltage at two ends of the sensing capacitor, so that the oscillation frequency of the oscillator circuit is increased, and the time for charging the sensing capacitor by the reference current in the sampling charge pump in the first step is shortened. Conversely, if the oscillator frequency is higher than the target frequency, the charge time of the sensing capacitor in the sampling charge pump is shortened, and the voltage across the sensing capacitor in the sampling charge pump is less than the reference voltage. The output end of the amplifying circuit will draw current from the sensing capacitor in the comparison charge pump to reduce the voltage at the two ends, and the output frequency of the oscillator circuit will be reduced. With the aid of such a negative feedback loop, the voltage across the sense capacitor in the charge pump will eventually be as equal as possible to the reference voltage in the first step, thus fixing the clock output frequency.
The reference voltages and reference currents used in the circuits are generated by the reference voltage generating circuit of fig. 3a and the reference current generating circuit of fig. 3b, respectively.
The reference current I output by the current reference generating circuit in the charge pump is sampled in the first step due to the existence of a negative feedback loop of the circuit REF Charging the induction capacitor to obtain the voltage V across the capacitor CAP Will eventually be as equal as possible to the reference voltage V REF Namely, the formula is satisfied:
finally, a fixed clock output frequency can be obtained:
as shown in fig. 4, the specific circuit of the amplifying circuit adopts a differential structure having a double-ended input and a single-ended output. The voltage across the sense capacitor in the sampling charge pump is connected to the positive input and the reference voltage is connected to the negative input, in this design, reference voltage V REF Is 1.2V. In FIG. 4, M1 to M8 have a W/L of 4 μm/4 μm, and the input NMOS M9, M10 has a W/L of 10 μm/500nm. In FIG. 4, the current idc is 1. Mu.A.
A specific circuit of the voltage-current conversion circuit is shown in fig. 5. The output current of the amplifying circuit charges a sensing capacitor in the comparison charge pump, and the voltage at two ends of the sensing capacitor is used as the input of the current starvation type ring oscillator circuit after passing through the low-pass filter circuit. The output current of the voltage-to-current conversion circuit is in a linear relationship with the input voltage of the current starved ring oscillator, such that the voltage of the input oscillator circuit is in a linear relationship with the frequency of the output.
A specific circuit of the current starved ring oscillator is shown in fig. 6. The current output of the voltage-to-current conversion circuit is connected to a current starving ring oscillator as its input to adjust the frequency. In fig. 6, vbias n is used to bias transistors MN 8-MN 10 of the same size to provide current to the current starved ring oscillator to ensure that the current starved ring oscillator can operate properly. Meanwhile, MP 1-MP 3 and MN 1-MN 3 have the same size respectively.
The output of the current starved ring oscillator circuit will be used as the divide-by-three circuit input shown in fig. 7 and the output of the divide-by-three circuit will be used as the signal to control the switch.
The actual simulation result is shown in fig. 8, and it can be seen in fig. 8 that the voltage across the sensing capacitor in the sampling charge pump is approximately equal to the reference voltage, and the voltage deviation is less than 0.6%. The example adopts a 0.18 mu m standard CMOS process, the frequency of the oscillator can reach 525KHz, the voltage precision is higher than 99.4 percent, and the frequency deviation is smaller than 0.6 percent in the temperature range of-40-125 ℃ in actual simulation, thereby realizing the invention targets of high precision, high stability and low power consumption.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (3)
1. A high-precision on-chip clock circuit is composed of a sampling charge pump circuit, an amplifying circuit, a comparison charge pump circuit, a low-pass filter circuit, an oscillator circuit, a frequency dividing circuit, a reference voltage generating circuit and a reference current generating circuit.
2. A high precision on-chip clock circuit as recited in claim 1, wherein: the oscillator circuit consists of a voltage-current conversion circuit and a current starvation type ring oscillator circuit, wherein the voltage-current conversion circuit linearly converts input voltage into output current, and the output current is input into the current starvation type ring oscillator circuit to obtain oscillation frequency which linearly changes with the input voltage.
3. A method of operating a high precision on-chip clock circuit according to claim 1 or 2, comprising the steps of:
the output signal of the oscillator circuit passes through the frequency dividing circuit to obtain a control signal with a pulse width of one oscillation period, and the control signal is used for controlling the reference current generated by the reference current generating circuit to charge a sensing capacitor in the sampling charge pump circuit;
the voltage at two ends of the induction capacitor is compared with the reference voltage generated by the reference voltage generating circuit through the amplifying circuit, the current output by the amplifying circuit charges the comparison charge pump circuit, the voltage output by the comparison charge pump circuit is input into the oscillator circuit after passing through the low-pass filter circuit, and the oscillation frequency of the oscillator is further regulated, so that the voltage at two ends of the induction capacitor is more approximate to the reference voltage;
the sampling charge pump circuit discharges;
and repeating the steps, and finally stabilizing the circuit in a state that the voltage at two ends of the induction capacitor in the sampling charge pump circuit is equal to the reference voltage, wherein the corresponding oscillation frequency is also stabilized in the ratio of the reference current to the product of the capacitance value of the induction capacitor in the sampling charge pump circuit and the reference voltage.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111668686.8A CN116418341A (en) | 2021-12-31 | 2021-12-31 | High-precision on-chip clock circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111668686.8A CN116418341A (en) | 2021-12-31 | 2021-12-31 | High-precision on-chip clock circuit |
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