CN116417907B - Laser chip with depletion type current non-injection layer and preparation method thereof - Google Patents
Laser chip with depletion type current non-injection layer and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
- H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/0607—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying physical parameters other than the potential of the electrodes, e.g. by an electric or magnetic field, mechanical deformation, pressure, light, temperature
- H01S5/0612—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying physical parameters other than the potential of the electrodes, e.g. by an electric or magnetic field, mechanical deformation, pressure, light, temperature controlled by temperature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/2205—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2304/00—Special growth methods for semiconductor lasers
- H01S2304/04—MOCVD or MOVPE
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The application provides a laser chip with a depletion type current non-injection layer, which sequentially comprises a cathode electrode, a substrate layer, a lower limiting layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper limiting layer, a ridge waveguide layer, an anode electrode and a third electrode along the epitaxial growth direction.
Description
Technical Field
The application relates to the technical field of semiconductor laser chips, in particular to a laser chip with a depletion type current non-injection layer and a preparation method thereof.
Background
Because of the advantages of high-power semiconductor laser chips, FP high-power semiconductor laser chips have been widely used in many fields such as production and processing, laser communication, medical cosmetology, automatic control, and military weapons. In view of the wide application prospect of the FP high-power semiconductor laser chip, various countries are accelerated to implement the development plan of the high-power semiconductor laser chip technology, and the high-power semiconductor laser chip industry is laid out, so that the FP semiconductor laser chip and related industries thereof are rapidly developed.
Cavity optical disaster damage (Catastrophic Optical Damage, COD) is a major challenge in the development of edge-emitting semiconductor laser chips. Aiming at how to inhibit COD at the cavity surface of a high-power semiconductor laser chip, the main flow method comprises the following steps: cavity surface passivation treatment technology, cavity surface coating technology, non-absorption window technology, induced current non-injection layer and current blocking layer technology. The technology of adding the current non-injection layer is shown in fig. 1, and has the characteristics of simple process, easy implementation and good process compatibility, so that the technology has become a main structural mode of the current high-power semiconductor laser chip.
Currently, the mainstream FP semiconductor laser chips include blue-violet laser chips using InGaN/GaN as an active region and AlInGaAs series red and infrared laser chips. The laser chip of whatever material and structure aims at reducing transverse current, improving reliability and current injection uniformity, reducing the temperature of an active region and improving device power.
However, the inventor of the present application has found in long-term research and development that the control effect of the non-injection structure of the existing laser chip design on the light field distribution still cannot be further away from the P-type layer, which causes light absorption of light in the P-region, thereby resulting in reduced efficiency and reduced reliability of the laser chip.
Disclosure of Invention
The application aims to provide a laser chip with a depletion type current non-injection layer for reducing the light absorption of a P region, aiming at the problem that the performance of the current FP laser chip device is greatly influenced by the light absorption of the P region.
The application provides a laser chip with a depletion type current non-injection layer, which is characterized by sequentially comprising a cathode electrode, a substrate layer, a lower limiting layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper limiting layer, a ridge waveguide layer, an anode electrode and a third electrode along an epitaxial growth direction, wherein the cathode electrode is arranged below the substrate layer, the anode electrode is arranged above the ridge waveguide, the front end surface of the ridge waveguide layer is recessed to form a step-shaped structure, the current non-injection layer is arranged on the step-shaped structure, the third electrode grows above the current non-injection layer, and the upper waveguide layer in the directions of two sides of the current non-injection layer forms a preset angle with the side surface of the upper limiting layer and the front end surface so as to form a gradual-change ridge height structure on two sides of the current non-injection layer.
The second aspect of the present application provides a method for manufacturing a laser chip having a depletion type current non-injection layer, characterized in that the method comprises epitaxially growing a GaAs FP laser chip epitaxial wafer by MOCVD; etching the ridge waveguide layer; gradient etching the upper limiting layer and the upper waveguide layer to enable the upper waveguide layer and the side surface of the upper limiting layer in the directions of two sides of the current non-injection layer to form a preset angle with the front end surface, and forming a gradient ridge height structure on two sides of the current non-injection layer; etching a step on the front end face side of the ridge waveguide; depositing a current non-injection layer on the step; plating a third electrode on the current non-injection layer; plating an anode electrode and a cathode electrode; depositing a passivation layer; plating a reflecting film on the rear end face, and plating an antireflection film on the front end face; finally, preparing the laser chip with the depletion type current non-injection layer.
The beneficial effects of the application are as follows:
the application makes gradual change ridge high structure through upper limit layer of current non-injection area of front end surface of gradient etching, upper waveguide layer, can make the whole light field down in place without electric injection, make the light field far away from P type layer, thus reduce loss scattering, reduce absorption, promote the device performance, and the application sets up the current non-injection layer in the ridge waveguide of laser chip, set up the third electrode above the current non-injection layer, lead to positive voltage, make the depletion layer of P type semiconductor below the insulating layer pass towards the active area, inhibit the carrier concentration of the part of the cavity, thus reduce the temperature of the cavity, reduce the non-radiative recombination, the light absorption relatively reduces, reduce the heat produced in the cavity, raise COD threshold, promote the device characteristic.
Drawings
FIG. 1 is a schematic diagram of a front view cross-section of a conventional laser chip described in the background art;
FIG. 2 is a schematic side view of a laser chip with a depletion type current non-injection layer according to the present application;
FIG. 3 is a schematic top view of a laser chip with a depletion type current non-injection layer according to the present application;
FIG. 4 is a schematic view of a gradient etched upper confinement layer and upper waveguide layer 3D structure of a laser chip with a depletion current non-injection layer of the present application;
FIG. 5 is a schematic diagram of a cross-sectional side view of a laser chip with a depletion current non-injection layer etched in the front end of a device ridge waveguide;
fig. 6 is a schematic diagram showing a side view cross-sectional structure of a growth current non-injection layer of a laser chip having a depletion current non-injection layer according to the present application.
The semiconductor device comprises a substrate layer 101, a lower limiting layer 103, a lower waveguide layer 104, a quantum well active layer 105, an upper waveguide layer 106, an upper limiting layer 107, a ridge waveguide layer 108, a cathode electrode 109, an anode electrode 110, a passivation layer 111, a current non-injection layer 112, a third electrode 113, a reflecting film 114, an antireflection film 115, photoresist sequence number rearrangement 116, a front end face 117, a rear end face 118 and a step.
Detailed Description
The application is further described below with reference to examples and drawings, which are not intended to limit the scope of the claims. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more; the terms "center," "longitudinal," "transverse," "upper," "lower," "left," "right," "inner," "outer," "front," "rear," "head," "tail," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used as references to orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and are not to be construed as limiting the application. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Referring to fig. 2 to 3, fig. 2 is a schematic side view cross-sectional structure of a laser chip with a depletion type current non-injection layer according to the present application, and fig. 3 is a schematic top view cross-sectional structure of a laser chip with a depletion type current non-injection layer according to the present application.
As shown in fig. 2 and 3, the laser chip sequentially includes a cathode electrode 108, a substrate layer 101, a lower confinement layer 102, a lower waveguide layer 103, a quantum well active layer 104, an upper waveguide layer 105, an upper confinement layer 106, a ridge waveguide layer 107, an anode electrode 109 and a third electrode 112 along the epitaxial growth direction, the cathode electrode 108 is disposed below the substrate layer 101, the anode electrode 109 is disposed above the ridge waveguide layer 107, the front end surface 116 of the ridge waveguide layer 107 is recessed to form a step structure, a current non-injection layer 111 is disposed on the step structure, the third electrode 112 is disposed above the current non-injection layer 111, and the sides of the upper waveguide layer 105 and the upper confinement layer 106 in the directions of two sides of the current non-injection layer 111 form a preset angle with the front end surface 116, so as to form a gradual ridge height structure on two sides of the current non-injection layer 111.
It can be appreciated that the third electrode alone can reduce the thickness of the current non-injection layer 111, so as to avoid unnecessary light scattering loss after the light field contacts with the current non-injection layer 111, and reduce the device performance.
In some embodiments, the sides of the upper waveguide layer 105 and the upper confinement layer 106 are at a predetermined angle to the front end surface 116 to form a graded ridge height structure, further comprising: the upper confinement layer 106 forms a predetermined angle with a portion of the side surface of the upper waveguide layer 105 and the front end surface 116.
In some embodiments, the lower surface length of upper waveguide layer 105 differs from the upper surface length of upper confinement layer 106 by no more than the length of the current non-injection layer.
In some embodiments, the graded ridge height structures on both sides of the current non-implanted layer 111 are symmetrically arranged.
In some embodiments, the laser chip further includes a passivation layer 110, a reflective film 113, and an anti-reflection film 114, the passivation layer 110 covers the laser chip upper, lower, left, and right surfaces except for the cathode electrode 108, the anode electrode 109, the third electrode 112, the front facet 116, and the back facet 117, and the laser chip back facet is coated with the reflective film 113 and the laser chip front facet is coated with the anti-reflection film 114.
In some embodiments, the material of the current non-injection layer 111 is Al 2 O 3 、SiN、SiO 2 And the thickness is 10-50 a nm a, and the third electrode 112 is made of Cr/Au, ti/Au or Ni/Au.
In some embodiments, the substrate layer 101 is specifically GaAs with a thickness of 200nm; the lower confinement layer 102 is made of AlGaAs and has a thickness of 0.3 μm; the lower waveguide layer 103 is made of AlGaAs and has a thickness of 0.5-3 μm; the material of the quantum well active layer 104 is AlGaAs well layer-AlGaAs barrier layer alternately grown, and the thickness is 0.1 μm; the upper waveguide layer 105 is made of AlGaAs and has a thickness of 0.1-3 μm; the upper confinement layer 106 is made of AlGaAs and has a thickness of 0.3-1 μm; the ridge waveguide layer 107 is made of AlGaAs and has a thickness of 280nm; the passivation layer 110 is made of SiO 2 The thickness is 50nm-500nm; the cathode electrode 108 and the anode electrode 109 are made of Cr/Au, ti/Au or Ni/Au; the reflectance of the reflection film 113 is 50% to 100%, and the reflectance of the antireflection film 114 is 10% or less.
The application also provides a preparation method of the laser chip with the depletion type current non-injection layer, which is characterized in that the method comprises the steps of epitaxially growing the GaAs FP laser chip epitaxial wafer through MOCVD; etching the ridge waveguide layer 107; gradient etching the upper limiting layer 106 and the upper waveguide layer 105 so that the upper waveguide layer 105 and the side surface and the front end surface 116 of the upper limiting layer 106 in the directions of two sides of the current non-injection layer form a preset angle, and a gradient ridge height structure is formed on two sides of the current non-injection layer; etching a step on the front end face side of the ridge waveguide; depositing a current non-implanted layer 111 on the step; plating a third electrode 112 on the current non-injection layer 111; plating an anode electrode 109 and a cathode electrode 108; depositing a passivation layer 110; the rear end surface 117 is coated with a reflective film 113, and the front end surface 116 is coated with an antireflection film 114; finally, preparing the laser chip with the depletion type current non-injection layer.
At this time, referring to fig. 4-6, fig. 4 is a schematic view of a 3D structure of an upper confinement layer and an upper waveguide layer of a gradient etching laser chip with a depletion type current non-injection layer according to the present application; FIG. 5 is a schematic diagram of a cross-sectional side view of a laser chip with a depletion current non-injection layer etched in the front end of a device ridge waveguide; fig. 6 is a schematic diagram of a side view cross-sectional structure of a current non-injection layer for a laser chip growth with a depletion current non-injection layer according to the present application.
Specifically, for example: the GaAs substrate 101 is placed in a MOCVD equipment growth chamber, a lower limiting layer 102, a lower waveguide layer 103, a quantum well active region 104, an upper waveguide layer 105, an upper limiting layer 106 and a ridge waveguide layer 107 are sequentially grown, an epitaxial structure of the GaAs FP laser chip is obtained, the ridge waveguide 107 is prepared through photoetching and dry etching processes, the height of the ridge waveguide is 280nm, the upper limiting layer 106 and the upper waveguide layer 105 are subjected to gradient etching through photoetching and dry etching processes, the upper limiting layer 106 of a non-ridge waveguide part of the front end face 116 is subjected to gradient etching, and the upper waveguide layer 105 of a non-ridge waveguide part of the front end face 116 is subjected to partial etching. Preparing a step of 10-50 nm on the front end face of the ridge waveguide by dry etching by taking photoresist as a mask through photoetching, then depositing SiN with the same thickness as the step depth as a current non-injection layer 111 through PECVD or magnetron sputtering without removing the photoresist, stripping SiN, and keeping SiN only on the step of the front end face; the cathode electrode 108, the anode electrode 109 and the third electrode 112 were fabricated by photolithography and an e-beam evaporation process, and SiO with a thickness of 300nm was deposited by PECVD 2 Passivation layer 110 and removal of SiO on the ridge waveguide surface by photolithographic techniques and using BOE etchant 2 A passivation layer forming an electric injection window; a reflection film 113 with a reflection coefficient of 50% -100% is plated on the rear end face of the active area of the device by chemical plating, electroplating and the like, and an antireflection film 114 with a reflection coefficient of less than or equal to 10% is plated on the front end face of the device.
In the above embodiment, the upper limiting layer of the non-ridge waveguide part of the front end surface is etched in a gradient manner, and the upper waveguide layer of the non-ridge waveguide part of the front end surface is etched in a partial manner to manufacture the graded ridge structure, so that the whole light field can be pressed down at the place without electric injection, and the light field is far away from the P-type layer, thereby reducing loss scattering, reducing absorption and improving the device performance. By arranging the current non-injection layer and the third electrode on the laser chip, the depletion layer of the p-type semiconductor below the current non-injection layer is pushed to the active region, and the carrier concentration of the cavity surface part is restrained, so that the temperature of the cavity surface is reduced, and the reliability and the photoelectric efficiency of the device are enhanced.
In addition, the effect of the laser chip is affected by the material, process and dimension variation of the waveguide layer, the confinement layer and the active layer in the laser chip, so that the laser chip has an optimal effect due to the fact that the laser chip needs to be properly optimized according to different device structures and different process methods.
The above examples are only preferred embodiments of the present application, it being noted that: it will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles of the present application, and these equivalents should be substituted for the claims set forth herein without departing from the scope of the application as defined by the appended claims and their equivalents.
Claims (6)
1. The laser chip with the depletion type current non-injection layer is characterized by sequentially comprising a cathode electrode (108), a substrate layer (101), a lower limiting layer (102), a lower waveguide layer (103), a quantum well active layer (104), an upper waveguide layer (105), an upper limiting layer (106), a ridge waveguide layer (107), an anode electrode (109) and a third electrode (112) along the epitaxial growth direction, wherein the cathode electrode (108) is arranged below the substrate layer (101), the anode electrode (109) is arranged above the ridge waveguide layer (107), the front end face (116) of the ridge waveguide layer (107) is recessed to form a step-shaped structure, the current non-injection layer (111) is arranged on the step-shaped structure, the third electrode (112) is arranged above the current non-injection layer (111), and the upper waveguide layer (105) and the side faces of the upper limiting layer (106) at two sides of the current non-injection layer (111) form preset angles with the front end face (116) so as to form gradient high ridge structures at two sides of the current non-injection layer (111);
the third electrode is used for applying positive voltage;
the difference between the length of the lower surface of the upper waveguide layer (105) and the length of the upper surface of the upper confinement layer (106) does not exceed the length of the current non-injection layer (111).
2. The laser chip with depletion current non-injection layer according to claim 1, characterized in that the sides of the upper waveguide layer (105) and the upper confinement layer (106) are at a predetermined angle to the front facet (116) to form a graded ridge height structure, further comprising: the upper limiting layer (106) and a part of the side surfaces of the upper waveguide layer (105) form a preset angle with the front end surface (116).
3. A laser chip with a depletion mode current non-injection layer as claimed in claim 1, characterized in that the graded ridge height structures on both sides of the current non-injection layer (111) are symmetrically arranged.
4. A laser chip with depletion current non-injection layer as claimed in claim 2, characterized in that the laser chip further comprises a passivation layer (110), a reflective film (113) and an antireflection film (114), the passivation layer (110) covers the laser chip upper, lower, left and right surfaces except for the cathode electrode (108), anode electrode (109), third electrode (112), the front end surface (116) and the back end surface (117) of the ridge waveguide layer (107), and the laser chip back end surface is plated with the reflective film (113), and the laser chip front end surface is plated with the antireflection film (114).
5. A laser chip with depletion type current non-injection layer as claimed in claim 1, characterized in that the current non-injection layer (111) material is Al 2 O 3 、SiN、SiO 2 The thickness is 10-50 and nm, and the third electrode (112) is made of Cr/Au, ti/Au or Ni/Au.
6. A laser chip with depletion type current non-injection layer as set forth in claim 4, wherein,
the substrate layer (101) is made of GaAs and has a thickness of 200nm;
the lower limiting layer (102) is made of AlGaAs and has a thickness of 0.3 mu m;
the lower waveguide layer (103) is made of AlGaAs and has a thickness of 0.5-3 mu m;
the quantum well active layer (104) is made of AlGaAs well layers-AlGaAs barrier layers alternately grown, and the thickness of the quantum well active layer is 0.1 mu m;
the upper waveguide layer (105) is made of AlGaAs and has a thickness of 0.1-3 mu m;
the upper limiting layer (106) is made of AlGaAs and has a thickness of 0.3-1 mu m;
the ridge waveguide layer (107) is made of AlGaAs and has a thickness of 280nm;
the passivation layer (110) is made of SiO 2 The thickness is 50nm-500nm;
the cathode electrode (108) and the anode electrode (109) are made of Cr/Au, ti/Au or Ni/Au;
the reflectivity of the reflection film (113) is 50% -100%, and the reflectivity of the antireflection film (114) is less than or equal to 10%.
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| WO2012150132A2 (en) * | 2011-05-02 | 2012-11-08 | Osram Opto Semiconductors Gmbh | Laser light source |
| CN107851952A (en) * | 2015-06-05 | 2018-03-27 | I·B·彼得雷斯库-普拉霍瓦 | Launching semiconductor laser type device |
| CN115000805A (en) * | 2022-07-18 | 2022-09-02 | 度亘激光技术（苏州）有限公司 | Chip and semiconductor laser |
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| US9755402B2 (en) * | 2010-06-28 | 2017-09-05 | Iulian Basarab Petrescu-Prahova | Edge emitter semiconductor laser type of device with end segments for mirrors protection |
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| JP2002057406A (en) * | 2000-08-14 | 2002-02-22 | Nec Corp | Edge non-injection type semiconductor laser and its manufacturing method |
| JP2010192769A (en) * | 2009-02-19 | 2010-09-02 | Renesas Electronics Corp | Semiconductor laser device and method of manufacturing the same |
| WO2012150132A2 (en) * | 2011-05-02 | 2012-11-08 | Osram Opto Semiconductors Gmbh | Laser light source |
| CN107851952A (en) * | 2015-06-05 | 2018-03-27 | I·B·彼得雷斯库-普拉霍瓦 | Launching semiconductor laser type device |
| CN115000805A (en) * | 2022-07-18 | 2022-09-02 | 度亘激光技术（苏州）有限公司 | Chip and semiconductor laser |
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