CN1164147A - Third order A-D converter - Google Patents
Third order A-D converter Download PDFInfo
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- CN1164147A CN1164147A CN 96104901 CN96104901A CN1164147A CN 1164147 A CN1164147 A CN 1164147A CN 96104901 CN96104901 CN 96104901 CN 96104901 A CN96104901 A CN 96104901A CN 1164147 A CN1164147 A CN 1164147A
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Abstract
A three-stage A/D converter features that a low-resolution comparator is first used to compare analog input signals with a low-resolution reference to output a low-resolution digital code, a middle-resolution comparator is then used to compare analog input signals with middle-resolution reference to output a middle-resolution digital code, a high-resolution comparator is next used to compare analog input signals with high-resolution reference to output a high-resolution digital code, and an encoder is finally used to encode said three digital output codes to obtain final digital output code.
Description
The present invention relates to A/D converter and conversion method thereof, more particularly, is about multistage run-in index transducer.It uses first switching stage to decide the rough range of input voltage, and follow-up switching stage solves the analog input signal again to more accurate increment.The present invention can be applicable to the field of videl signal and digital signal processing.
The digital processing of analogue data and a kind of technology of the application need of transmission convert their analog form to the representation mode of numeral.The kind of known A/D converter has successive approximation type, and it produces a numeral output, is to use D/A to produce with trial and error and approaches the accurate signal in input position; Another is comparator formula in parallel or flash type transducer, and its utilizes the relation of more a plurality of reference voltages and input voltage, and the result is exported by codimg logic, and in each conversion, digital code is represented the reference voltage near input voltage.Fig. 1 is the flash type A/D converter.In general, the part of output is the binary code of being set up by codimg logic 30, therefore can provide input signal n the resolution of bit.This framework needs 2 usually
n Individual reference voltage 10 and 2
nIndividual comparator 20.When the resolution of the transducer of this form increases (the bit number of output increases), the design intractable that will become.
In order to simplify the design of flash type A/D converter, known have two kinds of technology to use.The technology of these two kinds of multistage conversions can be used for finishing the conversion of mould/number.In first kind of technology, as U.S. Patent No. 5302869 (people such as Hosotani), U.S. Patent No. 5389929 (people such as Nayebi), U.S. Patent No. 5353027 (people such as Vorenkamp), U.S. Patent No. 5369309 (people such as Bacrania), shown in the U.S. Patent No. 5387914 (Mangelsdof), the first order is the flash type A/D converter of rough resolution; The second level with D/A is then adjusted the reference voltage of voltage comparator and is finished the better conversion of resolution.The result of these two kinds of conversions is encoded into numerical digit carry-out bit tuple again, with the size of representative simulation input voltage.In second kind of technology, as U.S. Patent No. 5291198 (people such as Dingwall), U.S. Patent No. 5223836 (Komatsu), U.S. Patent No. 5400029 (Kobayashi), U.S. Patent No. 4733217 (Dingwall), shown in the U.S. Patent No. 5349354 (people such as Ho), the technology of a plurality of switching stages of this use, be to utilize the result of decision logic according to last comparative degree, with reference voltage suitable switch to each the level.
Technology with second kind of multistage conversion is an example, please refer to Fig. 2, and it is the circuit diagram of United States Patent (USP) NO.4903028 (Fukashima).It produces one group of voltage source 1 earlier, by V
REFBOT(minimum) increases to V gradually
REFTOP(peak) is to set up the conversion range of voltage input (Vin).The 1a of one group of Vin that divides domain comparator 2 to be connected to input voltage roughly and set up, one group of reference voltage of 1b rough range in the interval that separates.The output 5 of rough branch domain comparator is the input of control logic and switch element 3, and unit 3 can be connected to one group of trickle minute domain comparator 4 the branch territory scope 1 of suitable reference voltage.Set of reference voltages 1a is divided into trickleer increment, becomes numeral output (D0, D1, D2..., maximum resolution Dn) to set up conversion Vin.When Vin changes, the value of output code or divide the output code 5 of domain comparator also to change roughly, and also control logic and switch element 3 also move trickle minute domain comparator 4 to the next one and divide territory scope (from 1a to 1b).
Because element is selected and the tolerance limit difference of processing procedure drift, the output code 5 that divides domain comparator 2 roughly may be wrong.In order to check this mistake, just need extra trickle minute domain comparator 4a and 4b, the size that they will look Vin is put the next door at minute territory 1a or 1b respectively.The output code of extra trickle minute domain comparator 4a and 4b is an error-correcting code 7, its with rough branchs territory sign indicating number 5 deliver to output encoder logic 8 with the numeral output of decision input voltage vin represent yard (D0, D1, D2 ... Dn).
Utilize foregoing technology, need two grouping error testing circuits.And error correcting function is when the compare cycle of each trickle minute domain comparator, one side only can make having an effect of rough minute territory.The extra power of this structure consumption, and increase the actual additional complexity of implementing.In order to reduce the number of extra comparator, and simplify the complexity of actual framework, with the TaiWan, China patent in the same applicant's of the present invention the application, application number is the 8410807 No. 0, promptly as shown in Figure 3, use one group of embedded rough minute domain comparator 140 to reach these purposes.The reference code that embedded rough minute domain comparator produces determines the suitable term of reference of trickle minute domain comparator 160.By rough minute domain comparator, embedded rough minute domain comparator, and the sign indicating number that trickle minute domain comparator obtains is respectively 170,180,190, is encoded into digital output code again.How selecting the input reference voltage 131 of embedded rough minute domain comparator 140, is to select logic and switch 130 by embedded rough minute territory, divides the output 170 of domain comparator to decide with reference to rough.And how to select the reference voltage 151 of trickle minute domain comparator, and be to select logic and switch 150 by thin differential domain, divide the output 170 of domain comparator and the output 180 of embedded rough minute domain comparator to decide with reference to rough.
An object of the present invention is to reduce the complexity of actual enforcement A/D converter in parallel; Another object of the present invention then is in order to reduce power consumption, and unnecessary circuit is removed.
In order to finish above purpose, third order A-D converter has the A/D converter of a rough resolution, one rough A/D converter, and a trickle A/D converter.Sampling is grasped the aanalogvoltage of an input with holding circuit at different time points, and to keep this analog input voltage be rough A/D converter, the input signal source of inferior rough A/D converter and trickle A/D converter.Other has a reference voltage generator then to be connected between two reference voltage sources, can produce one group of reference voltage.
Rough A/D converter is connected to the analog input signal of sampling, and it compares with one group of rough reference voltage from reference voltage generator again, produces a rough digital code then.This rough digital code is admitted to reference voltage and selects Logical processing unit, and it is connected with reference voltage selection switch, to select the reference voltage in one group rough branch territory.
Inferior rough A/D converter is connected to the input signal of sampling, and it compares with time rough reference voltage, produces rough digital code one time.Then, rough digital code of this time and rough digital code, supply reference voltage is selected Logical processing unit to make and is used for selecting reference voltage selection switch, produces one group of trickle reference voltage from reference voltage.
Trickle A/D converter is connected to the input signal of sampling, and it and trickle reference voltage are compared, and produces a trickle digital code.
Rough digital code, inferior rough digital code, and trickle digital code produces the output digital code in the conversion of output encoder processing unit.This output digital code is a binary digit, the size of representative simulation input voltage.
The present invention has 8 accompanying drawings:
Fig. 1 illustrates circuit diagram parallel or the preceding case technology of flash type A/D converter;
Fig. 2 illustrates the circuit diagram of the preceding case technology of two stepwise A/D converters;
Fig. 3 illustrates the circuit diagram of the preceding case technology of embedded A/D converter;
The functional block diagram of Fig. 4 preferred embodiment of the present invention;
The circuit diagram of reference voltage generator among Fig. 5 the present invention;
The key diagram of reference voltage selection mode among Fig. 6 the present invention;
Fig. 7 converting analogue signal of the present invention is to the flow chart of digital code method;
Fig. 8 change-over period sequential chart of the present invention.
The present invention discloses a preferred embodiment.
Please refer to Fig. 4, analog input voltage Vin400 is connected to sampling and holding circuit 410, periodically to (Vin) 400 sampling and be maintained the analog input signal voltage 425 of sampling.
Reference voltage generator 500 is connected between reference voltage source Vref1 450 and the Vref2 475.Reference voltage generator 500 can produce one group of reference voltage 505, and they increase gradually from Vref2 475 to Vref1 450.And the recruitment of reference voltage 505 can be determined by following formula: (Vref1-Vref2)/2
nWherein n is the bit number of digital output code 590.
These reference voltages 505 connect reference voltage switch networking 510.Rough set of reference voltages 512 is by acquisition in the reference voltage 505, and often can be connected to rough minute domain comparator 520.The analog input voltage signal 425 of sampling is organized rough reference voltage 512 relatively with this.Result relatively is rough temperature size 522 (thermometer code), and the temperature size is a kind of binary code, and the formation of sign indicating number is made up of continuous numeral, and when sign indicating number increased, continuous 1 number also increased, for example:
The minimum sign indicating number of 0000 value
0001
0011
0111
The highest sign indicating number of 1111 values.
Rough temperature size 522 is connected to reference voltage and selects Logical processing unit 570, after treatment, connects suitable switch selection wire 572.These switch selection wires 572 are connected to reference voltage switch networking 510, to start suitable switch, connect one group of reference voltage 505, produce time rough reference voltage 514.
Inferior rough reference voltage is connected to time rough domain comparator 530 and 540 that divides.The analog input voltage 425 of sampling compares with time rough reference voltage 514 in inferior coarse comparator 530 and 540, produces time rough temperature size 532 and 542.Inferior rough temperature size 532 and 542 is connected to time rough encoder 535 and 545 respectively.And inferior rough encoder will produce time rough numerical digit sign indicating number 537 and 547.
Inferior rough numerical digit sign indicating number 537 and 547 is connected to reference voltage and selects Logical processing unit 570.Reference voltage selects Logical processing unit 570 to handle rough sign indicating number 522 and time rough sign indicating number 537,547, sets suitable switch selection wire 572.Switch selection wire 572 is connected to the voltage switch networking to start suitable switch, connects one group of reference voltage 505, to produce trickle reference voltage 516.
Trickle reference voltage 516 is connected to trickle voltage comparator 550 and 560.The analog input voltage 425 of sampling is brought with trickle reference voltage 516 and is compared, and produces trickle temperature size 552 and 562.Trickle temperature size 552 and 562 is connected to trickle encoder 555 and 565.Trickle encoder 555 and 565 conversion trickle temperature sizes 552 and 562 produce trickle digital code 557 and 567.
Rough digital code 585, inferior rough digital code 537,547 and trickle digital code 557 and 567 are delivered to output encoder logic 580, convert output digital code 590 therein to.Output digital code 590 is a kind of binary digits, the size of representative simulation input voltage (Vin) 400.Digital code 585 can one group of binary digit of resolved one-tenth most significant digit unit.Inferior rough digital code 537 and 547 then resolved be the effective bit in centre of one group of binary digit.Last trickle digital code 557 and 567 are resolved to be the least significant bit (LSB) unit of one group of binary digit.Trickle digital code 557 and 567 also provides the error correction factor to the effective bit in centre.
The framework of A/D converter has a pair of coarse comparator 530,540 and trickle comparator 550,560 among Fig. 4, and a pair of rough encoder 535,545 and trickle encoder 555,565.So can allow the staggered mode of handling to make sampling faster with holding circuit 410 sampling Vin400 speed.First sampling point can be by inferior coarse comparator 530, inferior rough encoder 535, and trickle comparator 550 and trickle encoder 555 are handled.Next sampling point is then by inferior coarse comparator 540, inferior rough encoder 545, and trickle comparator 560 and trickle encoder 565 are handled.This staggered processing is constantly carried out, and to produce continuous digital code, represents Vin400.
Fig. 5 description references voltage generator (500 among Fig. 4).Reference voltage supplies device Vref1 is connected to resistance r111, and reference voltage supplies device Vref2 then is connected to r444.The resistance r11 of these series connection, r12 ..., r443 and r444 form the voltage dividing potential drop, resistance r111, the r12 of these series connection, r443, and each tie point of r444 on, be a reference voltage (505 among Fig. 4).
The reference voltage of coarse comparator (520 among Fig. 4) is created in 1000A, 1000B, 1000C and 1000D.These reference voltages directly are connected with coarse comparator (520 among Fig. 4).Effectively the reference voltage (530 among Fig. 4,540) of time coarse comparator be 1100A, 1100B ... 11000 and 1100P.These tie points are to be selected Logical processing unit (570 among Fig. 4) and connect time coarse comparator (530 among Fig. 4,540) via reference voltage switch networking (510 among Fig. 4) to decide by switch.All by series resistance r111, r112 ... the reference voltage that r443 and r444 produce can effectively connect trickle comparator (550 among Fig. 4 and 560), but they are gathered, and will connect via reference voltage switch networking (510 among Fig. 4) simultaneously as 1200 sections.
If the size of analog input signal (400 among Fig. 4) is position at X with respect to reference voltage generator, then coarse comparator (520 among Fig. 4) is output as 0011.This just illustrate series resistance r111, r112 ..., the 3rd section of the reference voltage generator that constitutes of r443 and r444, be to be used for connecting time rough reference voltage (514 among Fig. 4) section.Be connected to time coarse comparator (for example 535 among Fig. 4) 1100I, 1100J, 1100K and 1100L via reference voltage switch networking (510 among Fig. 4).Inferior coarse comparator is output as 0011.This expression series resistance r111, r112 ... r443 and r444 section 1200 wherein is reference voltage ranges that correct trickle comparator (for example 550 among Fig. 4) uses.The output of trickle comparator (550 among Fig. 4) will be 0000111.
Wherein one section of Fig. 6 account for voltage generator 700.Point 741 to 742 in the voltage generator is to be selected by the resolution of rough temperature size (522 among Fig. 4).In the 741-742 section, inferior rough reference point is 731,721 and 732.The reference voltage position of trickle voltage comparator (550 among Fig. 4,560) will be looked the position of size in this section of Vin (400 among Fig. 4) and decide.If Vin (400 among Fig. 4) is less than reference voltage 731, then trickle reference voltage (516 among Fig. 4) becomes section 701.If Vin (400 among Fig. 4) greater than reference voltage 731, becomes section 702 less than the then trickle reference voltage of reference voltage 721 (516 among Fig. 4).If Vin (400 among Fig. 4) is greater than reference voltage 721, and less than reference voltage 732, then trickle reference voltage (516 among Fig. 4) becomes section 703.If Vin (400 among Fig. 4) is greater than reference voltage 732, then trickle reference voltage (516 among Fig. 4) becomes section 704.
Fig. 7 becomes the flow chart of digital output signal 660 conversion methods for an analog input signal of conversion (Vin) 600.The first step 610 is sampling and the maintenance of Vi600; Second goes on foot 620 Vi600 for sampling compares with rough reference voltage.After obtaining rough digital signal 621 and 623, inferior rough reference voltage also selected 625.Next step is time rough relatively 630 and 635, and wherein the Vi600 that is taken a sample compares with selected rough reference voltage.Inferior rough digital signal 632 and 637 and rough digital signal 621 and 623 make and be used for selecting trickle reference voltage 640.Trickle then reference voltage again with the Vi600 of sampling relatively 645 and 650, to produce trickle digital signal 647 and 652 and the error correction signal 649 and 654 of inferior rough digital signal.Rough digital signal 621 and 623, inferior rough digital digital signal 632 and 637, error correction signal 649 and 654, and trickle digital signal 647 and 652 encodes 655, generation output code 660.
This method comprises two paths, and implement at the sampling point of first Vi600 in article one path 670.Implement at the sampling point of second Vi600 in second path 680.Article one, path 670 or 680 staggered selections cooperate Vin600 different sampling points continuously.It is the twice of respective paths that this staggered processing mode can allow the sampling rate of Vin600.
The sequential chart of A/D converter of the present invention sees Fig. 8.Analog input signal Vin805 is in 1 o'clock cycle of clock signal 800 sampling 803.The signal 812,822 and 832 of sampling remains on rough A/D converter 810 respectively, the rough A/D converter 820 of first time, and first trickle A/D converter 830.First is rough relatively 813 finishes in the cycle 2 of clock signal 800.First time is rough relatively 823 to be finished in the cycle 3 of clock signal 800.In the same cycle, second sampling point 807 of Vin805 also finished sampling action.817,842 and 852 of sampling remain on 810, the second rough A/D converters 840 of rough A/D converter respectively, and among the trickle A/D converter 850.First trickle comparison 833 and second rough comparison 817 were finished in the cycle 4 of clock signal 800.Roughly relatively 843 in the cycle 5 of clock signal 800, finish for second time.Simultaneously, first output mould/several 870 become effectively, and are maintained to the cycle 6 of clock signal 800.And second trickle comparison 853 also finished in the cycle 6 of clock signal 800.Second dateout 880 became effectively in the cycle 7 of clock signal 800.
The staggered handling procedure of this sequential explanation conversion.Constantly repeat this conversion, analog input voltage is carried out with the sampling rate that doubles single conversion.
Though the present invention represents with preferred embodiment especially and describes, and knows this area skill person and should understand, and on form or the detailed content different variations can be arranged, but still not break away from spirit of the present invention and category.
Claims (25)
1, a kind of with analog input voltage signal be converted to output digital code third order A-D converter, it is characterized in that it comprises:
A) sample-and-hold device was put the analog input voltage signal sampling in cycle time, and kept the analog input signal after this sampling in transfer process;
B) reference voltage generator is coupled in the first reference voltage source V
REF1With the second reference voltage source V
REF2Between, from the first above-mentioned voltage source V
REF1With second voltage source V
REF2Between produce one group of reference voltage;
C) reference voltage selection switch networking is connected with above-mentioned one group of reference voltage;
D) rough A/D converter of resolving is with the analog input signal coupling after the above-mentioned sampling, analog input signal after the above-mentioned sampling is converted to time roughly digital code;
E) one rough analytic simulation digital quantizer is with the analog input signal coupling after the above-mentioned sampling, analog input signal after the above-mentioned sampling is converted to time roughly digital code;
F) trickle parsing A/D converter is with the analog input signal coupling after the above-mentioned sampling, so that analog input signal after the above-mentioned sampling is converted to trickle digital code;
G) reference voltage is selected logic device, with above-mentioned reference voltage selection switch networking coupling, to select to be coupled to time rough and trickle A/D converter from one group of above-mentioned reference voltage;
H) output encoder device converts above-mentioned rough digital code, inferior rough digital code and trickle digital code to an output digital code, and this output digital code has n bit.
2, transducer as claimed in claim 1 is characterized in that this reference voltage generator comprises first resistance, is connected with above-mentioned first reference voltage source; A tail end resistance is connected to the second above-mentioned reference voltage source; And one group the serial connection resistance be coupled in this first and tail end resistance between, the contact voltage between series resistor is one of one group of above-mentioned reference voltage.
3, transducer as claimed in claim 2 is characterized in that the difference of the adjacent two contact voltages of reference voltage generator is (V
REF1-V
REF2)/2
n
4, transducer as claimed in claim 1, it is characterized in that exporting digital code is a binary digit, comprises one group of most significant digit unit, one group of middle effectively bit and one group of least significant bit (LSB) unit.
5, transducer as claimed in claim 1 is characterized in that resolving A/D converter roughly comprises:
A) first group of voltage comparator, wherein each comparator comprises a voltage input end, with the analog input voltage signal coupling after the above-mentioned sampling; A reference voltage end is with one group of above-mentioned one of them coupling of reference voltage; A reference voltage end is with one group of above-mentioned one of them coupling of reference voltage; An output relatively, on comparator output signal is arranged; And a voltage comparator device, producing above-mentioned comparator output signal, this comparator output signal during greater than the reference voltage in reference voltage end, is first attitude at analog input signal after the sampling of input; And when analog input signal is less than the reference voltage of reference voltage end after the sampling of input, then be second attitude;
B) rough digital encoder is converted to above-mentioned rough digital code in order to the comparator output signal with this first group of voltage comparator, to represent the rough approximation of the analog input signal size after this sampling.
6, transducer as claimed in claim 5 is characterized in that described rough digital code forms the most significant digit unit of this output digital code.
7, transducer as claimed in claim 1 is characterized in that described reference voltage selection switch networking comprises:
A) one group with rough parsing selector switch, first subclass of one group of above-mentioned reference voltage is selected be coupled to the above-mentioned time rough A/D converter of resolving;
B) one group of trickle parsing selector switch is to select to be coupled to above-mentioned trickle parsing A/D converter with second subclass of one group of above-mentioned reference voltage.
8, transducer as claimed in claim 1 is characterized in that time rough A/D converter of resolving comprises:
A) second group of voltage comparator, wherein each comparator comprises a voltage input end, with the analog input voltage signal coupling after the above-mentioned sampling; A reference voltage end is with one group time above-mentioned rough one of them coupling of reference voltage; An output relatively, on comparator output signal is arranged; And voltage comparator device, produce this comparator output signal, this comparator output signal is at analog input signal after the sampling of input during greater than time rough reference voltage in reference voltage end, it is first attitude, and when analog input voltage signal is less than time rough reference voltage of reference voltage end after the sampling of input, then be second attitude;
B) inferior rough resolution digital encoder is converted to rough digital code above-mentioned time in order to the comparator output signal with this second group of voltage comparator, with the precise and tiny difference in centre of the rough approximation of representing the analog input signal size after this sampling.
9, transducer as claimed in claim 8 is characterized in that secondly rough digital code forms the effective bit in centre of above-mentioned digital output code.
10, trickle parsing A/D converter as claimed in claim 1 comprises:
A) the 3rd group of voltage comparator, wherein each comparator comprises a voltage input end, with the analog input voltage signal coupling after the above-mentioned sampling; A reference voltage end is with one group of above-mentioned trickle reference voltage coupling; An output relatively, on comparator output signal is arranged; And voltage comparator device, produce above-mentioned comparator output signal, the analog input signal of this comparator output signal after the sampling of input is first attitude during greater than the trickle reference voltage of this reference voltage end, and be second attitude when analog input voltage is less than the trickle reference voltage of this reference voltage end after the sampling of input, and
B) trickle resolution digital encoder is converted to above-mentioned trickle digital code in order to the comparator output signal with the 3rd group of comparator, with the trickle decision of the rough approximation of representing the analog input signal after this sampling.
11, trickle parsing A/D converter as claimed in claim 10 is characterized in that trickle digital code forms the correction factor of the above-mentioned effective bit of least significant bit (LSB) unit and this centre.
12, transducer as claimed in claim 7 is characterized in that described reference voltage selection logic device comprises:
A) rough digital code input is connected with this rough D/A;
B) one rough digital code input is connected with the rough digital A/D converter of this time;
C) one rough position of the switch determination device is according to the above-mentioned time rough action of resolving selector switch of above-mentioned rough digital code decision;
D) trickle position of the switch determination device is according to the action of above-mentioned rough digital code and time trickle parsing selector switch that rough digital code decision is above-mentioned.
13, a kind of analog input signal is converted to the third order A-D converter of digital output code, it is characterized in that it comprises:
A) sample-and-hold device is taken a sample to analog input voltage signal with second sampling time point in first sampling of cycle staggering, and keeps the analog input signal after this sampling in transfer process;
B) reference voltage generator is coupled in the first reference voltage source V
REF1With the second reference voltage source V
REF2Between, from the first above-mentioned voltage source V
REF1With second voltage source V
REF2Between produce one group of reference voltage;
C) reference voltage selection switch networking is connected with above-mentioned one group of reference voltage;
D) rough voltage comparator device is with the analog input signal coupling after this sampling, above-mentioned analog input signal is converted to one group of rough temperature size;
E) rough encoder was converted to one group of rough digital code in order to should organize rough temperature size, to represent the rough approximation of this sampling back analog input signal size;
F) for the first time rough voltage comparator device with the analog input signal coupling after this sampling, is converted to one group of for the first time rough temperature size with the analog input signal after will taking a sample;
G) for the second time rough voltage comparator device with the analog input signal coupling after this sampling, is converted to one group of for the second time rough temperature size with the analog input signal after will taking a sample;
H) for the first time rough encoder is in order to be converted to rough digital code first group time with first group time above-mentioned rough temperature size;
I) for the second time rough encoder is in order to be converted to rough digital code second group time with second group time above-mentioned rough temperature size;
J) first group of micro voltage comparison means is connected with analog input signal after this sampling, is one group of first temperature size in order to should import analog signal conversion;
K) the second trickle voltage comparator device is connected with analog input signal after this sampling, is one group of second temperature size should import analog signal conversion;
L) the first trickle encoder is in order to be converted to first group of trickle digital code with first group of above-mentioned trickle temperature size;
M) the second trickle encoder is in order to be converted to second group of trickle digital code with second group of above-mentioned trickle temperature size;
N) reference voltage is selected logic device, is connected with above-mentioned reference voltage selection switch networking, to select to be coupled to the reference voltage that this time reaches this trickle A/D converter roughly;
O) output encoder device, in order to should rough digital code, the rough digital code of this time, this trickle digital code be converted to the output digit order number tuple that comprises the n bit.
14, reference voltage generator as claimed in claim 13 is characterized in that it comprises: first resistance is connected with above-mentioned first reference voltage source; A tail end resistance is connected to the second above-mentioned reference voltage source; And one group the serial connection resistance, be coupled in this first and tail end resistance between, the contact voltage between series resistor is one of one group of above-mentioned reference voltage.
15, transducer as claimed in claim 14 is characterized in that the difference of the adjacent two contact voltages of reference voltage generator is (V
REF1-V
REF2)/2
n
16, transducer as claimed in claim 13, it is characterized in that exporting the digit order number tuple is a binary digit, comprises one group of most significant digit unit, one group of middle effectively bit and one group of least significant bit (LSB) unit.
17, transducer as claimed in claim 13 is characterized in that rough digital code forms the most significant digit unit of output digit order number tuple.
18, transducer as claimed in claim 13 is characterized in that the reference voltage selection switch networking comprises:
A) one group the rough selector switch of resolving is coupled to the rough voltage comparator device of first and second above-mentioned time with first subclass with one group of above-mentioned reference voltage;
B) one group of trickle parsing selector switch is coupled to first and second above-mentioned trickle voltage comparator device with second subclass with one group of above-mentioned reference voltage.
19, transducer as claimed in claim 13 is characterized in that for the first time rough comparison means and for the second time rough comparison means respectively comprise:
A) voltage input end is with this analog input voltage signal coupling;
B) reference voltage end is with above-mentioned time rough one of them coupling of reference voltage;
C) output relatively, on comparator output signal is arranged;
D) voltage comparator device, produce comparator output signal, this comparator output signal is first attitude at the analog input voltage signal of input during greater than time rough reference voltage of this reference voltage end, and is second attitude at the analog input voltage of this input during less than time rough reference voltage of this reference voltage end.
20, transducer as claimed in claim 13 is characterized in that the first trickle comparison means and the second trickle comparison means respectively comprise:
A) voltage is gone into end, with the analog input voltage signal coupling after this sampling;
B) reference voltage end is with above-mentioned one of them coupling of trickle reference voltage;
C) output relatively, on comparator output signal is arranged;
D) voltage comparator device, produce comparator output signal, this comparator output signal is at the analog input voltage signal of input during greater than the trickle reference voltage of this reference voltage end, be first attitude, and be second attitude during less than the trickle reference voltage of this reference voltage end at the analog input voltage of this input.
21, the transducer above-mentioned as claim 18 is characterized in that described reference voltage selects logic device, comprises:
A) rough digital code input is connected with above-mentioned rough comparison means;
B) for the first time rough digital code input, with the above-mentioned first time rough encoder be connected;
C) for the second time rough digital code input, with the above-mentioned rough encoder second time be connected;
D) one rough position of the switch determination device is in order to reach time rough digital code from determining the action of above-mentioned time rough parsing selector switch according to above-mentioned rough digital code;
E) trickle position of the switch determination device is in order to the action according to the above-mentioned trickle parsing selector switch of above-mentioned rough digital code decision.
22, transducer as claimed in claim 13, it is characterized in that described rough voltage comparator device and rough encoder produce the first rough numerical digit sign indicating number at the first above-mentioned sampling time point, produce the second rough digital code at second sampling time point, to supply with the rough voltage comparator device of first and second time respectively, the rough encoder of first and second time, first and second trickle voltage comparator device, first and second trickle encoder are done staggered the processing.
23, a kind of is to represent the method for the output digital code of this analog voltage signal size with the input analog voltage conversion of signals, it is characterized in that the step of this method comprises:
A) at this analog voltage signal of some sampling cycle time;
B) should take a sample back analog voltage signal and one group of rough reference voltage relatively, to form rough digital code;
C), select rough reference voltage one group time according to this rough digital code;
D) should take a sample back analog voltage signal and this group time rough reference voltage relatively, to form time rough digital code.
E) select one group of trickle reference voltage according to this rough digital code and the rough digital code of this time;
F) the back analog voltage signal of should taking a sample is organized the comparison of trickle reference voltage with this, to form trickle digital code;
G) should rough digital code, inferior rough digital code and trickle digital code coding are to form the output digital code.
24, a kind of is to represent the method for the output digital code of this analog voltage signal size with the input analog voltage conversion of signals, it is characterized in that the step of this method comprises:
A) at this analog voltage signal of periodic sampling first and second of cycle staggering sample time;
B) will compare with one group of rough reference voltage one by one at the analog voltage signal of first and second above-mentioned sampling period sampling, to form first and second rough digital code in regular turn;
C) select rough reference voltage one group time according to this rough digital code;
D) analog signal of respectively this first and second sampling period being taken a sample and this group time rough reference voltage compares, to form the rough digital code of first and second time;
E) select one group of trickle reference voltage according to the rough digital code of this time with this rough digital code;
F) respectively the analog voltage signal of this first and second sampling period sampling and this are organized trickle reference voltage comparison to form first and second trickle digital code;
G) with the first above-mentioned rough digital code, for the first time rough digital code, the first trickle digital code, and the second rough digital code, for the second time rough digital code, the second trickle digital code produces first and second output digital code according to the interleaved order coding.
25, transducer as claimed in claim 24, the step f) that it is characterized in that this method is organized trickle reference voltage with the analog voltage signal of this first and second sampling period sampling and this respectively can form first and second error correcting code more again, forms this output digital code for the coding that is used in step g).
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| Application Number | Priority Date | Filing Date | Title |
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| CN96104901A CN1104777C (en) | 1996-04-26 | 1996-04-26 | Third order A-D converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN96104901A CN1104777C (en) | 1996-04-26 | 1996-04-26 | Third order A-D converter |
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| CN1164147A true CN1164147A (en) | 1997-11-05 |
| CN1104777C CN1104777C (en) | 2003-04-02 |
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| CN96104901A Expired - Fee Related CN1104777C (en) | 1996-04-26 | 1996-04-26 | Third order A-D converter |
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| CN (1) | CN1104777C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1316746C (en) * | 2003-06-24 | 2007-05-16 | 松翰科技股份有限公司 | Method and apparatus for processing digital signal |
| CN1649272B (en) * | 2003-11-28 | 2010-10-27 | 得州仪器公司 | Low-jitter clock distribution circuit |
| CN101354414B (en) * | 2007-07-26 | 2011-03-16 | 联华电子股份有限公司 | System and method for detecting defect with multi-step output function |
| CN103499733A (en) * | 2013-09-30 | 2014-01-08 | 中国科学院微电子研究所 | Circuit and method for high-precision voltage detection |
| CN106253905A (en) * | 2011-08-19 | 2016-12-21 | 路梅戴尼科技公司 | Time domain switching analog-digital converter apparatus and method for |
| US10234476B2 (en) | 2015-05-20 | 2019-03-19 | Google Llc | Extracting inertial information from nonlinear periodic signals |
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Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4733217A (en) * | 1986-05-08 | 1988-03-22 | Rca Corporation | Subranging analog to digital converter |
| GB9205727D0 (en) * | 1992-03-16 | 1992-04-29 | Sarnoff David Res Center | Averaging,flash analog to digital converter |
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- 1996-04-26 CN CN96104901A patent/CN1104777C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316746C (en) * | 2003-06-24 | 2007-05-16 | 松翰科技股份有限公司 | Method and apparatus for processing digital signal |
| CN1649272B (en) * | 2003-11-28 | 2010-10-27 | 得州仪器公司 | Low-jitter clock distribution circuit |
| CN101354414B (en) * | 2007-07-26 | 2011-03-16 | 联华电子股份有限公司 | System and method for detecting defect with multi-step output function |
| CN106253905A (en) * | 2011-08-19 | 2016-12-21 | 路梅戴尼科技公司 | Time domain switching analog-digital converter apparatus and method for |
| CN103499733A (en) * | 2013-09-30 | 2014-01-08 | 中国科学院微电子研究所 | Circuit and method for high-precision voltage detection |
| CN103499733B (en) * | 2013-09-30 | 2016-03-30 | 中国科学院微电子研究所 | A kind of high-accuracy voltage testing circuit and method |
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| CN1104777C (en) | 2003-04-02 |
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