CN116405432A - Tunnel acceleration mechanism for network-on-chip low-delay communication - Google Patents
Tunnel acceleration mechanism for network-on-chip low-delay communication Download PDFInfo
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/60—Router architectures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4633—Interconnection of networks using encapsulation techniques, e.g. tunneling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
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- H—ELECTRICITY
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- H04L45/12—Shortest path evaluation
- H04L45/121—Shortest path evaluation by minimising delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/58—Association of routers
- H04L45/586—Association of routers of virtual routers
Abstract
The invention relates to a tunnel acceleration mechanism for network-on-chip low-delay communication, belonging to the technical field of low-delay design research of network-on-chip communication architecture of a multi-core system-on-chip. The invention designs a tunnel entrance router architecture, a tunnel transit router architecture and a tunnel exit router architecture based on a five-stage pipeline router architecture of a network-on-chip, and uses three types of router architectures to build a tunnel path in the network-on-chip.
Description
Technical Field
The invention belongs to the technical field of low-delay design research of network-on-chip communication architecture of a multi-core system-on-chip, and particularly relates to a tunnel acceleration mechanism for network-on-chip low-delay communication.
Background
The rapid growth of semiconductor technology has driven the continuous growth of chip integration at an exponential rate. Today the number of transistors integrated on a single chip has reached the billion, even billion level, and multi-core system-on-chip (multiprocessor system on a chip, MPSoC) architecture has become the dominant architecture for processors. According to the existing data, the communication power consumption between the IP cores of the system-on-chip exceeds 30% of the total power consumption at a 100nm process node. Research shows that with the progress of process nodes and the improvement of chip integration, the communication power consumption ratio between IP cores is higher and higher, which brings about a huge communication challenge. The design based on the traditional bus structure is difficult to meet the increasing communication requirement of the MPSoC system due to low communication efficiency, poor expandability, high power consumption and the like, and gradually becomes one of the important reasons for restricting the development of the system-on-chip architecture. Compared with the traditional bus architecture, the communication architecture of the Network-on-Chip (NoC) has the advantages of high bandwidth, easy expansion, global asynchronous local synchronization and the like. Over 20 years of development, nocs have become the primary solution for interconnect technologies for multi-core systems on chip.
As the number of cores of MPSoC progresses from a few cores to tens or hundreds of cores, the size of network-on-chip increases rapidly, and packet communication for cores farther away in the network also requires more hops, resulting in greater delay. Taking an n×n2d Mesh network on chip as an example, from 9 cores to 100 cores, the number of hops required for packet communication between cores diagonal to the network increases from 4 hops to 18 hops, while the packet communication between adjacent cores still can be performed by only one hop, and the communication delay of the network is very unbalanced. But today, network-on-chip applications such as multimedia require higher demands on packet jitter (i.e., uniformity of delay), and some critical paths in the network are required to have lower delays in some applications, so it is important to find a mechanism for reducing jitter values of packet communications and reducing communication delays of critical paths of the network-on-chip.
Disclosure of Invention
The invention aims to provide a tunnel acceleration mechanism for network-on-chip low-delay communication, which is based on a five-stage pipeline router architecture of the network-on-chip, designs a tunnel entrance router architecture, a tunnel transit router architecture and a tunnel exit router architecture, uses three types of router architectures to build a tunnel path in the network-on-chip, and can forward a microchip of a data packet of the tunnel path with routing information meeting tunnel conditions in a tunnel acceleration mode except for a common pipeline data packet forwarding function so as to help reduce jitter of the data packet communication by a multi-hop routing node with lower delay and optimize communication delay of a network-on-chip critical path, thereby solving the problems of high jitter value of the data packet communication and serious communication delay of the network-on-chip critical path in the prior art.
The aim of the invention can be achieved by the following technical scheme:
a tunnel acceleration mechanism for network-on-chip low-delay communication comprises a network-on-chip tunnel path, a tunnel entrance router architecture, a tunnel transit router architecture and a tunnel exit router architecture;
the network-on-chip tunnel path comprises a data packet entering a tunnel entrance router, the tunnel transit router comprises a multiplexer, the data packet entering the tunnel entrance router comprises the data packet of the tunnel path and the subsequent path of the data packet does not comprise the data packet of the complete tunnel path; the data packet consists of a plurality of flits, wherein the flits are the minimum unit of flow control in the network on chip, and the communication bit width in the network on chip is assumed to be consistent with the size of the flits in the invention, namely, a router can transmit one flit to a next-level router in each period, and each pipeline stage of the router can process one flit in each period;
after the data packet of the tunnel path enters the tunnel entrance router, the router carries out route calculation according to the information such as the sending address, the destination address and the like contained in the packet header microchip, if the follow-up path of the data packet contains a complete tunnel path, the data packet is accelerated by a tunnel acceleration mechanism, otherwise, the data packet is sent to the next-stage router by a normal pipeline;
a network-on-chip tunnel path for transmitting data packet flits of the tunnel path with low delay;
the tunnel entrance router architecture is used for calculating whether a subsequent path of a data packet entering the tunnel entrance router contains a complete tunnel path according to the routing information of the data packet, determining whether to allow the data packet microchip of the tunnel path to be transmitted through the tunnel path according to the residual capacity of a tunnel exit buffer zone and a channel resource allocation strategy for the data packet of the on-chip communication path containing the complete tunnel path, and sending a tunnel establishment signal to the next-stage router;
the router architecture in the tunnel is used for determining whether to allow the packet flit of the router arriving at the next period to be transmitted through the tunnel according to the tunnel establishment signal sent by the previous stage, and forwarding the tunnel establishment signal to the router of the next stage; for the data packet flit of the tunnel path, the data packet flit is directly forwarded to an output port through one clock cycle, and a router buffer area in the tunnel is not occupied;
the tunnel exit router architecture is used for determining whether to store the data packet flit of the router arriving at the next cycle into a special tunnel exit buffer zone according to a tunnel establishment signal sent by the previous stage, and carrying out normal pipeline forwarding flow on the flit; judging whether a tunnel exit buffer area capacity early warning signal needs to be sent to a tunnel entrance router or not according to the tunnel exit buffer area capacity.
As a further scheme of the present invention, when the remaining on-chip communication paths of the data packets passing through the tunnel path entry include the whole tunnel path, the network-on-chip tunnel path can quickly transmit the flit to the tunnel exit through the tunnel mechanism with a delay far lower than that required by the normal pipeline router forwarding mechanism.
As a further aspect of the present invention, the tunnel entrance router architecture includes an input unit, a switch, a route calculation module, a virtual channel allocation module, and a switch allocation module.
As a further scheme of the invention, when the route calculation module carries out route calculation based on the route information of the data packet entering the tunnel entrance router, the route calculation module judges whether the subsequent path of the data packet contains a complete tunnel path, and for the data packet meeting the conditions, namely the data packet of the tunnel path, the route calculation module decides whether to run the data packet flit to transmit through the tunnel path according to the residual capacity of the tunnel exit buffer zone and the channel resource allocation strategy, and sends a tunnel establishment signal to the next-stage router.
As a further scheme of the invention, after receiving the tunnel establishment signal sent by the router at the previous stage, the tunnel transit router architecture directly sends the data packet flit of the tunnel path arriving at the next period to the entrance of the cross switch through the multiplexer, and sends the data packet flit to the output port through the cross switch in one period to transmit the data packet flit to the next stage.
As a further scheme of the present invention, after receiving a tunnel establishment signal sent by a previous-stage router, the tunnel exit router architecture stores a packet flit of a tunnel path arriving in a next period into a dedicated tunnel exit buffer area, and performs a normal pipeline forwarding flow on the flit, and determines whether a tunnel exit buffer area capacity early warning signal needs to be sent to a tunnel entrance router according to the capacity of the tunnel exit buffer area.
The invention has the beneficial effects that:
(1) The low-delay tunnel acceleration mechanism of the network-on-chip communication architecture of the multi-core system-on-chip comprises a network-on-chip tunnel path, wherein the network-on-chip tunnel path passes through a multi-hop tunnel router node from a tunnel entrance through a tunnel acceleration mode with lower delay by a data packet microchip with routing information meeting the condition and forwards the data packet to a tunnel exit; a tunnel entrance router forming a tunnel path judges whether the data packet head flit can be forwarded in a tunnel acceleration mode according to the routing information of the flit entering the tunnel intersection router in a route calculation module; the tunnel transit router is used for transmitting the data packet flits of the tunnel path forwarded in a tunnel acceleration mode to the router output port in one period; and the tunnel exit router is used for receiving the data packet flits of the tunnel path and storing the data packet flits in a special tunnel exit buffer zone, and judging whether an early warning signal needs to be sent to the tunnel entrance router according to the residual capacity of the tunnel exit buffer zone so as to pause the tunnel acceleration forwarding. The tunnel acceleration mechanism significantly reduces the delay in forwarding packets of the tunnel path from the tunnel ingress routing node to the tunnel egress routing node.
(2) The tunnel acceleration mechanism effectively reduces the communication delay of the data packets with high hops between remote nodes by reasonably arranging the positions of tunnel paths in the network-on-chip, thereby improving the jitter value of the data packet communication in the network-on-chip with larger scale so as to meet the application requirements of low jitter such as multimedia communication and the like. In addition, a tunnel path can be set on a critical path of the network on chip, so as to reduce communication delay of the critical path.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a network-on-chip low-delay tunnel structure of the present invention;
FIG. 2 is a schematic diagram of a tunnel ingress router architecture according to the present invention;
FIG. 3 is a schematic diagram of a tunnel transit router architecture according to the present invention;
fig. 4 is a schematic diagram of a tunnel exit router architecture according to the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A tunnel acceleration mechanism for network-on-chip low latency communications and a router architecture constituting a tunnel according to the present invention are described in detail below with reference to the accompanying drawings, including:
step one: the network-on-chip low-delay tunnel path establishes tunnel acceleration with a data packet microchip of the tunnel path;
referring to fig. 1, for convenience of description of the embodiment, it is assumed that each stage of pipeline stage of the five-stage pipeline router occupies one system clock cycle of the network on chip.
A continuous routing path is taken in the network-on-chip, a router on the continuous routing path is replaced by a tunnel router, a network-on-chip low-delay tunnel structure shown in figure 1 is formed, and a tunnel consists of 1 tunnel entrance router, a plurality of tunnel transit routers and 1 tunnel exit router;
when a data packet enters a tunnel entrance router, if the obtained data packet path completely contains a certain tunnel path according to a routing algorithm selected by a specific design, the data packet is called as a data packet meeting a tunnel acceleration condition, and the data packet meeting the tunnel acceleration condition is called as a data packet of the tunnel path. The data packet can skip part of pipeline stages of router nodes on a tunnel path, quickly pass through a plurality of router nodes in a tunnel acceleration mode, and further remarkably reduce the delay of the data packet. By reasonably arranging the tunnel paths in the network on chip, the transmission delay of the data packets with larger key paths or hops of the network on chip can be effectively reduced.
In fig. 1, a routing node 1 is a tunnel ingress router, and in addition to performing the function of a normal five-stage pipeline router, it is also determined whether a packet entering the tunnel ingress router is a packet of a tunnel path; the routing nodes 2 to (n-1) are tunnel transit routers, and besides the function of a common five-stage pipeline router, flits forwarded by a tunnel acceleration mode are forwarded from an input port to an output port in one period; the routing node n is a tunnel exit router, and besides completing the function of a normal five-stage pipeline router, the flit forwarded by a tunnel acceleration mode is stored in a special tunnel exit buffer zone, and a normal five-stage pipeline forwarding flow is executed on the flit.
Step two: the router architecture of the tunnel entrance judges whether the forwarding can be realized by a tunnel acceleration mode;
referring to fig. 2, the tunnel ingress router architecture shown in fig. 2 still includes related components of a conventional five-stage pipeline router, including an input unit, a switch, a route calculation module, a virtual channel allocation module, and a switch allocation module. Compared with a conventional network-on-chip pipeline router, the routing calculation module of the network-on-chip pipeline router judges whether a data packet to be forwarded is a data packet of a tunnel path or not;
the data packet of the tunnel path then applies for a virtual channel to a virtual channel distributor, and the virtual channel distributor distributes a virtual channel special for tunnel acceleration to the data packet; then applying a switch time slot to a switch distributor according to the microchip, and determining whether to distribute the switch time slot to the microchip of the data packet of the tunnel path by the switch distributor according to a specifically designed flow priority strategy and a tunnel exit buffer capacity early warning signal bf of the tunnel exit router; the ts signal is asserted and transmitted to the next level of routing nodes while the switch allocator grants the switch slot to the flit of the packet of the tunnel path. Since the ts signal has already begun the link-through phase of the network-on-chip during the switch-through period of the flit, i.e., the period of reading the flit from the input buffer of the tunnel ingress router and traversing the switch, the signal will arrive at the next router one period earlier than the first flit.
Step three: the router is transferred in the tunnel, and the microchip transferred in the tunnel acceleration mode is sent to the output port of the router in one period;
referring to fig. 3, after receiving the ts signal sent by the previous router, the switch distributor will establish the input-output path required by the tunnel in the next period, and pause the flit application of other data packets to the output port as shown in fig. 3; meanwhile, the ts signal with one clock period is delayed by the trigger, when the tunnel crossing microchip in the next period reaches the router, the alternative multiplexer is controlled, so that the tunnel accelerating microchip directly performs a switch crossing stage, and only one switch crossing period is consumed in the router of the stage. For the tunnel exit buffer zone early warning signal bf transmitted by the next-stage router, a trigger is used for registering one period and then transmitting the signal to the previous-stage router, so that the signal integrity is maintained, and the design of the tunnel exit buffer zone size and the pre-warning threshold of the residual capacity of the tunnel exit buffer zone are facilitated to be estimated.
Step four: the tunnel exit router receives the tunnel acceleration microchip and stores the tunnel acceleration microchip into a special tunnel exit buffer area, and judges whether the tunnel acceleration forwarding needs to be suspended or not;
referring to fig. 4, after receiving the ts signal sent by the previous router, the input unit stores the arriving tunnel acceleration flit in the dedicated tunnel exit buffer area in the next period, as shown in the tunnel exit router of fig. 4. The buffer area is specially used for storing flits which are transmitted through the tunnel acceleration, and after the residual capacity is lower than a certain threshold value, an early warning is sent to the tunnel entrance router through a signal line bf, and the sending of the data packet flits of the tunnel path is suspended. After storing the tunnel acceleration flit into the tunnel exit buffer of the input unit, the flit re-participates in the five-stage pipeline forwarding process of the network-on-chip router in the tunnel exit router.
Step five: determining a tunnel exit router buffer zone early warning threshold;
capacity early warning threshold c of tunnel exit buffer tb The method comprises the following steps:
c tb ＝(n-1)×(n LT +1)
wherein (n-1) represents the total number of hops of the tunnel path; n is n LT Representing the number of cycles required for data to be transmitted over the link in the network on chip.
And as shown in fig. 1, there are n router nodes in the tunnel path. When the buffer capacity is less than c tb And when the buffer area capacity is exhausted, forwarding the pre-warning signal to a switch allocation module of the tunnel entrance router, and suspending forwarding the microchip in a tunnel acceleration mode.
In the description of the present specification, the descriptions of the terms "one embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely illustrative and explanatory of the principles of the invention, as various modifications and additions may be made to the specific embodiments described, or similar thereto, by those skilled in the art, without departing from the principles of the invention or beyond the scope of the appended claims.
Claims (7)
1. A tunnel acceleration mechanism for network-on-chip low-latency communications, the tunnel acceleration mechanism comprising a network-on-chip tunnel path, a tunnel ingress router architecture, a tunnel transit router architecture, and a tunnel egress router architecture;
the network-on-chip tunnel path comprises a data packet entering a tunnel entrance router, the tunnel transit router comprises a multiplexer, the data packet entering the tunnel entrance router comprises the data packet of the tunnel path and the subsequent path of the data packet does not comprise the data packet of the complete tunnel path;
a network-on-chip tunnel path for transmitting data packet flits of the tunnel path with low delay;
a tunnel entrance router architecture for calculating whether a subsequent path of a data packet entering a tunnel entrance router contains a complete tunnel path according to routing information of the data packet;
the router architecture in the tunnel is used for determining whether to allow the packet flit of the router arriving at the next period to be transmitted through the tunnel according to the tunnel establishment signal sent by the previous stage, and forwarding the tunnel establishment signal to the router of the next stage; for the data packet flit of the tunnel path, the data packet flit is directly forwarded to an output port through one clock cycle, and a router buffer area in the tunnel is not occupied;
the tunnel exit router architecture is used for determining whether to store the data packet flit of the router arriving at the next cycle into a special tunnel exit buffer zone according to a tunnel establishment signal sent by the previous stage, and carrying out normal pipeline forwarding flow on the flit; judging whether a tunnel exit buffer area capacity early warning signal needs to be sent to a tunnel entrance router or not according to the tunnel exit buffer area capacity.
2. The tunneling mechanism for network-on-chip low latency communications according to claim 1, wherein a subsequent path of the tunneling path includes a complete tunneling path of the data packet, and wherein a subsequent path of the data packet does not include a complete tunneling path of the data packet as a non-tunneling path of the data packet, and is forwarded normally through a pipeline stage of a router without utilizing the tunneling mechanism;
and the data packet of the tunnel path is used for determining whether to allow the data packet flit of the tunnel path to be transmitted through the tunnel path according to the residual capacity of the tunnel exit buffer zone and the channel resource allocation strategy, and sending a tunnel establishment signal to the next-stage router.
3. A tunneling acceleration mechanism for network-on-chip low latency communications according to claim 1, wherein the network-on-chip tunnel path, a packet entering a tunnel ingress router, is able to pass through the tunneling mechanism when its subsequent path comprises the entire tunnel path.
4. The tunnel acceleration mechanism for network-on-chip low-latency communications according to claim 1, wherein the tunnel ingress router architecture comprises an input unit, a switch, a route calculation module, a virtual channel allocation module, and a switch allocation module.
5. The tunnel acceleration mechanism for network-on-chip low latency communication according to claim 4, wherein the routing computation module determines whether a subsequent path of a packet includes a complete tunnel path when performing routing computation based on routing information of the packet entering the tunnel ingress router, and determines whether to operate packet flits for transmission through the tunnel path according to a remaining capacity of a tunnel egress buffer and a channel resource allocation policy for a packet that conforms to a condition, i.e., a packet of the tunnel path, and sends a tunnel establishment signal to a next-level router.
6. The tunnel acceleration mechanism of claim 1, wherein the tunnel transit router architecture, after receiving the tunnel establishment signal from the previous level router, sends the packet flit of the tunnel path arriving in the next cycle directly to the crossbar entrance through the multiplexer, and sends the packet flit to the output port through the crossbar in one cycle for transmission to the next level.
7. The tunnel acceleration mechanism for network-on-chip low latency communication according to claim 1, wherein the tunnel exit router architecture, after receiving a tunnel establishment signal from a previous level router, stores a packet flit of a tunnel path arriving in a next period into a dedicated tunnel exit buffer, and performs a normal pipeline forwarding flow on the flit, and determines, according to a capacity of the tunnel exit buffer, whether a tunnel exit buffer capacity early warning signal needs to be sent to a tunnel entrance router.
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