CN116404076A - Light emitting diode and preparation method thereof - Google Patents

Light emitting diode and preparation method thereof Download PDF

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Publication number
CN116404076A
CN116404076A CN202310395533.3A CN202310395533A CN116404076A CN 116404076 A CN116404076 A CN 116404076A CN 202310395533 A CN202310395533 A CN 202310395533A CN 116404076 A CN116404076 A CN 116404076A
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layer
type semiconductor
semiconductor layer
forming
electrode
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周志兵
张星星
林潇雄
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Abstract

The invention discloses a light-emitting diode and a preparation method thereof, and relates to the technical field of light-emitting diodes. Specifically, the preparation method of the light-emitting diode comprises the step of purging the P-type semiconductor layer below the P electrode by silane. Based on the step, the P-type semiconductor layer of the preset quantity in the area can be disabled, so that the effect of current blocking is achieved, the transverse expansion of current is optimized, the traditional current blocking layer is canceled, light absorption is reduced, and the luminous efficiency is improved. In addition, the preparation method has low process cost and simple flow.

Description

Light emitting diode and preparation method thereof
Technical Field
The present invention relates to the field of light emitting diodes, and more particularly, to a light emitting diode and a method for manufacturing the same.
Background
In the existing light emitting diode, the lateral expansion capability of the P-type peninsula lifting layer below the P-type electrode is weak, so that when the forward voltage is applied to the two electrodes, current can flow from the P-type semiconductor layer to the N-type semiconductor layer vertically and directly, current crowding is caused, and especially in a large-size chip, current cannot be uniformly distributed in the chip, and the luminous intensity cannot reach the design index. The current solution is to insert a silicon dioxide structure under the P electrode as a current blocking layer to prevent current crowding at the P electrode. However, such a current blocking layer may cause a certain degree of light absorption, reducing light extraction efficiency.
Disclosure of Invention
The invention aims to solve the technical problem of providing a preparation method of a light-emitting diode, which can cancel a current blocking layer, avoid current congestion and improve the light-emitting efficiency of the light-emitting diode.
The invention also solves the technical problem of providing a light-emitting diode with high luminous efficiency.
In order to solve the above technical problems, the present invention provides a method for manufacturing a light emitting diode, which includes a step of purging a P-type semiconductor layer under a P-electrode with silane to disable a predetermined amount of the P-type semiconductor layer in the region.
As improvement of the technical scheme, the purging temperature is 200-300 ℃, the purging time is 240-500 s, and the silane flow is 100-150 sccm.
As an improvement of the technical scheme, silane purging is carried out in PECVD equipment, and the radio frequency power is 70W-150W.
As an improvement of the above technical solution, the method comprises the following steps:
(1) Providing a substrate;
(2) Forming an epitaxial layer on the substrate; the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate;
(3) Etching the epitaxial layer to form a first exposed area exposing the N-type semiconductor layer;
(4) Forming a mask on the substrate obtained in the step (4), and etching to form a second exposed area exposing the P-type semiconductor layer;
(5) Purging the second exposed region by silane to disable a preset amount of the P-type semiconductor layer exposed by the second exposed region;
(6) Removing the mask;
(7) Forming a transparent conductive layer on the substrate obtained in the step (6);
(8) Forming an N electrode in the first exposed region, and forming a P electrode on the transparent conductive layer at a position corresponding to the second exposed region;
(9) And (3) forming a passivation layer on the substrate obtained in the step (8), and opening holes to expose the N electrode and the P electrode.
As an improvement of the above technical solution, the method comprises the following steps:
(1) Providing a substrate;
(2) Forming an epitaxial layer on the substrate; the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate;
(3) Etching the epitaxial layer to form a first exposed area exposing the N-type semiconductor layer;
(4) Forming a mask on the substrate obtained in the step (4), and etching to form a second exposed area exposing the P-type semiconductor layer;
(5) Purging the second exposed region by silane to disable a preset amount of the P-type semiconductor layer exposed by the second exposed region;
(6) Removing the mask;
(7) Forming a transparent conductive layer on the substrate obtained in the step (6);
(8) Forming a reflective layer on the transparent conductive layer;
(9) Etching to expose the first exposed area and the transparent conductive layer above the second exposed area;
(10) Forming an N electrode in the first exposed region, and forming a P electrode on the transparent conductive layer at a position corresponding to the second exposed region;
(11) Forming a passivation layer on the substrate obtained in the step (10), and opening holes to expose the N electrode and the P electrode;
(12) And (3) forming a first bonding pad and a second bonding pad on the substrate obtained in the step (11).
As an improvement of the technical proposal, the mask is SiO 2 A layer having a thickness of 100nm to 500nm.
As an improvement of the technical scheme, the P-type semiconductor layer is a P-type GaN layer with the thickness of 200nm-300nm, the doping element is Mg, and the doping concentration is 5 multiplied by 10 17 cm -3 -1×10 20 cm -3 。
As an improvement of the technical proposal, the N-type semiconductor layer is an N-type GaN layer with the thickness of 1 μm-3 μm, the doping element is Si, and the doping concentration is 5 multiplied by 10 18 cm -3 -1×10 19 cm -3 。
As an improvement of the above technical solution, the mask is removed by etching with a BOE solution.
Correspondingly, the invention also discloses a light-emitting diode, which is prepared by the preparation method of the light-emitting diode.
The implementation of the invention has the following beneficial effects:
the preparation method of the light-emitting diode comprises the step of sweeping the P-type semiconductor layer below the P electrode by silane, and based on the step, the preset quantity of the P-type semiconductor layer in the area can be disabled, so that the effect of current blocking is achieved, the transverse expansion of current is optimized, the traditional current blocking layer is omitted, light absorption is reduced, and the light-emitting efficiency is improved. In addition, the preparation method has low process cost and simple flow.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a light emitting diode according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a light emitting diode according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a light emitting diode according to another embodiment;
fig. 4 is a schematic structural view of a light emitting diode according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It is only stated that the terms of orientation such as up, down, left, right, front, back, inner, outer, etc. used in this document or the imminent present invention, are used only with reference to the drawings of the present invention, and are not meant to be limiting in any way.
The invention discloses a preparation method of a light-emitting diode, which comprises the step of purging a P-type semiconductor layer below a P-electrode by silane so as to disable a preset amount of the P-type semiconductor layer in the region. Specifically, the purging may be performed in MOCVD equipment or PECVD equipment, but is not limited thereto. Preferably, in one embodiment of the present invention, purging is performed in a PECVD apparatus with a radio frequency power of 70W-150W, illustratively 72W, 80W, 92W, 100W, 110W, 125W, 130W or 140W, but is not limited thereto, preferably 100W-120W. The purging temperature is 200-300 ℃, the purging time is 250-500 s, and when the purging temperature is too low or the purging time is too short, the depth of the failed P-type semiconductor layer is shallow, so that the effect of blocking current is difficult to effectively play. When the purging temperature is too high or the purging time is too long, the area of the failed P-type semiconductor layer is large and deep, the hole concentration is reduced, and the light efficiency is affected. Exemplary purge temperatures are, but not limited to, 210 ℃, 220 ℃, 230 ℃, 240 ℃, 250 ℃, 260 ℃, 270 ℃, 280 ℃, or 290 ℃. The purge time is 280s, 310s, 340s, 370s, 400s, 430s, 460s or 490s, but is not limited thereto. Preferably, the purging temperature is 220-260 ℃ and the purging time is 300-400 s. The silane flow rate at the purge is 100sccm to 150sccm, and is exemplified by, but not limited to, 110sccm, 120sccm, 130sccm, or 140 sccm.
It should be noted that the method of purging with silane according to the present invention is applicable to various structures of LEDs, such as front-mounted LEDs, flip-chip LEDs, or vertical LEDs, but is not limited thereto.
Preferably, in one embodiment of the present invention, the light emitting diode is a front-mounted LED, and referring to fig. 1 and 2, the preparation method includes the following steps:
s100: providing a substrate;
wherein, the substrate can be sapphire, siC, znO, potassium oxide or monocrystalline silicon; but is not limited thereto.
S101: forming an epitaxial layer on a substrate;
specifically, the epitaxial layer may be grown by the MOCVD method. The epitaxial layer comprises a buffer layer, an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate. The N-type semiconductor layer and the P-type semiconductor layer may be made of GaN material or AlGaN material, but are not limited thereto. Preferably, in one embodiment of the present invention, the N-type semiconductor layer is an N-type GaN layer having a thickness of 1 μm to 3 μm, a doping element of Si, and a doping concentration of 5×10 18 cm -3 -1×10 19 cm -3 . The P-type semiconductor layer is a P-type GaN layer with thickness of 200nm-300nm, doping element of Mg and doping concentration of 5×10 17 cm -3 -1×10 20 cm -3 . The multi-quantum well may be an InGaN/GaN type multi-quantum well layer, an InGaN/AlGaN type multi-quantum well layer, an AlGaN/AlGaN type multi-quantum well layer, which are common in the art, but is not limited thereto. Preferably, in one embodiment of the present invention, the multiple quantum well layer 23 is InGaN/GaN type multipleAnd a quantum well layer.
S102: etching the epitaxial layer to form a first exposed area exposing the N-type semiconductor layer;
specifically, an ICP or RIE etching apparatus is used to etch the epitaxial layer 2 to form a first exposed region, where the first exposed region is etched to the first semiconductor layer.
S103: forming a mask on the substrate obtained in the step S102, and etching to form a second exposed area exposing the P-type semiconductor layer;
wherein the mask is SiO 2 A layer, but is not limited thereto. The thickness of the mask is 100nm to 500nm, and exemplary is 150nm, 190nm, 230nm, 250nm, 300nm, 350nm, 400nm or 460nm, but is not limited thereto.
The second exposed region corresponds to a region of the P electrode formed in the later stage.
S104: purging the second exposed region by silane to disable a preset amount of the P-type semiconductor layer exposed by the second exposed region;
s105: removing the mask;
wherein, the mask can be removed by dry etching or wet etching. Preferably, in one embodiment of the invention, the substrate is immersed in a BOE solution and the mask is removed.
S106: forming a transparent conductive layer on the substrate obtained in step S105;
specifically, the transparent conductive layer 3 may be formed by evaporation or magnetron sputtering, but is not limited thereto. The transparent conductive layer may be made of ITO, IZO or AZO, but is not limited thereto.
S107: forming an N electrode in the first exposed region, and forming a P electrode on the transparent conductive layer at a position corresponding to the second exposed region;
specifically, the N electrode 4 and the P electrode 5 are formed by using an electron beam evaporation, thermal evaporation, or magnetron sputtering process. The N electrode 4 and the P electrode 5 each include a Cr layer, an Al layer, a Ti layer, a first Ni layer, a first Pt layer, a second Ni layer, a second Pt layer, and an Au layer, which are laminated in this order.
S108: a passivation layer is formed on the substrate obtained in step S107, and openings are formed to expose the N electrode and the P electrode.
Wherein the passivation layer can be SiO 2 Layers and/or SiN x A layer, but is not limited thereto. The thickness is 50nm-120nm.
Specifically, referring to fig. 2, the light emitting diode manufactured based on the manufacturing method is a front-loading structure, and includes a substrate 1, an epitaxial layer 2 disposed on the substrate 1, a transparent conductive layer 3, an N electrode 4, a P electrode 5, and a passivation layer 6. The epitaxial layer 2 includes a buffer layer 21, an N-type semiconductor layer 22, a multiple quantum well layer 23, and a P-type semiconductor layer 24, which are sequentially stacked on the substrate 1. The P-type semiconductor layer 24 is provided with a predetermined region 25, and the thickness of the region 25 is 10% -25% of the thickness of the P-type semiconductor layer 24.
Preferably, the method for manufacturing the light emitting diode in this embodiment further includes:
s109: and grinding to reduce the thickness of the substrate, and splitting to form grains.
Preferably, in one embodiment of the present invention, the light emitting diode is a flip-chip LED, and referring to fig. 3 and 4, the preparation method includes the following steps:
s200: providing a substrate;
wherein, the substrate can be sapphire, siC, znO, potassium oxide or monocrystalline silicon; but is not limited thereto.
S201: forming an epitaxial layer on a substrate;
specifically, the epitaxial layer may be grown by the MOCVD method. The epitaxial layer comprises a buffer layer, an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate. The N-type semiconductor layer and the P-type semiconductor layer may be made of GaN material or AlGaN material, but are not limited thereto. Preferably, in one embodiment of the present invention, the N-type semiconductor layer is an N-type GaN layer having a thickness of 1 μm to 3 μm, a doping element of Si, and a doping concentration of 5×10 18 cm -3 -1×10 19 cm -3 . The P-type semiconductor layer is a P-type GaN layer with thickness of 200nm-300nm, doping element of Mg and doping concentration of 5×10 17 cm -3 -1×10 20 cm -3 . The multiple quantum well can be InGaN/GaN type multiple quantum well layer, inGaN/AlGaN type multiple quantum well layer, alGaN/AlGaN type multiple quantum well layer, or the like commonly known in the artThe well layer is not limited thereto. Preferably, in one embodiment of the present invention, the multiple quantum well layer is an InGaN/GaN type multiple quantum well layer.
S202: etching the epitaxial layer to form a first exposed area exposing the N-type semiconductor layer;
specifically, an ICP or RIE etching device is used for etching the epitaxial layer to form a first exposed area, and the first exposed area is etched to the first semiconductor layer.
S203: forming a mask on the substrate obtained in the step S102, and etching to form a second exposed area exposing the P-type semiconductor layer;
wherein the mask is SiO 2 A layer, but is not limited thereto. The thickness of the mask is 100nm to 500nm, and exemplary is 150nm, 190nm, 230nm, 250nm, 300nm, 350nm, 400nm or 460nm, but is not limited thereto.
The second exposed region corresponds to a region of the P electrode formed in the later stage.
S204: purging the second exposed region by silane to disable a preset amount of the P-type semiconductor layer exposed by the second exposed region;
s205: removing the mask;
wherein, the mask can be removed by dry etching or wet etching. Preferably, in one embodiment of the invention, the substrate is immersed in a BOE solution and the mask is removed.
S206: forming a transparent conductive layer on the substrate obtained in step S205;
specifically, the transparent conductive layer may be formed by evaporation or magnetron sputtering, but is not limited thereto. The transparent conductive layer may be made of ITO, IZO or AZO, but is not limited thereto.
S207: forming a reflective layer on the transparent conductive layer;
the emission layer is made of Ag, but is not limited to Ag, and can be formed by magnetron sputtering deposition or physical vapor deposition process, but is not limited to Ag.
Preferably, in one embodiment of the present invention, the reflective layer further comprises a protective layer made of one of Ti, ni, pt, W, pd, rh, tiW; preferably, tiW is selected. The protective layer can form good protection for the reflective layer.
S208: etching to expose the first exposed region and the transparent conductive layer above the second exposed region;
s209: forming an N electrode in the first exposed region, and forming a P electrode on the transparent conductive layer at a position corresponding to the second exposed region;
specifically, an N electrode and a P electrode are formed by adopting an electron beam evaporation, thermal evaporation or magnetron sputtering process. The N electrode and the P electrode each include a Cr layer, an Al layer, a Ti layer, a first Ni layer, a first Pt layer, a second Ni layer, a second Pt layer, and an Au layer, which are sequentially stacked.
S210: a passivation layer is formed on the substrate obtained in step S209, and the N electrode and the P electrode are exposed through the openings.
Wherein the passivation layer can be SiO 2 Layers and/or SiN x A layer, but is not limited thereto. The thickness is 50nm-120nm.
S211: the first and second pads are formed on the substrate obtained in step S210.
The first bonding pad and the second bonding pad are made of AuSn materials, the first bonding pad is communicated with the N electrode, and the second bonding pad is communicated with the P electrode.
Preferably, the method for manufacturing the light emitting diode in this embodiment further includes:
s212: and grinding to reduce the thickness of the substrate, and splitting to form grains.
Specifically, referring to fig. 4, the light emitting diode prepared based on the preparation method is in a flip-chip structure, and includes a substrate 1, an epitaxial layer 2 disposed on the substrate 1, a transparent conductive layer 3, a reflective layer 4, an N electrode 5, a P electrode 6, a passivation layer 7, a first bonding pad 8, and a second bonding pad 9. The epitaxial layer 2 includes a buffer layer 21, an N-type semiconductor layer 22, a multiple quantum well layer 23, and a P-type semiconductor layer 24, which are sequentially stacked on the substrate 1. The P-type semiconductor layer 24 is provided with a predetermined region 25, and the thickness of the region 25 is 10% -25% of the thickness of the P-type semiconductor layer 24.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. A preparation method of a light-emitting diode is characterized by comprising the step of purging a P-type semiconductor layer below a P-electrode by silane to disable a preset amount of the P-type semiconductor layer in the region.
2. The method of claim 1, wherein the purging temperature is 200 ℃ to 300 ℃, the purging time is 240s to 500s, and the silane flow rate is 100sccm to 150sccm.
3. The method of manufacturing a light emitting diode according to claim 1 or 2, wherein the silane purging is performed in a PECVD apparatus with a radio frequency power of 70W to 150W.
4. The method for manufacturing a light emitting diode according to claim 1, comprising the steps of:
(1) Providing a substrate;
(2) Forming an epitaxial layer on the substrate; the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate;
(3) Etching the epitaxial layer to form a first exposed area exposing the N-type semiconductor layer;
(4) Forming a mask on the substrate obtained in the step (4), and etching to form a second exposed area exposing the P-type semiconductor layer;
(5) Purging the second exposed region by silane to disable a preset amount of the P-type semiconductor layer exposed by the second exposed region;
(6) Removing the mask;
(7) Forming a transparent conductive layer on the substrate obtained in the step (6);
(8) Forming an N electrode in the first exposed region, and forming a P electrode on the transparent conductive layer at a position corresponding to the second exposed region;
(9) And (3) forming a passivation layer on the substrate obtained in the step (8), and opening holes to expose the N electrode and the P electrode.
5. The method for manufacturing a light emitting diode according to claim 1, comprising the steps of:
(1) Providing a substrate;
(2) Forming an epitaxial layer on the substrate; the epitaxial layer comprises a buffer layer, an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate;
(3) Etching the epitaxial layer to form a first exposed area exposing the N-type semiconductor layer;
(4) Forming a mask on the substrate obtained in the step (4), and etching to form a second exposed area exposing the P-type semiconductor layer;
(5) Purging the second exposed region by silane to disable a preset amount of the P-type semiconductor layer exposed by the second exposed region;
(6) Removing the mask;
(7) Forming a transparent conductive layer on the substrate obtained in the step (6);
(8) Forming a reflective layer on the transparent conductive layer;
(9) Etching to expose the first exposed area and the transparent conductive layer above the second exposed area;
(10) Forming an N electrode in the first exposed region, and forming a P electrode on the transparent conductive layer at a position corresponding to the second exposed region;
(11) Forming a passivation layer on the substrate obtained in the step (10), and opening holes to expose the N electrode and the P electrode;
(12) And (3) forming a first bonding pad and a second bonding pad on the substrate obtained in the step (11).
6. The method of manufacturing a light emitting diode according to claim 4 or 5, wherein the mask is SiO 2 A layer having a thickness of 100nm to 500nm.
7. The method of manufacturing a light-emitting diode according to claim 1, wherein the P-type semiconductor layer is a P-type GaN layer having a thickness of 200nm to 300nm, a doping element of Mg, and a doping concentration of 5×10 17 cm -3 -1×10 20 cm -3 。
8. The method of manufacturing a light emitting diode according to claim 4 or 5, wherein the N-type semiconductor layer is an N-type GaN layer having a thickness of 1 μm to 3 μm, a doping element of Si, and a doping concentration of 5×10 18 cm -3 -1×10 19 cm -3 。
9. The led of claim 4 or 5, wherein the mask is removed by etching with a BOE solution.
10. A light emitting diode prepared by the method of any one of claims 1-9.
CN202310395533.3A 2023-04-13 2023-04-13 Light emitting diode and preparation method thereof Pending CN116404076A (en)

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