CN116402145B - W-state preparation method and device, medium and electronic device - Google Patents
W-state preparation method and device, medium and electronic device Download PDFInfo
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Abstract
The invention discloses a W state preparation method, a device, a medium and an electronic device, wherein a double-bit gate is constructed based on a controlled single-bit gate and a CNOT gate, a W state preparation quantum circuit is constructed based on the double-bit gate, the quantum bit is excited to an initial state, and the W state preparation quantum circuit is used for driving the quantum bit to evolve from the initial state to the W state, so that the W state efficient preparation is realized.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a W-state preparation method, a device, a medium and an electronic device.
Background
The W-state is a quantum state first proposed by Wolfgang Tur in 2000, which can be regarded as an equal probability superposition of all quantum states with a Hamming weight of 1 under calculation, e.g. N qubits of W-state. The hamming weight can be regarded as the number of "1" s in a string of binary characters, e.g. the hamming weight of "000100010" is 2.
The W state is different from the common entanglement state, and even if a certain particle in the multi-particle system is measured by an untrusted user, the particle capable of loading bit information is lost due to the reason that the trusted user communication negotiates to discard the certain particle, and the like, the residual particles still have entanglement association. Based on this property, the W-state has wide application in the field of combinatorial optimization based on quantum computing. How to efficiently prepare the W-state is one of the problems that need to be resolved in quantum computing.
Disclosure of Invention
The invention aims to provide a W-state preparation method, a W-state preparation device, a W-state preparation medium and an electronic device, and aims to realize efficient W-state preparation.
One embodiment of the invention provides a method for preparing a W state, comprising the following steps:
Constructing a two-bit gate based on the controlled single-bit gate and the CNOT gate;
constructing a W-state preparation quantum circuit based on the double-bit gate;
Exciting the qubit to an initial state, and preparing a quantum wire based on the W state to drive the qubit to evolve from the initial state to the W state.
Optionally, the unitary matrix corresponding to the single bit gate in the controlled single bit gate isWherein the bit gate parameterA qubit determination based on the controlled single bit gate effect.
Optionally, the constructing a W-state preparation quantum circuit based on the dual bit gate includes:
and (3) enabling N-1 double-bit gates to act on N quantum bits to obtain a W-state preparation quantum circuit, wherein N is an integer greater than 1.
Optionally, said applying N-1 of said two-bit gates to N qubits includes:
Sequentially applying N-1 double-bit gates to two adjacent quantum bits, wherein the logic gate parameter of the ith double-bit gate Wherein, the value range of i is 1 to N-1.
Optionally, said applying N-1 of said two-bit gates to N qubits includes:
Constructing a binary tree structure of N quantum bits;
Determining a double-bit gate corresponding to each node in the binary tree structure;
and each double-bit gate is acted on two quantum bits corresponding to each double-bit gate.
Optionally, the binary tree structure comprisesThe double-bit gate corresponding to the kth node of the jth layer is the ith double-bit gate; the bit acted by the kth node of the jth layer is one of the quantum bits and the kth node acted by the father node corresponding to the kth nodeA quantum bit, wherein i=J and k are integers greater than or equal to 1.
Optionally, the method further comprises:
and if the quantum chip comprising the quantum bit does not support the double-bit gate, converting the double-bit gate into a basic bit gate supported by the quantum chip.
Yet another embodiment of the present invention provides a W-state preparation apparatus, the apparatus comprising:
the bit gate construction unit is used for constructing a double bit gate based on the controlled single bit gate and the CNOT gate;
The circuit construction unit is used for constructing a W-state preparation quantum circuit based on the double-bit gate;
and the quantum state preparation unit is used for exciting the quantum bit to an initial state and preparing a quantum circuit based on the W state to drive the quantum bit to evolve from the initial state to the W state.
Optionally, the unitary matrix corresponding to the single bit gate in the controlled single bit gate isWherein the bit gate parameterA qubit determination based on the controlled single bit gate effect.
Optionally, in the aspect of preparing the quantum circuit based on the W state of the dual bit gate construction, the circuit construction unit is specifically configured to:
and (3) enabling N-1 double-bit gates to act on N quantum bits to obtain a W-state preparation quantum circuit, wherein N is an integer greater than 1.
Optionally, in the aspect of applying N-1 of the two-bit gates to N qubits, the circuit building unit is specifically configured to:
Sequentially applying N-1 double-bit gates to two adjacent quantum bits, wherein the logic gate parameter of the ith double-bit gate Wherein, the value range of i is 1 to N-1.
Optionally, in the aspect of applying N-1 of the two-bit gates to N qubits, the circuit building unit is specifically configured to:
Constructing a binary tree structure of N quantum bits;
Determining a double-bit gate corresponding to each node in the binary tree structure;
and each double-bit gate is acted on two quantum bits corresponding to each double-bit gate.
Optionally, the binary tree structure comprisesThe double-bit gate corresponding to the kth node of the jth layer is the ith double-bit gate; the bit acted by the kth node of the jth layer is one of the quantum bits and the kth node acted by the father node corresponding to the kth nodeA quantum bit, wherein i=J and k are integers greater than or equal to 1.
Optionally, the apparatus further comprises a logic gate conversion unit for:
and if the quantum chip comprising the quantum bit does not support the double-bit gate, converting the double-bit gate into a basic bit gate supported by the quantum chip.
A further embodiment of the invention provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the preceding claims when run.
Yet another embodiment of the invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the method described in any of the above.
Compared with the prior art, the W-state preparation method, the device, the medium and the electronic device provided by the invention realize the efficient preparation of the W state by constructing the double-bit gate based on the controlled single-bit gate and the CNOT gate, constructing the W-state preparation quantum circuit based on the double-bit gate, exciting the quantum bit to an initial state, and driving the quantum bit to evolve from the initial state to the W state based on the W-state preparation quantum circuit.
Drawings
FIG. 1 is a network block diagram of a W-state preparation system according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a W-state preparation method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a dual bit gate according to an embodiment of the present invention;
Fig. 4 is a schematic structural diagram of a W-state fabricated quantum circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a binary tree structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a exploded dual bit gate according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of a W-state preparation device according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
Fig. 1 is a network block diagram of a W-state preparation system according to an embodiment of the present invention. The W-state preparation system may include a network 110, a server 120, a wireless device 130, a client 140, a store 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, classical processors, quantum processors, and other devices not shown.
Network 110 is a medium used to provide a communications link between various devices and computers connected together within the W-state production system, including but not limited to the internet, intranets, local area networks, mobile communication networks, and combinations thereof, by wired, wireless communication links, or fiber optic cables, etc.
Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and have applications or software tools that perform conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, tablet, notebook, smart wearable device, or the like. The memory unit 150 may include a database 151 that may be configured to store data of qubit parameters, quantum logic gate parameters, quantum wires, quantum programs, and the like.
Classical computing unit 160 (quantum computing unit 170) may include classical processor 161 (quantum processor 171) for processing classical data (quantum data), which may be boot files, operating system images, and application 163 (application 173), and memory 162 (memory 172) for storing classical data (quantum data), which may be a quantum algorithm for implementing W-state preparation method compilation provided in accordance with embodiments of the present invention.
Any data or information stored or generated in classical computing unit 160 (quantum computing unit 170) may also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, as may any application program that it executes.
It should be noted that, the real quantum computer is a hybrid structure, and it includes at least two major parts in fig. 1: a classical calculation unit 160 responsible for performing classical calculations and controls; the quantum computing unit 170 is responsible for running a quantum program to realize quantum computing.
The classical computing unit 160 and the quantum computing unit 170 may be integrated in one device or may be distributed among two different devices. A first device, for example, comprising a classical computing unit 160 runs a classical computer operating system on which quantum application development tools and services are provided, and also the storage and network services required for quantum applications. The user develops the quantum program through a quantum application development tool and service thereon, and transmits the quantum program to a second device including the quantum computing unit 170 through a web service thereon. The second device runs a quantum computer operating system, the code of the quantum program is analyzed and compiled into an instruction which can be identified and executed by the quantum processor 170 through the quantum computer operating system, and the quantum processor 170 realizes a quantum algorithm corresponding to the quantum program according to the instruction.
The computation unit of the classical processor 161 in the classical computation unit 160 is a CMOS tube based on silicon chips, which is not limited by time and coherence, i.e. which is not limited by the time of use, which is available at any time. Furthermore, the number of such computational units is also sufficient in silicon chips, the number of computational units in a classical processor 161 is now thousands of, the number of computational units is sufficient and the CMOS pipe selectable computational logic is fixed, e.g. and logic. When the CMOS tube is used for operation, a large number of CMOS tubes are combined with limited logic functions, so that the operation effect is realized.
The basic computational unit of quantum processor 171 in quantum computational unit 170 is a qubit, the input of which is limited by coherence and also by coherence time, i.e., the qubit is limited in terms of time of use and is not readily available. Full use of qubits within the usable lifetime of the qubits is a critical challenge for quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of the performance of the quantum computer, each qubit realizes a calculation function by a logic function configured as needed, whereas the logic function in the field of quantum calculation is diversified in view of the limited number of qubits, such as Hadamard gate (H gate), brix gate (X gate), brix-Y gate (Y gate) brix-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, toffoli gate, and the like. In quantum computation, the operation effect is realized by combining limited quantum bits with various logic function combinations.
Based on these differences, the design of classical logic functions acting on CMOS transistors and the design of quantum logic functions acting on qubits are significantly and essentially different; the classical logic function acts on the design of the CMOS tube without considering the individuality of the CMOS tube, such as the individuality identification and the position of the CMOS tube in the silicon chip, and the usable time length of each CMOS tube, so the classical algorithm formed by the classical logic function only expresses the operation relation of the algorithm, and does not express the dependence of the algorithm on the individuals of the CMOS tube.
The quantum logic function acts on the qubit, and the individuality of the qubit needs to be considered, such as the individuality identification, the position and the relation with surrounding qubits of the number of the qubit in the quantum chip, and the usable duration of each qubit. Therefore, the quantum algorithm formed by the quantum logic functions not only expresses the operation relation of the algorithm, but also expresses the dependence of the algorithm on quantum bit individuals.
Exemplary:
quantum algorithm one: h1, H2, CNOT (1, 3), H3, CNOT (2, 3);
and a quantum algorithm II: h1, H2, CNOT (1, 2), H3, CNOT (2, 3);
Wherein 1/2/3 respectively represents three sequentially connected qubits Q1, Q2, Q3 or mutually connected qubits Q1, Q2, Q3;
an exemplary explanation of the quantum algorithm's influence by the quantum bit coherence time is as follows:
defining the execution time of a single-quantum bit logic gate as t, and 1 two single-quantum bit logic gates acting on adjacent bits as 2t; then:
When three Q1, Q2, Q3 are mutually connected, the first quantum algorithm needs to be calculated in 6t and 4 time periods, the time period needed by each time period is respectively t,2t, and the operations executed in each time period are as follows: h1 and H2; CNOT (1, 3); h3; CNOT (2, 3);
the first quantum algorithm is calculated by 5t and is carried out in 3 time periods, the time duration required by each time period is t,2t and 2t respectively, and the operation executed in each time period is as follows: h1, H2, H3; CNOT (1, 2); CNOT (2, 3);
When the Q1, the Q2 and the Q3 are connected in sequence, the quantum algorithm one needs to be equivalent to: h1 and H2; swap (1, 2), CNOT (2, 3), swap (1, 2); h3; CNOT (2, 3); the equivalent quantum algorithm I needs 10t to be calculated, and 4 time periods are divided, and the time duration needed by each time period is t,6t, t and 2t respectively. The operations performed in each time period are: h1 and H2; swap (1, 2), CNOT (2, 3), swap (1, 2); h3; CNOT (2, 3).
Therefore, the design of the quantum logic function acting on the quantum bit (including the design of whether the quantum bit is used or not and the design of the use efficiency of each quantum bit) is the key for improving the operation performance of the quantum computer, and special design is required, which is the uniqueness of the quantum algorithm realized based on the quantum logic function and is different from the nature and the significance of the classical algorithm realized based on the classical logic function. The above design for qubits is a technical problem that is not considered nor faced by common computing devices. Based on the above, the invention provides a W-state preparation method and a related device aiming at how to efficiently prepare a W state in quantum computation, and aims to realize the efficient preparation of the W state.
Referring to fig. 2, fig. 2 is a schematic flow chart of a W-state preparation method according to an embodiment of the present invention. The method comprises the following steps:
step 201: constructing a two-bit gate based on the controlled single-bit gate and the CNOT gate;
it is envisaged that there is a unitary transformation of two bits, with special manipulation of the state with hamming weight 1, to control the amplitude of the quantum states with equal hamming weight by reasonable rotation angle parameters, ultimately producing an equi-probability superposition state.
And decomposing the double-bit gate corresponding to the double-bit unitary transformation to obtain a controlled single-bit gate and a CNOT gate. In quantum computing, quantum logic gates are applied to corresponding qubits through their corresponding control waveforms, driving the evolution of the quantum states of the qubits. For the double-bit gate, the corresponding control waveform is more complex than that of the single-bit gate, and is more difficult to determine.
In a specific implementation, the control bit of the controlled single bit gate is the same as the control bit of the CNOT gate, and the control bit of the controlled single bit gate is the same as the control bit of the CNOT gate.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a dual bit gate according to an embodiment of the present invention. Double bit gateBy controlled single-bit gates acting on the same two qubits in turnAnd the control bit of the controlled single-bit gate is the same as the control bit of the CNOT gate, and the control bit of the controlled single-bit gate is the same as the control bit of the CNOT gate. Wherein the bit gate parameterA qubit determination based on the controlled single bit gate effect.
Step 202: constructing a W-state preparation quantum circuit based on the double-bit gate;
Specifically, the building of the W-state preparation quantum circuit based on the dual bit gate includes: and determining the number of the double-bit gates and the bit acted by each double-bit gate, and acting the double-bit gate on the corresponding bit to realize the construction of the W-state preparation quantum circuit.
Step 203: exciting the qubit to an initial state, and preparing a quantum wire based on the W state to drive the qubit to evolve from the initial state to the W state.
Wherein the initial state is a quantum state with Hamming weight of 1, and if the W-state preparation quantum circuit only comprises 2 quantum bits, the initial state can beOr (b); If 3 qubits are included, the initial state may be、Or (b); A specific implementation may first initialize all qubits toThen determining that excitation is requiredIs applied to the qubit by a control waveform of an not gate (X gate), to obtain an initial state.
Specifically, the step of driving the quantum bit to evolve from the initial state to the W state based on the W state preparation quantum circuit includes applying corresponding control waveforms to the corresponding quantum bits according to information such as a bit gate in the W state preparation quantum circuit, a bit acted by the bit gate, an action time sequence and the like, so as to realize driving the quantum bit to evolve from the initial state to the W state.
Compared with the prior art, the method has the advantages that the double-bit gate is built based on the controlled single-bit gate and the CNOT gate, the W-state preparation quantum circuit is built based on the double-bit gate, the quantum bit is excited to an initial state, and the W-state preparation quantum circuit drives the quantum bit to evolve from the initial state to the W state, so that the W-state efficient preparation is realized.
Further, the unitary matrix corresponding to the single bit gate in the controlled single bit gate isWherein the bit gate parameterA qubit determination based on the controlled single bit gate effect.
Wherein,The value of (2) is in the range of 0 to 1.
Can simply verify that the unitary matrix corresponds to the double-bit gateThe following properties are satisfied:
thus, for a system of N qubits, if the initial state is Only N-1 double bit gates are neededAdjusting each two-bit gateBit gate parameters of (2)The size, the W state can be obtained.
Specifically, the building of the W-state preparation quantum circuit based on the dual bit gate includes:
and (3) enabling N-1 double-bit gates to act on N quantum bits to obtain a W-state preparation quantum circuit, wherein N is an integer greater than 1.
In one embodiment of the present invention, the applying N-1 of the two-bit gates to N qubits includes:
Sequentially applying N-1 double-bit gates to two adjacent quantum bits, wherein the logic gate parameter of the ith double-bit gate Wherein, the value range of i is 1 to N-1.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a W-state fabricated quantum circuit according to an embodiment of the present invention. The W-state preparation quantum circuit includes N qubits: N-1 double bit gates: 。 acting on adjacent ，；Acting on adjacent，；······Acting on adjacent，。
From this embodiment it can be seen that each two-bit gate is based on the result of the previous two-bit gate acting on the qubit except for the first two-bit gate, and that only the quantum states of the co-action of the previous and the subsequent two-bit gates are used asIs not in quantum state ofIs N-1. Therefore, if rearrangement optimization can be performed on the double-bit gate, the depth of the quantum circuit can be reduced.
In another embodiment of the present invention, the applying N-1 of the two-bit gates to N qubits includes:
Constructing a binary tree structure of N quantum bits;
Determining a double-bit gate corresponding to each node in the binary tree structure;
and each double-bit gate is acted on two quantum bits corresponding to each double-bit gate.
Wherein the binary tree structure comprisesThe double-bit gate corresponding to the kth node of the jth layer is the ith double-bit gate; the bit acted by the kth node of the jth layer is one of the quantum bits and the kth node acted by the father node corresponding to the kth nodeA quantum bit, wherein i=J and k are integers greater than or equal to 1.
Wherein,Representing a rounding up, e.g. n=3, then=2; N=5, then=3. For layer 1, the node comprises 1 node, and the corresponding double-bit gate of the node is 1 st double-bit gateActing on the 1 st and 2 nd qubits) ; For the layer 2 comprising 2 nodes, the two-bit gate corresponding to the layer 2 node 1 is the 2 nd two-bit gateFather nodeOne of the qubits of action isTherefore it acts on the 1 st and 3 rd qubits [ ]) ; For the layer 2 comprising 2 nodes, the two-bit gate corresponding to the layer 2 node is the 3 rd two-bit gateFather nodeOne of the qubits of action isSo it acts on the 2 nd and 4 th qubits [ ]) ; Referring to fig. 5, fig. 5 is a schematic diagram of a binary tree structure according to an embodiment of the present invention.
It should be noted that, forWhen the bit gate parameter is an integer, the bit gate parameter corresponds to each double bit gateAll 1/2, i.e. the logic gate parameters of the ith said two-bit gateWherein, the value range of i is 1 to N-1.
For the followingIf not, the binary tree structure root node corresponds to the bit gate parameter of the double bit gateIs thatIf the parent node weight of any node isThen its left subtree root node weight isIts right subtree root node weight isWherein a and b are integers.
For n=5, for layer 1, comprising 1 node, the bit gate parameter of the corresponding two bit gate of this node is 2/5; for the layer 2 comprising 2 nodes, the bit gate parameter of the double bit gate corresponding to the layer 2 node 1 is 1/2; for the layer 2 comprising 2 nodes, the bit gate parameter of the double bit gate corresponding to the layer 2 node is 2/3; for the layer 3 comprising 1 node, the bit gate parameter of the double bit gate corresponding to the layer 3 node 1 is 1/2;
It can be seen that the two-bit gate parameters used in the embodiment of the present invention are still N-1, but the line depth is exponentially decreased, for example, at timing 2, and can be simultaneously applied AndWhile the previous embodimentCan only be atThis then acts to shorten the run time of the quantum program, which is critical to enhance the operational performance of quantum computers that suffer from coherence time.
Optionally, the method further comprises:
and if the quantum chip comprising the quantum bit does not support the double-bit gate, converting the double-bit gate into a basic bit gate supported by the quantum chip.
In the invention, the double-bit gate is constructed by the controlled single-bit gate and the CNOT gate, so that the double-bit gate is converted into the basic bit gate supported by the quantum chip, and only the controlled single-bit gate is required to be decomposed.
Any single bit gate can be decomposed intoIn the form of (a), wherein:
According to In matrix form, its decomposition form can be specifically given and various rotation angles and parameters can be obtainedIs the relation of: . Due to By controlling whether or not to act on two of the decomposed formsThe gate can be made as an arbitrary controlled single bit gate. Finally, a double-bit gate can be obtainedBy sequentially actingA gate, a CNOT gate,The control bit of the third CNOT gate is the same as the control bit of the first two CNOT gates, and the control bit of the third CNOT gate is the same as the control bit of the first two CNOT gates. Referring to fig. 6, fig. 6 is a schematic diagram of a disassembled structure of a dual bit gate according to an embodiment of the present invention.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a W-state preparation device according to an embodiment of the present invention. The device comprises:
A bit gate construction unit 701 for constructing a two-bit gate based on a controlled single-bit gate and a CNOT gate;
A circuit construction unit 702, configured to construct a W-state preparation quantum circuit based on the two-bit gate;
A quantum state preparation unit 703 for exciting the qubit to an initial state and preparing a quantum wire based on the W state to drive the qubit to evolve from the initial state to the W state.
Optionally, the unitary matrix corresponding to the single bit gate in the controlled single bit gate isWherein the bit gate parameterA qubit determination based on the controlled single bit gate effect.
Optionally, in the aspect of preparing a quantum wire based on the W state of the dual bit gate construction, the wire construction unit 702 is specifically configured to:
and (3) enabling N-1 double-bit gates to act on N quantum bits to obtain a W-state preparation quantum circuit, wherein N is an integer greater than 1.
Optionally, in the aspect of applying N-1 of the two-bit gates to N qubits, the circuit building unit 702 is specifically configured to:
Sequentially applying N-1 double-bit gates to two adjacent quantum bits, wherein the logic gate parameter of the ith double-bit gate Wherein, the value range of i is 1 to N-1.
Optionally, in the aspect of applying N-1 of the two-bit gates to N qubits, the circuit building unit 702 is specifically configured to:
Constructing a binary tree structure of N quantum bits;
Determining a double-bit gate corresponding to each node in the binary tree structure;
and each double-bit gate is acted on two quantum bits corresponding to each double-bit gate.
Optionally, the binary tree structure comprisesThe double-bit gate corresponding to the kth node of the jth layer is the ith double-bit gate; the bit acted by the kth node of the jth layer is one of the quantum bits and the kth node acted by the father node corresponding to the kth nodeA quantum bit, wherein i=J and k are integers greater than or equal to 1.
Optionally, the apparatus further comprises a logic gate conversion unit 704, configured to:
and if the quantum chip comprising the quantum bit does not support the double-bit gate, converting the double-bit gate into a basic bit gate supported by the quantum chip.
A further embodiment of the invention provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of the method embodiment of any of the above-mentioned methods when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
Constructing a two-bit gate based on the controlled single-bit gate and the CNOT gate;
constructing a W-state preparation quantum circuit based on the double-bit gate;
Exciting the qubit to an initial state, and preparing a quantum wire based on the W state to drive the qubit to evolve from the initial state to the W state.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Still another embodiment of the present invention provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the steps of the method embodiment of any of the above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
Constructing a two-bit gate based on the controlled single-bit gate and the CNOT gate;
constructing a W-state preparation quantum circuit based on the double-bit gate;
Exciting the qubit to an initial state, and preparing a quantum wire based on the W state to drive the qubit to evolve from the initial state to the W state.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (9)
1. A method for preparing a W-state, the method comprising:
Constructing a double-bit gate based on a controlled single-bit gate and a CNOT gate, wherein a unitary matrix corresponding to the single-bit gate in the controlled single-bit gate is as follows Wherein the bit gate parameterBased on the qubit determination of the controlled single bit gate effect,The value range of (2) is 0 to 1;
Sequentially applying N-1 double-bit gates to two adjacent quantum bits, wherein the logic gate parameter of the ith double-bit gate Wherein N is an integer greater than 1, and the value range of i is 1 to N-1;
exciting the quantum bit to an initial state, and preparing a quantum circuit based on the W state to drive the quantum bit to evolve from the initial state to the W state, wherein the initial state is a quantum state with Hamming weight of 1.
2. The method of claim 1, wherein the method further comprises:
and if the quantum chip comprising the quantum bit does not support the double-bit gate, converting the double-bit gate into a basic bit gate supported by the quantum chip.
3. A method for preparing a W-state, the method comprising:
Constructing a double-bit gate based on a controlled single-bit gate and a CNOT gate, wherein a unitary matrix corresponding to the single-bit gate in the controlled single-bit gate is as follows Wherein the bit gate parameterBased on the qubit determination of the controlled single bit gate effect,The value range of (2) is 0 to 1;
Constructing a binary tree structure of N quantum bits, and acting a double-bit gate corresponding to each node in the binary tree structure on two quantum bits corresponding to each double-bit gate, wherein N is an integer greater than 1;
exciting the quantum bit to an initial state, and preparing a quantum circuit based on the W state to drive the quantum bit to evolve from the initial state to the W state, wherein the initial state is a quantum state with Hamming weight of 1.
4. The method of claim 3, wherein the binary tree structure comprisesThe double-bit gate corresponding to the kth node of the jth layer is the ith double-bit gate; the bit acted by the kth node of the jth layer is one of the quantum bits and the kth node acted by the father node corresponding to the kth nodeA quantum bit, wherein i=J and k are integers greater than or equal to 1.
5. The method of any one of claims 3 or 4, wherein the method further comprises:
and if the quantum chip comprising the quantum bit does not support the double-bit gate, converting the double-bit gate into a basic bit gate supported by the quantum chip.
6. A W-state preparation device, the device comprising:
The bit gate construction unit is used for constructing a double-bit gate based on a controlled single-bit gate and a CNOT gate, wherein a unitary matrix corresponding to the single-bit gate in the controlled single-bit gate is that Wherein the bit gate parameterBased on the qubit determination of the controlled single bit gate effect,The value range of (2) is 0 to 1;
The circuit construction unit is used for sequentially acting N-1 double-bit gates on two adjacent quantum bits, wherein the logic gate parameter of the ith double-bit gate is N, N is an integer greater than 1, and the value range of i is 1 to N-1;
The quantum state preparation unit is used for exciting the quantum bit to an initial state and preparing a quantum circuit based on the W state to drive the quantum bit to evolve from the initial state to the W state, wherein the initial state is a quantum state with Hamming weight of 1.
7. A W-state preparation device, the device comprising:
The bit gate construction unit is used for constructing a double-bit gate based on a controlled single-bit gate and a CNOT gate, wherein a unitary matrix corresponding to the single-bit gate in the controlled single-bit gate is that Wherein the bit gate parameterBased on the qubit determination of the controlled single bit gate effect,The value range of (2) is 0 to 1;
the circuit construction unit is used for constructing a binary tree structure of N quantum bits and acting a double-bit gate corresponding to each node in the binary tree structure on two quantum bits corresponding to each double-bit gate, wherein N is an integer greater than 1;
The quantum state preparation unit is used for exciting the quantum bit to an initial state and preparing a quantum circuit based on the W state to drive the quantum bit to evolve from the initial state to the W state, wherein the initial state is a quantum state with Hamming weight of 1.
8. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 2 or 3 to 5 when run.
9. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of claims 1 to 2 or 3 to 5.
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| CN113222155A (en) * | 2020-01-21 | 2021-08-06 | 合肥本源量子计算科技有限责任公司 | Quantum line construction method and device, electronic device and storage medium |
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| US8849124B2 (en) * | 2012-05-04 | 2014-09-30 | Raytheon BBN Technologies, Corp. | Boundless reading of information bits with a single photon |
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