CN116402107A - Memristive bionic circuit for full-function pavlov associative memory and fear learning - Google Patents
Memristive bionic circuit for full-function pavlov associative memory and fear learning Download PDFInfo
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Abstract
The invention provides a memristive bionic circuit for full-function pavlov associative memory and fear learning, which is designed into nine neuron modules of an olfactory neuron module, an auditory neuron module, a visual neuron module, a pain neuron module, an auditory olfactory associative neuron module, a visual olfactory associative neuron module, an audiovisual sensory associative neuron module, an auditory pain associative neuron module and a visual pain associative neuron module. The neuron module constructed by using memristor has the advantages of more energy conservation and more visual weight change, and the interconnection of the nine neuron modules realizes the associative learning process of learning, forgetting, secondary learning, secondary forgetting, aibinhaos forgetting, stimulus interval learning, delay learning, blocking recovery, secondary regulation, intermittent stimulus promotion, potential inhibition and fear learning under three different conditions among different signals, so that the possibility of realizing a bio-bionic circuit by using hardware is widened.
Description
Technical Field
The invention relates to the technical field of neural network circuits, in particular to a memristive circuit for full-function pavlov associative memory and fear learning.
Background
In 2009, the teaching of Ventra and Pershin in combination with "parent of memristor" Cai Shaotang extended the concept and theory of memristors to the field of capacitive and inductive devices at Proceedings of the IEEE, and accordingly proposed memristive and memristive systems. The memcapacitor is used as a novel nonlinear passive device, the capacitance value of the memcapacitor is related to the history of input voltage/charge, the memcapacitor is an ideal device which is constructed together with the memristor and the like and is similar to an ultralow-energy nerve network of a memristor system, compared with the memristor-based nerve morphology calculation, the energy consumed on neuron receiving and transmitting signals by the memristor-based nerve morphology calculation is less, the capacitance state and the stored charge quantity of the memcapacitor before power failure can be stored after power failure, and the operation principle of the memcapacitor nerve morphology calculation circuit is more suitable for the signal transmission mode among neurons of actual living beings.
Associative learning is the association between conditional and unconditional stimuli that occur in biological cognition after a period of time when the organism is subjected to both stimuli. Fear learning is the fear response of an organism to a certain object. Some scholars have proposed memrist-based associative learning or emotion circuits, but do not use memrist to realize more comprehensive classical conditional reflex learning and fear learning circuits including time delay memory, potential suppression, secondary regulation, blocking and unblocking, etc., and the neural network circuit proposed by the present invention solves these problems.
Disclosure of Invention
Aiming at the technical problem that the existing neural network circuit does not consider the full-function pavlov associative memory and fear learning based on the memristive device, the invention provides the full-function pavlov associative memory and fear learning memristive bionic circuit, which realizes the associative learning of four signals and realizes that two similar stimulations can realize habituation.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows: a memristive bionic circuit for full-function pavlov associative memory and fear learning comprises an input signal end I 1 -I 4 Olfactory neuron module and pain godThe channel element module, the auditory neuron module, the visual neuron module, the auditory pain associated neuron module, the visual pain associated neuron module, the auditory olfactory associated neuron module, the visual olfactory associated neuron module, the audiovisual associated neuron module and the output signal end O 1 -O 2 Input signal terminal I representing a positive stimulus signal 1 The input end of the olfactory neuron module is connected with the input end of the olfactory neuron module; input signal terminal I representing a negative stimulus signal 3 The pain sensing neuron module is connected with the input end of the pain sensing neuron module; input signal terminal I representing neutral stimulus signal 2 Is connected with the input ends of the auditory neuron module, the auditory olfactory association neuron module, the auditory pain association neuron module and the audiovisual association neuron module respectively, and represents the input signal end I of the neutral stimulation signal 4 The input ends of the visual nerve cell module, the visual olfactory sensation association nerve cell module, the visual pain sensation association nerve cell module and the visual and audio association nerve cell module are respectively connected; the output end of the olfactory neuron module is respectively connected with the input ends of the auditory olfactory association neuron module and the visual olfactory association neuron module; the output end of the pain neuron module is respectively connected with the input ends of the auditory pain associated neuron module, the visual pain associated neuron module and the output protrusion module; the output end of the auditory neuron module is respectively connected with the input ends of the pain neuron module, the audiovisual association neuron module and the auditory sense and olfactory association neuron module, the output end of the visual neuron module is respectively connected with the input ends of the pain neuron module, the audiovisual association neuron module and the visual sense and olfactory association neuron module, the output end of the pain neuron module is respectively connected with the input ends of the auditory pain association neuron module and the visual sense and pain association neuron module, the output end of the auditory pain association neuron module is respectively connected with the input end of the auditory sense and olfactory association neuron module and the input end of the output protrusion module, and the output end of the visual pain association neuron module is respectively connected with the input ends of the visual sense and olfactory association neuron module and the output protrusion module; the output ends of the hearing-smell association neuron module are respectively used for viewing and viewing the association neuron module and the vision-smell association neuron module The output end is connected with the input end of the output synaptic module; the output end of the visual olfactory sensation association neuron module is respectively connected with the output ends of the auditory olfactory sensation association neuron module and the audiovisual association neuron module and the input end of the output synapse module; the output end of the audio-visual association neuron module is connected with the input end of the output protrusion module, and the output ends of the output protrusion module respectively obtain output signal ends O 1 And output signal terminal O 2 。
Preferably, the olfactory neuron module comprises a memristive MC 1 Arithmetic unit ABM 1 A first integrating circuit, a first voltage comparator, an NMOS tube T 1 And a first voltage control unit, the input signal terminal I 1 Respectively with resistance R 1 Is connected with one end of the first voltage-controlled unit, resistor R 1 The other end of (2) is respectively connected with the memristive MC 1 Positive terminal of (a), mathematical operation unit ABM 1 Is one input end of the memcapacitor MC 1 Negative terminal of (a) is respectively connected with the mathematical operation unit ABM 1 Is connected with the other input end of the NMOS tube T 1 The grid electrode of the NMOS tube T is connected with 1 The drain electrode of (2) is connected with a power supply V 1 Positive electrode of (a), power supply V 1 Is connected with the negative electrode of NMOS tube T 1 The sources of the transistors are all grounded; the mathematical operation unit ABM 1 The output end of the first voltage-controlled unit is an output end U1, and the output end U1 is respectively connected with the input ends of the auditory olfactory association neuron module and the visual olfactory association neuron module.
Preferably, the auditory neuron module and the visual neuron circuit each comprise a first memcapacitor, a first mathematical operation unit, a second integration circuit, a third integration circuit, a second voltage comparator, a third voltage comparator, a first inverting amplifier, a first summing amplifier circuit, a third inverting amplifier, a first inverting proportional amplifier, a fourth inverting amplifier and a second voltage control unit, and an input signal terminal I 2 Or input signal terminal I 4 Respectively with the firstOne end of a resistor is connected with one input end of a second voltage-controlled unit, the output end of a second integrator is connected with the input end of a third voltage comparator, the output end of the third voltage comparator is connected with the grid electrode of a first NMOS tube, the source electrode of the first NMOS tube is connected with the positive electrode of a first power supply, the negative electrode of the first power supply is grounded, the drain electrode of the first NMOS tube is respectively connected with one end of a second resistor and the input end of a first inverting amplifier, the other end of the second resistor is grounded, the output end of the first inverting amplifier is respectively connected with the other end of the first resistor and the input end of a first summing amplifier circuit through a third resistor, the output end of the first summing amplifier circuit is connected with the input end of a third inverting amplifier, the output end of the third inverting amplifier is respectively connected with the positive end of the first memcapacitor and one input end of the first mathematical operation unit through a fourth resistor, the negative end of the first memcapacitor is respectively connected with the other input end of the first mathematical operation unit and the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube is respectively connected with the positive electrode of the second mathematical operation unit and the second source electrode of the second NMOS tube is grounded; the output end of the first mathematical operation unit is respectively connected with the input ends of the second integration circuit and the third integration circuit, the output end of the second integration circuit is respectively connected with the anode of the third power supply and the source electrode of the third NMOS tube through a fifth resistor, the cathode of the third power supply is connected with the cathode of the first diode, and the anode of the first diode is grounded; the output end of the third integrating circuit is connected with the input end of the second voltage comparator, the output end of the second voltage comparator is connected with the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube is respectively connected with one end of the sixth resistor and the input end of the first inverting proportional amplifier, the other end of the sixth resistor is grounded, the output end of the first inverting proportional amplifier is connected with the input end of the fourth inverting amplifier, the output end of the fourth inverting amplifier is the first output end of the auditory neuron module or the visual neuron circuit, the first output end of the fourth inverting amplifier is connected with the other input end of the second voltage-controlled unit, and the output end of the second voltage-controlled unit is the second output end of the auditory neuron module or the visual neuron circuit; second outputs of the auditory neuron module and the visual neuron circuit All are connected with the input end of the audio-visual association neuron module; the first output end of the auditory neuron module is respectively connected with the input ends of the pain neuron module and the auditory olfactory association neuron module, and the first output end of the visual neuron module is respectively connected with the input ends of the pain neuron module and the visual olfactory association neuron module.
Preferably, the pain neuron module comprises a memristive MC 3 Arithmetic unit ABM 3 The input signal end I comprises a fourth integrating circuit, a fifth integrating circuit, a fourth voltage comparator, a fifth voltage comparator, a second inverting amplifier, a second summing amplifier circuit, a fifth inverting amplifier, a sixth voltage comparator, a sixth inverting amplifier, a third voltage-controlled unit and a fourth voltage-controlled unit 3 The output end of the fourth integrator is connected with the input end of a fifth voltage comparator, the output end of the fifth voltage comparator is connected with the grid electrode of a fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the positive electrode of a fourth power supply, the negative electrode of the fourth power supply is grounded, the drain electrode of the fourth NMOS tube is respectively connected with one end of an eighth resistor and the input end of a second inverting amplifier, the other end of the eighth resistor is grounded, the output end of the second inverting amplifier is respectively connected with the other end of the seventh resistor and the input end of a second summing amplifier circuit through a ninth resistor, the output end of the second summing amplifier circuit is connected with the input end of the fifth inverting amplifier circuit, and the output end of the fifth inverting amplifier circuit is respectively connected with the memcapacitor MC through a tenth resistor 3 Positive terminal of (a), mathematical operation unit ABM 3 Is connected with one input end of the memristive MC 3 Negative terminal of (a) is respectively connected with the mathematical operation unit ABM 3 The other input end of the fifth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the positive electrode of the fifth power supply, and the source electrode of the fifth NMOS tube and the negative electrode of the fifth power supply are grounded; the mathematical operation unit ABM 3 The output end of the fourth integrating circuit is respectively connected with the positive electrode and the second electrode of the sixth power supply through an eleventh resistorThe source electrode of the sixth NMOS tube is connected, the cathode of the sixth power supply is connected with the cathode of the second diode, and the anode of the second diode is grounded; the output end of the fifth integrating circuit is connected with the input end of the fourth voltage comparator, the output end of the fourth voltage comparator is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is connected with one end of the twelfth resistor and the input end of the sixth voltage comparator respectively, the other end of the twelfth resistor is grounded, the output end of the sixth voltage comparator is connected with the input end of the sixth inverting amplifier, the output end of the sixth inverting amplifier is connected with the input end of the first voltage summing module, the output end of the first voltage summing module is the output end U4 of the pain sense neuron module, the first output end of the auditory neuron module is connected with the other input end of the third voltage control unit, the output end of the third voltage control unit is the output end U5 of the pain sense neuron module, the first output end of the auditory neuron module is connected with the other input end of the fourth voltage control unit, and the output end of the fourth voltage control unit is the output end U6 of the pain sense neuron module.
Preferably, the auditory pain associated neuron module and the visual pain associated neuron module each comprise a second voltage summing module, a fifth voltage control unit, a third voltage summing module, a second memcapacitor, a second digital operation unit, a sixth integration circuit, a seventh voltage comparator, an eighth voltage comparator, a seventh inverting amplifier, a ninth voltage comparator, a tenth voltage comparator and a sixth voltage control unit, and an input signal terminal I 2 Or input signal terminal I 4 An input end of the second voltage summation module and an input end of the sixth voltage summation module are respectively connected, an output end U5 or an output end U6 of the pain sense neuron module is respectively connected with an input end of the first OR gate, an input end of the fifth voltage summation module and another input end of the second voltage summation module, an output end of the second voltage summation module is connected with another input end of the sixth voltage summation module, an output end of the sixth voltage summation module is connected with an input end of the third voltage summation module, another input end of the third voltage summation module is connected with an output end of the seventh inverting amplifier, and an output end of the third voltage summation module is connected with an output end of the seventh inverting amplifierThe thirteenth resistor is respectively connected with the positive end of the second memristor and one end of the second digital operation unit, the negative end of the second memristor is respectively connected with the other end of the second digital operation unit and the grid electrode of the seventh NMOS tube, the drain electrode of the seventh NMOS tube is connected with the positive electrode of the seventh power supply, and the negative electrode of the seventh power supply and the source electrode of the seventh NMOS tube are grounded; the output end of the second mathematical operation unit is respectively connected with the input ends of a sixth integration circuit and a seventh integration circuit, the output end of the sixth integration circuit is respectively connected with the positive electrode of an eighth power supply, one end of a fifteenth resistor and the source electrode of an eighth NMOS tube through a fourteenth resistor, the negative electrode of the eighth power supply is connected with the negative electrode of a third diode, the positive electrode of the third diode is grounded, the other end of the fifteenth resistor is connected with the input end of an eighth voltage comparator, the output end of the eighth voltage comparator is connected with the grid electrode of a ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the positive electrode of the ninth power supply, and the drain electrode of the ninth NMOS tube is respectively connected with one end of a seventeenth resistor and the input end of a seventh inverting amplifier; the output end of the seventh integrating circuit is connected with the input end of a seventh voltage comparator, the output end of the seventh voltage comparator is connected with the grid electrode of an eighth NMOS tube, the drain electrode of the eighth NMOS tube is connected with one end of a sixteenth resistor and the input end of a ninth voltage comparator, and the other end of the sixteenth resistor and the other end of a seventeenth resistor are grounded; the output end of the ninth voltage comparator is respectively connected with one end of the first capacitor, the other input end of the sixth voltage control unit and the input end of the tenth voltage comparator, the other end of the first capacitor is grounded, the output end of the sixth voltage control unit is connected with the other input end of the first OR gate, the output end of the first OR gate is the first output end of the auditory pain sensation association neuron module or the visual pain sensation association neuron module, the output end of the tenth voltage comparator is connected with one input end of the fourth voltage summation module, the other input end of the fourth voltage summation module is grounded through a tenth power supply, and the output end of the fourth voltage summation module is the second output end of the auditory pain sensation association neuron module or the visual pain sensation association neuron module; a first output terminal of the auditory pain associated neuron module and The input end of the auditory sense and sense of smell association neuron module is connected, the first output end of the visual sense and sense of pain association neuron module is connected with the input end of the visual sense and sense of smell association neuron module, and the second output ends of the auditory sense of pain association neuron module and the visual sense of pain association neuron module are connected with the input end of the output protrusion module.
Preferably, the auditory sense and olfactory sense association neuron module and the visual sense and olfactory sense association neuron module each comprise a seventh voltage-controlled unit, a fifth voltage-summing module, an eighth voltage-controlled unit, a ninth voltage-controlled unit, a tenth voltage-summing module, a sixth voltage-summing module, an eleventh voltage-controlled unit, a twelfth voltage-controlled unit, a seventh voltage-summing module, an eleventh voltage comparator, an eighth inverting amplifier, a third memristive, a third mathematical operation unit, an eighth integrating circuit, a ninth integrating circuit, a twelfth voltage comparator, a third inverting amplifier, a ninth inverting amplifier, a thirteenth voltage-controlled unit, a tenth inverting amplifier, a fourth inverting proportional amplifier, a tenth integrating circuit and a thirteenth voltage comparator, wherein the second output end of the auditory sense association neuron module is connected with the input end of a first non-gate of the visual sense association neuron module, the second output end of the visual sense association neuron module is connected with the input end of a first non-gate of the olfactory sense association neuron module, the output end of the first non-gate is connected with the first input end of the ninth voltage-controlled unit, the output end of the first non-gate voltage-controlled unit is connected with the eighteenth output end of the auditory sense association neuron module, the other end of the output unit is connected with the eighteenth output end of the second output resistor of the auditory sense association neuron module, and the eighteenth output end of the ninth output unit is connected with the eighteenth end of the eighth output resistor of the auditory sense association neuron module, and the eighteenth output end of the auditory sense association neuron module is connected with the eighth input end of the eighth resistor of the eighth input unit, respectively; the other input end of the tenth voltage-controlled unit is connected with the first output end of the auditory neuron module or the visual neuron module, the output end of the tenth voltage-controlled unit and the second output end of the auditory neuron module or the visual neuron module are connected with the input end of the sixth voltage summation module, the output end of the sixth voltage summation module is connected with the other input end of the eleventh voltage-controlled unit, and the output end of the eleventh voltage-controlled unit The output end of the eighth voltage-controlled unit is connected with one input end of the twelfth voltage-controlled unit, and the other input end of the twelfth voltage-controlled unit is connected with the first output end of the auditory pain sensation association neuron module or the visual pain sensation association neuron module; the output end of the eighth integrating circuit is connected with one input end of an eleventh voltage comparator through a nineteenth resistor, the other input end of the eleventh voltage comparator is grounded through a twelfth power supply, the output end of the eleventh voltage comparator is connected with the grid electrode of a tenth NMOS tube, the source electrode of the tenth NMOS tube is grounded through a thirteenth power supply, the drain electrode of the tenth NMOS tube is respectively connected with one end of the twentieth resistor and the input end of an eighth inverting amplifier, the other end of the twentieth resistor is grounded, the output end of the eighth inverting amplifier and the output end of a twelfth voltage-controlled unit are both connected with the input end of a seventh voltage summation module, the output end of the seventh voltage summation module is respectively connected with the positive end of a third memristive capacitor and one input end of the third mathematical operation unit, the negative end of the third memristive capacitor is respectively connected with the other input end of the third mathematical operation unit and the grid electrode of the eleventh NMOS tube, the source electrode of the eleventh NMOS tube is grounded, and the drain electrode of the eleventh NMOS tube is grounded through the thirteenth power supply; the output end of the third mathematical operation unit is respectively connected with the input ends of an eighth integration circuit and a ninth integration circuit, the output end of the eighth integration circuit is respectively connected with the anode of a fifteenth power supply and the source electrode of a twelfth NMOS tube through a twenty-first resistor, the cathode of the fifteenth power supply is connected with the cathode of a fourth diode, and the anode of the fourth diode is grounded; the output end of the ninth integrating circuit is connected with one input end of a twelfth voltage comparator, the other input end of the twelfth voltage comparator is grounded through a fourteenth power supply, and the output end of the twelfth voltage comparator is connected with a twelfth NMOS The drain electrode of the twelfth NMOS tube is respectively connected with one end of a twenty-second resistor and the input end of a third inverting amplifier, the other end of the twenty-second resistor is grounded, the output end of the third inverting amplifier is connected with the input end of a ninth inverting amplifier, the output end of the ninth inverting amplifier is connected with one input end of a thirteenth voltage-controlled unit, and the other input end of the thirteenth voltage-controlled unit is connected with an input signal end I 2 Or input signal terminal I 4 The output end of the thirteenth voltage-controlled unit is connected with the input end of a fourth inverting proportional amplifier, the output end of the fourth inverting proportional amplifier is connected with the input end of a tenth inverting amplifier, the output end of the tenth inverting amplifier and the output end U1 of the olfactory neuron module are both connected with the input end of a third OR gate, and the output end of the third OR gate is the first output end of the auditory olfactory associative neuron module or the visual olfactory associative neuron module; the output end of the third mathematical operation unit is also connected with the input end of a tenth integration circuit, the output end of the tenth integration circuit is connected with one input end of a thirteenth voltage comparator, the other input end of the thirteenth voltage comparator is grounded through a sixteenth power supply, and the output end of the thirteenth voltage comparator is a second output end of the hearing-smell association neuron module or the vision-smell association neuron module.
Preferably, the audiovisual association neuron module comprises a memristive MC 7 Arithmetic unit ABM 7 An eleventh integrating circuit, a twelfth integrating circuit, a fourteenth voltage comparator, a fifteenth voltage comparator, an eleventh inverting amplifier, a fifth inverting proportional amplifier, a twelfth inverting amplifier, an NMOS tube T 17 NMOS tube T 18 NMOS tube T 19 A fourteenth voltage control unit, a fifteenth voltage control unit, a sixteenth voltage control unit and a seventeenth voltage control unit, and a second output end of the hearing-smell associated neuron module is connected with a NAND gate G 3 Is connected with the input end of the NAND gate G 3 The output end of the fifteenth voltage control unit is connected with one input end of the fifteenth voltage control unit, and the other input end of the fifteenth voltage control unit is connected with the second output end of the visual neuron module; the visual sense and olfactory sense associated neuron moduleSecond output NAND gate G 2 Is connected with the input end of the NAND gate G 2 The output end of the fourteenth voltage-controlled unit is connected with one input end of the fourteenth voltage-controlled unit, and the other input end of the fourteenth voltage-controlled unit is connected with the second output end of the auditory neuron module; the output ends of the fourteenth voltage control unit and the fifteenth voltage control unit are both connected with the voltage summation module SUM 10 Is connected with the input end of the voltage summation module SUM 10 An output end of the sixteenth voltage-controlled unit is connected with an input end of the sixteenth voltage-controlled unit, and an input signal end I 2 And input signal terminal I 4 Are all connected with a voltage summation module SUM 12 Is connected with the input end of the voltage summation module SUM 12 The output end of the sixteenth voltage-controlled unit is connected with the voltage summation module SUM 11 Is connected with an input end of the power supply; the output end of the eleventh integrating circuit is connected with the resistor R 131 Is connected with one input end of the fifteenth voltage comparator, and the other input end of the fifteenth voltage comparator is connected with the power supply V 30 The output end of the fifteenth voltage comparator is grounded and connected with the NMOS tube T 19 The grid electrode of the NMOS tube T is connected with 19 Is connected with the source of the power supply V 31 Grounded NMOS tube T 19 The drain electrode of (a) is respectively connected with the resistor R 132 Is connected with the input end of the eleventh inverting amplifier, the output end of the eleventh inverting amplifier is connected with the SUM 11 Is connected with the other input end of the voltage summation module SUM 11 Output terminal of (d) and resistor R 124 Is connected with one end of resistor R 124 The other end of (2) is respectively connected with the memristive MC 7 Positive terminal of (a), mathematical operation unit ABM 7 Is connected with one input end of the memristive MC 7 Negative terminal of (a) is respectively connected with the mathematical operation unit ABM 7 Another input end of NMOS tube T 17 The grid electrode of the NMOS tube T is connected with 17 The source electrode of (2) is grounded, NMOS tube T 17 Through the grid of the power supply V 29 Grounded, mathematical operation unit ABM 7 The output end of the eleventh integrating circuit is connected with the input end of the eleventh integrating circuit and the input end of the twelfth integrating circuit respectively, and the output end of the eleventh integrating circuit is connected with the output end of the twelfth integrating circuit through a resistor R 130 Respectively are provided withWith power supply V 32 Positive electrode of (2), NMOS tube T 18 Is connected with the source of the power supply V 32 Cathode of (D) and diode D 7 Is connected with the cathode of the diode D 7 The positive electrode of (2) is grounded; the output end of the twelfth integrating circuit is connected with one input end of a fourteenth voltage comparator, the other input end of the fourteenth voltage comparator is grounded, and the output end of the fourteenth voltage comparator is connected with an NMOS tube T 18 The grid electrode of the NMOS tube T is connected with 18 The grid electrode of (C) is respectively connected with the resistor R 133 One end of each of the fifth inverting proportional amplifier is connected with the input end of the resistor R 133 The output end of the fifth inverting proportional amplifier is connected with the input end of the twelfth inverting amplifier, the output end of the twelfth inverting amplifier is connected with the other input end of the seventeenth voltage-controlled unit, and the output end of the seventeenth voltage-controlled unit is the output end U13 of the audio-visual association neuron module.
Preferably, the output synapse module comprises a sixteenth voltage comparator, a seventeenth voltage comparator, an eighteenth voltage control unit, a nineteenth voltage control unit and a twentieth voltage control unit, and the second output end of the auditory pain sensation association neuron module is respectively connected with the input end of the sixteenth voltage comparator and the OR gate G 7 An output end of the sixteenth voltage comparator is connected with the SUM 8 Is a voltage summing module SUM 8 Through the other input of the power supply V 28 Grounded, voltage summing module SUM 8 Output of (1) and AND gate G 8 Is connected with the input end I of the circuit board; the second output end of the visual pain associated neuron module is respectively provided with an input end of a seventeenth voltage comparator and an OR gate G 7 Is connected to the other input terminal of OR gate G 7 The output end of (2) is an output signal end O 1 The method comprises the steps of carrying out a first treatment on the surface of the The output end of the seventeenth voltage comparator and the voltage summation module SUM 9 Is a voltage summing module SUM 9 Through the other input of the power supply V 27 Grounded, voltage summing module SUM 9 Output of (1) and AND gate G 8 Is connected with the input end II of the pain neuron module, and the output end U4 of the pain neuron module is connected with the AND gate G 8 Is connected to the input terminal III of (C)Door G 8 The output end of the first voltage control unit is connected with one input end of the eighth voltage control unit, one input end of the nineteenth voltage control unit and one input end of the twentieth voltage control unit respectively; the first output end of the auditory sense and olfactory sense association neuron module is connected with one input end of an eighteenth voltage-controlled unit, the output end U13 of the auditory sense association neuron module is connected with the other input end of a nineteenth voltage-controlled unit, the first output end of the visual sense and olfactory sense association neuron module is connected with the other input end of a twentieth voltage-controlled unit, and the output ends of the eighteenth voltage-controlled unit, the nineteenth voltage-controlled unit and the twentieth voltage-controlled unit are all connected with an OR gate G 10 Is connected with the input end of OR gate G 10 The output end of (2) is an output signal end O 2 。
Compared with the prior art, the invention has the beneficial effects that:
(1) Based on the working principle of memristor, an integral bionic circuit is built, and the circuit structure is closer to a signal transmission mode among actual biological neurons.
(2) The use of nine similar neuron modules to achieve the mutual associative memory of two unconditional stimulation signals and two neutral stimulation signals is considered, and classical conditional reflex phenomena including learning, forgetting, secondary learning, aibinhaos memory, delayed associative memory, stimulus interval associative memory, occlusion deblocking, secondary regulation, potential inhibition, intermittent stimulation promotion are considered.
(3) Considering the influence of negative stimulus on normal associative learning in fear learning, the first established fear condition reflex influences the condition reflex to be established later, when two unconditional stimuli are applied simultaneously, the fear condition reflex is established by organisms preferentially, the fear learning can be simultaneously connected with the two conditional stimuli, and the effect is better than that of single condition stimulus.
According to the invention, through the connection among nine different memristive neuron modules, the pavlovian full-function associative memory is realized by using a circuit. In addition, the circuit constructed by the information transmission mode of the biological-like neurons has the advantages that the structure of the biological-like neurons is easier to expand and the signal transmission logic is clearer. The invention realizes different physiological reactions of organisms by associative learning of different unconditional stimuli through the output synaptic module.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a simplified schematic circuit diagram of the present invention.
FIG. 2 is a circuit diagram of the olfactory neuron module of FIG. 1 according to the present invention.
Fig. 3 is a circuit diagram of the auditory or visual neuron module of fig. 1 according to the present invention.
Fig. 4 is a circuit diagram of the pain neuron module of fig. 1 according to the present invention.
Fig. 5 is a circuit diagram of the auditory or visual pain neuron module of fig. 1 according to the present invention.
Fig. 6 is a circuit diagram of the auditory or visual olfactory associative neuron module of fig. 1 according to the present invention.
Fig. 7 is a circuit diagram of the auditory association neuron module of fig. 1 according to the present invention.
FIG. 8 is a graph showing simulation results of learning, forgetting, secondary learning and secondary forgetting, wherein (a) is the potential voltage of auditory olfactory associative neurons and (b) is the input signal terminal I 1 And (c) is the input signal terminal I 2 And (d) is the signal output terminal O 2 Is provided.
FIG. 9 is a diagram showing simulation results of learning and forgetting at short time intervals according to the present invention, wherein (a) is the potential voltage of auditory olfactory associative neurons and (b) is the input signal terminal I 1 And (c) is the input signal terminal I 2 And (d) is the output signal terminal O 2 Is provided.
FIG. 10 is a graph of simulation results of the secondary modulation of the present invention, wherein (a) is an audiovisual associative neuronPotential voltage, (b) is input signal terminal I 1 And (c) is the input signal terminal I 2 And (d) is the input signal terminal I 4 And (e) is the output signal terminal O 2 Is provided.
FIG. 11 is a graph of simulation results of intermittent stimulation according to the present invention, wherein (a) is the potential voltage of the audiovisual associative neurons and (b) is the input signal terminal I 1 And (c) is the input signal terminal I 2 And (d) is the input signal terminal I 4 And (e) is the output signal terminal O 2 Is provided.
FIG. 12 is a graph showing simulation results of a fear learning situation according to the present invention, in which (a) is the potential voltage of auditory pain associated neurons, (b) is the potential voltage of visual pain associated neurons, and (c) is the input signal terminal I 2 And (d) is the input signal terminal I 4 And (e) is the input signal terminal I 2 And (f) is the output signal terminal O 1 Is provided.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.
As shown in FIG. 1, a memristive bionic circuit for full-function pavlov associative memory and fear learning comprises an input signal terminal I 1 -I 4 Olfactory neuron module, pain neuron module, auditory neuron module, visual neuron module, auditory pain association neuron module, visual pain association neuron module, auditory olfactory association neuron module, visual olfactory association neuron module, audiovisual association neuron module, and output signal terminal O 1 -O 2 Input signal terminal I representing a positive stimulus signal 1 Inputs to olfactory neuron modules The ends are connected; input signal terminal I representing a negative stimulus signal 3 The pain sensing neuron module is connected with the input end of the pain sensing neuron module; input signal terminal I representing neutral stimulus signal 2 Is connected with the input ends of the auditory neuron module, the auditory olfactory association neuron module, the auditory pain association neuron module and the audiovisual association neuron module respectively, and represents the input signal end I of the neutral stimulation signal 4 The input ends of the visual nerve cell module, the visual olfactory sensation association nerve cell module, the visual pain sensation association nerve cell module and the visual and audio association nerve cell module are respectively connected; the output end of the olfactory neuron module is respectively connected with the input ends of the auditory olfactory association neuron module and the visual olfactory association neuron module; the output end of the pain neuron module is respectively connected with the input ends of the auditory pain associated neuron module, the visual pain associated neuron module and the output protrusion module; the output end of the auditory neuron module is respectively connected with the input ends of the pain neuron module, the audiovisual association neuron module and the auditory sense and olfactory association neuron module, the output end of the visual neuron module is respectively connected with the input ends of the pain neuron module, the audiovisual association neuron module and the visual sense and olfactory association neuron module, the output end of the pain neuron module is respectively connected with the input ends of the auditory pain association neuron module and the visual sense and pain association neuron module, the output end of the auditory pain association neuron module is respectively connected with the input end of the auditory sense and olfactory association neuron module and the input end of the output protrusion module, and the output end of the visual pain association neuron module is respectively connected with the input ends of the visual sense and olfactory association neuron module and the output protrusion module; the output ends of the hearing and smell association neuron module are respectively connected with the output ends of the hearing and smell association neuron module and the output end of the visual and smell association neuron module; the output end of the visual olfactory sensation association neuron module is respectively connected with the output ends of the auditory olfactory sensation association neuron module and the audiovisual association neuron module and the input end of the output synapse module; the output end of the audio-visual association neuron module is connected with the input end of the output protruding module, and the output ends of the output protruding module are respectively provided with an input Output signal end O 1 And output signal terminal O 2 . The auditory sense and olfactory sense association neuron module is connected with the visual sense and olfactory sense association neuron module; the output ends of the auditory sense and olfactory sense association neuron module, the visual sense and olfactory sense association neuron module and the audiovisual association neuron module are signal output ends O 2 The method comprises the steps of carrying out a first treatment on the surface of the The output end of the auditory pain sensation association neuron module and the visual pain sensation association neuron module is a signal output end O 1 And is connected with the output end O 2 Is connected with each other. Olfactory neuron module passes food-induced salivation signals through synapses U 1 To other neuron modules, the pain neuron module passes escape signals caused by electric shock through synapse U 4 、U 5 And U 6 To other neuron modules, the auditory neuron modules pass auditory signals caused by ringing through synapses U 2 And U 3 To other neuron modules, the visual neuron module transmits the auditory signal caused by the light through synapse U 7 And U 8 To other neuron modules, the auditory pain-associated neuron module passes escape signals caused by ringing through synapses U 10 To other neuronal modules, through synapses U 9 To the output module, the visual pain associated neuron module transmits escape signals caused by light through the synapse U 17 To other neuronal modules, through synapses U 16 Transmitting to an output module, and the auditory sense and sense association neuron module transmits the salivation signal caused by the bell to the synapse U 12 To other neuronal modules, through synapses U 11 Transmitting to an output module, and passing the salivation signal caused by the bell through synapse U by a visual olfactory association neuron module 15 To other neuronal modules, through synapses U 14 Transmitting to the output module, the audio-visual association neuron module passing the salivation signal caused by the bell through the synapse U 13 To the output module.
As shown in fig. 2, the input signal terminal I 1 Is connected with the input end of an olfactory neuron module, and the olfactory neuron module comprises memristive MC 1 Arithmetic unit ABM 1 Operational amplifier OP 1 -OP 2 NMOS tube T 1 DC voltageSource V 1 And a voltage-controlled switch S 1 Memristive MC 1 Respectively with resistor R 1 Sum mathematical operation unit ABM 1 Is connected with the IN1 end of the memristor MC 1 Respectively with the negative terminal of NMOS tube T 1 Grid and mathematical operation unit ABM 1 Is connected with the IN2 end of the NMOS tube T 1 The source electrode of (2) is grounded, NMOS tube T 1 The drain electrode of (2) is connected with a power supply V 1 Positive electrode of (a), power supply V 1 Is grounded with the negative electrode of NMOS tube T 1 And controlling the charge and discharge process of the memristor. Mathematical operation unit ABM 1 Memristive MC 1 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 1 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 1 If pass through memcapacitor MC 1 Is greater than NMOS transistor T 1 Voltage difference between drain and source of memcapacitor MC 1 Begin to charge accumulation, memristive MC 1 Capacitance value gradually becomes smaller and memristive capacitance MC 1 The required charging time is shorter, and the mathematical operation unit ABM 1 Output terminal OUT and resistor R of (1) 2 Is connected with a mathematical operation unit ABM 1 The output of Vout= - (V) IN1 -V IN2 ) Mathematical operation list ABM 1 Output memristive MC 1 The voltage at both ends of (a) increases and decreases, the resistance R 2 Respectively with the other end of the operational amplifier OP 1 Is the inverting input terminal of (C) and capacitor (C) 1 Connected with a capacitor C 1 Respectively with the other end of the operational amplifier OP 1 Is connected with the output end of the resistor R 3 One end of (a) and an operational amplifier OP 1 Is connected with the non-inverting input terminal of the resistor R 3 Is grounded at the other end of the operational amplifier OP 1 Resistance R 2 -R 3 And capacitor C 1 Forming a first integrating circuit; the output of the first integrating circuit is
Output end of integrating circuit and resistor R 4 Is connected with the resistor R 4 Respectively with diode D 1 Negative electrode of (a) and operational amplifier OP 2 Is connected to the non-inverting input terminal of diode D 1 The positive electrode of (D) is grounded 1 Limit the firstThe minimum voltage of the output end of the integrating circuit is 0V, and the resistor R 5 One end of (a) and an operational amplifier OP 2 Is connected with the inverting input terminal of the resistor R 5 Is grounded at the other end of the operational amplifier OP 2 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 2 An operational amplifier OP for inverting the input voltage 2 The output end of the (a) outputs a high level; operational amplifier OP 2 And resistance R 5 A first voltage comparator is formed. Input signal terminal I 1 Respectively with resistance R 1 And voltage-controlled switch S 1 Is connected with the first contact of the operational amplifier OP 2 Output terminal of (d) and voltage-controlled switch S 1 Is connected with the positive input terminal of the voltage-controlled switch S 1 Second contact of (2) and resistor R 6 Is connected with one end of resistor R 6 And voltage-controlled switch S 1 Is grounded, and a voltage-controlled switch S 1 The second contact of (2) is the output end of the olfactory neuron module. Voltage-controlled switch S 1 And resistance R 6 Forms a first voltage-controlled unit, a voltage-controlled switch S 1 Control whether salivation signals are transmitted to other neurons. When the operational amplifier OP 2 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 1 Voltage-controlled switch S at the time of the potential of the inverting input terminal 1 Switch on, voltage-controlled switch S 1 Second contact output voltage-controlled switch S 1 Is provided for the first contact of the first contact.
As shown in fig. 3, the input signal terminal I 2 Is connected with the input end of an auditory neuron module, wherein the auditory neuron module comprises a memristive MC 2 Arithmetic unit ABM 2 Operational amplifier OP 3 -OP 11 NMOS tube T 2 -T 4 DC voltage source V 2 -V 5 And a voltage-controlled switch S 2 Memristive MC 2 Respectively with resistor R 7 Sum mathematical operation unit ABM 2 Is connected with the IN1 end of the memristor MC 2 Respectively with the negative terminal of NMOS tube T 2 Grid and mathematical operation unit ABM 2 Is connected with the IN2 end of the NMOS tube T 2 The source electrode of (2) is grounded, NMOS tube T 2 The drain electrode of (2) is connected with a power supply V 2 Positive electrode of (a), power supply V 2 Is connected with the negative electrode ofGround, mathematical operation unit ABM 2 Memristive MC 2 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 2 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 2 If pass through memcapacitor MC 2 Is greater than NMOS transistor T 2 Voltage difference between drain and source of memcapacitor MC 2 Begin to charge accumulation, memristive MC 2 The capacitance value gradually becomes larger, and the memristive capacitance MC 2 The capacitance value of (a) can be increased along with the voltage increase, and the mathematical operation unit ABM 2 The output terminal OUT of (1) is respectively connected with the resistor R 8 And resistance R 10 Is connected with one end of the mathematical operation unit ABM 2 The output of Vout= - (V) IN1 -V IN2 ) Mathematical operation unit ABM 2 Output memristive MC 2 The voltage at both ends of (a) increases and decreases, the resistance R 8 Respectively with the other end of the operational amplifier OP 3 Is the inverting input terminal of (C) and capacitor (C) 2 Connected with a capacitor C 2 Respectively with the other end of the operational amplifier OP 3 Is connected with the output end of the resistor R 9 One end of (a) and an operational amplifier OP 3 Is connected with the non-inverting input terminal of the resistor R 9 Is grounded at the other end of the operational amplifier OP 3 Resistance R 8 -R 9 And capacitance C 2 Forming a second integrating circuit; resistor R 10 Respectively with the other end of the operational amplifier OP 4 Is the inverting input terminal of (C) and capacitor (C) 3 One end of (C) is connected to 3 Respectively with the other end of the operational amplifier OP 4 Is connected with the output end of the resistor R 11 One end of (a) and an operational amplifier OP 4 Is connected with the non-inverting input terminal of the resistor R 11 Is grounded at the other end of the operational amplifier OP 4 Resistance R 10 -R 11 And capacitance C 3 A third integrating circuit is formed. The output of the third integrating circuit is
The output end of the third integrating circuit and the operational amplifier OP 5 Is connected with the non-inverting input terminal of the resistor R 12 One end of (a) and an operational amplifier OP 5 Is connected with the inverting input terminal of the resistor R 12 Another of (2)Grounded, operational amplifier OP 5 And resistance R 12 A voltage comparator is formed. When the operational amplifier OP 5 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 5 An operational amplifier OP for inverting the input voltage 5 Output end of (a) outputs high level, operational amplifier OP 5 And NMOS transistor T 3 The gate of the second integrating circuit is connected with the output of the first integrating circuit >
The output end of the second integrating circuit is respectively connected with the resistor R 14 And resistance R 13 Is connected with one end of resistor R 13 The other end of (a) is respectively connected with the NMOS tube T 3 Source of (V) and power supply V 3 The positive electrode of NMOS tube T is connected with 3 The switch of (2) ensures that the output signal is positive. NMOS tube T 3 The drain electrode of (a) is respectively connected with the resistor R 26 And resistance R 27 Is connected with the resistor R 26 Is grounded at the other end of the operational amplifier OP 5 NMOS tube T when outputting high level 3 Conducting; resistor R 14 Is connected with the other end of the operational amplifier OP 6 Is connected with the non-inverting input terminal of the operational amplifier OP 6 Is an inverting input terminal of (a) and a resistor R 15 Is connected with one end of resistor R 15 Is connected with the other end of the power supply V 4 Is connected with the positive electrode of the power supply V 4 Is grounded at the negative electrode of the resistor R 15 Power supply V 4 Operational amplifier OP 6 A voltage comparator is formed. When the operational amplifier OP 6 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 6 A high level is output. Operational amplifier OP 6 And NMOS transistor T 4 The grid electrode of the NMOS tube T is connected with 4 Source of (V) and power supply V 5 Is connected with the positive electrode of the power supply V 5 Is grounded with the negative electrode of NMOS tube T 4 Switch determination forgetting voltage V 5 Whether to turn on. NMOS tube T 4 The drain electrode of (a) is respectively connected with the resistor R 16 And resistance R 17 Is connected with one end of resistor R 16 Is grounded at the other end of the operational amplifier OP 6 NMOS tube T when outputting high level 4 On, resistance R 17 Respectively with resistor R at the other end 19 Sum operational amplifier OP 7 Is connected with the inverting input terminal of the resistor R 18 One end of (a) and an operational amplifier OP 7 Is connected with the non-inverting input terminal of the operational amplifier OP 7 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 7 Respectively with resistor R 19 And the other end of (2) and the resistor R 20 Is connected with each other; operational amplifier OP 7 Resistance R 17 Resistance R 18 Resistance R 19 An inverting amplifier is formed. The input signal end I 2 Respectively with resistance R 21 And a voltage-controlled switch S 2 Is connected with the first contact of the resistor R 21 Respectively with resistor R at the other end 22 Resistance R 20 And an operational amplifier OP 8 Is connected with the inverting input terminal of the operational amplifier OP 8 Is grounded, and an operational amplifier OP 8 Resistance R 22 Forms a summing amplifier circuit, an operational amplifier OP 8 Output the input signal end I 2 And operational amplifier OP 8 The inverse of the sum of the voltages of the output signals. Operational amplifier OP 8 Output terminal of (d) and resistor R 23 Is connected with the resistor R 23 Respectively with resistor R at the other end 25 And operational amplifier OP 9 Is connected with the non-inverting input terminal of the operational amplifier OP 9 Is an inverting input terminal of (a) and a resistor R 24 Is connected with the resistor R 24 Is grounded at the other end of the operational amplifier OP 9 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 9 Respectively with resistor R 25 And the other end of (2) and the resistor R 7 The other end of the first connecting piece is connected with the other end of the second connecting piece; operational amplifier OP 9 Resistance R 23 Resistance R 24 Resistance R 25 An inverting amplifier is formed. Power supply V 3 Cathode of (D) and diode D 2 Is connected with the cathode of the diode D 2 The positive electrode of (D) is grounded 2 Limiting the lowest voltage of the output end of the second integrating circuit to be the power supply V 3 Voltage, resistance R 27 Respectively with resistor R at the other end 28 And operational amplifier OP 10 Is the phase of the inverting input terminal of (a)Connected to, operational amplifier OP 10 Is grounded, and an operational amplifier OP 10 Output ten times of the opposite voltage of the inverting input terminal thereof, operational amplifier OP 10 Resistance R 27 Resistance R 28 An inverting proportional amplifier is formed. Operational amplifier OP 10 Respectively with resistor R 28 And the other end of (2) and the resistor R 29 Is connected with the resistor R 29 Respectively with resistor R at the other end 30 And operational amplifier OP 11 Is connected with the inverting input terminal of the operational amplifier OP 11 Is grounded, and an operational amplifier OP 11 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 11 Output terminal of (d) and resistor R 30 Is connected with the other end of the operational amplifier OP 11 The output end of the (a) is the output end of the auditory neuron module; operational amplifier OP 11 Resistance R 29 Resistance R 30 An inverting amplifier is formed. The output end of the auditory neuron module is respectively connected with a voltage-controlled switch S 2 Voltage-controlled switch S 7 Voltage-controlled switch S 12 And a voltage-controlled switch S 13 Is connected with the non-inverting input terminal of the voltage-controlled switch S 2 Second contact of (2) and resistor R 188 Is connected with one end of resistor R 188 And voltage-controlled switch S 2 Is grounded when the operational amplifier OP 11 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 2 Voltage-controlled switch S at the time of the potential of the inverting input terminal 2 Switch on, voltage-controlled switch S 2 Second contact output voltage-controlled switch S 2 Is provided for the first contact of the first contact. Voltage-controlled switch S 2 Control whether to transmit a ring signal to the next neuron module.
As shown in fig. 4, the input signal terminal I 3 Is connected with the input end of the pain neuron module, and the pain neuron module comprises memristive MC 3 Arithmetic unit ABM 3 Operational amplifier OP 12 -OP 20 NMOS tube T 5 -T 7 DC voltage source V 6 -V 8 、V 26 And a voltage-controlled switch S 3 、S 13 Memristive MC 3 Respectively with resistor R 31 Sum mathematical operation unit ABM 3 Is connected with the IN1 end of the memristor MC 3 Respectively with the negative terminal of NMOS tube T 5 Grid and mathematical operation unit ABM 3 Is connected with the IN2 end of the NMOS tube T 5 The source electrode of (2) is grounded, NMOS tube T 5 The drain electrode of (2) is connected with a power supply V 6 Positive electrode of (a), power supply V 6 Is grounded by the negative electrode of the mathematical operation unit ABM 3 Memristive MC 3 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 3 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 3 If pass through memcapacitor MC 3 Is greater than NMOS transistor T 5 Voltage difference between drain and source of memcapacitor MC 3 Begin to charge accumulation, memristive MC 3 The capacitance value gradually becomes larger, and the memristive capacitance MC 3 The capacitance of (2) may increase with increasing voltage; mathematical operation unit ABM 3 The output terminal OUT of (1) is respectively connected with the resistor R 32 And resistance R 34 Is connected with a mathematical operation unit ABM 3 The output of Vout= - (V) IN1 -V IN2 ) Mathematical operation unit ABM 3 Output memristive MC 3 The voltage at both ends of (a) increases and decreases, the resistance R 32 Respectively with the other end of the operational amplifier OP 12 Is the inverting input terminal of (C) and capacitor (C) 4 Connected with a capacitor C 4 Respectively with the other end of the operational amplifier OP 12 Is connected with the output end of the resistor R 33 One end of (a) and an operational amplifier OP 12 Is connected with the non-inverting input terminal of the resistor R 33 Is grounded at the other end of the operational amplifier OP 12 Resistance R 32 -R 33 And capacitance C 4 Forming a fourth integrating circuit; resistor R 34 Respectively with the other end of the operational amplifier OP 13 Is the inverting input terminal of (C) and capacitor (C) 5 Connected with a capacitor C 5 Respectively with the other end of the operational amplifier OP 13 Is connected with the output end of the resistor R 35 One end of (a) and an operational amplifier OP 13 Is connected with the non-inverting input terminal of the resistor R 35 Is grounded at the other end of the operational amplifier OP 13 Resistance R 34 -R 35 And capacitance C 5 Forming a fifth integrating circuit; the output of the fifth integrating circuit is
Output end of fifth integrating circuit and operational amplifier OP 14 Is connected with the non-inverting input terminal of the resistor R 36 One end of (a) and an operational amplifier OP 14 Is connected with the inverting input terminal of the resistor R 36 Is grounded at the other end of the operational amplifier OP 5 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 5 An operational amplifier OP for inverting the input voltage 5 Output end of (a) outputs high level, operational amplifier OP 14 And NMOS transistor T 6 Is connected to the gate of the transistor. The output of the fourth integrating circuit is +.>
The output end of the fourth integrating circuit is respectively connected with the resistor R 37 And resistance R 38 Is connected with the resistor R 37 The other end of (a) is respectively connected with the NMOS tube T 6 Source of (V) and power supply V 7 The positive electrode of NMOS tube T is connected with 6 The drain electrode of (a) is respectively connected with the resistor R 50 And resistance R 51 Is connected with the resistor R 50 Is grounded at the other end of the operational amplifier OP 14 NMOS tube T when outputting high level 6 Conducting; resistor R 38 Is connected with the other end of the operational amplifier OP 15 Is connected with the non-inverting input terminal of the operational amplifier OP 15 Is an inverting input terminal of (a) and a resistor R 39 Is connected with the resistor R 39 Is grounded at the other end of the operational amplifier OP 15 Resistance R 39 A voltage comparator is formed. When the operational amplifier OP 15 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 15 Output high level, operational amplifier OP 15 And NMOS transistor T 7 The grid electrode of the NMOS tube T is connected with 7 Source of (V) and power supply V 8 Is connected with the positive electrode of the power supply V 8 Is grounded with the negative electrode of NMOS tube T 7 The drain electrode of (a) is respectively connected with the resistor R 40 And resistance R 41 Is connected with the resistor R 40 Is grounded at the other end of the operational amplifier OP 15 NMOS tube T when outputting high level 7 On, resistance R 41 Respectively with resistor R at the other end 43 Sum operational amplifier OP 16 Is connected with the inverting input terminal of the resistor R 42 One end of (a) and an operational amplifier OP 16 Is connected with the non-inverting input terminal of the resistor R 42 Is grounded at the other end of the resistor R 41 Resistance R 42 Resistance R 43 And operational amplifier OP 16 Constitutes an inverting amplifier, an operational amplifier OP 16 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 16 Respectively with resistor R 43 And the other end of (2) and the resistor R 44 Is connected with each other; the input signal end I 3 Respectively with resistance R 45 And a voltage-controlled switch S 3 、S 13 Is connected with the first contact of the resistor R 45 Respectively with resistor R at the other end 46 Resistance R 44 And an operational amplifier OP 17 Is connected with the inverting input terminal of the operational amplifier OP 17 Is grounded, and an operational amplifier OP 17 And resistance R 45 Forms a second summing amplifier circuit and an operational amplifier OP 17 Input/output signal terminal I 3 And operational amplifier OP 16 The inverse of the sum of the voltages of the output signals, operational amplifier OP 17 Output terminal of (d) and resistor R 47 Is connected with the resistor R 47 Respectively with resistor R at the other end 49 And operational amplifier OP 18 Is connected with the non-inverting input terminal of the operational amplifier OP 18 Is an inverting input terminal of (a) and a resistor R 48 Is connected with the resistor R 48 Is grounded at the other end of the resistor R 47 Resistance R 48 Resistance R 49 And operational amplifier OP 18 An inverting amplifier is formed. Operational amplifier OP 18 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 18 Respectively with resistor R 49 And the other end of (2) and the resistor R 31 Is connected with the other end of the connecting rod. Power supply V 7 Cathode of (D) and diode D 3 Is connected with the cathode of the diode D 3 The positive electrode of (D) is grounded 3 Limiting the minimum voltage at the output end of the integrating circuit I to be the power supply V 7 Voltage, resistance R 51 Another end of (a) and operationAmplifier OP 19 Is connected with the non-inverting input terminal of the operational amplifier OP 19 Through resistor R 52 Ground, resistance R 52 And operational amplifier OP 19 A voltage comparator is formed. When the operational amplifier OP 19 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 19 Output high level, operational amplifier OP 19 Output terminal of (a) and operational amplifier OP 20 Is connected with the inverting input terminal of the operational amplifier OP 20 Is connected with the non-inverting input terminal of the resistor R 53 Is connected with the resistor R 53 Is grounded at the other end of the resistor R 53 And operational amplifier OP 20 Constitutes an inverting amplifier, an operational amplifier OP 20 Output the voltage signal with opposite inverting input end, operational amplifier OP 20 Output terminal of (a) and voltage summation module SUM 7 Is connected with one input end of the power supply V 26 SUM of positive and voltage summation module SUM 7 Is connected with the other input end of the power supply V 26 Is grounded at the negative electrode of the voltage summation module SUM 7 The sum of the two input voltages is output. The input signal end I 3 Respectively with voltage-controlled switch S 3 And a voltage-controlled switch S 13 Is connected with the first contact of the auditory neuron module, and the output end of the auditory neuron module is connected with the voltage-controlled switch S 13 Is connected with the non-inverting input terminal of the voltage-controlled switch S 13 Second contact of (2) and resistor R 190 Is connected with one end of resistor R 190 And voltage-controlled switch S 13 When the potential of the output end of the auditory neuron module is larger than that of the voltage-controlled switch S 13 Voltage-controlled switch S at the time of the potential of the inverting input terminal 13 Switch on, voltage-controlled switch S 13 Second contact output voltage-controlled switch S 13 The output end of the visual neuron module is connected with the voltage-controlled switch S 3 Is connected with the non-inverting input terminal of the voltage-controlled switch S 3 Second contact of (2) and resistor R 194 Is connected with one end of resistor R 194 And voltage-controlled switch S 3 When the potential of the output end of the optical neuron module is larger than that of the voltage-controlled switch S 3 Is the voltage of the reverse phase input terminalControl switch S 3 Switch on, voltage-controlled switch S 3 Second contact output voltage-controlled switch S 3 Is provided for the first contact of the first contact. Voltage-controlled switch S 13 And a voltage-controlled switch S 3 Whether to transmit escape signals to the corresponding neuron module is controlled by the auditory signal and the visual signal, respectively.
As shown in fig. 1, an input signal terminal I 4 Is connected with the input end of the visual neuron module, and the visual neuron module comprises memristive MC 4 Arithmetic unit ABM 4 Operational amplifier OP 21 -OP 29 NMOS tube T 8 -T 10 DC voltage source V 9 -V 12 And a voltage-controlled switch S 18 Memristive MC 4 Respectively with resistor R 54 Sum mathematical operation unit ABM 4 Is connected with the IN1 end of the memristor MC 4 Respectively with the negative terminal of NMOS tube T 8 Grid and mathematical operation unit ABM 4 Is connected with the IN2 end of the NMOS tube T 8 The source electrode of (2) is grounded, NMOS tube T 8 The drain electrode of (2) is connected with a power supply V 9 Positive electrode of (a), power supply V 9 Is grounded by the negative electrode of the mathematical operation unit ABM 4 Memristive MC 4 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 4 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 4 If pass through memcapacitor MC 4 Is greater than NMOS transistor T 8 Voltage difference between drain and source of memcapacitor MC 4 Begin to charge accumulation, memristive MC 4 The capacitance value gradually becomes larger, and the memristive capacitance MC 4 The passable voltage of (2) increases with the capacitance value; mathematical operation unit ABM 4 The output terminal OUT of (1) is respectively connected with the resistor R 55 And resistance R 57 Is connected with a mathematical operation unit ABM 4 The output of Vout= - (V) IN1 -V IN2 )，ABM 4 Output memristive MC 4 The voltage at both ends of (a) increases and decreases, the resistance R 55 Respectively with the other end of the operational amplifier OP 21 Is the inverting input terminal of (C) and capacitor (C) 6 Connected with a capacitor C 6 Respectively with the other end of the operational amplifier OP 21 Is connected with the output end of the resistor R 56 One end of (a) and an operational amplifier OP 21 Is connected to the non-inverting input terminal of (a)Is connected with the resistor R 56 Is grounded at the other end of the operational amplifier OP 21 Resistance R 55 -R 56 And capacitance C 6 An integrating circuit I is formed; resistor R 57 Respectively with the other end of the operational amplifier OP 22 Is the inverting input terminal of (C) and capacitor (C) 7 Connected with a capacitor C 7 Respectively with the other end of the operational amplifier OP 22 Is connected with the output end of the resistor R 58 One end of (a) and an operational amplifier OP 22 Is connected with the non-inverting input terminal of the resistor R 58 Is grounded at the other end of the operational amplifier OP 22 Resistance R 57 -R 58 And capacitance C 7 Forming an integrating circuit; the output of the integrating circuit is
Output end of integrating circuit and operational amplifier OP 23 Is connected with the non-inverting input terminal of the resistor R 59 One end of (a) and an operational amplifier OP 23 Is connected with the inverting input terminal of the resistor R 59 Is grounded at the other end of the operational amplifier OP 23 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 23 An operational amplifier OP for inverting the input voltage 23 Output end of (a) outputs high level, operational amplifier OP 23 And NMOS transistor T 9 The gate of the integrating circuit is connected with
The output end of the integrating circuit is respectively connected with the resistor R 61 And resistance R 60 Is connected with the resistor R 60 The other end of (a) is respectively connected with the NMOS tube T 9 Source of (V) and power supply V 10 The positive electrode of NMOS tube T is connected with 9 The drain electrode of (a) is respectively connected with the resistor R 73 And resistance R 74 Is connected with the resistor R 73 Is grounded at the other end of the operational amplifier OP 23 NMOS tube T when outputting high level 9 Conducting; resistor R 61 Is connected with the other end of the operational amplifier OP 24 Is connected with the non-inverting input terminal of the operational amplifier OP 24 Is an inverting input terminal of (a) and a resistor R 62 Is connected with one end of resistor R 62 Is connected with the other end of the power supply V 11 Is connected with the positive electrode of the power supply V 11 Is grounded at the negative electrode of the operational amplifier OP 24 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 24 Output high level, operational amplifier OP 24 And NMOS transistor T 10 The grid electrode of the NMOS tube T is connected with 10 Source of (V) and power supply V 12 Is connected with the positive electrode of the power supply V 12 Is grounded with the negative electrode of NMOS tube T 10 The drain electrode of (a) is respectively connected with the resistor R 63 And resistance R 64 Is connected with the resistor R 63 Is grounded at the other end of the operational amplifier OP 24 NMOS tube T when outputting high level 10 On, resistance R 64 Respectively with resistor R at the other end 66 Sum operational amplifier OP 25 Is connected with the inverting input terminal of the resistor R 65 One end of (a) and an operational amplifier OP 25 Is connected with the non-inverting input terminal of the resistor R 65 Is grounded at the other end of the operational amplifier OP 25 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 25 Respectively with resistor R 66 And the other end of (2) and the resistor R 67 Is connected with each other; the input signal end I 4 Respectively with resistance R 68 And a voltage-controlled switch S 18 Is connected with the first contact of the resistor R 68 Respectively with resistor R at the other end 69 Resistance R 67 And an operational amplifier OP 26 Is connected with the inverting input terminal of the operational amplifier OP 26 Is grounded, and an operational amplifier OP 26 Output the input signal end I 4 And operational amplifier OP 25 The inverse of the sum of the voltages of the output signals, operational amplifier OP 26 Output terminal of (d) and resistor R 70 Is connected with the resistor R 70 Respectively with resistor R at the other end 72 And operational amplifier OP 27 Is connected with the non-inverting input terminal of the operational amplifier OP 27 Is an inverting input terminal of (a) and a resistor R 71 Is connected with the resistor R 71 Is grounded at the other end of the operational amplifier OP 27 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 27 Respectively with the resistorR 72 And the other end of (2) and the resistor R 54 The other end of the first connecting piece is connected with the other end of the second connecting piece; power supply V 10 Cathode of (D) and diode D 4 Is connected with the cathode of the diode D 4 The positive electrode of (D) is grounded 4 Limiting the minimum voltage at the output end of the integrating circuit I to be the power supply V 10 Voltage, resistance R 74 Respectively with resistor R at the other end 75 And operational amplifier OP 28 Is connected with the inverting input terminal of the operational amplifier OP 28 Is grounded, and an operational amplifier OP 28 Output ten times of the opposite voltage of the inverting input terminal thereof, operational amplifier OP 28 Respectively with resistor R 75 And the other end of (2) and the resistor R 76 Is connected with the resistor R 76 Respectively with resistor R at the other end 77 And operational amplifier OP 29 Is connected with the inverting input terminal of the operational amplifier OP 29 Is grounded, and an operational amplifier OP 29 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 29 Output terminal of (d) and resistor R 77 Is connected with the other end of the operational amplifier OP 29 The output end of the (2) is the output end of the visual neuron module; the output end of the visual neuron module is respectively connected with a voltage-controlled switch S 3 Voltage-controlled switch S 18 And a voltage-controlled switch S 19 Is connected with the non-inverting input terminal of the voltage-controlled switch S 18 Second contact of (2) and resistor R 195 Is connected with one end of R 195 And voltage-controlled switch S 18 Is grounded when the operational amplifier OP 29 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 18 Voltage-controlled switch S at the time of the potential of the inverting input terminal 18 Switch on, voltage-controlled switch S 18 Second contact output voltage-controlled switch S 2 Is provided for the first contact of the first contact.
As shown in fig. 5, the input signal terminal I 2 SUM-and-voltage summing module SUM 1 Is connected to one input terminal of the voltage-controlled switch S 13 Respectively with the resistor R 78 SUM-voltage summing module SUM 1 Is connected to the other input terminal of the voltage summing module SUM 1 Output input Signal I 2 And a voltage-controlled switch S 13 The SUM of the output signal potentials of the second contacts of (a) and the SUM of the voltage module SUM 1 Output terminal of (d) and voltage-controlled switch S 4 Is connected with the first contact of the resistor R 78 Respectively with the other end of the capacitor C 25 And a voltage-controlled switch S 4 A capacitor C connected with the non-inverting input terminal of (C) 25 Is grounded at the other end of the resistor R 78 And capacitor C 25 For removing noise from the signal. Voltage-controlled switch S 4 Respectively with the voltage summation module SUM 2 One end input of (2) and resistor R 79 Is connected with one end of resistor R 79 And voltage-controlled switch S 4 Is grounded when the voltage-controlled switch S 13 The potential of the output end of the second contact of (a) is larger than that of the voltage-controlled switch S 4 Voltage-controlled switch S at the time of the potential of the inverting input terminal 4 Switch on, voltage-controlled switch S 4 Second contact output voltage-controlled switch S 4 Is a signal of the first contact of the voltage summing module SUM 2 Output voltage-controlled switch S 4 Second contact output signal of (a) and operational amplifier OP 34 Output signal potential SUM, voltage summation module SUM 2 Output terminal of (d) and resistor R 80 Is connected with each other. The auditory pain associated neuron module comprises memristive MC 5 Arithmetic unit ABM 5 Operational amplifier OP 30 -OP 36 NMOS tube T 11 -T 13 Logic gate G 5 DC voltage source V 13 -V 18 And a voltage-controlled switch S 4 -S 5 Memristive MC 5 Respectively with resistor R 80 The other end and the mathematical operation unit ABM 5 Is connected with the IN1 end of the memristor MC 5 Respectively with the negative terminal of NMOS tube T 11 Grid and mathematical operation unit ABM 5 Is connected with the IN2 end of the NMOS tube T 11 The source electrode of (2) is grounded, NMOS tube T 11 The drain electrode of (2) is connected with a power supply V 13 Positive electrode of (a), power supply V 13 Is grounded by the negative electrode of the mathematical operation unit ABM 5 Memristive MC 5 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 5 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 5 If pass through memcapacitor MC 5 Is greater than NMOS transistor T 11 Drain and of (2)Voltage difference of source electrode and memcapacitor MC 5 Begin to charge accumulation, memristive MC 5 The capacitance value gradually becomes larger, and the memristive capacitance MC 5 The passable voltage of (2) increases with the capacitance value; mathematical operation unit ABM 5 The output terminal OUT of (1) is respectively connected with the resistor R 81 And resistance R 84 Is connected with a mathematical operation unit ABM 5 The output of Vout= - (V) IN1 -V IN2 )，ABM 5 Output memristive MC 5 The voltage at both ends of (a) increases and decreases, the resistance R 81 Respectively with the other end of the operational amplifier OP 30 Is the inverting input terminal of (C) and capacitor (C) 8 Connected with a capacitor C 8 Respectively with the other end of the operational amplifier OP 30 Is connected with the output end of the resistor R 82 One end of (a) and an operational amplifier OP 30 Is connected with the non-inverting input terminal of the resistor R 82 Is grounded at the other end of the operational amplifier OP 30 Resistance R 81 -R 82 And capacitance C 8 An integrating circuit I is formed; resistor R 84 Respectively with the other end of the operational amplifier OP 31 Is the inverting input terminal of (C) and capacitor (C) 9 Connected with a capacitor C 9 Respectively with the other end of the operational amplifier OP 31 Is connected with the output end of the resistor R 85 One end of (a) and an operational amplifier OP 31 Is connected with the non-inverting input terminal of the resistor R 85 Is grounded at the other end of the operational amplifier OP 31 Resistance R 84 -R 85 And capacitance C 9 Forming an integrating circuit II; the output of the integrating circuit II is
Output end of integrating circuit II and operational amplifier OP 32 Is connected with the non-inverting input terminal of the resistor R 86 One end of (a) and an operational amplifier OP 32 Is connected with the inverting input terminal of the resistor R 86 Is grounded at the other end of the operational amplifier OP 32 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 32 An operational amplifier OP for inverting the input voltage 32 Output end of (a) outputs high level, operational amplifier OP 32 And NMOS transistor T 12 Is connected with the grid of the integrationThe output of circuit I is->
The output end of the integrating circuit I and a resistor R 83 Is connected with the resistor R 83 Respectively with resistor R at the other end 87 NMOS tube T 12 Source of (V) and power supply V 14 The positive electrode of NMOS tube T is connected with 12 The drain electrode of (a) is respectively connected with the resistor R 92 And operational amplifier OP 35 Is connected with the non-inverting input terminal of the resistor R 92 Is grounded at the other end of the resistor R 92 And operational amplifier OP 35 A voltage comparator is formed. When the operational amplifier OP 32 NMOS tube T when outputting high level 12 Conducting; resistor R 87 Is connected with the other end of the operational amplifier OP 33 Is connected with the non-inverting input terminal of the operational amplifier OP 33 Is an inverting input terminal of (a) and a resistor R 88 Is connected with one end of resistor R 88 Is connected with the other end of the power supply V 15 Is connected with the positive electrode of the power supply V 15 Is grounded at the negative electrode of the resistor R 88 Power supply V 15 And operational amplifier OP 33 A voltage comparator is formed. When the operational amplifier OP 33 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 33 Output high level, operational amplifier OP 33 And NMOS transistor T 13 The grid electrode of the NMOS tube T is connected with 13 Source of (V) and power supply V 16 Is connected with the positive electrode of the power supply V 16 Is grounded with the negative electrode of NMOS tube T 13 The drain electrode of (a) is respectively connected with the resistor R 89 And resistance R 90 Is connected with the resistor R 89 Is grounded at the other end of the operational amplifier OP 33 NMOS tube T when outputting high level 13 On, resistance R 90 Respectively with resistor R at the other end 92 Is connected to one end of the operational amplifier OP 34 Is connected with the inverting input terminal of the resistor R 91 One end of (a) and an operational amplifier OP 34 Is connected with the non-inverting input terminal of the resistor R 91 Is grounded at the other end of the resistor R 92 Is connected with the other end of the operational amplifier OP 34 Is connected with the output end of the resistor R 90 Resistance R 91 Resistance R 92 And operational amplifier OP 34 Constitutes an inverting amplifier, an operational amplifier OP 34 Outputting a voltage opposite to its inverting input. Operational amplifier OP 34 Output terminal of (a) and voltage summation module SUM 2 Is connected with the other input end of the first power supply; power supply V 14 Cathode of (D) and diode D 5 Is connected with the cathode of the diode D 5 The positive electrode of (D) is grounded 5 Limiting the minimum voltage at the output end of the integrating circuit I to be the power supply V 14 Voltage of (1), operational amplifier OP 35 Is an inverting input terminal of (a) and a resistor R 93 Is connected with the resistor R 93 Is connected with the other end of the power supply V 17 Is connected with the positive electrode of the power supply V 17 Is grounded at the negative electrode of the resistor R 93 Power supply V 17 And operational amplifier OP 35 A voltage comparator is formed. When the operational amplifier OP 35 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 35 Output high level, operational amplifier OP 35 Respectively with the capacitor C 10 Voltage-controlled switch S 5 Is connected to the non-inverting input terminal of the operational amplifier OP 36 Is connected with the non-inverting input terminal of the resistor R 94 And operational amplifier OP 36 Is connected with the inverting input terminal of the resistor R 94 Is grounded at the other end of the resistor R 94 And operational amplifier OP 36 Constitutes a voltage comparator, when the operational amplifier OP 36 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 36 Output high level, operational amplifier OP 36 Output of (1) and SUM 3 Is connected with one input end of the power supply V 18 SUM of positive and voltage summation module SUM 3 Is connected with the other end of the power supply V 18 Is grounded at the negative electrode of the voltage summation module SUM 3 Output operational amplifier OP 36 Output signal and power supply V 18 Is a sum of voltages of the plurality of voltages. The input signal end I 2 And a voltage-controlled switch S 5 Is connected with the first contact of the voltage-controlled switch S 5 Respectively with resistor R 95 And or gate G 5 Is connected to one input terminal of resistor R 95 And voltage-controlled switch S 5 Is connected to the inverting input terminal of (a)Grounded, when the operational amplifier OP 35 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 5 Voltage-controlled switch S at the time of the potential of the inverting input terminal 5 Switch on, voltage-controlled switch S 5 Second contact output voltage-controlled switch S 5 Is a signal of the first contact of the voltage-controlled switch S 13 And OR gate G 5 Is connected to another input terminal of OR gate G 5 Or gate G when any input terminal of (a) has a high level input 5 Output high level, OR gate G 5 The output end of the (2) is the output end of the auditory pain sense association neuron module; the output ends of the auditory pain associated neuron modules are respectively connected with an OR gate G 7 And an operational amplifier OP 53 Is connected to the inverting input terminal of (c).
Input signal terminal I 4 SUM unit SUM 15 Is connected to one input terminal of the unit SUM 15 Output input Signal I 4 And a voltage-controlled switch S 3 The sum of the output signal potentials of the second contacts of the voltage-controlled switch S 3 Respectively with the resistor R 164 SUM unit SUM 15 Is connected to the other input terminal of the unit SUM 15 Output terminal of (d) and voltage-controlled switch S 24 Is connected with the first contact of the resistor R 164 Respectively with the other end of the capacitor C 21 And a voltage-controlled switch S 24 A capacitor C connected with the non-inverting input terminal of (C) 21 Is grounded, voltage-controlled switch S 24 Respectively with the unit SUM 16 One end input of (2) and resistor R 165 Is connected with one end of resistor R 165 And voltage-controlled switch S 24 Is grounded when the voltage-controlled switch S 3 The potential of the output end of the second contact of (a) is larger than that of the voltage-controlled switch S 24 Voltage-controlled switch S at the time of the potential of the inverting input terminal 24 Switch on, voltage-controlled switch S 24 Second contact output voltage-controlled switch S 24 Signal of the first contact of (a), unit SUM 16 Output voltage-controlled switch S 24 Second contact output signal of (a) and operational amplifier OP 68 Output signal potential SUM, unit SUM 16 Output terminal of (d) and resistor R 166 Connected, the visual pain associated neuron module comprises a memristive MC 9 Arithmetic unit ABM 9 Operational amplifier OP 64 -OP 70 NMOS tube T 23 -T 25 Logic gate G 11 DC voltage source V 37 -V 42 And a voltage-controlled switch S 24 -S 25 Memristive MC 9 Respectively with resistor R 166 The other end and the mathematical operation unit ABM 9 Is connected with the IN1 end of the memristor MC 9 Respectively with the negative terminal of NMOS tube T 23 Grid and mathematical operation unit ABM 9 Is connected with the IN2 end of the NMOS tube T 23 The source electrode of (2) is grounded, NMOS tube T 23 The drain electrode of (2) is connected with a power supply V 37 Positive electrode of (a), power supply V 37 Is grounded by the negative electrode of the mathematical operation unit ABM 9 Memristive MC 9 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 9 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 9 If pass through memcapacitor MC 9 Is greater than NMOS transistor T 23 Voltage difference between drain and source of memcapacitor MC 9 Begin to charge accumulation, memristive MC 9 The capacitance value gradually becomes larger, and the memristive capacitance MC 9 The passable voltage of (2) increases with the capacitance value; mathematical operation unit ABM 9 The output terminal OUT of (1) is respectively connected with the resistor R 168 And resistance R 170 Is connected with a mathematical operation unit ABM 9 The output of Vout= - (V) IN1 -V IN2 )，ABM 9 Output memristive MC 9 The voltage at both ends of (a) increases and decreases, the resistance R 168 Respectively with the other end of the operational amplifier OP 64 Is the inverting input terminal of (C) and capacitor (C) 19 Connected with a capacitor C 19 Respectively with the other end of the operational amplifier OP 64 Is connected with the output end of the resistor R 167 One end of (a) and an operational amplifier OP 64 Is connected with the non-inverting input terminal of the resistor R 167 Is grounded at the other end of the operational amplifier OP 64 Resistance R 167 -R 168 And capacitance C 19 An integrating circuit I is formed; resistor R 170 Respectively with the other end of the operational amplifier OP 65 Is the inverting input terminal of (C) and capacitor (C) 20 Connected with a capacitor C 20 Respectively with the other end of the operational amplifier OP 65 Output phase of (2)Connection, resistance R 171 One end of (a) and an operational amplifier OP 65 Is connected with the non-inverting input terminal of the resistor R 171 Is grounded at the other end of the operational amplifier OP 65 Resistance R 170 -R 171 And capacitance C 20 Forming an integrating circuit II; the output of the integrating circuit II is
Output end of integrating circuit II and operational amplifier OP 66 Is connected with the non-inverting input terminal of the resistor R 172 One end of (a) and an operational amplifier OP 66 Is connected with the inverting input terminal of the resistor R 172 Is grounded at the other end of the operational amplifier OP 66 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 66 An operational amplifier OP for inverting the input voltage 66 Output end of (a) outputs high level, operational amplifier OP 66 And NMOS transistor T 24 The gate of the integration circuit I is connected with the output of the integration circuit I>
Output end of integrating circuit I and resistor R 169 Is connected with the resistor R 169 Respectively with resistor R at the other end 173 NMOS tube T 24 Source of (V) and power supply V 38 The positive electrode of NMOS tube T is connected with 24 The drain electrode of (a) is respectively connected with the resistor R 178 And operational amplifier OP 69 Is connected with the non-inverting input terminal of the resistor R 178 Is grounded at the other end of the operational amplifier OP 66 NMOS tube T when outputting high level 24 Conducting; resistor R 173 Is connected with the other end of the operational amplifier OP 67 Is connected with the non-inverting input terminal of the operational amplifier OP 67 Is an inverting input terminal of (a) and a resistor R 174 Is connected with one end of resistor R 174 Is connected with the other end of the power supply V 39 Is connected with the positive electrode of the power supply V 39 Is grounded at the negative electrode of the operational amplifier OP 67 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 67 Output high level, operational amplifier OP 67 And NMOS transistor T 25 The grid electrode of the NMOS tube T is connected with 25 Source of (V) and power supply V 40 Is connected with the positive electrode of the power supply V 40 Is grounded with the negative electrode of NMOS tube T 25 The drain electrode of (a) is respectively connected with the resistor R 175 And resistance R 176 Is connected with the resistor R 175 Is grounded at the other end of the operational amplifier OP 67 NMOS tube T when outputting high level 25 On, resistance R 176 Respectively with resistor R at the other end 178 Sum operational amplifier OP 68 Is connected with the inverting input terminal of the resistor R 177 One end of (a) and an operational amplifier OP 68 Is connected with the non-inverting input terminal of the resistor R 177 Is grounded at the other end of the operational amplifier OP 68 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 68 Output of (a) and unit SUM 16 Is connected with the other input end of the first power supply; power supply V 38 Cathode of (D) and diode D 9 Is connected with the cathode of the diode D 9 The positive electrode of (D) is grounded 9 Limiting the minimum voltage at the output end of the integrating circuit I to be the power supply V 38 Voltage of (1), operational amplifier OP 69 Is an inverting input terminal of (a) and a resistor R 179 Is connected with the resistor R 179 And the other end of the sum is connected with a power supply V 41 Is connected with the positive electrode of the power supply V 41 Is grounded at the negative electrode of the operational amplifier OP 69 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 69 Output high level, operational amplifier OP 69 Respectively with the capacitor C 22 Voltage-controlled switch S 25 Is connected to the non-inverting input terminal of the operational amplifier OP 70 Is connected with the non-inverting input terminal of the resistor R 180 And operational amplifier OP 70 Is connected with the inverting input terminal of the resistor R 180 Is grounded at the other end of the operational amplifier OP 70 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 70 Output high level, operational amplifier OP 70 Output of (a) and unit SUM 17 Is connected with one input end of the power supply V 42 Positive electrode of (a) and unit SUM 17 Is connected with the other end of the power supply V 42 Is grounded to the negative electrode of the unit SUM 17 Output operational amplifier OP 70 Output signal and power supply V 42 Is a sum of voltages of (a) and (b); the input signal end I 4 And a voltage-controlled switch S 25 Is connected with the first contact of the voltage-controlled switch S 25 Respectively with resistor R 181 And or gate G 11 Is connected to one input terminal of resistor R 181 And voltage-controlled switch S 25 Is grounded when the operational amplifier OP 69 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 25 Voltage-controlled switch S at the time of the potential of the inverting input terminal 25 Switch on, voltage-controlled switch S 25 Second contact output voltage-controlled switch S 25 Is a signal of the first contact of the voltage-controlled switch S 3 And OR gate G 11 Is connected to another input terminal of OR gate G 11 Or gate G when any input terminal of (a) has a high level input 11 Output high level, OR gate G 11 The output end of the (2) is the output end of the visual pain sensation association neuron module; the output end of the auditory-visual pain association neuron module is respectively connected with an OR gate G 7 Is connected to the other input terminal of the operational amplifier OP 54 Is connected to the inverting input terminal of (c).
As shown in fig. 6, the auditory olfactory associative neuron module includes a memristive MC 6 Arithmetic unit ABM 6 Operational amplifier OP 37 -OP 45 And OP (optical path) 71 -OP 72 NMOS tube T 14 -T 16 Logic gate G 1 And G 6 DC voltage source V 43 And V is equal to 19 -V 25 And a voltage-controlled switch S 6 -S 12 The output end of the olfactory neuron module is respectively connected with a voltage-controlled switch S 6 And OR gate G 6 Is connected to one input terminal of the NOT gate G 1 Is a voltage-controlled switch S 6 Is connected with the non-inverting input terminal of the voltage-controlled switch S 6 The visual sense and olfactory sense association neuron module controls whether to transmit salivation signals to the auditory sense and olfactory sense association neuron module. Voltage-controlled switch S 6 Respectively with resistor R 182 Resistance R 183 And a voltage-controlled switch S 7 Is connected to the first contact of the NOT gate G 1 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 6 Voltage-controlled switch S at the time of the potential of the inverting input terminal 6 Switch on, voltage-controlled switch S 6 Second contact output voltage-controlled switch S 6 Is a signal of the first contact of the voltage-controlled switch S 7 Respectively with resistor R 184 SUM unit SUM 4 Is connected to one input terminal of the resistor R 184 And voltage-controlled switch S 7 Is grounded when the operational amplifier OP 11 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 7 Voltage-controlled switch S at the time of the potential of the inverting input terminal 7 Switch on, voltage-controlled switch S 7 Second contact output voltage-controlled switch S 6 Is a signal of the first contact of the voltage-controlled switch S 2 Second contact of (a) and unit SUM 4 Is connected to the other input terminal of the resistor R 183 Respectively with the other end of the capacitor C 11 And a voltage-controlled switch S 8 Is connected with the non-inverting input terminal of the capacitor C 11 Is grounded at the other end of the voltage summation module SUM 4 Output voltage-controlled switch S 7 Second contact output signal of (a) and voltage-controlled switch S 2 The second contact of (2) outputs a signal potential SUM, unit SUM 4 Output terminal of (d) and voltage-controlled switch S 8 Is connected with the first contact of the voltage-controlled switch S 8 Respectively with resistor R 185 And a voltage-controlled switch S 9 Is connected with the first contact of the resistor R 185 And voltage-controlled switch S 8 Is grounded when the voltage-controlled switch S 6 The potential of the output end of the second contact of (a) is larger than that of the voltage-controlled switch S 8 Voltage-controlled switch S at the time of the potential of the inverting input terminal 8 Switch on, voltage-controlled switch S 8 Second contact output voltage-controlled switch S 8 Is a signal of the first contact of the voltage-controlled switch S 9 Respectively with resistor R 186 And a voltage-controlled switch S 10 Is connected with the first contact of the resistor R 186 And voltage-controlled switch S 9 Is grounded when the voltage summation module SUM 6 The potential of the output end is greater than that of the voltage-controlled switch S 9 Voltage-controlled switch S at the time of the potential of the inverting input terminal 9 Switch on, voltage-controlled switch S 9 Second contact output voltage-controlled switch S 9 Is a signal of the first contact of the hearing aidOutput end of the sensory neuron module and voltage-controlled switch S 12 Is connected with the non-inverting input terminal of the voltage-controlled switch S 12 Is connected with the power supply V 25 Positive electrode of (a) is connected with a voltage-controlled switch S 12 Respectively with resistor R 189 SUM-voltage summing module SUM 6 Is connected to one input terminal of the resistor R 189 Respectively with the other end of the power V 24 Negative electrode of (d) and voltage-controlled switch S 12 Is grounded when the operational amplifier OP 11 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 12 Voltage-controlled switch S at the time of the potential of the inverting input terminal 12 Switch on, voltage-controlled switch S 12 Second contact output voltage-controlled switch S 12 Signal of the first contact of (a), power supply V 25 SUM of positive and voltage summation module SUM 6 Is connected with the other input end of the power supply V 25 Is grounded to the negative electrode of the unit SUM 6 Output voltage-controlled switch S 12 And a second contact of (2) outputs a signal and a power supply V 25 The SUM of the positive potentials of the cells SUM 6 Output terminal of (d) and voltage-controlled switch S 9 Is connected with the non-inverting input terminal of the voltage-controlled switch S 10 Respectively with resistor R 187 SUM unit SUM 5 Is connected to one input terminal of the resistor R 187 And voltage-controlled switch S 10 Is grounded, unit SUM 3 Output terminal of (d) and voltage-controlled switch S 10 Is connected to the non-inverting input terminal of the voltage summing module SUM 3 The potential of the output end is greater than that of the voltage-controlled switch S 10 Voltage-controlled switch S at the time of the potential of the inverting input terminal 10 Switch on, voltage-controlled switch S 10 Second contact output voltage-controlled switch S 10 Is a signal of the first contact of the voltage summing module SUM 5 Output voltage-controlled switch S 10 Second contact output signal of (a) and operational amplifier OP 41 Output signal potential SUM, voltage summation module SUM 5 Output terminal of (d) and resistor R 98 One end of (a) is connected with the memristive MC 6 Respectively with resistor R 98 The other end and the mathematical operation unit ABM 6 Is connected with the IN1 end of the memristor MC 6 Respectively with the negative terminal of NMOS tube T 14 Grid and mathematical operation unit ABM 6 Is connected with the IN2 end of the NMOS tube T 14 The source electrode of (2) is grounded, NMOS tube T 14 The drain electrode of (2) is connected with a power supply V 19 Positive electrode of (a), power supply V 19 Is grounded by the negative electrode of the mathematical operation unit ABM 6 Memristive MC 6 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 6 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 6 If pass through memcapacitor MC 6 Is greater than NMOS transistor T 14 Voltage difference between drain and source of memcapacitor MC 6 Begin to charge accumulation, memristive MC 6 Capacitance value gradually becomes smaller and memristive capacitance MC 6 The charging speed of (2) is faster; mathematical operation unit ABM 6 The output terminal OUT of (1) is respectively connected with the resistor R 99 Resistance R 101 And resistance R 121 Is connected with a mathematical operation unit ABM 6 The output of Vout= - (V) IN1 -V IN2 ) Mathematical operation unit ABM 6 Output memristive MC 6 The voltage at both ends of (a) increases and decreases, the resistance R 99 Respectively with the other end of the operational amplifier OP 37 Is the inverting input terminal of (C) and capacitor (C) 12 Connected with a capacitor C 12 Respectively with the other end of the operational amplifier OP 37 Is connected with the output end of the resistor R 100 One end of (a) and an operational amplifier OP 37 Is connected with the non-inverting input terminal of the resistor R 100 Is grounded at the other end of the operational amplifier OP 37 Resistance R 99 -R 100 And capacitance C 12 An integrating circuit I is formed; resistor R 101 Respectively with the other end of the operational amplifier OP 38 Is the inverting input terminal of (C) and capacitor (C) 13 Connected with a capacitor C 13 Is connected with the other end of the operational amplifier OP 38 Is connected with the output end of the resistor R 102 One end of (a) and an operational amplifier OP 38 Is connected with the non-inverting input terminal of the resistor R 102 Is grounded at the other end of the operational amplifier OP 38 Resistance R 101 -R 102 And capacitance C 13 Forming an integrating circuit II; resistor R 121 Respectively with the other end of the operational amplifier OP 71 Is the inverting input terminal of (C) and capacitor (C) 23 Connected with a capacitor C 23 Is connected with the other end of the operational amplifier OP 71 Output phase of (2)Connection, resistance R 122 One end of (a) and an operational amplifier OP 71 Is connected with the non-inverting input terminal of the resistor R 122 Is grounded at the other end of the operational amplifier OP 71 Resistance R 121 -R 122 And capacitance C 23 An integrating circuit III is formed. The output of the integrating circuit III is
Output end of integrating circuit III and operational amplifier OP 72 Is connected with the non-inverting input terminal of the resistor R 123 One end of (a) and an operational amplifier OP 72 Is connected with the inverting input terminal of the resistor R 123 Is connected with the other end of the power supply V 43 Is connected with the positive electrode of the power supply V 43 Is grounded at the negative electrode of the resistor R 123 Power supply V 43 And operational amplifier OP 72 A voltage comparator is formed. When the operational amplifier OP 72 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 72 An operational amplifier OP for inverting the input voltage 72 The output end of the integration circuit II outputs high level, and the output end of the integration circuit II is +>
Output end of integrating circuit II and operational amplifier OP 39 Is connected with the non-inverting input terminal of the resistor R 103 One end of (a) and an operational amplifier OP 39 Is connected with the inverting input terminal of the resistor R 103 Is connected with the other end of the power supply V 20 Is connected with the positive electrode of the power supply V 20 Is grounded at the negative electrode of the resistor R 103 Power supply V 20 And operational amplifier OP 72 A voltage comparator is formed. When the operational amplifier OP 39 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 39 An operational amplifier OP for inverting the input voltage 39 Outputs a high level. Operational amplifier OP 39 And NMOS transistor T 15 The gate of the integration circuit I is connected with the output of the integration circuit I>
Output terminal of integrating circuit IIs not connected with resistor R 104 And resistance R 105 Is connected with the resistor R 104 The other end of (a) is respectively connected with the NMOS tube T 15 Source of (V) and power supply V 23 Is connected with the positive electrode of the power supply V 23 Cathode of (D) and diode D 6 Is connected with the cathode of the diode D 6 The positive electrode of (D) is grounded 6 Limiting the minimum voltage at the output end of the integrating circuit I to be the power supply V 23 NMOS tube T 15 The drain electrode of (a) is respectively connected with the resistor R 111 And resistance R 112 Is connected with the resistor R 111 Is grounded at the other end of the operational amplifier OP 39 NMOS tube T when outputting high level 15 Conducting; resistor R 105 Is connected with the other end of the operational amplifier OP 40 Is connected with the non-inverting input terminal of the operational amplifier OP 40 Is an inverting input terminal of (a) and a resistor R 106 Is connected with one end of resistor R 106 Is connected with the other end of the power supply V 21 Is connected with the positive electrode of the power supply V 21 Is grounded at the negative electrode of the resistor R 106 Power supply V 21 And operational amplifier OP 72 A voltage comparator is formed. When the operational amplifier OP 40 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 40 A high level is output. Operational amplifier OP 40 And NMOS transistor T 16 The grid electrode of the NMOS tube T is connected with 16 Source of (V) and power supply V 22 Is connected with the positive electrode of the power supply V 22 Is grounded with the negative electrode of NMOS tube T 16 The drain electrode of (a) is respectively connected with the resistor R 107 And resistance R 108 Is connected with the resistor R 107 Is grounded at the other end of the operational amplifier OP 40 NMOS tube T when outputting high level 16 On, resistance R 108 Respectively with resistor R at the other end 110 Sum operational amplifier OP 25 Is connected with the inverting input terminal of the resistor R 109 One end of (a) and an operational amplifier OP 41 Is connected with the non-inverting input terminal of the resistor R 109 Is grounded at the other end of the resistor R 108 Resistance R 109 Resistance R 110 Operational amplifier OP 41 Constitutes an inverting amplifier, an operational amplifier OP 41 Output voltage opposite to its inverting input terminal, operational amplifier Amplifier OP 41 Respectively with resistor R 110 Is connected with the other end of the unit SUM 5 Is connected with the other input end of the first power supply; resistor R 112 Respectively with resistor R at the other end 113 And an operational amplifier OP 42 Is connected with the inverting input terminal of the operational amplifier OP 42 The non-inverting input terminal of (2) is grounded, the resistor R 112 Resistance R 113 Operational amplifier OP 42 An inverting proportional amplifier is formed. Operational amplifier OP 42 Ten times the voltage output opposite to its inverting input, OP 42 Output terminal of (d) and resistor R 114 Is connected with the resistor R 114 Respectively with resistor R at the other end 115 And operational amplifier OP 43 Is connected with the inverting input terminal of the operational amplifier OP 43 The non-inverting input terminal of (2) is grounded, the resistor R 114 Resistance R 115 Operational amplifier OP 43 Constitutes an inverting amplifier, when the operational amplifier OP 43 Outputting a voltage opposite to its inverting input. Operational amplifier OP 43 Respectively with resistor R 115 And voltage-controlled switch S 11 Is connected with the non-inverting input terminal of the input signal terminal I 2 And a voltage-controlled switch S 11 Is connected with the first contact of the voltage-controlled switch S 11 Respectively with resistor R 116 And resistance R 117 Is connected with a resistor R 116 And voltage-controlled switch S 11 Is grounded when the operational amplifier OP 43 The potential of the output end is greater than that of the voltage-controlled switch S 11 Voltage-controlled switch S at the time of the potential of the inverting input terminal 11 Switch on, voltage-controlled switch S 11 Second contact output voltage-controlled switch S 11 Signal of the first contact of (a), resistance R 117 Respectively with resistor R at the other end 118 And operational amplifier OP 44 Is connected with the inverting input terminal of the operational amplifier OP 44 The non-inverting input terminal of (2) is grounded, the resistor R 117 Resistance R 118 Operational amplifier OP 44 An inverting proportional amplifier is formed. . Operational amplifier OP 44 Ten times the voltage opposite to its inverting input is output. Operational amplifier OP 44 Output terminal of (2)Respectively with resistance R 118 And the other end of (2) and the resistor R 119 Is connected with the resistor R 119 Respectively with resistor R at the other end 120 And operational amplifier OP 45 Is connected with the inverting input terminal of the operational amplifier OP 45 The non-inverting input terminal of (2) is grounded, the resistor R 119 Resistance R 120 Operational amplifier OP 45 Constitutes an inverting amplifier, an operational amplifier OP 45 Outputting a voltage opposite to its inverting input. Operational amplifier OP 45 Output of (1) and OR gate G 6 The output end of the olfactory neuron module is connected with an OR gate G 6 Is connected to another input terminal of the OR gate G 6 Or gate G when any input terminal of (a) has a high level input 6 Output high level, OR gate G 6 Output terminal of (d) and voltage-controlled switch S 26 Is connected to the first contact of OR gate G 6 The output end of the (2) is the output end of the olfactory auditory association neuron module.
Visual olfactory sense association neuron module comprises memristive MC 8 Arithmetic unit ABM 8 Operational amplifier OP 55 -OP 63 And OP (optical path) 73 -OP 74 NMOS tube T 20 -T 22 Logic gate G 4 And G 9 DC voltage source V 44 -V 45 And V is equal to 33 -V 36 And a voltage-controlled switch S 29 -S 30 And S is equal to 19 -S 23 The output end of the olfactory neuron module is respectively connected with a voltage-controlled switch S 23 And OR gate G 9 Is connected to one input terminal of the NOT gate G 4 Is a voltage-controlled switch S 23 Is connected with the non-inverting input terminal of the voltage-controlled switch S 23 Respectively with resistor R 197 Resistance R 198 And a voltage-controlled switch S 19 Is connected to the first contact of the NOT gate G 4 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 23 Voltage-controlled switch S at the time of the potential of the inverting input terminal 23 Switch on, voltage-controlled switch S 23 Second contact output voltage-controlled switch S 23 Is a signal of the first contact of the voltage-controlled switch S 19 Respectively with resistor R 196 SUM unit SUM 13 Is connected to one input terminal of the resistor R 196 And voltage-controlled switch S 19 Is grounded when the operational amplifier OP 29 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 19 Voltage-controlled switch S at the time of the potential of the inverting input terminal 19 Switch on, voltage-controlled switch S 19 Second contact output voltage-controlled switch S 19 Is a signal of the first contact of the voltage-controlled switch S 18 Second contact of (a) and unit SUM 13 Is connected to the other input terminal of the resistor R 198 Respectively with the other end of the capacitor C 18 And a voltage-controlled switch S 20 Is connected with the non-inverting input terminal of the capacitor C 18 Is grounded at the other end of the unit SUM 13 Output voltage-controlled switch S 18 Second contact output signal of (a) and voltage-controlled switch S 19 The second contact of (2) outputs a signal potential SUM, unit SUM 13 Output terminal of (d) and voltage-controlled switch S 20 Is connected with the first contact of the voltage-controlled switch S 20 Respectively with resistor R 199 And a voltage-controlled switch S 30 Is connected with the first contact of the resistor R 199 And voltage-controlled switch S 20 Is grounded when the voltage-controlled switch S 23 The potential of the output end of the second contact of (a) is larger than that of the voltage-controlled switch S 20 Voltage-controlled switch S at the time of the potential of the inverting input terminal 20 Switch on, voltage-controlled switch S 20 Second contact output voltage-controlled switch S 20 Is a signal of the first contact of the voltage-controlled switch S 30 Respectively with resistor R 211 And a voltage-controlled switch S 21 Is connected with the first contact of the resistor R 211 And voltage-controlled switch S 30 Is grounded when the cell SUM 18 The potential of the output end is greater than that of the voltage-controlled switch S 30 Voltage-controlled switch S at the time of the potential of the inverting input terminal 30 Switch on, voltage-controlled switch S 30 Second contact output voltage-controlled switch S 30 The output end of the visual neuron module is connected with the voltage-controlled switch S 29 Is connected with the non-inverting input terminal of the voltage-controlled switch S 29 Is connected with the power supply V 45 Positive electrode of (a) is connected with a voltage-controlled switch S 29 Respectively with resistor R 210 SUM unit SUM 18 Is connected to one input terminal of the resistor R 210 Respectively with the other end of the power V 45 Negative electrode of (d) and voltage-controlled switch S 29 Is grounded when the operational amplifier OP 29 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 29 Voltage-controlled switch S at the time of the potential of the inverting input terminal 29 Switch on, voltage-controlled switch S 29 Second contact output voltage-controlled switch S 29 Signal of the first contact of (a), power supply V 46 Positive electrode of (a) and unit SUM 18 Is connected with the other input end of the power supply V 46 Is grounded to the negative electrode of the unit SUM 18 Output voltage-controlled switch S 29 And a second contact of (2) outputs a signal and a power supply V 46 The SUM of the positive potentials of the cells SUM 18 Output terminal of (d) and voltage-controlled switch S 30 Is connected with the non-inverting input terminal of the voltage-controlled switch S 21 Respectively with resistor R 200 SUM unit SUM 14 Is connected to one input terminal of the resistor R 200 And voltage-controlled switch S 21 Is grounded, unit SUM 17 Output terminal of (d) and voltage-controlled switch S 21 Is connected to the non-inverting input terminal of the unit SUM 17 The potential of the output end is greater than that of the voltage-controlled switch S 21 Voltage-controlled switch S at the time of the potential of the inverting input terminal 21 Switch on, voltage-controlled switch S 21 Second contact output voltage-controlled switch S 21 Signal of the first contact of (a), unit SUM 14 Output voltage-controlled switch S 21 Second contact output signal of (a) and operational amplifier OP 59 Output signal potential SUM, unit SUM 14 Output terminal of (d) and resistor R 142 One end of (a) is connected with the memristive MC 8 Respectively with resistor R 98 The other end and the mathematical operation unit ABM 8 Is connected with the IN1 end of the memristor MC 8 Respectively with the negative terminal of NMOS tube T 20 Grid and mathematical operation unit ABM 8 Is connected with the IN2 end of the NMOS tube T 20 The source electrode of (2) is grounded, NMOS tube T 20 The drain electrode of (2) is connected with a power supply V 33 Positive electrode of (a), power supply V 33 Is grounded by the negative electrode of the mathematical operation unit ABM 8 Memristive MC 8 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 8 Electric at both endsCurrent value, when stimulus signal voltage passes through memristive capacitor MC 8 If pass through memcapacitor MC 8 Is greater than NMOS transistor T 20 Voltage difference between drain and source of memcapacitor MC 8 Begin to charge accumulation, memristive MC 8 The capacitance value gradually becomes larger, and the memristive capacitance MC 8 The passable voltage of (2) increases with the capacitance value; mathematical operation unit ABM 8 The output terminal OUT of (1) is respectively connected with the resistor R 143 Resistance R 145 And resistance R 201 Is connected with a mathematical operation unit ABM 8 The output of Vout= - (V) IN1 -V IN2 )，ABM 8 Output memristive MC 8 The voltage at both ends of (a) increases and decreases, the resistance R 143 Respectively with the other end of the operational amplifier OP 55 Is the inverting input terminal of (C) and capacitor (C) 16 Connected with a capacitor C 16 Respectively with the other end of the operational amplifier OP 55 Is connected with the output end of the resistor R 144 One end of (a) and an operational amplifier OP 55 Is connected with the non-inverting input terminal of the resistor R 144 Is grounded at the other end of the operational amplifier OP 55 Resistance R 143 -R 144 And capacitance C 16 An integrating circuit I is formed; resistor R 145 Respectively with the other end of the operational amplifier OP 56 Is the inverting input terminal of (C) and capacitor (C) 17 Connected with a capacitor C 17 Is connected with the other end of the operational amplifier OP 56 Is connected with the output end of the resistor R 146 One end of (a) and an operational amplifier OP 56 Is connected with the non-inverting input terminal of the resistor R 146 Is grounded at the other end of the operational amplifier OP 56 Resistance R 145 -R 146 And capacitance C 17 Forming an integrating circuit II; resistor R 201 Respectively with the other end of the operational amplifier OP 73 Is the inverting input terminal of (C) and capacitor (C) 24 Connected with a capacitor C 24 Is connected with the other end of the operational amplifier OP 73 Is connected with the output end of the resistor R 202 One end of (a) and an operational amplifier OP 73 Is connected with the non-inverting input terminal of the resistor R 202 Is grounded at the other end of the operational amplifier OP 73 Resistance R 201 -R 202 And capacitance C 24 Forming an integrating circuit III; the integrating circuitThe output of III is
Output end of integrating circuit III and operational amplifier OP 74 Is connected with the non-inverting input terminal of the resistor R 203 One end of (a) and an operational amplifier OP 74 Is connected with the inverting input terminal of the resistor R 203 Is connected with the other end of the power supply V 44 Is connected with the positive electrode of the power supply V 44 Is grounded at the negative electrode of the operational amplifier OP 72 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 74 An operational amplifier OP for inverting the input voltage 74 The output end of the integration circuit II outputs high level
Output end of integrating circuit II and operational amplifier OP 57 Is connected with the non-inverting input terminal of the resistor R 147 One end of (a) and an operational amplifier OP 57 Is connected with the inverting input terminal of the resistor R 147 Is grounded when the operational amplifier OP 57 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 57 An operational amplifier OP for inverting the input voltage 57 Output end of (a) outputs high level, operational amplifier OP 57 And NMOS transistor T 21 The grid of the integrating circuit I is connected with
The output end of the integrating circuit I is respectively connected with the resistor R 148 And resistance R 153 Is connected with the resistor R 153 The other end of (a) is respectively connected with the NMOS tube T 21 Source of (V) and power supply V 36 Is connected with the positive electrode of the power supply V 36 Cathode of (D) and diode D 8 Is connected with the cathode of the diode D 8 The positive electrode of (D) is grounded 8 Limiting the minimum voltage at the output end of the integrating circuit I to be the power supply V 36 NMOS tube T 36 The drain electrode of (a) is respectively connected with the resistor R 154 And resistance R 155 Is connected with the resistor R 154 Is grounded at the other end of the operational amplifier OP 57 High outputNMOS tube T at level 21 Conducting; resistor R 148 Is connected with the other end of the operational amplifier OP 58 Is connected with the non-inverting input terminal of the operational amplifier OP 58 Is an inverting input terminal of (a) and a resistor R 149 Is connected with one end of resistor R 149 Is connected with the other end of the power supply V 34 Is connected with the positive electrode of the power supply V 34 Is grounded at the negative electrode of the operational amplifier OP 58 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 58 Output high level, operational amplifier OP 58 And NMOS transistor T 22 The grid electrode of the NMOS tube T is connected with 22 Source of (V) and power supply V 35 Is connected with the positive electrode of the power supply V 35 Is grounded with the negative electrode of NMOS tube T 22 The drain electrode of (a) is respectively connected with the resistor R 150 And resistance R 151 Is connected with the resistor R 150 Is grounded at the other end of the operational amplifier OP 58 NMOS tube T when outputting high level 22 On, resistance R 151 Respectively with resistor R at the other end 152 Sum operational amplifier OP 59 Is connected with the inverting input terminal of the resistor R 152 One end of (a) and an operational amplifier OP 59 Is connected with the non-inverting input terminal of the resistor R 152 Is grounded at the other end of the operational amplifier OP 59 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 59 Respectively with resistor R 152 Is connected with the other end of the unit SUM 14 Is connected with the other input end of the first power supply; resistor R 155 Respectively with resistor R at the other end 156 And an operational amplifier OP 60 Is connected with the inverting input terminal of the operational amplifier OP 60 Is grounded, and an operational amplifier OP 60 Ten times the voltage output opposite to its inverting input, OP 60 Output terminal of (d) and resistor R 157 Is connected with the resistor R 157 Respectively with resistor R at the other end 158 And operational amplifier OP 61 Is connected with the inverting input terminal of the operational amplifier OP 61 Is connected to the non-inverting input terminal of (1) and ground, and is an operational amplifier OP 61 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 61 Respectively and electrically connected with the output end of (a)R resistance 158 And voltage-controlled switch S 22 Is connected to the non-inverting input terminal of the input signal terminal I 4 And a voltage-controlled switch S 22 Is connected with the first contact of the voltage-controlled switch S 22 Respectively with resistor R 159 And resistance R 160 Is connected with the resistor R 159 And voltage-controlled switch S 22 Is grounded when the operational amplifier OP 61 The potential of the output end is greater than that of the voltage-controlled switch S 22 Voltage-controlled switch S at the time of the potential of the inverting input terminal 22 Switch on, voltage-controlled switch S 22 Second contact output voltage-controlled switch S 22 Signal of the first contact of (a), resistance R 160 Respectively with resistor R at the other end 161 And operational amplifier OP 62 Is connected with the inverting input terminal of the operational amplifier OP 62 Is grounded, and an operational amplifier OP 62 Ten times the voltage output opposite to its inverting input, OP 62 Respectively with resistor R 161 And the other end of (2) and the resistor R 162 Is connected with the resistor R 162 Respectively with resistor R at the other end 163 And operational amplifier OP 63 Is connected with the inverting input terminal of the operational amplifier OP 63 Is grounded, and an operational amplifier OP 63 An operational amplifier OP outputting a voltage opposite to the voltage of the inverting input terminal 63 Output of (1) and OR gate G 9 The output end of the olfactory neuron module is connected with an OR gate G 9 Is connected to another input terminal of the OR gate G 9 Or gate G when any input terminal of (a) has a high level input 9 Output high level, OR gate G 9 Output terminal of (d) and voltage-controlled switch S 28 Is connected to the first contact of OR gate G 9 The output end of the (2) is the output end of the olfactory visual association neuron module.
As shown in fig. 7, the input signal terminal I 2 SUM-and-voltage summing module SUM 12 Is connected to an input terminal of the input signal terminal I 4 SUM-and-voltage summing module SUM 12 Is connected to the other input terminal of the voltage summing module SUM 12 Input/output signal terminal I 2 And input of letter (letter)Number (number) terminal I 4 Is a sum of the potentials of the electrodes. Operational amplifier OP device 72 Output of (2) NAND gate G 3 Is connected with the input end of the connecting rod, NOT gate G 3 Output a voltage opposite to its input, NOT gate G 3 Output terminal of (d) and voltage-controlled switch S 15 Is connected with the non-inverting input terminal of the voltage-controlled switch S 15 Is a first contact of a voltage-controlled switch S 18 Is connected with the second contact of the voltage-controlled switch S 15 Respectively with resistor R 193 SUM-voltage summing module SUM 10 Is connected to one input terminal of the resistor R 193 And voltage-controlled switch S 15 Is grounded when not gate G 3 The potential of the output end is greater than that of the voltage-controlled switch S 15 Voltage-controlled switch S at the time of the potential of the inverting input terminal 15 Switch on, voltage-controlled switch S 15 Second contact output voltage-controlled switch S 15 Signal of the first contact of (a), operational amplifier OP 74 Output of (2) NAND gate G 2 Is connected with the input end of the NOT gate G 2 Output a voltage opposite to its input, NOT gate G 2 Output terminal of (d) and voltage-controlled switch S 14 Is connected with the non-inverting input terminal of the voltage-controlled switch S 14 Is a first contact of a voltage-controlled switch S 2 Is connected with the second contact of the voltage-controlled switch S 14 Respectively with resistor R 191 SUM-voltage summing module SUM 10 Is connected to the other input terminal of the resistor R 191 And voltage-controlled switch S 14 Is grounded when not gate G 2 The potential of the output end is greater than that of the voltage-controlled switch S 14 Voltage-controlled switch S at the time of the potential of the inverting input terminal 14 Switch on, voltage-controlled switch S 14 Second contact output voltage-controlled switch S 14 Is a signal of the first contact of the voltage summing module SUM 10 Output voltage-controlled switch S 14 Second contact of (a) and voltage-controlled switch S 15 SUM of the potentials of the second contacts of (a) a voltage summing module SUM 10 Output terminal of (d) and voltage-controlled switch S 16 Is connected with the first contact of the voltage-controlled switch S 16 Respectively with the unit SUM 11 An input terminal of (a) and a resistor R 192 Is connected with one end of resistor R 192 And voltage-controlled switch S 16 Is grounded when the voltage summation module SUM 10 The potential of the output end is greater than that of the voltage-controlled switch S 16 Voltage-controlled switch S at the time of the potential of the inverting input terminal 16 Switch on, voltage-controlled switch S 16 Second contact output voltage-controlled switch S 16 Is a signal of the first contact of the voltage summing module SUM 11 Output voltage-controlled switch S 16 Second contact of (a) and operational amplifier OP 50 SUM of output terminal potential, voltage summation module SUM 11 Output terminal of (d) and resistor R 124 Is connected with each other. The audiovisual association neuron module comprises a memristive MC 7 Arithmetic unit ABM 7 Operational amplifier OP 46 -OP 52 NMOS tube T 17 -T 19 Logic gate G 2 -G 3 DC voltage source V 29 -V 32 And a voltage-controlled switch S 14 -S 17 Memristive MC 7 Respectively with resistor R 124 The other end and the mathematical operation unit ABM 7 Is connected with the IN1 end of the memristor MC 7 Respectively with the negative terminal of NMOS tube T 17 Grid and mathematical operation unit ABM 7 Is connected with the IN2 end of the NMOS tube T 17 The source electrode of (2) is grounded, NMOS tube T 17 The drain electrode of (2) is connected with a power supply V 29 Positive electrode of (a), power supply V 29 Is grounded by the negative electrode of the mathematical operation unit ABM 7 Memristive MC 7 The voltage difference between the two ends is converted into flowing through the memcapacitor MC 7 The current values at the two ends when the voltage of the stimulating signal passes through the memcapacitor MC 7 If pass through memcapacitor MC 7 Is greater than NMOS transistor T 17 Voltage difference between drain and source of memcapacitor MC 7 Begin to charge accumulation, memristive MC 7 Capacitance value gradually becomes smaller and memristive capacitance MC 7 The charging speed of (2) becomes fast; mathematical operation unit ABM 7 The output terminal OUT of (1) is respectively connected with the resistor R 125 And resistance R 127 Is connected with a mathematical operation unit ABM 7 The output of Vout= - (V) IN1 -V IN2 )，ABM 7 Output memristive MC 7 The voltage at both ends of (a) increases and decreases, the resistance R 125 Respectively with the other end of the operational amplifier OP 46 Is the inverting input terminal of (C) and capacitor (C) 14 Connected with a capacitor C 14 Respectively with the other end of the operational amplifier OP 46 Is connected with the output end of the resistor R 126 One end of (a) and an operational amplifier OP 46 Is connected with the non-inverting input terminal of the resistor R 126 Is grounded at the other end of the operational amplifier OP 46 Resistance R 125 -R 126 And capacitance C 14 An integrating circuit I is formed; resistor R 127 Respectively with the other end of the operational amplifier OP 47 Is the inverting input terminal of (C) and capacitor (C) 15 Connected with a capacitor C 15 Respectively with the other end of the operational amplifier OP 47 Is connected with the output end of the resistor R 128 One end of (a) and an operational amplifier OP 47 Is connected with the non-inverting input terminal of the resistor R 128 Is grounded at the other end of the operational amplifier OP 47 Resistance R 127 -R 128 And capacitance C 15 Forming an integrating circuit II; the output of the integrating circuit II is
Output end of integrating circuit II and operational amplifier OP 48 Is connected with the non-inverting input terminal of the resistor R 129 One end of (a) and an operational amplifier OP 48 Is connected with the inverting input terminal of the resistor R 129 Is grounded at the other end of the operational amplifier OP 48 The potential of the non-inverting input terminal of (a) is greater than that of the operational amplifier OP 48 An operational amplifier OP for inverting the input voltage 48 Output end of (a) outputs high level, operational amplifier OP 48 And NMOS transistor T 18 The gate of the integration circuit I is connected with the output of the integration circuit I>
The output end of the integrating circuit I is respectively connected with the resistor R 130 And resistance R 131 Is connected with the resistor R 130 The other end of (a) is respectively connected with the NMOS tube T 18 Source of (V) and power supply V 32 The positive electrode of NMOS tube T is connected with 18 The drain electrode of (a) is respectively connected with the resistor R 137 And resistance R 138 Is connected with the resistor R 137 Is grounded at the other end of the operational amplifier OP 46 NMOS tube T when outputting high level 12 Conducting; resistor R 131 Is connected with the other end of the operational amplifier OP 49 Is connected with the non-inverting input terminal of the operational amplifier OP 49 Is an inverting input terminal of (a) and a resistor R 132 Is connected with one end of resistor R 132 Is connected with the other end of the power supply V 30 Is connected with the positive electrode of the power supply V 30 Is grounded at the negative electrode of the resistor R 132 Power supply V 30 Operational amplifier OP 49 Constitutes a voltage comparator, when the operational amplifier OP 49 When the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the operational amplifier OP 49 A high level is output. Operational amplifier OP 49 And NMOS transistor T 19 The grid electrode of the NMOS tube T is connected with 19 Source of (V) and power supply V 31 Is connected with the positive electrode of the power supply V 31 Is grounded with the negative electrode of NMOS tube T 19 The drain electrode of (a) is respectively connected with the resistor R 133 And resistance R 134 Is connected with the resistor R 133 Is grounded at the other end of the operational amplifier OP 49 NMOS tube T when outputting high level 19 On, resistance R 134 Respectively with resistor R at the other end 136 Sum operational amplifier OP 50 Is connected with the inverting input terminal of the resistor R 135 One end of (a) and an operational amplifier OP 50 Is connected with the non-inverting input terminal of the resistor R 135 Is grounded at the other end of the resistor R 135 Resistance R 134 Resistance R 136 Operational amplifier OP 49 Make up of voltage comparator, operational amplifier OP 50 Outputting a voltage opposite to its inverting input. Operational amplifier OP 50 Output terminal of (a) and voltage summation module SUM 11 Is connected with the other input end of the first power supply; power supply V 32 Cathode of (D) and diode D 7 Is connected with the cathode of the diode D 7 The positive electrode of (D) is grounded 7 Limiting the minimum voltage at the output end of the integrating circuit I to be the power supply V 32 Voltage, resistance R 138 Respectively with resistor R at the other end 139 And operational amplifier OP 51 Is connected with the inverting input terminal of the operational amplifier OP 51 The non-inverting input terminal of (2) is grounded, the resistor R 138 Resistance R 139 And operational amplifier OP 51 Composition of inverse proportionAmplifier, operational amplifier OP 51 Outputting a proportional voltage opposite to the inverting input terminal thereof. Operational amplifier OP 51 Respectively with resistor R 139 And the other end of (2) and the resistor R 140 Is connected with the resistor R 140 Respectively with resistor R at the other end 141 And operational amplifier OP 52 Is connected with the inverting input terminal of the operational amplifier OP 52 The non-inverting input terminal of (2) is grounded, the resistor R 140 Resistance R 141 And operational amplifier OP 52 Constitutes an inverting amplifier, an operational amplifier OP 52 Outputting a voltage opposite to its inverting input. Operational amplifier OP 52 Respectively with the output end of the voltage-controlled switch S 17 Is connected to the non-inverting input terminal of the unit SUM 12 Output terminal of (d) and voltage-controlled switch S 17 Is connected with the first contact of the voltage-controlled switch S 17 Respectively with resistor R 206 And a voltage-controlled switch S 27 Is connected with the first contact of the resistor R 206 And voltage-controlled switch S 17 Is grounded when the operational amplifier OP 52 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 17 Voltage-controlled switch S at the time of the potential of the inverting input terminal 17 Switch on, voltage-controlled switch S 17 Second contact output voltage-controlled switch S 17 Is a signal of the first contact of the voltage-controlled switch S 17 The second contact of (2) is the output of the audiovisual association neuron module.
The output synapse module comprises an operational amplifier OP 53 -OP 54 Logic gate G 7 -G 8 And G 10 DC voltage source V 27 -V 28 And a voltage-controlled switch S 26 -S 28 The output ends of the auditory pain associated neurons are respectively connected with the OR gate G 7 And an operational amplifier OP 53 Is connected with the inverting input terminal of the visual pain sensation association neuron output terminal and the OR gate G respectively 7 Is connected to the other input terminal of the operational amplifier OP 54 Is connected to the inverting input terminal of OR gate G 7 Or gate G when any input terminal of (a) has a high level input 7 Output high level, OR gate G 7 The output end of the (a) is an evasion reflection output end O of the whole circuit 1 Operational amplifier OP 53 Is connected with the non-inverting input terminal of the resistor R 204 Is connected with the resistor R 204 Is grounded at the other end of the resistor R 204 And operational amplifier OP 5 Constitutes a voltage comparator, when the operational amplifier OP 53 When the potential of the inverting input terminal is lower than the potential of the equidirectional input terminal, the operational amplifier OP 53 A low level is output. Operational amplifier OP 53 Output of (a) and unit SUM 8 Is connected with one input end of the power supply V 28 Positive electrode of (a) and unit SUM 8 Is connected with the other end of the power supply V 28 Is grounded to the negative electrode of the unit SUM 8 Output operational amplifier OP 53 Output signal and power supply V 28 SUM of voltages of unit SUM 8 Output of (1) and AND gate G 8 Is connected to the first input terminal of the unit SUM 7 Output of (1) and AND gate G 8 Is connected to the second input terminal of the operational amplifier OP 54 Is connected with the non-inverting input terminal of the resistor R 205 Is connected with the resistor R 205 Is grounded at the other end of the resistor R 205 Operational amplifier OP 54 Constitutes a voltage comparator, when the operational amplifier OP 54 When the potential of the inverting input terminal is lower than the potential of the equidirectional input terminal, the operational amplifier OP 54 A low level is output. Operational amplifier OP 54 Output of (a) and unit SUM 9 Is connected with one input end of the power supply V 27 Positive electrode of (a) and unit SUM 9 Is connected with the other end of the power supply V 27 Is grounded to the negative electrode of the unit SUM 9 Output operational amplifier OP 54 Output signal and power supply V 27 SUM of voltages of unit SUM 9 Output of (1) and AND gate G 8 Is connected to the third input terminal of the AND gate G 8 When the three input terminals of (a) are all high level input, and gate G 8 Output high level and gate G 8 Respectively with the output end of the voltage-controlled switch S 26 Is a non-inverting input terminal of a voltage-controlled switch S 27 Is a non-inverting input terminal of (C) and voltage-controlled switch S 28 Is connected to the non-inverting input terminal of (c). Output end of auditory sense and olfactory sense association neuron module and voltage-controlled switch S 26 Is connected with the first contact of the voltage-controlled switch S 26 Respectively with resistor R 207 And or gate G 10 Is connected to the first input terminal of the resistor R 207 And voltage-controlled switch S 26 Is grounded when the AND gate G 8 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 26 Voltage-controlled switch S at the time of the potential of the inverting input terminal 26 Switch on, voltage-controlled switch S 26 Second contact output voltage-controlled switch S 26 The audio-visual association neuron module output end and the voltage-controlled switch S 27 Is connected with the first contact of the voltage-controlled switch S 27 Respectively with resistor R 208 And or gate G 10 Is connected to the second input terminal of the resistor R 208 And voltage-controlled switch S 27 Is grounded when the AND gate G 8 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 27 Voltage-controlled switch S at the time of the potential of the inverting input terminal 27 Switch on, voltage-controlled switch S 27 Second contact output voltage-controlled switch S 27 Is provided for the first contact of the first contact. Visual sense olfactory sense association neuron module output end and voltage-controlled switch S 28 Is connected with the first contact of the voltage-controlled switch S 28 Respectively with resistor R 209 And or gate G 10 Is connected to the third input terminal of the resistor R 209 And voltage-controlled switch S 28 Is grounded when the AND gate G 8 The potential of the output terminal of (a) is greater than that of the voltage-controlled switch S 28 Voltage-controlled switch S at the time of the potential of the inverting input terminal 28 Switch on, voltage-controlled switch S 28 Second contact output voltage-controlled switch S 28 When OR gate G 10 Or gate G when any input terminal of (a) has a high level input 10 Output high level, OR gate G 10 The output end of the (C) is the salivation reflection output end O of the whole circuit 2 。
FIG. 8 is a diagram showing simulation results of learning, forgetting, secondary learning and secondary forgetting, in which the input signal terminal I 1 Input positive unconditional stimulation signal, input signal terminal I 2 Inputting a conditional stimulus signal V T15 Or gate G for auditory olfactory association neuron potential 10 The output voltage of (1) is salivation output signal, 0s-30s is signal test stage, smell senseMemristive MC of neuron module 1 Memristive MC with auditory neuron module 2 Already in the state to be excited, the corresponding signal is already familiar to a certain extent. 30s-40s is the first learning stage, when the input signal I 1 And input signal I 2 When being input to the hearing and olfactory neuron module at the same time, the memristive MC 6 The capacitance value of the memory capacitor is increased, the stored charge quantity is increased, meanwhile, the association module simultaneously starts the forgetting function, 40s-58s is the first forgetting process, 70s-80s is the second learning stage, and the previous learning history is reserved in the memory capacitor MC 6 In the same time and frequency, the memristive MC 6 The larger the capacitance rise, the more the stored charge quantity, 80s-128s is the second forgetting process, and the second forgetting and forgetting process is slower.
FIG. 9 is a diagram of simulation results of learning and forgetting in a short time interval, in which the input signal terminal I 1 Input positive unconditional stimulation signal, input signal terminal I 2 Inputting a conditional stimulus signal V T15 Or gate G for auditory olfactory association neuron potential 10 The output voltage of (1) is the salivation output signal, 0s-40s is the first learning stage, the input signal I 1 And input signal I 2 Each pulse is spaced half a second apart, and when two signals are input to the auditory olfactory neuron module, the memristive MC 6 The capacity of the memory module is increased, the stored charge quantity is increased, meanwhile, the association module simultaneously starts a forgetting function, and 40s-98s is a forgetting process.
FIG. 10 is a graph of simulation results of the secondary adjustment, in which the input signal I is 1 Input positive unconditional stimulation signal, input signal terminal I 2 Input condition stimulus signal, input signal end I 4 Inputting another condition stimulus signal, V T18 For audiovisual association of neuronal potentials, OR gate G 10 The output voltage of (1) is salivation output signal, 0s-30s is test stage, 30s-60s is secondary regulation stage from bell signal to light signal, the association is established by audio-visual association neuron after the association is established by auditory-olfactory association neuron, and the memristive MC is formed 6 Memristance MC after rising of capacitance value of (2) 7 The capacity value of the test module rises again, meanwhile, the two association modules start the forgetting function, 90s-120s is the retest process,120s-150s is the secondary regulation stage from light signal to bell signal, the association is established by visual olfactory association neuron, then the association is established by audiovisual association neuron, and the memristor MC 8 Memristance MC after rising of capacitance value of (2) 7 The capacity value of the memory module rises again, and the two association modules start the forgetting function.
FIG. 11 is a graph of simulation results of intermittent stimulation in which the input signal terminal I 1 Input positive unconditional stimulation signal, input signal terminal I 2 Input condition stimulus signal, input signal end I 4 Inputting another condition stimulus signal, V T18 For audiovisual association of neuronal potentials, OR gate G 10 The output voltage of (1) is salivation output signal, 0s-150s is intermittent stimulation to promote learning stage, and input signal I 1 And input signal I 2 Interposed input signal I 4 The interval between the three signals is shortened so as to generate association learning, and 150s-200s is a normal forgetting stage.
FIG. 12 is a diagram showing simulation results of fear study case B, in which the input signal terminal I 2 Input condition stimulus signal, input signal end I 4 Inputting another condition stimulus signal, input signal end I 3 Input of negative unconditional stimulus signals, V T12 To correlate neuron potential for auditory pain sensation, V T24 To correlate neuron potential for visual pain sensation, OR gate G 7 The output voltage of (1) is escape output signal, 0s-40s is dual-condition stimulation signal to establish fear learning, and the memristor MC is used at the moment 5 Memristive MC 9 The capacitance values of the capacitor (C) rise together to jointly establish fear learning, then the circuit can make escape response when receiving one of the condition stimulus signals independently, the fear learning is established for a single stimulus signal in 60s-100s, and the memristive MC is realized under the training of the same time and frequency 5 The capacity of (2) is not as high as the associative learning established under the bi-conditional stimulus signal.
The neuron module constructed by using the memristor has the advantages of more energy conservation and more visual weight change, the interconnection of the nine neuron modules realizes the associative learning process of learning, forgetting, secondary learning, secondary forgetting, aibinhaos forgetting, stimulus interval learning, delay learning, blocking recovery, secondary regulation, intermittent stimulus promotion, potential inhibition and fear learning under three different conditions among different signals, widens the possibility of realizing a biological bionic circuit by using hardware, and is beneficial to constructing a more realistic and feasible neural network circuit.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (8)
1. A memristive bionic circuit for full-function pavlov associative memory and fear learning is characterized by comprising an input signal end I 1 -I 4 Olfactory neuron module, pain neuron module, auditory neuron module, visual neuron module, auditory pain association neuron module, visual pain association neuron module, auditory olfactory association neuron module, visual olfactory association neuron module, audiovisual association neuron module, and output signal terminal O 1 -O 2 Input signal terminal I representing a positive stimulus signal 1 The input end of the olfactory neuron module is connected with the input end of the olfactory neuron module; input signal terminal I representing a negative stimulus signal 3 The pain sensing neuron module is connected with the input end of the pain sensing neuron module; input signal terminal I representing neutral stimulus signal 2 Is connected with the input ends of the auditory neuron module, the auditory olfactory association neuron module, the auditory pain association neuron module and the audiovisual association neuron module respectively, and represents the input signal end I of the neutral stimulation signal 4 The input ends of the visual nerve cell module, the visual olfactory sensation association nerve cell module, the visual pain sensation association nerve cell module and the visual and audio association nerve cell module are respectively connected; the output end of the olfactory neuron module is respectively connected with the input ends of the auditory olfactory association neuron module and the visual olfactory association neuron module; the output end of the pain neuron module is respectively connected with the input ends of the auditory pain associated neuron module, the visual pain associated neuron module and the output protrusion module; the hearingThe output end of the neuron module is respectively connected with the pain neuron module, the audio-visual association neuron module and the auditory sense and olfactory association neuron module, the output end of the visual neuron module is respectively connected with the input ends of the pain neuron module, the audio-visual association neuron module and the visual sense and olfactory association neuron module, the output end of the pain neuron module is respectively connected with the input ends of the auditory sense and pain association neuron module and the visual sense and pain association neuron module, the output end of the auditory sense and pain association neuron module is respectively connected with the input ends of the auditory sense and olfactory association neuron module and the output protrusion module, and the output end of the visual sense and pain association neuron module is respectively connected with the input ends of the visual sense and olfactory association neuron module and the output protrusion module; the output ends of the hearing and smell association neuron module are respectively connected with the output ends of the hearing and smell association neuron module and the output end of the visual and smell association neuron module; the output end of the visual olfactory sensation association neuron module is respectively connected with the output ends of the auditory olfactory sensation association neuron module and the audiovisual association neuron module and the input end of the output synapse module; the output end of the audio-visual association neuron module is connected with the input end of the output protrusion module, and the output ends of the output protrusion module respectively obtain output signal ends O 1 And output signal terminal O 2 。
2. The full-function pavlovian associative memory and fear learning memcapacitor bionic circuit according to claim 1, wherein the olfactory neuron module comprises memcapacitor MC 1 Arithmetic unit ABM 1 A first integrating circuit, a first voltage comparator, an NMOS tube T 1 And a first voltage control unit, the input signal terminal I 1 Respectively with resistance R 1 Is connected with one end of the first voltage-controlled unit, resistor R 1 The other end of (2) is respectively connected with the memristive MC 1 Positive terminal of (a), mathematical operation unit ABM 1 Is one input end of the memcapacitor MC 1 Negative terminal of (a) is respectively connected with the mathematical operation unit ABM 1 Is connected with the other input end of the NMOS tube T 1 The grid electrode of the NMOS tube T is connected with 1 The drain electrode of (2) is connected with a power supplyV 1 Positive electrode of (a), power supply V 1 Is connected with the negative electrode of NMOS tube T 1 The sources of the transistors are all grounded; the mathematical operation unit ABM 1 The output end of the first voltage-controlled unit is an output end U1, and the output end U1 is respectively connected with the input ends of the auditory olfactory association neuron module and the visual olfactory association neuron module.
3. The full-function pavlovian associative memory and fear learning memristive circuit according to claim 1 or 2, wherein the auditory neuron module and the visual neuron circuit each comprise a first memristive, a first mathematical operation unit, a second integration circuit, a third integration circuit, a second voltage comparator, a third voltage comparator, a first inverting amplifier, a first summing amplifier circuit, a third inverting amplifier, a first inverting proportional amplifier, a fourth inverting amplifier, and a second voltage control unit, and the input signal terminal I 2 Or input signal terminal I 4 The output end of the second integrator is connected with the input end of a third voltage comparator, the output end of the third voltage comparator is connected with the grid electrode of a first NMOS tube, the source electrode of the first NMOS tube is connected with the positive electrode of a first power supply, the negative electrode of the first power supply is grounded, the drain electrode of the first NMOS tube is respectively connected with one end of a second resistor and the input end of a first inverting amplifier, the other end of the second resistor is grounded, the output end of the first inverting amplifier is respectively connected with the other end of the first resistor and the input end of a first summing amplifier circuit through a third resistor, the output end of the first summing amplifier circuit is connected with the input end of a third inverting amplifier, the output end of the third inverting amplifier is respectively connected with the positive end of the first memcapacitor and the input end of the first mathematical operation unit through a fourth resistor, the negative end of the first capacitor is respectively connected with the other input end of the first mathematical operation unit and the grid electrode of the second NMOS tube The drain electrode of the NMOS tube is connected with the positive electrode of the second power supply, and the source electrode of the second NMOS tube and the negative electrode of the second power supply are grounded; the output end of the first mathematical operation unit is respectively connected with the input ends of the second integration circuit and the third integration circuit, the output end of the second integration circuit is respectively connected with the anode of the third power supply and the source electrode of the third NMOS tube through a fifth resistor, the cathode of the third power supply is connected with the cathode of the first diode, and the anode of the first diode is grounded; the output end of the third integrating circuit is connected with the input end of the second voltage comparator, the output end of the second voltage comparator is connected with the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube is respectively connected with one end of the sixth resistor and the input end of the first inverting proportional amplifier, the other end of the sixth resistor is grounded, the output end of the first inverting proportional amplifier is connected with the input end of the fourth inverting amplifier, the output end of the fourth inverting amplifier is the first output end of the auditory neuron module or the visual neuron circuit, the first output end of the fourth inverting amplifier is connected with the other input end of the second voltage-controlled unit, and the output end of the second voltage-controlled unit is the second output end of the auditory neuron module or the visual neuron circuit; the second output ends of the auditory neuron module and the visual neuron circuit are connected with the input end of the audio-visual association neuron module; the first output end of the auditory neuron module is respectively connected with the input ends of the pain neuron module and the auditory olfactory association neuron module, and the first output end of the visual neuron module is respectively connected with the input ends of the pain neuron module and the visual olfactory association neuron module.
4. The full-function pavlovian associative memory and fear learning memristive circuit of claim 3, wherein the pain neuron module comprises memristive MC 3 Arithmetic unit ABM 3 The input signal end I comprises a fourth integrating circuit, a fifth integrating circuit, a fourth voltage comparator, a fifth voltage comparator, a second inverting amplifier, a second summing amplifier circuit, a fifth inverting amplifier, a sixth voltage comparator, a sixth inverting amplifier, a third voltage-controlled unit and a fourth voltage-controlled unit 3 Respectively withOne end of a seventh resistor, one input end of a third voltage-controlled unit and one input end of a fourth voltage-controlled unit are connected, the output end of a fourth integrator is connected with the input end of a fifth voltage comparator, the output end of the fifth voltage comparator is connected with the grid electrode of a fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the positive electrode of a fourth power supply, the negative electrode of the fourth power supply is grounded, the drain electrode of the fourth NMOS tube is respectively connected with one end of an eighth resistor and the input end of a second inverting amplifier, the other end of the eighth resistor is grounded, the output end of the second inverting amplifier is respectively connected with the other end of the seventh resistor and the input end of a second summing amplifier circuit through a ninth resistor, the output end of the second summing amplifier circuit is connected with the input end of the fifth inverting amplifier circuit, and the output end of the fifth inverting amplifier circuit is respectively connected with a memcapacitor MC through a tenth resistor 3 Positive terminal of (a), mathematical operation unit ABM 3 Is connected with one input end of the memristive MC 3 Negative terminal of (a) is respectively connected with the mathematical operation unit ABM 3 The other input end of the fifth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the positive electrode of the fifth power supply, and the source electrode of the fifth NMOS tube and the negative electrode of the fifth power supply are grounded; the mathematical operation unit ABM 3 The output end of the fourth integrating circuit is respectively connected with the positive electrode of a sixth power supply and the source electrode of a sixth NMOS tube through an eleventh resistor, the negative electrode of the sixth power supply is connected with the negative electrode of a second diode, and the positive electrode of the second diode is grounded; the output end of the fifth integrating circuit is connected with the input end of a fourth voltage comparator, the output end of the fourth voltage comparator is connected with the grid electrode of a sixth NMOS tube, the drain electrode of the sixth NMOS tube is respectively connected with one end of a twelfth resistor and the input end of the sixth voltage comparator, the other end of the twelfth resistor is grounded, the output end of the sixth voltage comparator is connected with the input end of a sixth inverting amplifier, the output end of the sixth inverting amplifier is connected with the input end of a first voltage summation module, the output end of the first voltage summation module is the output end U4 of a pain sense neuron module, the first output end of an auditory neuron module is connected with the other input end of a third voltage control unit, The output end of the third voltage control unit is the output end U5 of the pain sense neuron module, the first output end of the auditory neuron module is connected with the other input end of the fourth voltage control unit, and the output end of the fourth voltage control unit is the output end U6 of the pain sense neuron module.
5. The full-function pavlovian associative memory and fear learning memristive circuit of claim 4, wherein the auditory pain associated neuron module and the visual pain associated neuron module each comprise a second voltage summing module, a fifth voltage control unit, a third voltage summing module, a second memristive, a second mathematical operation unit, a sixth integration circuit, a seventh voltage comparator, an eighth voltage comparator, a seventh inverting amplifier, a ninth voltage comparator, a tenth voltage comparator, and a sixth voltage control unit, and an input signal terminal I 2 Or input signal terminal I 4 The output end U5 or the output end U6 of the pain sense neuron module is respectively connected with one input end of a first OR gate, one input end of a fifth voltage control unit and the other input end of the second voltage summation module, the output end of the second voltage summation module is connected with the other input end of the sixth voltage control unit, the output end of the sixth voltage summation module is connected with one input end of a third voltage summation module, the other input end of the third voltage summation module is connected with the output end of a seventh inverting amplifier, the output end of the third voltage summation module is respectively connected with the positive end of a second memristive capacitor and one end of the second learning operation unit through a thirteenth resistor, the negative end of the second memristive capacitor is respectively connected with the other end of the second learning operation unit and the grid electrode of a seventh NMOS tube, the drain electrode of the seventh NMOS tube is connected with the positive electrode of the seventh power supply, and the negative electrode of the seventh power supply and the source electrode of the seventh NMOS tube are grounded; the output end of the second digital operation unit is respectively connected with the input ends of a sixth integration circuit and a seventh integration circuit, the output end of the sixth integration circuit is respectively connected with the anode of an eighth power supply, one end of a fifteenth resistor and the source electrode of an eighth NMOS tube through a fourteenth resistor, and the cathode of the eighth power supply is connected with the output end of the seventh integration circuit The negative electrode of the third diode is connected with the ground, the other end of the fifteenth resistor is connected with the input end of the eighth voltage comparator, the output end of the eighth voltage comparator is connected with the grid electrode of the ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the positive electrode of the ninth power supply, the negative electrode of the ninth power supply is grounded, and the drain electrode of the ninth NMOS tube is respectively connected with one end of the seventeenth resistor and the input end of the seventh inverting amplifier; the output end of the seventh integrating circuit is connected with the input end of a seventh voltage comparator, the output end of the seventh voltage comparator is connected with the grid electrode of an eighth NMOS tube, the drain electrode of the eighth NMOS tube is connected with one end of a sixteenth resistor and the input end of a ninth voltage comparator, and the other end of the sixteenth resistor and the other end of a seventeenth resistor are grounded; the output end of the ninth voltage comparator is respectively connected with one end of the first capacitor, the other input end of the sixth voltage control unit and the input end of the tenth voltage comparator, the other end of the first capacitor is grounded, the output end of the sixth voltage control unit is connected with the other input end of the first OR gate, the output end of the first OR gate is the first output end of the auditory pain sensation association neuron module or the visual pain sensation association neuron module, the output end of the tenth voltage comparator is connected with one input end of the fourth voltage summation module, the other input end of the fourth voltage summation module is grounded through a tenth power supply, and the output end of the fourth voltage summation module is the second output end of the auditory pain sensation association neuron module or the visual pain sensation association neuron module; the first output end of the auditory sense pain associated neuron module is connected with the input end of the auditory sense and olfactory sense associated neuron module, the first output end of the visual sense pain associated neuron module is connected with the input end of the visual sense and olfactory sense associated neuron module, and the second output ends of the auditory sense pain associated neuron module and the visual sense pain associated neuron module are connected with the input end of the output protrusion module.
6. The full-function pavlovian associative memory and fear learning memristive circuit according to claim 5, wherein the auditory olfactory associative neuron module and the visual olfactory associative neuron module each compriseA seventh voltage control unit, a fifth voltage summation module, an eighth voltage control unit, a ninth voltage control unit, a tenth voltage control unit, a sixth voltage summation module, an eleventh voltage control unit, a twelfth voltage control unit, a seventh voltage summation module, an eleventh voltage comparator, an eighth inverting amplifier, a third memcapacitor, a third mathematical operation unit, an eighth integration circuit, a ninth integration circuit, a twelfth voltage comparator, a third inverting amplifier, a ninth inverting amplifier, a thirteenth voltage control unit, a tenth inverting amplifier, a fourth inverting proportional amplifier, a tenth integration circuit and a thirteenth voltage comparator, wherein a second output end of the auditory sense association neuron module is connected with an input end of a first NOT gate of the visual sense association neuron module, an output end of the first NOT gate is connected with an input end of the ninth voltage control neuron module, another input end of the ninth voltage control unit is connected with an output end U1 of the auditory sense association neuron module, an output end of the eighth voltage control unit is connected with an output end U1 of the ninth voltage control neuron module, and an output end of the eighth voltage control unit is connected with another input end of the eighth voltage control neuron module, an eighteenth resistor is connected with another input end of the eighth voltage control unit, and an eighteenth resistor is connected with another end of the eighth resistor; the other input end of the tenth voltage-controlled unit is connected with the first output end of the auditory neuron module or the visual neuron module, the output end of the tenth voltage-controlled unit and the second output end of the auditory neuron module or the visual neuron module are connected with the input end of the sixth voltage summation module, the output end of the sixth voltage summation module is connected with the other input end of the eleventh voltage-controlled unit, the output end of the eleventh voltage-controlled unit is connected with one input end of the eighth voltage-controlled unit, the first output end of the auditory neuron module or the visual neuron module is connected with the input end of the seventh voltage-controlled unit, the output end of the seventh voltage-controlled unit and the positive electrode of the eleventh power supply are connected with the input end of the fifth voltage summation module, the negative electrode of the eleventh power supply is grounded, the output end of the fifth voltage summation module is connected with the other input end of the eighth voltage-controlled unit, and the output end of the eighth voltage-controlled unit is connected with the twelfth voltage-controlled unit One input end of the element is connected, and the other input end of the twelfth voltage-controlled unit is connected with the first output end of the auditory pain sensation association neuron module or the visual pain sensation association neuron module; the output end of the eighth integrating circuit is connected with one input end of an eleventh voltage comparator through a nineteenth resistor, the other input end of the eleventh voltage comparator is grounded through a twelfth power supply, the output end of the eleventh voltage comparator is connected with the grid electrode of a tenth NMOS tube, the source electrode of the tenth NMOS tube is grounded through a thirteenth power supply, the drain electrode of the tenth NMOS tube is respectively connected with one end of the twentieth resistor and the input end of an eighth inverting amplifier, the other end of the twentieth resistor is grounded, the output end of the eighth inverting amplifier and the output end of a twelfth voltage-controlled unit are both connected with the input end of a seventh voltage summation module, the output end of the seventh voltage summation module is respectively connected with the positive end of a third memristive capacitor and one input end of the third mathematical operation unit, the negative end of the third memristive capacitor is respectively connected with the other input end of the third mathematical operation unit and the grid electrode of the eleventh NMOS tube, the source electrode of the eleventh NMOS tube is grounded, and the drain electrode of the eleventh NMOS tube is grounded through the thirteenth power supply; the output end of the third mathematical operation unit is respectively connected with the input ends of an eighth integration circuit and a ninth integration circuit, the output end of the eighth integration circuit is respectively connected with the anode of a fifteenth power supply and the source electrode of a twelfth NMOS tube through a twenty-first resistor, the cathode of the fifteenth power supply is connected with the cathode of a fourth diode, and the anode of the fourth diode is grounded; the output end of the ninth integrating circuit is connected with one input end of a twelfth voltage comparator, the other input end of the twelfth voltage comparator is grounded through a fourteenth power supply, the output end of the twelfth voltage comparator is connected with the grid electrode of a twelfth NMOS tube, the drain electrode of the twelfth NMOS tube is respectively connected with one end of a twenty-second resistor and the input end of a third inverting amplifier, the other end of the twenty-second resistor is grounded, the output end of the third inverting amplifier is connected with the input end of the ninth inverting amplifier, the output end of the ninth inverting amplifier is connected with one input end of a thirteenth voltage-controlled unit, and the other input end of the thirteenth voltage-controlled unit is connected with an input signal end I 2 Or input signal endI 4 The output end of the thirteenth voltage-controlled unit is connected with the input end of a fourth inverting proportional amplifier, the output end of the fourth inverting proportional amplifier is connected with the input end of a tenth inverting amplifier, the output end of the tenth inverting amplifier and the output end U1 of the olfactory neuron module are both connected with the input end of a third OR gate, and the output end of the third OR gate is the first output end of the auditory olfactory associative neuron module or the visual olfactory associative neuron module; the output end of the third mathematical operation unit is also connected with the input end of a tenth integration circuit, the output end of the tenth integration circuit is connected with one input end of a thirteenth voltage comparator, the other input end of the thirteenth voltage comparator is grounded through a sixteenth power supply, and the output end of the thirteenth voltage comparator is a second output end of the hearing-smell association neuron module or the vision-smell association neuron module.
7. The full-function pavlovian associative memory and fear learning memristive circuit of claim 6, wherein the audiovisual associative neuron module comprises memristive MC 7 Arithmetic unit ABM 7 An eleventh integrating circuit, a twelfth integrating circuit, a fourteenth voltage comparator, a fifteenth voltage comparator, an eleventh inverting amplifier, a fifth inverting proportional amplifier, a twelfth inverting amplifier, an NMOS tube T 17 NMOS tube T 18 NMOS tube T 19 A fourteenth voltage control unit, a fifteenth voltage control unit, a sixteenth voltage control unit and a seventeenth voltage control unit, and a second output end of the hearing-smell associated neuron module is connected with a NAND gate G 3 Is connected with the input end of the NAND gate G 3 The output end of the fifteenth voltage control unit is connected with one input end of the fifteenth voltage control unit, and the other input end of the fifteenth voltage control unit is connected with the second output end of the visual neuron module; the second output end of the visual olfactory association neuron module is provided with a NAND gate G 2 Is connected with the input end of the NAND gate G 2 The output end of the fourteenth voltage-controlled unit is connected with one input end of the fourteenth voltage-controlled unit, and the other input end of the fourteenth voltage-controlled unit is connected with the second output end of the auditory neuron module; the fourteenth voltage control unit and the fifteenth voltage control unitThe output ends of the voltage-controlled units are all connected with a voltage summation module SUM 10 Is connected with the input end of the voltage summation module SUM 10 An output end of the sixteenth voltage-controlled unit is connected with an input end of the sixteenth voltage-controlled unit, and an input signal end I 2 And input signal terminal I 4 Are all connected with a voltage summation module SUM 12 Is connected with the input end of the voltage summation module SUM 12 The output end of the sixteenth voltage-controlled unit is connected with the voltage summation module SUM 11 Is connected with an input end of the power supply; the output end of the eleventh integrating circuit is connected with the resistor R 131 Is connected with one input end of the fifteenth voltage comparator, and the other input end of the fifteenth voltage comparator is connected with the power supply V 30 The output end of the fifteenth voltage comparator is grounded and connected with the NMOS tube T 19 The grid electrode of the NMOS tube T is connected with 19 Is connected with the source of the power supply V 31 Grounded NMOS tube T 19 The drain electrode of (a) is respectively connected with the resistor R 132 Is connected with the input end of the eleventh inverting amplifier, the output end of the eleventh inverting amplifier is connected with the SUM 11 Is connected with the other input end of the voltage summation module SUM 11 Output terminal of (d) and resistor R 124 Is connected with one end of resistor R 124 The other end of (2) is respectively connected with the memristive MC 7 Positive terminal of (a), mathematical operation unit ABM 7 Is connected with one input end of the memristive MC 7 Negative terminal of (a) is respectively connected with the mathematical operation unit ABM 7 Another input end of NMOS tube T 17 The grid electrode of the NMOS tube T is connected with 17 The source electrode of (2) is grounded, NMOS tube T 17 Through the grid of the power supply V 29 Grounded, mathematical operation unit ABM 7 The output end of the eleventh integrating circuit is connected with the input end of the eleventh integrating circuit and the input end of the twelfth integrating circuit respectively, and the output end of the eleventh integrating circuit is connected with the output end of the twelfth integrating circuit through a resistor R 130 Respectively with power supply V 32 Positive electrode of (2), NMOS tube T 18 Is connected with the source of the power supply V 32 Cathode of (D) and diode D 7 Is connected with the cathode of the diode D 7 The positive electrode of (2) is grounded; the output end of the twelfth integrating circuit is connected with one input end of the fourteenth voltage comparatorThe other input end of the fourteenth voltage comparator is grounded, and the output end of the fourteenth voltage comparator is connected with the NMOS tube T 18 The grid electrode of the NMOS tube T is connected with 18 The grid electrode of (C) is respectively connected with the resistor R 133 One end of each of the fifth inverting proportional amplifier is connected with the input end of the resistor R 133 The output end of the fifth inverting proportional amplifier is connected with the input end of the twelfth inverting amplifier, the output end of the twelfth inverting amplifier is connected with the other input end of the seventeenth voltage-controlled unit, and the output end of the seventeenth voltage-controlled unit is the output end U13 of the audio-visual association neuron module.
8. The full-function pavlovian associative memory and fear learning memristive circuit according to any one of claims 4 to 7, wherein the output synapse module includes a sixteenth voltage comparator, a seventeenth voltage comparator, an eighteenth voltage-controlled unit, a nineteenth voltage-controlled unit and a twentieth voltage-controlled unit, and the second output terminal of the auditory pain sense associative neuron module is an input terminal of the sixteenth voltage comparator, an or gate G, respectively 7 An output end of the sixteenth voltage comparator is connected with the SUM 8 Is a voltage summing module SUM 8 Through the other input of the power supply V 28 Grounded, voltage summing module SUM 8 Output of (1) and AND gate G 8 Is connected with the input end I of the circuit board; the second output end of the visual pain associated neuron module is respectively provided with an input end of a seventeenth voltage comparator and an OR gate G 7 Is connected to the other input terminal of OR gate G 7 The output end of (2) is an output signal end O 1 The method comprises the steps of carrying out a first treatment on the surface of the The output end of the seventeenth voltage comparator and the voltage summation module SUM 9 Is a voltage summing module SUM 9 Through the other input of the power supply V 27 Grounded, voltage summing module SUM 9 Output of (1) and AND gate G 8 Is connected with the input end II of the pain neuron module, and the output end U4 of the pain neuron module is connected with the AND gate G 8 Is connected to the input terminal III of the AND gate G 8 The output ends of the (a) are respectively connected with an eighteenth voltage control unit, a nineteenth voltage control unit and a twentieth voltage control unitAn input end of the element is connected; the first output end of the auditory sense and olfactory sense association neuron module is connected with one input end of an eighteenth voltage-controlled unit, the output end U13 of the auditory sense association neuron module is connected with the other input end of a nineteenth voltage-controlled unit, the first output end of the visual sense and olfactory sense association neuron module is connected with the other input end of a twentieth voltage-controlled unit, and the output ends of the eighteenth voltage-controlled unit, the nineteenth voltage-controlled unit and the twentieth voltage-controlled unit are all connected with an OR gate G 10 Is connected with the input end of OR gate G 10 The output end of (2) is an output signal end O 2 。
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