CN116401993A - Capacitor design method and device, electronic equipment, medium and program product - Google Patents
Capacitor design method and device, electronic equipment, medium and program product Download PDFInfo
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Abstract
The application discloses a capacitor design method and device, electronic equipment, a medium and a program product, and belongs to the field of quantum computing. The design method of the capacitor comprises the following steps: obtaining a theoretical model for carrying out capacitance calculation to obtain capacitance; and inputting calculation parameters serving as model parameters into a theoretical model to execute capacitance calculation so as to obtain capacitance. The calculation parameters are formed by correcting reference parameters of the different-surface structure, and the correction is made according to the reference parameters under the working temperature of the superconducting quantum chip in response to the change of the working temperature. The design method of the two capacitors considers the influence of the chip on the different-surface structure at the temperature of superconducting in actual operation, so that the capacitors with different-surface structures can be determined more accurately and in accordance with actual use, and the quantum chip with better performance can be obtained.
Description
Technical Field
The present application relates to the field of quantum information, and in particular, to a method and apparatus for designing a capacitor, an electronic device, a medium, and a program product.
Background
Various basic cell structures are typically configured in superconducting qubit chips. The basic cell structures include, for example, qubit cells, tunable couplers, readout resonators, control lines, and the like. Parameters such as coupling capacitance among basic unit structures have influence on characteristics such as coupling strength, dispersion displacement and energy dissipation in the quantum bit test. Thus, it would be clearly beneficial to accurately determine the coupling capacitance in the process of designing a quantum chip.
Disclosure of Invention
Examples of the application provide a capacitor design method and device, an electronic device, a medium and a program product. The scheme can be used for more accurately determining the capacitance of the structure with different surface distribution in the superconducting quantum chip, thereby being beneficial to improving the performance of the superconducting quantum chip manufactured based on the capacitance determined by the scheme.
The scheme exemplified by the application is implemented as follows.
In a first aspect, examples of the present application provide a method of designing a capacitor. The capacitor is a capacitor with a specified heterofacial structure in the superconducting quantum chip, and the heterofacial structure comprises a first structure and a second structure which are distributed in a heterofacial manner.
The design method of the capacitor comprises the following steps:
obtaining a theoretical model for carrying out capacitance calculation to obtain capacitance, wherein the theoretical model carries out capacitance calculation depending on input model parameters;
inputting calculation parameters serving as model parameters into a theoretical model to execute capacitance calculation so as to obtain capacitance;
the calculated parameter is formed by correcting the reference parameter of the out-of-plane structure, and the correction is made according to the reference parameter in response to the change of the working temperature of the superconducting quantum chip at the working temperature.
The capacitance design method is used for calculating the capacitance of the different-surface structure in the superconducting quantum chip, and can relatively truly reflect the actual value of the capacitance of the different-surface structure in the actual working state of the superconducting quantum chip. Thus, when designing a superconducting quantum chip, various components and structures in the chip can be designed in a targeted manner based on the calculated capacitance. Moreover, the influence of the working environment on the capacitance of the different-surface structure in the actual working state of the superconducting quantum chip can be examined through the scheme, so that compensatory adjustment can be carried out in design. The structure based on the adjusted design can play more positive performance and effect when the superconducting quantum chip works.
In the scheme, parameters required by capacitance calculation of the theoretical model are corrected, and then the corrected parameters are utilized to calculate the capacitance of the different-surface structure through the theoretical model, so that the capacitance of the different-surface structure is obtained. Wherein the parameter is from a heteroplanar structure and the modification to the parameter is made in response to a change in the operating temperature of the superconducting quantum chip at the operating temperature. Then, the parameter is corrected by considering the working temperature, and then the performance of the parameter under the actual working state of the chip can be reflected. Correspondingly, the capacitance of the different-surface structure obtained by calculation through the theoretical model by utilizing the corrected parameters is closer to or accords with the actual capacitance of the different-surface structure under the working state of the superconducting quantum chip.
Therefore, the scheme of the embodiment of the application can be used in the design and manufacturing process of the superconducting quantum chip to assist research and development personnel to obtain a more ideal different-surface structure, so that the performance and design expectation of the manufactured superconducting quantum chip can be better met, or the actual design performance is met.
In a second aspect, examples of the present application provide a method for designing a capacitor, for determining a capacitor of a specified hetero-planar structure in a superconducting quantum chip, where the hetero-planar structure includes a first structure and a second structure distributed in different planes, the method for designing a capacitor including:
determining a working capacitance required by the different-surface structure under the operation state of the superconducting quantum chip;
calculating a first capacitance of a vacuum-mediated parallel plate capacitor;
respectively carrying out simulation calculation on the parallel plate capacitors by using a plurality of simulation software to obtain a plurality of second capacitors;
comparing the plurality of second capacitors with the first capacitors respectively, and selecting simulation software corresponding to the second capacitor closest to the value of the first capacitor from the plurality of simulation software as target software;
determining simulation parameters which are required by simulation calculation of target software and depend on an out-of-plane structure, and correcting the simulation parameters based on the superconducting working temperature of the superconducting quantum chip to obtain working parameters;
and calculating through target software and working parameters to obtain the process capacitance with the different-surface structure.
In a third aspect, examples of the present application provide an apparatus for designing a capacitance for determining a capacitance of a specified hetero-planar structure in a superconducting quantum chip, the hetero-planar structure including a first structure and a second structure distributed in different planes, the apparatus comprising:
the first extraction module is used for obtaining a working capacitor required by the different-surface structure under the running state of the superconducting quantum chip;
a first calculation module for calculating a first capacitance of a vacuum-mediated parallel plate capacitor;
the second calculation module is used for respectively carrying out simulation calculation on the parallel plate capacitors by utilizing a plurality of simulation software to obtain a plurality of second capacitors;
the selection module is used for comparing the plurality of second capacitors with the first capacitors respectively and selecting simulation software corresponding to the second capacitor closest to the value of the first capacitor from the plurality of simulation software as target software;
the correction module is used for determining simulation parameters which are required by the target software for simulation calculation and depend on the different-surface structure, and correcting the simulation parameters based on the superconducting working temperature of the superconducting quantum chip so as to obtain the working parameters;
and the third calculation module is used for calculating through target software and working parameters to obtain the process capacitance of the different-surface structure.
In a fourth aspect, examples of the present application provide an apparatus for designing a capacitance, where the capacitance is a capacitance specifying an out-of-plane structure in a superconducting quantum chip, and the out-of-plane structure includes a first structure and a second structure distributed out-of-plane, including:
an acquisition module configured to acquire a theoretical model for performing capacitance calculation to obtain capacitance, wherein the theoretical model includes a theoretical model for performing capacitance calculation, and the theoretical model performs capacitance calculation depending on input model parameters;
a calculation module configured to input a theoretical model as a model parameter to perform capacitance calculation to obtain capacitance;
the calculation parameters are formed by correcting reference parameters of the different-surface structure, and the correction is made according to the reference parameters under the working temperature of the superconducting quantum chip in response to the change of the working temperature.
In a fifth aspect, examples of the present application provide an electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of designing a capacitor as described above.
In a sixth aspect, examples of the present application provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the foregoing method of designing a capacitor.
In a seventh aspect, examples of the present application provide a computer program product comprising a computer program which, when executed by a processor, implements the aforementioned method of designing a capacitance.
The scheme of the application has at least the following beneficial effects:
the exemplary scheme considers the operating temperature of the superconducting quantum chip in the actual operating state and the response behavior of the out-of-plane structure in the chip at that operating temperature. Based on this, the capacitance of the above-described hetero-planar structure is calculated. The capacitance of the different-surface structure obtained through calculation according to the scheme can be closer to and meet the design requirement of the chip, so that the superconducting quantum chip with expected performance is obtained.
Drawings
For a clearer description, the drawings that are required to be used in the description will be briefly introduced below.
FIG. 1 is a schematic diagram of a structure of a qubit on a quantum chip according to the related art;
fig. 2 is a schematic structural diagram of a superconducting quantum chip based on flip-chip interconnection technology in the example of the present application;
FIG. 3 is a schematic diagram of a parallel plate capacitor in an example of the present application;
FIG. 4 is a flow chart of a first method of designing a capacitor in the examples of the present application;
FIG. 5 is a flow chart of a second method of designing a capacitor in the examples of the present application;
fig. 6 is a flow chart of a third method for designing a capacitor in the example of the present application.
Reference numerals illustrate: 100-superconducting quantum chips; 101-a first structure; 102-a second structure; 103-heterofacial structure.
Detailed Description
Referring to fig. 1, a quantum chip based on a superconducting quantum circuit includes superconducting circuit structures such as a qubit and a microwave resonant cavity. The qubit is a two-level system formed by using a capacitor and a Josephson junction with nonlinear inductance characteristic. The electric parameter states of capacitance, inductance and the like of different targets are realized by designing different shapes. The shape of the Transmon qubit (transmitter qubit) is shaped like a "+" and consists of a cross-shaped capacitor and a superconducting quantum interference device (Superconducting Quantum Interference Device, short for short, required) connected to the end of one branch of the capacitor. Wherein the superconducting quantum interference device (squid) comprises one or more josephson junctions; josephson junctions are devices comprising two electrodes and a thin insulating barrier separating the two electrodes, and the materials of the two electrodes may exhibit a superconducting property at or below their own critical temperature.
In the above-described qubit architecture, there are a number of different functional circuit structures around the qubit, such as a read resonator and a coupler for coupling between the qubits.
The circuit structure further includes a drive Control signal Line (XY-Control Line, also called XY Control Line or pulse Control signal Line) for performing XY rotation operation on the qubit. By applying a driving voltage signal in the circuit, transition excitation can be performed on the qubit; which is associated with the qubit by capacitive coupling.
The circuit structure further comprises a circuit structure for performing a Z rotation operation on the qubit and is completed by a control signal line near the superconducting quantum interference device (squid); it is called a magnetic flux Control signal Line (also called a Z Control signal Line or a frequency Control signal Line). As previously mentioned, the flux modulating signal line is arranged in the vicinity of the superconducting quantum interference device (squid), which excites the current and is inductively coupled to the superconducting quantum interference device (squid) by a magnetic field.
It should be noted that both the magnetic flux controlling signal line and the drive control line may be used to control the qubit, but their control forms and purposes are essentially different.
Wherein the drive control signal line applies a pulse to the qubit in the form of an electric field, the pulse causing a transition in the energy level of the qubit.
The signal transmitted by the magnetic flux regulating signal line generates a magnetic field and is applied to the superconducting quantum interference device (squid) region, and the magnetic flux passing through the quantum interference device (squid) region can cause the critical current of squid to change. The change of the critical current causes the change of the frequency of the tunable qubit, namely, the control of the frequency of the qubit can be realized through the signal transmitted by the magnetic flux control signal line.
As previously mentioned, there are multiple basic cell structures in a superconducting qubit chip, such as qubit cells, tunable couplings, readout resonators, control lines, and the like. And parameters such as coupling capacitance among basic units have influence on coupling strength, dispersion displacement, energy dissipation and the like of the quantum bit in the test. Therefore, in the design and fabrication process of the superconducting quantum chip, consideration is required for the coupling capacitance.
In practice, however, the inventors have found that the coupling capacitance values in current chip designs and fabrication do not meet the performance expectations of the chip well. Therefore, the inventors consider the numerical accuracy of the coupling capacitance to be questionable. As a result of the study, the inventors found that inaccuracy of the coupling capacitance can be attributed to the characteristic change of the calculated coupling unit at low temperatures. For example, superconducting quantum chips are currently required to operate at low temperature conditions and are typically provided in a dilution refrigerator. The coupling element material may undergo a change such as a dielectric constant in a low temperature environment, and thus cause a parameter of the basic element to be changed, thereby affecting the coupling capacitance.
Therefore, considering the actual working condition of the chip, whether the environment has an influence on the basic unit or not, and what kind of influence, and further evaluating the correlation of the influence and the coupling capacitance of the basic unit, it is helpful to obtain a more accurate coupling capacitance.
Under such knowledge, the inventors have proposed a new method of designing a capacitor. And as previously mentioned, in the examples of the present application, the capacitance therein describes the capacitance of the specified out-of-plane structure 103 in the superconducting quantum chip 100 as shown in fig. 2; and the out-of-plane structure includes first and second structures 101 and 102 in out-of-plane distribution.
For example, superconducting quantum chips are alternatively implemented as flip chips. In other examples, the superconducting quantum chip is a flip chip consisting of two or more chips, and the first structure and the second structure are heterohedonically distributed to two different ones of the at least two chips. Wherein the out-of-plane structure is for example a resonator distributed in an out-of-plane in a flip-chip superconducting quantum chip. Thus, the corresponding first and second structures may then be two-segment resonators, and may typically be implemented as coplanar waveguide structures. Alternatively, the first structure and the second structure in the out-of-plane structure may also be tunable couplers for coupling between qubits and may be implemented as tunable qubits. Alternatively, the first and second structures in the out-of-plane structure may also be control lines for qubit control, e.g. implemented as coplanar waveguide transmission lines.
It is understood that the solution in the examples of the present application may also be applied to other types of chips, and is not limited to a superconducting quantum chip.
In an example, referring to fig. 4, 5 and 6, the method for designing the capacitor includes:
in step S101, a theoretical model for capacitance calculation is obtained, and the theoretical model performs capacitance calculation depending on the input model parameters.
The process of calculating capacitance, i.e., capacitance calculation, can be implemented in conjunction with the theoretical model therein and the model parameters.
The theoretical model may be a reliable model that has been validated provided by the practitioner of the solution, or a model that is reasonably generalized in practice. There are a variety of correlation models already known to the inventors that are well-established in the industry. Thus, the theoretical model may alternatively be provided by simulation software. And the theoretical model mentioned is, for example, using commercial software such as maxwell, Q3D, sonnect, comsol, CST, or the like.
In actual use, although these simulation software may be based on close and identical physical models, they may also take into account different specifics when embodying respective corresponding computational models. In other words, the particular models used by these simulation software may be subject to particular differences, and therefore, selecting more efficient and appropriate simulation software will help improve the accuracy of the capacitance calculation results obtained when considering the design capacitance.
That is, where multiple simulation software is available, it would be advantageous to evaluate which simulation software. To enable evaluation of simulation software, based on the calculation of the capacitance of the out-of-plane structure, in an example, the simulation software is selected in the following manner. In an example, alternatively, a method of selecting target simulation software includes:
calculating a first capacitance of the preset parallel plate capacitor using vacuum as a medium by using a capacitance calculation formula c=epsilon S/4 pi kd of the parallel plate capacitor as shown in fig. 3; wherein epsilon is the dielectric constant of the medium between the polar plates, S is the facing area of the two polar plates, and k is the electrostatic force constant 8.988N.m 2 / 2 D is the plate spacing.
The second capacitance of the parallel plate capacitor is calculated using simulation software.
Based on the first capacitance and the second capacitance, simulation software is selected as target simulation software. For example, when the first capacitance and the second capacitance are the same, the simulation software is selected as the target simulation software. Alternatively, when the absolute value of the difference between the first capacitance and the second capacitance satisfies a certain range, the simulation software is selected as the target simulation software. It will also be appreciated that in some examples, if the absolute value of the difference between the first capacitance and the second capacitance is too large, it may be necessary to consider that the model of the simulation software is problematic, thereby suggesting replacement of other simulation software or considering self-building of the model.
As previously mentioned, a number of simulation software options are currently available, and thus, targeted selection of such software is contemplated. For example, when the number of simulation software is two or more and each is different (it is understood that the calculation models provided by the simulation software are also different), capacitance calculation is performed by each simulation software, respectively, so that a plurality of second capacitances corresponding to each simulation software are obtained. Then, based on the first capacitance and the second capacitance, selecting the simulation software as the target simulation software includes: and calculating the difference value of each second capacitor and each first capacitor, and selecting simulation software as target simulation software according to each difference value. For example, a threshold is set, and when a certain difference is smaller than the threshold, simulation software corresponding to the difference can be selected. Or, when a certain difference value is between a and B, the simulation software corresponding to the difference value can be selected. Or selecting the simulation software corresponding to the minimum value of the absolute values in all the difference values as the target simulation software.
Step S102, inputting calculation parameters serving as model parameters into a theoretical model to execute capacitance calculation so as to obtain capacitance.
In this step, the calculated parameter is formed by modifying a reference parameter of the out-of-plane structure, and the modification is made in response to a change in the operating temperature of the superconducting quantum chip at the operating temperature in accordance with the reference parameter.
The reference parameters may vary according to the theoretical model selected. Also, it is worth noting that the reference parameter is a model required for achieving capacitance calculation from a theoretical model, and is obtained (e.g., measured, determined, or set) from an out-of-plane structure. Parameters such as upper and lower substrate materials, medium between upper and lower substrates, etc. may need to be considered when selecting, for example, maxwell for parallel plate capacitor 3D simulation.
On the basis of the reference parameter, it is corrected. The correction is made in view of the fact that one or more of these reference parameters may vary under the actual operating conditions of the chip as described above. If no correction is made, the subsequent calculation results deviate from the actual results. And, moreover, the method comprises the steps of. When considering the use of superconducting quantum chips, the change in dielectric constant occurs when they operate at very low temperatures (e.g., milli-kelvin). Thus, the dielectric constant in the reference parameter is adjusted (e.g., increased or decreased), while other parameters may be considered to remain unchanged.
Alternatively, when the out-of-plane structure is provided by other devices and the operating conditions of the devices may have some non-negligible effect on the capacitance of the out-of-plane structure, it is also necessary to correct the reference parameters used for calculation based on this effect. For example, if the device is required to operate at high temperatures or in high electric or magnetic fields, which may cause one or more of its reference parameters to be altered, then correction is also required.
By the above means, the reference parameter is corrected to form the calculated parameter. It can be understood that the calculated parameters are obtained by partially or completely modifying the reference parameters by taking the environment of the different-surface structure in the actual service process into consideration. Taking the capacitance calculation of a parallel plate capacitor as an example, c=εS/4πkd, where the reference parameters may be ε, S, k, pi, d. At the (superconducting) temperature of the superconducting quantum chip, if epsilon increases, s needs to be increased by taking this amount into consideration in actual calculation. Similarly, if ε is reduced, s needs to be reduced by taking this amount into account in the actual calculation.
On the basis, the calculation parameters obtained after the reference parameters are corrected are input into a calculation model to perform capacitance calculation, so that a more accurate capacitance value or a capacitance value which is closer to the actual requirement can be obtained.
From another perspective, the capacitance value calculated by the design method of the capacitor can enable the heteroplanar structure to have better performance during use due to consideration of the performance of the device realized based on the heteroplanar structure in the actual working environment.
As more specific and alternative examples, the method of designing the capacitor includes the steps of:
step S201, determining a working capacitor required by the different-surface structure under the operation state of the superconducting quantum chip.
The working capacitance refers to, for example, a capacitance value that the superconducting quantum chip is expected to exhibit when performing quantum computation. I.e. the capacitance that the superconducting quantum chip is expected to exhibit in the operating state. And it is understood that for superconducting quantum chips, the working capacitance may be generated by a corresponding change in the characteristic of the material at superconducting temperature of the subsequently mentioned process capacitance.
Step S202, calculating a first capacitance of a parallel plate capacitor using vacuum as a medium.
The capacitance calculation of the parallel plate capacitor can be calculated with the formula εS/4πkd.
Step S203, respectively performing simulation calculation on the parallel plate capacitors by using a plurality of simulation software to obtain a plurality of second capacitors.
The manner in which capacitance is calculated by the simulation software varies depending on the particular software selected; the specific calculation process and the use manner of the software are provided by the software provider, and are not described herein.
And S204, comparing the plurality of second capacitors with the first capacitors, and selecting simulation software corresponding to the second capacitor closest to the first capacitor in the plurality of simulation software as target software.
And when the second capacitance calculated by only one piece of simulation software is closest to the first capacitance in the alternative plurality of simulation software, the corresponding simulation software is taken as target software. If the second capacitance calculated by more than two simulation software is closest to the first capacitance, one of the more than two simulation software can be arbitrarily selected as the target software. And if the process capacitance and the working capacitance calculated later do not meet the requirements, the design method can be repeated again, and one of the two or more simulation software is selected as the target software.
Step S205, determining simulation parameters which are needed by the target software for simulation calculation and depend on the different-surface structure, and correcting the simulation parameters based on the superconducting working temperature of the superconducting quantum chip to obtain the working parameters.
The simulation parameters are defined by the corresponding theoretical model provided by the simulation software, and may be, for example, various suitable parameters corresponding to the out-of-plane structure, such as structural parameters, electrical parameters, physical parameters, and the like. And wherein the modification may be, for example, modifying a dielectric parameter implementation in the simulation parameters.
And S206, calculating through target software and working parameters to obtain the process capacitance of the different-surface structure.
The process capacitance refers to the capacitance value representation of the manufactured different-surface structure after the actual manufacturing after designing the superconducting quantum chip based on the different-surface structure. Alternatively, the superconducting quantum chip based on the hetero-planar structure is manufactured depending on the process capacitance determined by the method of the present example, and the capacitance value of the hetero-planar structure measured at the actual operating temperature (superconducting temperature) may be matched or identical to the operating capacitance.
And, therefore, by comparing the working capacitance and the process capacitance, it can be judged whether the design method of the capacitance meets the expectations or whether the selection of the simulation software is necessary to adjust or select other simulation software. Which can be readily determined and decided by the researcher.
Correspondingly, an apparatus for designing a capacitance is presented in the examples. The device comprises:
the first extraction module is used for obtaining a working capacitor required by the different-surface structure under the running state of the superconducting quantum chip;
a first calculation module for calculating a first capacitance of a vacuum-mediated parallel plate capacitor;
the second calculation module is used for respectively carrying out simulation calculation on the parallel plate capacitors by utilizing a plurality of simulation software to obtain a plurality of second capacitors;
the selection module is used for comparing the plurality of second capacitors with the first capacitors respectively and selecting simulation software corresponding to the second capacitor closest to the value of the first capacitor from the plurality of simulation software as target software;
the correction module is used for determining simulation parameters which are required by the target software for simulation calculation and depend on the different-surface structure, and correcting the simulation parameters based on the superconducting working temperature of the superconducting quantum chip so as to obtain the working parameters;
and the third calculation module is used for calculating through target software and working parameters to obtain the process capacitance of the different-surface structure.
As another example, an apparatus for designing a capacitor is also presented in the examples. The method comprises the following steps:
an acquisition module configured to acquire a theoretical model for performing capacitance calculation to obtain capacitance, and the theoretical model performs capacitance calculation depending on input model parameters;
a calculation module configured to input calculation parameters as model parameters into a theoretical model to perform capacitance calculation to obtain capacitance;
the calculation parameters are formed by correcting reference parameters of the different-surface structure, and the correction is made according to the reference parameters under the working temperature of the superconducting quantum chip in response to the change of the working temperature.
The acquisition module comprises a selection module, for example. The selection module is configured to select target simulation software, and the target simulation software is capable of providing a theoretical model required for performing capacitance calculations. In some specific examples, the selection module includes, for example:
a first calculation module configured to calculate a first capacitance of a preset parallel plate capacitor using vacuum as a medium using a capacitance calculation formula c=εs/4pi kd of the parallel plate capacitor;
a second calculation module for calculating a second capacitance of the parallel plate capacitor using simulation software;
a selection sub-module configured to select simulation software as target simulation software based on the first capacitance and the second capacitance;
wherein epsilon is the dielectric constant of the medium between the polar plates, S is the facing area of the two polar plates, and k is the electrostatic force constant 8.988N.m 2 /C 2 D is the plate spacing.
Further, when the simulation software has a plurality of alternatives, that is, the number of simulation software is two or more and each is different, the method of calculating the second capacitance of the parallel plate capacitor includes, for example: capacitance calculation is performed by using each simulation software, respectively, so as to obtain a plurality of second capacitances corresponding to each simulation software.
The selecting submodule includes:
a difference calculating unit configured to calculate a difference of each of the second capacitances and the first capacitances;
and the selection unit is configured to select the simulation software as target simulation software according to each difference value. Still further, the selecting unit is configured to: and selecting the simulation software corresponding to the minimum value of the absolute values in all the difference values as target simulation software.
The methods and apparatus of the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination of the preceding. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. Accordingly, a computer program product is presented in the examples of this application. Which comprises a computer program which, when executed by a processor, implements the aforementioned method of designing a capacitor.
The aforementioned computer instructions may be stored in or transmitted across a computer-readable storage medium. Accordingly, a non-transitory computer-readable storage medium storing computer instructions is also presented in the examples of this application. The computer instructions are for causing a computer to perform the method of designing a capacitor described above. The computer instructions may be transmitted from one network site, computer, server, or data center to another network site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.).
The storage media may be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. As non-limiting examples, the usable medium may be a read-only memory (ROM), or a random-access memory (RandomAccessMemory, RAM), or a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape, a magnetic disk, or an optical medium, such as a Digital Versatile Disk (DVD), or a semiconductor medium, such as a Solid State Disk (SSD), or the like.
Furthermore, an electronic device is proposed in the examples. Which includes at least one processor and a memory communicatively coupled to the at least one processor. The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of designing the capacitor. The processor is, for example, a Central Processing Unit (CPU), a Network Processor (NP), or a combination of CPU and NP. Alternatively, the processor may be further configured with a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a general-purpose array logic (GAL), or any combination thereof.
The embodiments described above by referring to the drawings are exemplary only and are not to be construed as limiting the present application.
For purposes of clarity, technical solutions, and advantages of embodiments of the present application, one or more embodiments have been described above with reference to the accompanying drawings. Wherein like reference numerals are used to refer to like elements throughout. In the description above, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced without these specific details, and that such embodiments may be incorporated by reference herein without departing from the scope of the claims.
It should be noted that the terms "first," "second," "third," "fourth," and the like in the description and claims of the present application and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The foregoing detailed description of the construction, features and advantages of the present application will be presented in terms of embodiments illustrated in the drawings, wherein the foregoing description is merely illustrative of preferred embodiments of the application, and the scope of the application is not limited to the embodiments illustrated in the drawings.
Claims (13)
1. The design method of the capacitor is characterized in that the capacitor is a capacitor with a specified different-surface structure in a superconducting quantum chip, and the different-surface structure comprises a first structure and a second structure which are distributed in different surfaces, and the design method of the capacitor comprises the following steps:
obtaining a theoretical model for performing a capacitance calculation to obtain a capacitance, the theoretical model performing the capacitance calculation in dependence on input model parameters;
inputting calculation parameters serving as model parameters into a theoretical model to execute capacitance calculation so as to obtain capacitance;
the calculation parameters are formed by correcting reference parameters of the different-surface structure, and the correction is made according to the reference parameters under the working temperature of the superconducting quantum chip in response to the change of the working temperature.
2. The method of claim 1, wherein the theoretical model is provided by simulation software, wherein the simulation software is optionally provided by maxwell, Q3D, sonnect, comsol, or CST;
and/or obtaining a theoretical model for capacitance calculation comprises: target simulation software is selected and is capable of providing the theoretical model.
3. The method of designing a capacitor according to claim 1, wherein obtaining a theoretical model for performing a capacitance calculation to obtain a capacitance comprises: selecting target simulation software, wherein the target simulation software can provide the theoretical model, and the method for selecting target simulation software comprises the following steps:
calculating a first capacitance of a preset parallel plate capacitor taking vacuum as a medium by using a capacitance calculation formula C=epsilon S/4 pi kd of the parallel plate capacitor;
calculating a second capacitance of the parallel plate capacitor using simulation software;
selecting the simulation software as target simulation software based on the first capacitor and the second capacitor;
wherein epsilon is the dielectric constant of the medium between the polar plates, S is the facing area of the two polar plates, and k is the electrostatic force constant of 8.988N.m 2 /c 2 D is the plate spacing.
4. The method according to claim 3, wherein in the step of calculating the second capacitance of the parallel plate capacitor using simulation software, the number of simulation software is two or more and each is different, and calculating the second capacitance of the parallel plate capacitor includes: respectively carrying out capacitance calculation by using each simulation software so as to obtain a plurality of second capacitances corresponding to each simulation software;
based on the first capacitance and the second capacitance, selecting the simulation software as the target simulation software includes: calculating the difference value of each second capacitor and each first capacitor, and selecting the simulation software as target simulation software according to each difference value;
optionally, selecting the simulation software as the target simulation software according to each difference value includes:
and selecting the simulation software corresponding to the minimum value of the absolute values in all the difference values as target simulation software.
5. The method of claim 1, wherein the modifying includes numerically adjusting at least one of the reference parameters;
optionally, the at least one parameter includes a dielectric constant corresponding to a material of which the hetero-planar structure is made.
6. The method of designing a capacitor according to claim 1, wherein the superconducting quantum chip is a flip chip;
alternatively, the superconducting quantum chip is a flip chip formed by at least two chips, and the first structure and the second structure are distributed on different sides of two different chips in the at least two chips.
7. The design method of the capacitor is used for determining the capacitor of the specified different-surface structure in the superconducting quantum chip, and the different-surface structure comprises a first structure and a second structure which are distributed in different surfaces, and is characterized by comprising the following steps:
determining a working capacitance required by the different-surface structure under the operation state of the superconducting quantum chip;
calculating a first capacitance of a vacuum-mediated parallel plate capacitor;
respectively carrying out simulation calculation on the parallel plate capacitors by using a plurality of simulation software to obtain a plurality of second capacitors;
comparing the plurality of second capacitors with the first capacitors respectively, and selecting simulation software corresponding to the second capacitor closest to the value of the first capacitor from the plurality of simulation software as target software;
determining simulation parameters which are required by target software for simulation calculation and depend on the different-surface structure, and correcting the simulation parameters based on the superconducting working temperature of the superconducting quantum chip to obtain working parameters, wherein, optionally, in the step of correcting the simulation parameters based on the superconducting working temperature of the superconducting quantum chip, at least dielectric parameters in the simulation parameters are corrected;
and calculating through the target software and the working parameters to obtain the process capacitance of the different-surface structure.
8. An apparatus for designing a capacitance for determining a capacitance of a specified heterofacial structure in a superconducting quantum chip, the heterofacial structure comprising a first structure and a second structure distributed heterofacial, the apparatus comprising:
the first extraction module is used for obtaining a working capacitor required by the different-surface structure under the running state of the superconducting quantum chip;
a first calculation module for calculating a first capacitance of a vacuum-mediated parallel plate capacitor;
the second calculation module is used for respectively carrying out simulation calculation on the parallel plate capacitors by utilizing a plurality of simulation software to obtain a plurality of second capacitors;
the selection module is used for comparing the plurality of second capacitors with the first capacitors respectively and selecting simulation software corresponding to the second capacitor closest to the value of the first capacitor from the plurality of simulation software as target software;
the correction module is used for determining simulation parameters which are required by simulation calculation of target software and depend on the different-surface structure, and correcting the simulation parameters based on the superconducting working temperature of the superconducting quantum chip so as to obtain working parameters;
and the third calculation module is used for calculating through the target software and the working parameters to obtain the process capacitance of the different-surface structure.
9. A device for designing a capacitance, the capacitance being a capacitance of a specified heterofacial structure in a superconducting quantum chip, and the heterofacial structure comprising a first structure and a second structure distributed heterofacial, comprising:
an acquisition module configured to obtain a theoretical model for performing a capacitance calculation to obtain a capacitance, and the theoretical model performs the capacitance calculation in dependence on input model parameters;
a calculation module configured to input calculation parameters as model parameters into a theoretical model to perform the capacitance calculation to obtain a capacitance;
the calculation parameters are formed by correcting reference parameters of the different-surface structure, and the correction is made according to the reference parameters under the working temperature of the superconducting quantum chip in response to the change of the working temperature.
10. The apparatus for designing a capacitor of claim 9, wherein the acquisition module comprises a selection module configured to select a target simulation software, and the target simulation software is capable of providing the theoretical model;
optionally, the selecting module includes:
a first calculation module configured to calculate a first capacitance of a preset parallel plate capacitor using vacuum as a medium using a capacitance calculation formula c=εs/4pi kd of the parallel plate capacitor;
a second calculation module that calculates a second capacitance of the parallel plate capacitor using simulation software, wherein optionally the number of simulation software is two or more and each is different, and calculating the second capacitance of the parallel plate capacitor comprises: respectively carrying out capacitance calculation by using each simulation software so as to obtain a plurality of second capacitances corresponding to each simulation software; and selecting the sub-module comprises: a difference calculating unit configured to calculate a difference of each of the second capacitances and the first capacitances; and a selection unit configured to select the simulation software as a target simulation software according to the respective differences; wherein, optionally, the selection unit is configured to: selecting simulation software corresponding to the minimum value of absolute values in all the difference values as target simulation software; and
a selection sub-module configured to select the simulation software as a target simulation software based on the first capacitance and the second capacitance;
wherein epsilon is the dielectric constant of the medium between the polar plates, S is the facing area of the two polar plates, and k is the electrostatic force constant 8.988N.m 2 /c 2 D is the plate spacing.
11. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of designing a capacitor according to any one of claims 1-7.
12. A non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the method of designing a capacitor according to any one of claims 1 to 7.
13. Computer program product, characterized in that it comprises a computer program which, when executed by a processor, implements a method of designing a capacitance according to any one of claims 1-7.
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