CN116401900A - Method and device for communication among multiple systems of software simulation - Google Patents
Method and device for communication among multiple systems of software simulation Download PDFInfo
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Abstract
The invention discloses a method and a device for communication among multiple systems of software simulation, and belongs to the technical field of wireless communication. Running lower computer software on a host machine, running an upper computer system on a virtual machine, internally configuring and running software simulation PCIE equipment in the virtual machine, and running a PCIE equipment driver for finding and driving the software simulation PCIE equipment in the upper computer system; taking the shared memory of the preassigned host as the running memory of the upper computer; the lower computer software completes the access operation to the upper computer operation memory through the shared memory; the access of the upper computer system to the shared lower computer memory and the interrupt notification between the upper computer system and the lower computer software are completed through the participation of the software simulation PCIE equipment. The invention solves the problem of interrupt notification and memory sharing among different systems, realizes seamless combination with the internal software design of a real system, greatly reduces the software integration difficulty and workload, and improves the software and hardware integration efficiency and simulation similarity.
Description
Technical Field
The invention relates to a communication simulation method among multiple systems, and belongs to the technical field of wireless communication.
Background
In a hardware platform commonly used in the communication field, IPC is generally used together with a PCI/PCIe bus as a basic structure for implementing hardware-level communication between multiple systems.
Their functions mainly include:
1. interrupt mutual notification between different systems is done using IPC (different interrupt numbers represent different meanings, which are used as message numbers by the software layer).
2. The notifier writes notification content into a local running memory SRAM or DDR, and the notifier addresses the running memory SRAM or DDR of the opposite party through the PCI/PCIe bus and reads the data written by the opposite party (the software layer takes the data as message content).
By using the set of mechanism, the business behaviors such as event notification, data synchronization and the like among different systems can be realized. There is currently a linux-based open source library called vhost-user in the software domain. The vhost-user is mainly used for communication between two processes in a user space, and adopts a shared memory as a bearing of a data plane and a socket as a bearing of a control plane. The Vhost-user aims at supporting the operation of the cloud network application at the beginning of design, and the most typical use scene is a fast forwarding back end developed by using dpdk in a matching way, so that more efficient network message forwarding performance is provided for the cloud application at the front end. The vhost-user open source library is not suitable for emulating such hardware-based inter-system communication mechanisms, and is mainly characterized by the following limitations:
1. the front-end interface developed based on the vhost-user is a network interface with a type of virtio in a linux system on a control surface, and is based on a vring API data interaction mode on a data surface. Such interface types are commonly used to develop specialized applications and are not suitable for common network applications such as ping, iperf, etc. And extensive support for such applications is required in simulation systems for telecommunication products.
2. The data plane adopts a vring API mode to encapsulate the shared memory mechanism of the bottom layer, and the mechanism is not complex, but can not realize seamless connection with the bottom layer of the data plane of the original system. The transplanting work is completed with larger workload, the original system structure is destroyed, and the simulation similarity is greatly reduced.
The development of products in the communication field is usually carried out in a way that the development progress of hardware is later than that of software development, so that a software simulation means is needed, the hardware behavior is simulated to the maximum extent before the hardware is in place, the software logic correctness is verified, and the software and hardware integration efficiency is improved.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a method and a device for communication among multiple systems by software simulation.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method for software to simulate communication among multiple systems,
running lower computer software on a host machine, running an upper computer system on a virtual machine, and internally configuring and running software to simulate PCIE equipment, wherein a PCIE equipment driver is run in the upper computer system and used for finding and driving the software to simulate the PCIE equipment;
taking the shared memory of the preassigned host as the running memory of the upper computer;
the software simulation PCIE equipment supports the interrupt of the PCIE equipment and PCIE address addressing, and at least comprises a base address register, wherein the base address register is used for mapping IPC interrupt register space and sharing a lower computer memory;
the lower computer software completes the access operation of any position of the upper computer operation memory through the shared memory;
the access of the upper computer system to the shared lower computer memory and the interrupt notification between the upper computer system and the lower computer software are completed through the participation of the software simulation PCIE equipment.
Further, the actual memory space of the base address register is applied by the software simulation PCIE device itself on the host in a shared memory manner.
Further, the PCIE device driver maps the first address of the shared memory to a virtual address of the upper computer by using a memory remapping manner, and the virtual address is accessed by the upper computer system.
Further, the step of accessing the shared lower computer memory initiated by the upper computer system comprises the following steps:
11 The upper computer system carries a PCIE equipment memory virtual address and an operand value to initiate read-write access to the shared lower computer memory;
12 The PCIE address conversion unit in the software simulation PCIE equipment converts the memory virtual address carried by the upper computer system into an address offset and an operand which are used for sharing the memory of the lower computer as objects to read and write; according to the data type of the read-write access target of the upper computer system to the PCIE equipment, the PCIE address conversion unit executes the read-write access operation of the corresponding byte length to the shared lower computer memory;
13 The lower computer software adopts a shared memory standard read-write access mode to carry out read-write access on the shared lower computer memory.
Further, the step of accessing the shared lower computer memory initiated by the lower computer is as follows: and the lower computer software performs read-write access on the shared lower computer memory by adopting a shared memory standard read-write access mode.
Further, the step of accessing the running memory of the upper computer initiated by the lower computer software comprises the following steps:
31 The upper computer system directly writes data at the physical address of the upper computer running memory;
32 The upper computer system writes the value of the physical address into a specific address of the virtual address of the internal memory of the PCIE equipment in the upper computer;
33 Software simulation PCIE equipment converts the specific address into a specific address offset of the shared lower computer memory, and writes the value of the physical address into the specific address offset of the shared lower computer memory;
34 The lower computer software directly obtains the value of the physical address by accessing the specific address offset of the shared lower computer memory;
35 The lower computer software obtains the virtual machine base address of the running memory of the upper computer by adopting a shared memory standard access mode, converts the read physical address into a virtual address, and reads the data written by the upper computer system by using the virtual address.
Further, the step of the upper computer running memory access initiated by the upper computer system is as follows: the upper computer system directly writes data at the physical address of the upper computer running memory.
Further, the step of notifying the lower computer software of the interrupt initiated by the upper computer system is as follows: the software simulates the write-in behavior of the PCIE equipment to the IPC interrupt register, if the write-in is detected, the corresponding write-in bit is converted into a predefined message, and the predefined message is sent to the lower computer software through a socket channel.
Further, the step of notifying the upper computer system of the interrupt initiated by the lower computer software is as follows: the software simulation PCIE equipment receives a predefined message sent by the lower computer software in a socket channel, analyzes the predefined message into a corresponding interrupt signal, and initiates a PCIE interrupt to inform an upper computer system.
An apparatus for software emulation of multi-system communication, comprising:
the upper computer system operates on the virtual machine, and takes the shared memory of the preassigned host as the upper computer operation memory; a PCIE device driver is operated in the upper computer system;
configuring software running in the virtual machine to simulate PCIE equipment, and finding and driving by a PCIE equipment driver; the software simulation PCIE equipment supports the interrupt of the PCIE equipment and PCIE address addressing, and at least comprises a base address register, wherein the base address register is used for mapping IPC interrupt register space and sharing a lower computer memory;
the lower computer software runs on the host machine and completes access operation on any position of the upper computer running memory through the shared memory;
the access of the upper computer system to the shared lower computer memory and the interrupt notification between the upper computer system and the lower computer software are completed through the participation of the software simulation PCIE equipment.
The invention has the beneficial effects that:
the invention fully considers the project realizability, simulation degree, performance loss of a simulation system, development workload and other factors of the simulation environment, proposes a mode of simulating PCIE equipment by socket matching with a shared memory and customized software based on a virtual machine, uses the socket to transmit control information, uses a shared memory to simulate the behavior of SRAM and IPC registers (the SRAM is used as the running memory of a lower computer in the simulated system), uses another shared memory to simulate the behavior of DDR (the running memory of an upper computer in the simulated system), uses software based on the virtual machine to simulate the behavior of PCIE bus controllers in the original system (the software based on the virtual machine is used for realizing the mutual addressing between the upper computer system and the lower computer software), perfectly solves the problems of interrupt notification and memory sharing among different systems, and simultaneously can realize seamless combination with the internal software design of a real system at an interface level, thereby greatly reducing software integration and workload and improving software integration efficiency and simulation difficulty and simulation similarity. The method is particularly suitable for software simulation of the hardware interconnection model of the upper computer and the lower computer in the fields of wireless communication and the like, and is used for realizing interrupt notification and data communication among multiple simulation systems under the condition of hardware deficiency.
Drawings
FIG. 1 is a schematic diagram of the overall framework of the software of the present method;
FIG. 2 is a diagram of the upper computer system accessing the lower computer software memory;
FIG. 3 is a schematic diagram of the lower computer software accessing the upper computer running memory;
FIG. 4 is a schematic diagram of the software of the lower computer for notifying the interrupt initiated by the upper computer system;
FIG. 5 is a schematic diagram of a host system for interrupt notification initiated by a host software.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
Example 1
The embodiment discloses an embodiment of a device for simulating communication among multiple systems by software, wherein the device and the systems, modules, software and the like in the device can be in a physical structure at times, can be realized by adopting hardware, can be realized by adopting a virtual structure at times, can be realized by adopting software, can be realized by combining the physical structure with the virtual structure at times, and can be realized by combining the hardware with the software. The device comprises:
the upper computer system operates on the virtual machine, and takes the shared memory of the preassigned host as the upper computer operation memory; a PCIE device driver is operated in the upper computer system;
configuring software running in the virtual machine to simulate PCIE equipment, and finding and driving by a PCIE equipment driver; the software simulation PCIE equipment supports the interrupt of the PCIE equipment and PCIE address addressing, and at least comprises a base address register, wherein the base address register is used for mapping IPC interrupt register space and sharing a lower computer memory;
the lower computer software runs on the host machine and completes access operation on any position of the upper computer running memory through the shared memory;
the access of the upper computer system to the shared lower computer memory and the interrupt notification between the upper computer system and the lower computer software are completed through the participation of the software simulation PCIE equipment.
The framework of the device mainly comprises three parts, namely an upper computer system (comprising an operation memory configured in a shared memory mode), software simulation PCIE equipment and lower computer software (comprising an operation memory configured in a shared memory mode). The entire framework of the software is shown in fig. 1.
The system software structure is described as follows:
1. and the upper computer system. The upper computer system is a complex embedded system (generally linux or other various varieties, such as Openwrt, android) running on the virtual machine, and is a main component of the simulation environment. And taking the shared memory of the pre-allocated host machine as the running memory of the upper computer system (the running memory of the upper computer for short) through the virtual machine starting parameters. Thus, other programs (such as a lower computer system which is simulated and executed as a common application program) running in the host can access any running period data in the running memory of the upper computer through a direct read-write mode of the shared memory. In contrast, the action of accessing the running memory of the lower computer (for short, "shared lower computer memory") or other device memories (such as IPC device registers) actively initiated by the upper computer needs to be completed together by the PCIE device driver and the software simulation PCIE device. The PCIE device driver operates in the upper computer system, and is used for finding and driving software to simulate PCIE devices and complete access operation to the running memory of the lower computer or the memory of other devices in cooperation with the upper computer system. From the perspective of the upper computer, the software simulates PCIE equipment to be a real and complete peripheral equipment. It supports both interruption of PCIE devices and PCIE address addressing.
2. The software simulates PCIE devices. The software simulation PCIE equipment is configured and operated as an internal component of the virtual machine and is mainly responsible for completing access of the upper computer to the memory of the shared lower computer and interrupt notification between the upper computer and the lower computer.
A) And (5) accessing a memory. And the virtual machine completes the creation of the software simulation PCIE equipment and the allocation of resources when being started, and the upper computer system performs discovery and driving after the upper computer system is started. The PCIE device mainly has two base address registers, which are divided into BAR0, BAR1. Wherein BAR0 has no real function in the present method. The main function of the BAR1 is to map IPC interrupt register space and share the memory of the lower computer, so as to realize IPC communication between the upper computer and the lower computer. The actual memory space represented by the base address register of BAR1 is applied by the software simulation PCIE device itself on the host in a shared memory manner. The PCIE device driver of the upper computer maps the first address of the shared memory into the virtual address of the upper computer for access by the upper computer in a memory remapping mode. Through the mapped virtual address, the service program component of the upper computer can complete access operation to the IPC register of the lower computer and the shared memory of the lower computer (other running memories are irrelevant to the running of the upper computer in the simulation environment, so that no access is necessary).
B) Interrupt notification. Interrupt notification between the upper computer system and the lower computer system is also assisted by software simulation of PCIE devices. The specific process of the downlink interrupt notification (initiated by the upper computer and received by the lower computer) is that the software simulates the write-in behavior of the PCIE equipment to the IPC interrupt register by the upper computer, if write-in is detected, the corresponding write-in bit is analyzed and then converted into a predefined message, and the predefined message is sent to the lower computer through a socket channel. The specific process of the uplink interrupt notification (initiated by the lower computer and received by the upper computer) is that the software simulates the PCIE device to receive a predefined message sent by the lower computer software in a socket channel, and then the corresponding processing logic interprets the predefined message as a specific interrupt number and sends a PCIE interrupt notification to the upper computer system.
3. Lower computer software. The lower computer software is a simulation program running on the host machine. The running memory space of the lower computer software is roughly divided into three parts: program code and internally used data structures. The partial memory is the dynamic memory space allocated for the host machine when the simulation program is started. And secondly, partial memory space written by the upper computer system is needed. The part of memory space is the shared lower computer memory created in the software simulation PCIE equipment. Because the memory is in a shared memory form when being created, the memory can be directly accessed by a simulation program serving as a lower computer. Third, the upper computer memory space is needed to be frequently written by the lower computer. Because the upper computer uses the pre-allocated shared memory as the running memory when being started, the lower computer can complete the access operation of any position of the running memory of the upper computer through the shared memory.
The invention builds a simulation environment by matching a socket with a shared memory and simulating PCIE equipment by customized software based on a virtual machine, uses the socket to transmit control information, uses one shared memory to simulate the behavior of SRAM and IPC registers (the SRAM is used as the running memory of a lower computer in a simulated system), uses another shared memory to simulate the behavior of DDR (the shared memory is used as the running memory of an upper computer in the simulated system), uses software based on the virtual machine to simulate the behavior of PCIE bus controllers in an original system (the simulated system is used for realizing the mutual addressing between the upper computer system and the lower computer software), perfectly solves the problems of interrupt notification and memory sharing among different systems, and realizes interrupt notification and data communication among multiple simulated systems under the condition of hardware deficiency. Meanwhile, seamless combination with the software design in a real system can be achieved at the interface level, the software integration difficulty and workload are greatly reduced, and the software and hardware integration efficiency and simulation similarity are improved.
Example 2
The embodiment discloses an embodiment of a method for simulating communication among multiple systems by software, which is shown in fig. 1.
Running lower computer software on a host machine, running an upper computer system on a virtual machine, and internally configuring and running software to simulate PCIE equipment, wherein a PCIE equipment driver is run in the upper computer system and used for finding and driving the software to simulate the PCIE equipment;
taking the shared memory of the preassigned host as the running memory of the upper computer;
the software simulation PCIE equipment supports the interrupt of the PCIE equipment and PCIE address addressing, and at least comprises a base address register, wherein the base address register is used for mapping IPC interrupt register space and sharing a lower computer memory;
the lower computer software completes the access operation of any position of the upper computer operation memory through the shared memory;
the access of the upper computer system to the shared lower computer memory and the interrupt notification between the upper computer system and the lower computer software are completed through the participation of the software simulation PCIE equipment.
The actual memory space of the base address register is applied by the software simulation PCIE equipment on the host computer in a shared memory mode.
The PCIE device driver maps the head address of the shared memory into the virtual address of the upper computer for the upper computer system access in a memory remapping mode.
The main application occasions of the method are as follows:
1. and the access initiated by the upper computer system shares the memory operation of the lower computer. As shown in fig. 2, the three main steps are divided:
11 The upper computer system initiates a read-write access shared lower computer memory operation, wherein the operation carries a virtual address and an operand (value) of the PCIE equipment memory, the write operation comprises the operand, and the read operation has no operand).
12 Software simulation PCIE devices initiate access to shared lower computer memory. When the shared lower computer memory is accessed, a PCIE address conversion unit in the software simulation PCIE equipment converts a memory virtual address of a read-write operation initiated by an upper computer system into an address offset (m is set as an offset in the embodiment) and an operand (n is set as an operand in the embodiment) which take the shared lower computer memory as an object to read and write. According to the data type of the read-write access target of the upper computer system to the PCIE device, the PCIE address conversion unit performs read-write access operations of 1 byte (character), 2 bytes (short integer), 4 bytes (integer) and 8 bytes (long integer) length on the shared lower computer memory respectively.
13 The lower computer software directly uses the standard read-write access mode of the shared memory to execute read-write access operation on the shared lower computer memory.
2. And the lower computer software initiates self-shared memory access operation. The method comprises the following specific steps: and the lower computer directly uses a shared memory standard read-write access mode to execute read-write access operation on the shared lower computer memory.
3. And the operation of accessing the running memory of the upper computer is initiated by the lower computer. The method comprises the following specific steps:
31 The virtual machine takes the pre-allocated shared memory of the host machine as the running memory of the upper computer system by taking the physical base address 0x40000000, and the upper computer system directly performs read-write access. As shown in fig. 3, the host system writes data at the physical address n of the host running memory (in this embodiment, the written data is set to y).
32 The upper computer system writes the value of the physical address n into a specific address of the virtual address of the internal memory of the PCIE equipment in the upper computer system.
33 The software simulates the PCIE device to convert the specific address into a specific address offset (in this embodiment, the offset is set to m) of the shared lower computer memory, and writes the value of the physical address n into the specific address offset of the shared lower computer memory.
34 The lower computer software directly obtains the value of the physical address n by accessing the specific address offset of the shared lower computer memory.
35 The lower computer software obtains the virtual base address of the running memory of the upper computer by using the standard access mode of the shared memory (for example, 0xFF000000 in the embodiment), converts the read physical address N into a virtual address by the following formula (the virtual address after conversion is set as N in the embodiment), and reads the data written by the upper computer system by using the virtual address N (for example, the data written by the upper computer read in the embodiment is y):
virtual address = virtual base address + (physical address-physical base address),
that is, n=0xff 000000+ (N-0 x 40000000).
4. The self-running memory access operation initiated by the host computer system is as described in step 31) above. The virtual machine takes the pre-allocated shared memory of the host machine as the running memory of the upper computer system by using the physical base address 0x40000000, and the upper computer system directly performs read-write access.
An interrupt initiated by the upper computer system notifies the lower computer software operation as shown in fig. 4. The software simulates the write-in behavior of the PCIE equipment to the IPC interrupt register, if the write-in is detected, the corresponding write-in value is converted into a predefined message, and the predefined message is sent to the lower computer software through a socket channel.
The method comprises the following specific steps:
51 The host system converts the interrupt status to be sent to the value x of the interrupt trigger register and writes the value to the host-to-lower interrupt trigger register using the mapped host-to-lower interrupt trigger register virtual address.
52 The software simulates the behavior that the PCIE device captures the interrupt trigger register from the upper computer to the lower computer, writes the value into the interrupt trigger register from the upper computer to the lower computer, converts the virtual address of the interrupt trigger register from the upper computer to the lower computer into a specific address offset (m is set as the offset in the embodiment) for accessing the interrupt trigger register from the upper computer to the lower computer in the IPC register, and obtains the interrupt trigger register address from the upper computer to the lower computer in the shared memory according to the offset m. And writing the value x of the interrupt trigger register into the interrupt trigger register from the upper computer to the lower computer in the shared memory.
53 The software simulation PCIE equipment monitors that the value x stored in the interrupt trigger register from the upper computer to the lower computer in the shared memory changes, converts the written value x into a predefined message, and sends the predefined message to the lower computer software through a Socket channel. After the lower computer software analyzes the predefined message received by the Socket, the message is converted into an interrupt state, so that the process of notifying the lower computer of the interrupt initiated by the upper computer is realized, and the corresponding service is completed.
6. An interrupt initiated by the lower computer notifies the upper computer of the system operation, as shown in fig. 5. The software simulation PCIE equipment receives a predefined message sent by the lower computer software in a socket channel, analyzes the predefined message into a corresponding interrupt signal, and initiates a PCIE interrupt to inform an upper computer system.
The method comprises the following specific steps:
61 The lower computer software converts the interrupt state to be sent into the value y of the interrupt register, and writes the value into the interrupt trigger register of the lower computer to the upper computer directly through the access mode of the shared memory.
62 The lower computer software sends the predefined message to the software simulation PCIE equipment through a Socket channel, wherein the message does not contain an interrupt state.
63 The software simulates PCIE equipment to analyze the predefined message received by the Socket channel and send a corresponding interrupt signal to the upper computer system.
64 The upper computer system receives the interrupt signal sent by the software simulation PICE equipment and directly reads the interrupt trigger register from the lower computer to the upper computer in the internal virtual address of the PCIE equipment of the upper computer system.
65 Software simulation PCIE device translates the interrupt register virtual address into a specific address offset (in this embodiment, offset is set to n) for accessing the lower to upper interrupt trigger registers in the IPC register. And sending the value y of the interrupt trigger register from the lower computer to the upper computer system. And the upper computer system converts the read value y into an interrupt state and completes corresponding service.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. A method for simulating communication among multiple systems by software is characterized in that,
running lower computer software on a host machine, running an upper computer system on a virtual machine, and internally configuring and running software to simulate PCIE equipment, wherein a PCIE equipment driver is run in the upper computer system and used for finding and driving the software to simulate the PCIE equipment;
taking the shared memory of the preassigned host as the running memory of the upper computer;
the software simulation PCIE equipment supports the interrupt of the PCIE equipment and PCIE address addressing, and at least comprises a base address register, wherein the base address register is used for mapping IPC interrupt register space and sharing a lower computer memory;
the lower computer software completes the access operation of any position of the upper computer operation memory through the shared memory;
the access of the upper computer system to the shared lower computer memory and the interrupt notification between the upper computer system and the lower computer software are completed through the participation of the software simulation PCIE equipment.
2. The method of claim 1, wherein the actual memory space of the base address register is applied for by the software emulation PCIE device itself on the host in a shared memory manner.
3. The method of claim 1 wherein the PCIE device driver maps the first address of the shared memory to a virtual address of the upper computer for access by the upper computer system by means of memory remapping.
4. The method for simulating multi-system communication by software according to claim 1, wherein the step of accessing the shared lower computer memory initiated by the upper computer system comprises the steps of:
11 The upper computer system carries a PCIE equipment memory virtual address and an operand value to initiate read-write access to the shared lower computer memory;
12 The PCIE address conversion unit in the software simulation PCIE equipment converts the memory virtual address carried by the upper computer system into an address offset and an operand which are used for sharing the memory of the lower computer as objects to read and write; according to the data type of the read-write access target of the upper computer system to the PCIE equipment, the PCIE address conversion unit executes the read-write access operation of the corresponding byte length to the shared lower computer memory;
13 The lower computer software adopts a shared memory standard read-write access mode to carry out read-write access on the shared lower computer memory.
5. A method of software emulation intersystem communication as claimed in claim 1, wherein,
the method for accessing the shared lower computer memory initiated by the lower computer comprises the following steps: and the lower computer software performs read-write access on the shared lower computer memory by adopting a shared memory standard read-write access mode.
6. The method for simulating multi-system communication by software according to claim 1, wherein the step of accessing the upper computer running memory initiated by the lower computer software comprises the steps of:
31 The upper computer system directly writes data at the physical address of the upper computer running memory;
32 The upper computer system writes the value of the physical address into a specific address of the virtual address of the internal memory of the PCIE equipment in the upper computer;
33 Software simulation PCIE equipment converts the specific address into a specific address offset of the shared lower computer memory, and writes the value of the physical address into the specific address offset of the shared lower computer memory;
34 The lower computer software directly obtains the value of the physical address by accessing the specific address offset of the shared lower computer memory;
35 The lower computer software obtains the virtual base address of the running memory of the upper computer by adopting a shared memory standard access mode, converts the read physical address into a virtual address, and reads the data written by the upper computer system by using the virtual address.
7. A method of software emulation intersystem communication as claimed in claim 1, wherein,
the method for operating the memory access of the upper computer initiated by the upper computer system comprises the following steps: the upper computer system directly writes data at the physical address of the upper computer running memory.
8. A method of software emulation intersystem communication as claimed in claim 1, wherein,
the step of the interrupt initiated by the upper computer system to inform the lower computer software is as follows: the software simulates the write-in behavior of the PCIE equipment to the IPC interrupt register, if the write-in is detected, the corresponding write-in value is converted into a predefined message, and the predefined message is sent to the lower computer software through a socket channel.
9. A method of software emulation intersystem communication as claimed in claim 1, wherein,
the step of the interrupt notification upper computer system initiated by the lower computer software is as follows: the software simulation PCIE equipment receives a predefined message sent by the lower computer software in a socket channel, analyzes the predefined message into a corresponding interrupt signal, and initiates a PCIE interrupt to inform an upper computer system.
10. An apparatus for software emulation of multi-system communication, comprising:
the upper computer system operates on the virtual machine, and takes the shared memory of the preassigned host as the upper computer operation memory; a PCIE device driver is operated in the upper computer system;
configuring software running in the virtual machine to simulate PCIE equipment, and finding and driving by a PCIE equipment driver; the software simulation PCIE equipment supports the interrupt of the PCIE equipment and PCIE address addressing, and at least comprises a base address register, wherein the base address register is used for mapping IPC interrupt register space and sharing a lower computer memory;
the lower computer software runs on the host machine and completes access operation on any position of the upper computer running memory through the shared memory;
the access of the upper computer system to the shared lower computer memory and the interrupt notification between the upper computer system and the lower computer software are completed through the participation of the software simulation PCIE equipment.
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| CN117411842A (en) * | 2023-12-13 | 2024-01-16 | 苏州元脑智能科技有限公司 | Event suppression method, device, equipment, heterogeneous platform and storage medium |
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| CN106874128A (en) * | 2017-01-22 | 2017-06-20 | 广州华多网络科技有限公司 | Data transmission method and device |
| CN107346260A (en) * | 2017-06-29 | 2017-11-14 | 郑州云海信息技术有限公司 | A kind of data transmission method, apparatus and system |
| CN113778611A (en) * | 2021-07-06 | 2021-12-10 | 锐捷网络(苏州)有限公司 | Data transmission method, device, system and storage medium |
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| CN106874128A (en) * | 2017-01-22 | 2017-06-20 | 广州华多网络科技有限公司 | Data transmission method and device |
| CN107346260A (en) * | 2017-06-29 | 2017-11-14 | 郑州云海信息技术有限公司 | A kind of data transmission method, apparatus and system |
| CN113778611A (en) * | 2021-07-06 | 2021-12-10 | 锐捷网络(苏州)有限公司 | Data transmission method, device, system and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117411842A (en) * | 2023-12-13 | 2024-01-16 | 苏州元脑智能科技有限公司 | Event suppression method, device, equipment, heterogeneous platform and storage medium |
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