CN116389655A

CN116389655A - Signal transmission method and device and electronic equipment

Info

Publication number: CN116389655A
Application number: CN202310449905.6A
Authority: CN
Inventors: 王尹
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2023-04-24
Filing date: 2023-04-24
Publication date: 2023-07-04

Abstract

A signal transmission method, a signal transmission device and an electronic device. The method comprises the following steps: acquiring a source signal, wherein the source signal at least comprises an image data signal; periodically generating a target line synchronization signal for indicating the start of transmission of a line of image data signals; generating a target field synchronizing signal based on the target line synchronizing signal, wherein the target field synchronizing signal is used for indicating the start of transmitting a frame of image data signal, the effective jump edge of the target field synchronizing signal is synchronous with the effective jump edge of the target line synchronizing signal, and the time length of the effective level of the target field synchronizing signal is m times of the period length of the target line synchronizing signal; providing a target line synchronizing signal and a target field synchronizing signal; and providing an image data signal to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal. The method can reduce design complexity and logic resources.

Description

Signal transmission method and device and electronic equipment

Technical Field

The embodiment of the disclosure relates to a signal transmission method, a signal transmission device and electronic equipment.

Background

In the field of image signal processing, since the amount of data in an image is large, algorithms involved are large, and real-time performance is required, a hardware circuit is often used for image signal processing. The image sensor typically transmits pixel values (pixels) of image data point by point and line by line to a back-end device (e.g., an image signal processing apparatus) which performs image signal processing.

Disclosure of Invention

At least one embodiment of the present disclosure provides a signal transmission method applied to a first image signal processing module, the method including: acquiring a source signal, wherein the source signal at least comprises an image data signal; generating a target line synchronization signal, which is a periodic signal and is used to indicate the start of transmission of a line of image data signals; generating a target field synchronizing signal based on the target line synchronizing signal, wherein the target field synchronizing signal is used for indicating the start of transmitting a frame of image data signal, the jump edge of the target field synchronizing signal is synchronous with the effective jump edge of the target line synchronizing signal, the time length of the effective level of the target field synchronizing signal is m times of the period length of the target line synchronizing signal, and m is a positive integer; providing the target line synchronization signal and the target field synchronization signal to the second image signal processing module; and providing the image data signal to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal.

For example, in a signal transmission method provided in an embodiment of the present disclosure, a source signal includes a source field synchronization signal, and generating the target field synchronization signal based on the target line synchronization signal includes: and under the condition that the first image processing module carries out k line delay on the image data signal, carrying out k line delay on the source field synchronous signal based on the target line synchronous signal to obtain the target field synchronous signal, wherein k is a positive integer.

For example, in the signal transmission method provided in an embodiment of the present disclosure, based on the target line synchronization signal, performing k line delay on the source field synchronization signal to obtain the target field synchronization signal includes: carrying out one clock period delay on the source field synchronous signal to obtain a beat delay field synchronous signal; and sampling the k-1 line delay target field synchronizing signal at the effective jump edge of the target line synchronizing signal to obtain the k line delay target field synchronizing signal, wherein the 0 line delay field synchronizing signal is the beat delay field synchronizing signal.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the source signal includes a source field synchronization signal and a source line synchronization signal, and the periodically generating the target line synchronization signal includes: under the condition that the first image signal processing module carries out pixel-level delay on the image data signal, carrying out pixel-level delay on the source line synchronous signal to obtain the target line synchronous signal; generating a target field sync signal based on the target row sync signal, comprising: and sampling a source field synchronizing signal at the effective jump edge of the target line synchronizing signal to obtain the target field synchronizing signal.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the method further includes: and providing a target data valid signal to the second image signal processing module, wherein the target data valid signal is used for indicating whether the image data signal is valid or not.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the method further includes: providing a target field effective signal to the second image signal processing module based on the target line synchronous signal, wherein an effective jump edge and an ineffective jump edge of the target field effective signal are respectively aligned with two effective jump edges of the target line synchronous signal; and periodically providing a row valid signal, the row valid signal and the target data valid signal being identical during an active level of the target field valid signal in the case that the target data valid signal is continuous.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the source signal further includes a source field effective signal, and the providing the target field effective signal to the second image signal processing module includes: and under the condition that the first image signal processing module carries out k line delay on the image data signals, carrying out k line delay on the source field effective signals to obtain the target field effective signals, wherein k is a positive integer.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the source data signal further includes a source field effective signal, and performing k line delay on the source field effective signal based on the target line synchronization signal to obtain the target field effective signal includes: performing one clock period delay on the source field effective signal to obtain a beat delay field effective signal; and sampling the k-1 line delay field effective signal at the effective jump edge of the target line synchronous signal to obtain the target field effective signal with k line delay, wherein the 0 line delay field effective signal is the beat delay field effective signal.

For example, in the signal transmission method provided in an embodiment of the present disclosure, providing the target data valid signal to the second image signal processing module includes: and performing AND operation on the target field effective signal and the row effective signal to obtain the target data effective signal.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the method further includes: in response to receiving an effective image data signal, performing an AND operation on the non-sum i-1 th row delay field effective signal of the i row delay field effective signal to obtain a first operation result, wherein i is a positive integer; and responding to the first operation result being equal to 1, wherein the effective image data signal is the image data signal of the ith row.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the method further includes: responding to receiving effective image data signals, performing AND operation on the non-sum of j pixel-level delay line effective signals and the j-1 pixel-level delay line effective signals to obtain a second operation result, wherein j is a positive integer; and responding to the second operation result being equal to 1, wherein the effective image data signal is the image data signal of the j-th column.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the source signal includes a source line synchronization signal, and periodically generating the target line synchronization signal includes: and recovering the jump edge of the source line synchronizing signal in the intermittent period to obtain the target line synchronizing signal under the condition that the source line synchronizing signal is intermittent between the jump edge of the last line of the first frame and the jump edge of the first line of the second frame.

For example, in the signal transmission method provided in an embodiment of the present disclosure, the method further includes: acquiring a switch indication signal; and judging whether the break exists between the effective jump edge of the last line of the first frame and the effective jump edge of the first line of the second frame of the source line synchronous signal according to the switch indication signal.

At least one embodiment of the present disclosure provides a signal transmission apparatus applied to a first image signal processing module, the apparatus including: a fetching unit configured to acquire a source signal including at least an image data signal; a line synchronization signal generation unit configured to periodically generate a target line synchronization signal for indicating the start of transmission of a line of image data signals; a field synchronizing signal generating unit configured to generate a target field synchronizing signal for indicating the start of transmission of one frame of image data signal based on the target line synchronizing signal, wherein an effective transition edge of the target field synchronizing signal is synchronized with an effective transition edge of the target line synchronizing signal, and a time length of an effective level of the target field synchronizing signal is m times a period length of the target line synchronizing signal, and m is a positive integer; a first transmitting unit configured to provide the target line synchronization signal and the target field synchronization signal to the second image signal processing module; and a second transmitting unit configured to supply the image data signal to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal.

At least one embodiment of the present disclosure provides an electronic device, including a first image signal processing module, including a signal transmission apparatus provided in any one embodiment of the present disclosure; and a second image signal processing module coupled to the first image signal processing module to receive the target line synchronization signal, the target field synchronization signal, and the image data signal provided by the first image signal processing module.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIGS. 1A and 1B show timing diagrams of two video stream bus interface signals;

FIG. 2 illustrates a system architecture diagram for applying a signal processing method provided by at least one embodiment of the present disclosure;

FIG. 3A illustrates a flow chart of a signal transmission method provided by at least one embodiment of the present disclosure;

FIG. 3B illustrates a timing diagram of a VBUS video stream bus signal provided by at least one embodiment of the present disclosure;

FIG. 3C illustrates a flow chart of another signal transmission method provided by at least one embodiment of the present disclosure;

FIG. 4A is a flow chart illustrating a method for k-line delay of a source field sync signal to obtain a target field sync signal according to at least one embodiment of the present disclosure;

FIG. 4B is a timing diagram of a source field sync signal with k line delays to obtain a target field sync signal according to at least one embodiment of the present disclosure;

FIG. 5 illustrates a timing diagram for k-line delay of a VBUS video stream bus signal provided by at least one embodiment of the present disclosure;

FIG. 6 shows a timing diagram after a line delay of an image data signal in the case where the line synchronization signal is discontinuous;

fig. 7 shows a schematic block diagram of a signal transmission apparatus provided by at least one embodiment of the present disclosure; and

fig. 8 illustrates a schematic diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The image sensor generally transmits pixel values of image data to the back-end device point by point and line by line, and according to the characteristic, each manufacturer can summarize a set of own video stream interface specifications, when the pipeline (pipeline) processes images, the image processing module interfaces are unified according to the video stream interface specifications, and the image processing module interfaces written by different engineers are unified, so that understanding is convenient, and more importantly, the system compatibility is good, and system integration is easy.

Because the video stream bus interface between the digital circuit internal modules does not have a unified standard, each manufacturer defines a set of own standards according to practicality. Each custom video stream bus has its own advantages and disadvantages, imperfect bus definition may increase design complexity and even logic resources.

Fig. 1A and 1B show timing diagrams of two video stream bus interface signals.

As shown in fig. 1A and 1B, the video stream bus interface often includes a field sync signal Vsync, a line sync signal Hsync, and a Valid (Valid) signal. The field sync signal Vsync is for indicating the start of one frame of image data, and the line sync signal Hsync is for indicating the start of one line of image data. The Valid signal is active during the high period.

The timing diagrams of the two video stream bus interface signals are simple and clear, but have a lot of troubles in actual use. For example, in the image signal processing process, it is often necessary to determine the first or last lines of the image, and under the signal conditions described above, it is often determined by a counter, which introduces additional parameter registers and counter logic. For another example, the algorithms involved in the image signal processing are more, a large number of algorithms have a line delay requirement, and if the line delay required is large or the line delay of the requirement is too small, the image data of the previous frame may enter the field synchronizing signal of the image of the next frame, which may cause problems in image processing. This requires image processing such that the field sync signal remains synchronized with the delay. Storing the field sync signal, the line sync signal and the image data signal together into the buffer memory can delay the synchronization of the field sync signal and the line sync signal, but the field sync signal and the line sync signal are unchanged in most of the time, which causes waste of memory resources; or the field sync signal and the row sync signal are regenerated by a counter, which results in an increase in design complexity. As another example, during image signal processing, if a line delay is encountered, it is difficult to generate a new line signal, and a counter is also required to generate the line signal according to the bus interface signal.

Thus, the video stream bus increases the complexity of the design, and as the complexity of the design increases, the design risk increases.

At least one embodiment of the present disclosure provides a signal transmission method, a signal transmission device and an electronic device. The signal transmission method is applied to the first image signal processing module to provide signals to the second image signal processing module. The method comprises the following steps: acquiring a source signal, wherein the source signal at least comprises an image data signal; generating a target line synchronization signal which is a periodic signal and is used for indicating the start of transmitting a line of image data signals; generating a target field synchronizing signal based on the target line synchronizing signal, wherein the target field synchronizing signal is used for indicating the start of transmitting a frame of image data signal, the jump edge of the target field synchronizing signal is synchronous with the effective jump edge of the target line synchronizing signal, the time length of the effective level of the target field synchronizing signal is m times of the period length of the target line synchronizing signal, and m is a positive integer; providing a target line synchronization signal and a target field synchronization signal to a second image signal processing module; and providing an image data signal to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal. The embodiment of the disclosure provides a custom video stream bus which can realize the unification of video stream interfaces of different image signal processing sub-modules, has good compatibility among different sub-modules and is convenient for system integration; and the bus is easy to understand aiming at the characteristic of realizing image signal processing of hardware logic, and reduces design complexity and logic resources to a certain extent.

Fig. 2 illustrates a system architecture diagram for applying a signal processing method according to at least one embodiment of the present disclosure.

As shown in fig. 2, an image sensor 110 and an image signal processing device 120 are included in the system architecture.

The image sensor 110 is used to acquire image data and to provide a data signal including the image data to the image signal processing device 120 in response to a driving signal of the image signal processing device 120. The image sensor 110 may be, for example, a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensor, a charge coupled device (charge coupled device, CCD) image sensor, or the like.

The image signal processing apparatus 120 includes a signal receiving and converting module 121 and an image signal processing module 122.

The signal receiving and converting module 121 is configured to receive the data signal provided by the image sensor 110, and convert the data signal into a video stream signal provided by at least one embodiment of the present disclosure, and provide the video stream bus signal to the image signal processing module 122 through the video stream signal bus provided by the at least one embodiment of the present disclosure. Hereinafter, the video stream signal provided by the embodiment of the present disclosure is referred to as a VBUS video stream bus signal, and the video stream signal bus provided by the embodiment of the present disclosure is referred to as a VBUS video stream bus.

The image signal processing module 122 may include at least one image signal processing sub-module. In the example of fig. 2, the image signal processing module 122 shows two image signal processing sub-modules 1221 and 1222, but in practical applications, the image signal processing module 122 may include more than 2 or less than 2 image signal processing sub-modules.

Each image signal processing sub-module processes the image data separately. For example, the image signal processing sub-module 1221 may be for filtering image data, the image signal processing sub-module 1222 may be for sharpening image data, or the like.

For example, the image signal processing sub-module 1221 needs to delay the VBUS signal supplied from the signal receiving and converting module 121 when filtering the image data, and then supplies the VBUS signal to the image processing sub-module 1222.

The video stream signals transmitted among the plurality of image processing sub-modules included in the image signal processing module 122 are VBUS video stream signals, so that unification of video stream interfaces of different image signal processing sub-modules can be realized, compatibility among different sub-modules is good, and system integration is facilitated; the VBUS video stream bus is used for realizing image signal processing aiming at hardware logic, and is easy to understand, so that design complexity and logic resources are reduced to a certain extent.

Fig. 3A illustrates a flow chart of a signal transmission method provided by at least one embodiment of the present disclosure.

The signal transmission method is applied to the first image signal processing module to provide signals to the second image signal processing module. The first image signal processing module may be, for example, the signal receiving and converting module 121 in fig. 2, and the second image signal processing module may be any one of the image signal processing modules 122 coupled to the signal receiving and converting module, for example, the second image signal processing module is the image signal processing sub-module 1221. The first image signal processing module may be, for example, the image signal processing sub-module 1221 in fig. 2, and the second image signal processing module may be any one of the image signal processing modules 122 coupled to the image signal processing sub-module 1221, for example, the second image signal processing module is the image signal processing sub-module 1222. That is, the first image signal processing module and the second image signal processing module are sub-modules coupled to any two of the image signal processing devices 120, respectively, or any one of the first image signal processing module and the second image signal processing module coupled to the image sensor 110 and a module or sub-module coupled to the signal receiving and converting module, respectively.

As shown in fig. 3A, the signal transmission method includes steps S301 to S305.

Step S301: a source signal is acquired, the source signal including at least an image data signal.

Step S302: a target line synchronization signal is generated, the target line synchronization signal being a periodic signal and indicating the start of transmission of a line of image data signals.

Step S303: and generating a target field synchronizing signal based on the target line synchronizing signal, wherein the target field synchronizing signal is used for indicating the start of transmitting a frame of image data signal, the jump edge of the target field synchronizing signal is synchronous with the effective jump edge of the target line synchronizing signal, the time length of the effective level of the target field synchronizing signal is m times of the period length of the target line synchronizing signal, and m is a positive integer.

Step S304: the target line synchronization signal and the target field synchronization signal are supplied to the second image signal processing module.

Step S305: the image data signal is provided to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal.

It should be noted that, in the embodiments of the present disclosure, "first", "second", and the like are merely for distinguishing between different signals, and do not represent a sequence number. For example, the target field sync signal is essentially a field sync signal, only to distinguish from, for example, a beat delay sync signal, hereinafter.

According to the signal transmission method, the target line synchronizing signal is a periodic signal, the jump edge of the target field synchronizing signal is synchronous with the effective jump edge of the target line synchronizing signal, the time length of the effective level of the target field synchronizing signal is m times of the period length of the target line synchronizing signal, so that under the condition that the image data is subjected to line delay, the field synchronizing signal can carry out the same line delay based on the relationship between the field synchronizing signal and the line synchronizing signal, and the line delay can be carried out on the field synchronizing signal without a counter.

For step S301, for example, the first image signal processing module is the signal receiving and converting module 121 in fig. 2, the second image signal processing module is the image signal processing sub-module 1221, and the source signal is, for example, a data signal provided by the image sensor 110. For another example, the first image signal processing module is the image signal processing sub-module 1221 in fig. 2, the second image signal processing module is the image signal processing sub-module 1222, and the source signal may be the VBUS video stream bus signal provided by the signal receiving and converting module 121, or the VBUS video stream bus signal provided by other sub-modules in the image signal processing apparatus 120. In the embodiment of the present disclosure, the signal output by any one of the modules or sub-modules of the image signal processing apparatus 120 meets the specification of the VBUS video stream bus signal. The source signal may be a VBUS video stream bus signal or a signal compliant with a sensor interface provided by an image sensor coupled to the image signal processing device 120.

The source signal includes an image data signal including image data acquired by the image sensor 110. The source signal may include a field sync signal, a line sync signal, a valid signal, etc., in addition to the image data signal.

If the source signal is provided by the image sensor 110, the source signal conforms to the signal transfer interface protocol of the image sensor 110. If the source signal is provided by a module or sub-module in the image signal processing apparatus 120, the source signal conforms to the VBUS video stream bus interface protocol, i.e., the source signal is the VBUS video stream bus signal provided by an embodiment of the present disclosure.

Step S302 and step S303 are described below with reference to fig. 3B. Fig. 3B illustrates a timing diagram of a VBUS video stream bus signal provided by at least one embodiment of the present disclosure.

As shown in fig. 3B, the VBUS video stream bus signal includes a line synchronization signal hsync and a field synchronization signal vsync. The line synchronization signal hsync is an example of a target line synchronization signal, and the field synchronization signal vsync is an example of a target field synchronization signal.

As shown in fig. 3B, the line synchronization signal hsync is periodically generated, i.e., the line synchronization signal hsync is a periodic signal. The active level duration of the line synchronization signal hsync is M clock cycles, for example, 1 clock cycle of the clock signal clk, and M is an integer greater than or equal to 1.

As shown in fig. 3B, the transition edge of the field sync signal vsync includes a rising edge B1 and a falling edge B2. In some embodiments of the present disclosure, the changes in both the rising edge b1 and the falling edge b2 remain synchronized with the rising edge of the row synchronization signal hsync. For example, at the rising edge of the row synchronizing signal hsync, the field synchronizing signal vsync becomes high level; at the rising edge of the next row synchronization signal hsync, the field synchronization signal vsync becomes low level.

The active level of the field sync signal vsync is, for example, a high level, and the time length of the active level is the time length between the rising edge and the falling edge of the field sync signal vsync in the same period.

For example, the time length T1 of the active level is m times the period length of the target line synchronization signal, that is, m times the time required for transmitting one line of image data, m being an integer greater than or equal to 1, for example, in the example of fig. 3B, m=1. That is, when the rising edge of the row synchronization signal hsync is generated, the field synchronization signal vsync goes high, and continues to be pulled low until the rising edge of the next row synchronization signal hsync.

For step S304, a line synchronization signal hsync and a field synchronization signal vsync are supplied to the second image signal processing module, for example.

For step S305, the image data signal is supplied to the second image signal processing module, for example, in accordance with the timing of the line synchronization signal hsync and the field synchronization signal vsync. For example, the image data signal is supplied to the second image signal processing module in a timing relationship with the line synchronization signal hsync and the field synchronization signal vsync, respectively, as shown in fig. 3B. For example, after each transition of the Line synchronization signal hsync (i.e., after an active level), transmission of a Line of image data signals starts, for example, after transition Q, transmission of image data Line0 of Line 1 starts.

In other embodiments of the present disclosure, the VBUS video stream bus signal includes a data valid signal in addition to a field sync signal, a line sync signal, and an image data signal.

In the embodiments of the present disclosure, the active level is a high level, and the inactive level is a low level, for example, but this has no limiting effect on the present disclosure. In some other embodiments, the active level may be low, and the inactive level may be high.

Fig. 3C illustrates a flow chart of another signal transmission method provided by at least one embodiment of the present disclosure.

As shown in fig. 3C, the signal transmission method includes step S306 in addition to transmission steps S301 to S305 (not shown) shown in fig. 3A.

Step S306: the second image signal processing module is provided with a target data valid signal for indicating whether the image data signal is valid.

The target data valid signal is, for example, a data valid signal den shown in fig. 3B. The data valid signal den is an identifier that the image data is valid. As shown in fig. 3B, when the data valid signal den is at a valid level (e.g., high level), the Line image data Line0 to Line are transmitted; when the data valid signal den is at an invalid level (e.g., low level), the signal line transmitting the line image data transmits the invalid data.

In other embodiments of the present disclosure, the VBUS video stream bus signal includes a field-active signal and a line-active signal in addition to a field-sync signal, a line-sync signal, an image data signal, and a data-active signal.

As shown in fig. 3C, the transmission method includes steps S307 to S308 in addition to steps S301 to S306 (not shown).

Step S307: and providing a target field effective signal to the second image signal processing module, wherein the effective transition edge and the ineffective transition edge of the target field effective signal are aligned with the two effective transition edges of the target line synchronous signal respectively.

Step S308: the line valid signal is periodically supplied, and in the case where the target data valid signal is continuous, the line valid signal coincides with the target data valid signal during the active level of the target field valid signal.

For step S307, as shown in fig. 3B, for example, a field effective signal vact (an example of a target field effective signal) is supplied to the second image signal processing module.

In some embodiments of the present disclosure, the high level is an active signal, the low level is an inactive signal, the active transition edge is a rising edge, and the inactive transition edge is a falling edge.

For example, the two active transitions of the line synchronization signal are respectively a rising edge corresponding to the start of the active line of the frame data and a rising edge corresponding to the end of the active line of the frame data. The frame data valid Line refers to a valid Line of one frame of image data, and the frame data valid Line is, for example, a first Line of image data transmitted first among a plurality of lines of image data included in one frame of image data, for example, line0 in fig. 3B is the first Line of image data. The end of a valid line of frame data refers to, for example, the nth line of image data transmitted last among a plurality of lines of image data included in one frame of image data.

The active transition edge P1 of the field active signal vact is synchronized with the rising edge of the Line synchronizing signal hsync (i.e., the rising edge in transition Q1) corresponding to the first Line image data Line 0. The invalid transition edge P2 of the field valid signal vact is synchronized with the first valid transition edge q2 after the valid transition edge q1 of the row synchronizing signal hsync corresponding to the nth row image data. That is, in some embodiments of the present disclosure, the field valid signal vact is similar to the field sync signal vsync, and both the rising and falling edge changes of the field valid signal vact remain synchronized with the valid transition edge of the row sync signal hsync. At the beginning of the frame data valid line and when the rising edge of the line synchronization signal hsync is generated, the field valid signal vact becomes high level, and the rising edge of the line synchronization signal hsync is pulled low until the end of the frame valid line.

When processing image signals using hardware circuitry, there is often a significant amount of line delay due to the need for algorithms. As algorithms increase, the accumulated line delay may span the field sync signal of the original image video stream, which may cause anomalies in image processing. Thus, in dealing with such problems, it is necessary to complete the synchronization delay of the corresponding field signals within, for example, the image signal processing sub-module. The delay of the field synchronization signal vsync can be accomplished very simply by using the VBUS video stream bus. Therefore, step S303 includes, in the case where the first image processing module performs k line delays on the image data signal, performing k line delays on the source field synchronization signal based on the target line synchronization signal to obtain the target field synchronization signal, where k is a positive integer, and the source field synchronization signal is a signal in the source signal.

For example, the first image signal processing module is the image signal processing sub-module 1221 in fig. 2, the second image signal processing module is the image signal processing sub-module 1222 in fig. 2, and the source signal is the VBUS video stream bus signal provided by the signal receiving and converting module 121. The source field sync signal is a field sync signal in the source signal. Hereinafter, taking the source signal as the VBUS video stream bus signal provided by the signal receiving and converting module 121, the first image signal processing module is the image signal processing sub-module 1221 in fig. 2, and the second image signal processing module is the image signal processing sub-module 1222 in fig. 2 as an example to illustrate an embodiment of the disclosure.

If the image signal processing sub-module 1221 performs k line delays on the image data signal during the filtering process on the image data, the image signal processing sub-module 1221 needs to perform k line delays on the source field synchronization signal to obtain the target field synchronization signal.

Fig. 4A is a flowchart illustrating a method for performing k-line delay on a source field synchronization signal to obtain a target field synchronization signal according to at least one embodiment of the present disclosure. Fig. 4B is a timing diagram illustrating performing k-line delay on a source field synchronization signal to obtain a target field synchronization signal according to at least one embodiment of the present disclosure.

As shown in fig. 4A, the method includes steps S401 to S402.

Step S401: and delaying the source field synchronous signal for one clock period to obtain the beat delay field synchronous signal.

Step S402: and sampling the field synchronizing signal with k-1 line delay at the effective jump edge of the target line synchronizing signal to obtain the target field synchronizing signal with k line delay, wherein the 0 line delay field synchronizing signal is a beat delay field synchronizing signal.

For step S401, as shown in fig. 4B, the source field synchronization signal is vsync ', and the source field synchronization signal is vsync ' is delayed by one clock period to obtain a beat delayed field synchronization signal vsync ' _d.

For step S402, for example, the active transition edge of the line synchronization signal hsync samples the 0-line-delay field synchronization signal vsync ' _d to obtain the 1-line-delay field synchronization signal vsync ' _ld1, where the 0-line-delay field synchronization signal is the beat-delay field synchronization signal vsync ' _d. For example, the active transition edge of the line sync signal hsync samples the 1-line-delayed field sync signal vsync '_ld1 to obtain the 2-line-delayed field sync signal vsync' _ld2. And the target field synchronous signal with any line delay is obtained by the pushing.

As shown in fig. 4B, if the active transition edge of the row synchronization signal hsync is sampled to obtain a first level (e.g., a high level), the k-row delayed field synchronization signal transitions to the first level at the next active transition edge of the clock signal, and if the active transition edge of the row synchronization signal hsync is sampled to obtain a second level (e.g., a low level), the k-row delayed field synchronization signal transitions to the second level at the next active transition edge of the clock signal.

For example, in the process of filtering the image data signal by the image signal processing sub-module 1221, i line delays are performed on the image data signal, so that i line delays are performed on the source field synchronization signal vsync ' in the image signal processing sub-module 1221 in the method described in fig. 4A and fig. 4B to obtain a field synchronization signal vsync ' _ ldi (for example, i=1, 2 …), where the field synchronization signal vsync ' _ ldi is output as a target field synchronization signal (i.e., the field synchronization signal vsync in fig. 3B), and the target field synchronization signal output by the image signal processing sub-module 1221 is denoted by different marks in fig. 4B only for distinguishing the line delays. In practice, the VBUS video stream bus signal output by the image signal processing sub-module 1221 conforms to the characteristics described in fig. 3A and 3B, no matter how many lines of line delay are performed on the source field sync signal.

In the case where the image data signal has only a line delay, since the transition of the line synchronization signal is generated corresponding to each line of the image data, the line delay of the line synchronization signal is not required. Therefore, the line delay signal after the image data signal is line-delayed coincides with the line synchronization signal in the source signal.

Therefore, the VBUS video stream bus signal provided by the embodiment of the disclosure can obtain the k-line delay target field synchronous signal by sampling the k-1 line delay field synchronous signal at the effective jump edge of the line synchronous signal hsync, and the line delay of any line can be carried out on the field synchronous signal without a counter, so that the VBUS video stream bus signal is easy to realize.

If the source signal includes signals other than the line synchronizing signal, the field synchronizing signal, and the image data signal, the image data signal and the field synchronizing signal are subjected to line-level delay, and the other signals are subjected to corresponding line-level delay.

In some image signal processing processes, pixel-level delay is required for the image data signal, and pixel-level delay is required for the line synchronization signal and the field synchronization signal.

For example, the source signal includes a source field sync signal and a source row sync signal, and the target row sync signal is periodically generated, including: under the condition that the first image signal processing module carries out pixel-level delay on the image data signal, carrying out pixel-level delay on the source line synchronizing signal to obtain a target line synchronizing signal; and generating a target field synchronizing signal based on the target line synchronizing signal, wherein the target field synchronizing signal is obtained by sampling the source field synchronizing signal at the effective jump edge of the target line synchronizing signal.

For example, in the case where the image signal processing sub-module 1221 performs pixel-level delay on the image data signal, the source line synchronization signal is subjected to pixel-level delay to obtain the line synchronization signal hsync. For example, the pixel data of 1 pixel requires y clock cycles, and if the image data signal is delayed by 5 pixels, the source line synchronization signal is delayed by (5×y) clock cycles, and y is an integer of 1 or more.

The active transition edge of the row sync signal hsync samples a source field sync signal (e.g., a field sync signal vsync') to obtain a target field sync signal.

If the source signal comprises a source field valid signal, then k line delays are required for the source field valid signal if k line delays are to be performed for the image data signal. Providing a target field effective signal to a second image signal processing module based on the target line synchronization signal, comprising: under the condition that the first image signal processing module carries out k line delay on the image data signal, carrying out k line delay on the source field effective signal based on the target line synchronous signal to obtain the target field effective signal, wherein k is a positive integer.

In some embodiments of the present disclosure, the method of k-line-delaying the field-effect signal based on the line synchronization signal is similar to the method of k-line-delaying the field-effect signal based on the line synchronization signal. For example, the source field effective signal is delayed by one clock period to obtain a beat delay field effective signal; and sampling the k-1 line delay field effective signal at the effective jump edge of the target line synchronous signal to obtain the k line delay target field effective signal, wherein the 0 line delay field effective signal is a beat delay field effective signal.

Fig. 5 illustrates a timing diagram for k-line delay of a VBUS video stream bus signal provided by at least one embodiment of the present disclosure.

As shown in fig. 5, the source signal includes a field sync signal vsync ', a line sync signal hsync, a field valid signal vact, a line valid signal hact, a data valid signal den ', and an image data signal data '. In the example of fig. 5, the signal located above the broken line A-A 'is a source signal, and the signal located below the broken line A-A' is a signal output from the image signal processing sub-module 1221 to the image signal processing sub-module 1222.

As shown in fig. 5, the image signal processing sub-module 1221 performs k line delay, for example, 2 line delay, on the image data signal data ', and then performs k line delay on the field sync signal vsync', the field valid signal vact, and the data valid signal den. As shown in fig. 5, the first Line image data Line0 of the image data signal data output by the image signal processing sub-module 1221 has a 2-Line delay with respect to the first Line image data Line0 of the image data signal data'.

For the field effective signal vact, k line delay is carried out, firstly, the field effective signal vact is beaten by a clock signal to generate a vact_d signal, then a line synchronizing signal hsync is adopted to sample the vact_d signal, so that the field effective signal vact_ld1 with one line delay can be obtained, then the line synchronizing signal hsync is adopted to sample the vact_ld1 signal, so that a new field effective signal new_vact with two line delays can be obtained, and the field effective signal with k line delays can be obtained by analogy.

The field synchronization signal vsync' is subjected to 2-line delay according to the method described in fig. 4A to obtain a new field synchronization signal vsync, and so on to obtain a field synchronization signal with k-line delay.

In some embodiments of the present disclosure, providing the target data valid signal to the second image signal processing module includes: and performing AND operation on the target field effective signal and the line effective signal to obtain a target data effective signal.

For example, the field valid signal new_vact and the line valid signal hact are anded (i.e., new_act & & hact) to obtain a new data valid signal den (i.e., a target data valid signal).

Note that in the example of fig. 5, k=2 results in a VBUS video stream bus signal with a 2-line delay, but the value of k is not limited by the present disclosure.

Similarly to the line synchronization signal, in the case where the image data signal has only a line delay, a transition of the line valid signal is generated corresponding to each line of the image data signal, and thus, the line delay of the line valid signal is not required. Therefore, the line valid signal after the image data signal is line-delayed coincides with the line valid signal in the source signal.

In view of the scene of line delay, it is generally necessary to identify the edges of an image and perform a trimming operation during image signal processing, which requires determining the number of lines of an image data signal.

In some embodiments of the present disclosure, the transmission method further includes performing an and operation on a non-sum i-1 th line delay field effective signal of the i line delay field effective signal to obtain a first operation result in response to receiving an effective image data signal, where i is a positive integer and the 0 line delay field effective signal is a beat delay field effective signal; and in response to the first operation result being equal to 1, the effective image data signal is the image data signal of the i-th line.

The valid image data signal may be an image data signal acquired during a high level of the data valid signal den.

For example, as shown in fig. 5, the image signal processing sub-module 1221 acquires a source signal (a field sync signal vsync ', a line sync signal hsync, a field effective signal vact, a line effective signal hact, a data effective signal den', and an image data signal data ', which is obtained by acquiring a signal transmitted on an image data signal line during a high level of the data effective signal den'. For example, determining what line of the image is the currently received image data signal during the acquisition of the image data signal data' may obtain vact_d, vact_ld1, new_vact, etc. according to the method described in fig. 5, so as to determine what line of the image is the currently received image data signal according to vact_d, vact_ld1, new_vact.

For example, by judging whether the expression (vact_d ≡ (|vact_ld1))= 1 holds, it can be judged whether the current line is the first line of the image. If (vact_d & (| vact_ld1))= 1, the valid image data signal (i.e., the current line) is the image data signal of the 1 st line. Similar principle, (vact_ld1 & (| new_vact))= 1 determines whether the current line is the second line of the image. If (vact_ld1 ≡ (| new_vact))= 1, the second line of the current-line image. By analogy, if (vact_d (i-1) & (| vact_ ldi))= 1, the valid image data signal (i.e., the current line) is the image data signal of the i-th line. When i=1, vact_d0 is the beat delay field valid signal vact_d. Similarly, the image penultimate line can be determined. For example, by judging whether or not the expression (| vact_d ≡ (vact_ld1))= 1 holds, it is judged whether or not the valid image data signal is the image penultimate 1 line; if (|vact_d & (vact_ld1))= 1 holds, the valid image data signal is the image reciprocal 1 line, and if (|vact_d & (vact_ld1))= 1 does not hold, the valid image data signal is not the image reciprocal 1 line. By analogy, if (| vact_d (i-1) & (vact_ ldi))= 1, the valid image data signal is the image data signal of the i-th line.

The embodiment of the disclosure can judge the row of the image to which the effective image data signal received currently belongs through simple logic operation, and a counter is not needed for counting, so that design complexity and logic resources are simplified.

The upper and lower edges of the image can be identified by the method described above. But within a row the data valid signal is not necessarily continuous (e.g., the data valid signal den' is discontinuous). For example, the data valid signal den' may not be continuous after the cross-clock domain processing or downsampling operation, which is troublesome for identifying the left and right edges of the image, and most of the current schemes may use a counter method for identification. In the VBUS video stream bus provided in the embodiments of the present disclosure, when this situation is met, in the field valid signal vact, the rising edge of the line valid signal hact is kept synchronous with the data valid signal den 'of the first valid pixel of the line, and the falling edge is kept synchronous with the data valid signal den' of the last valid pixel of the line, so that the H pixel position of the left and right edges can be identified by a method similar to that for judging the upper edge and the lower edge. Meanwhile, in order to ensure that the line delay exists, the VBUS video stream bus specifies that the length of the line valid signal hact outside the field valid signal vact is consistent with the image width. In this way, generating a new data valid signal can be kept consistent with the actual image size.

In some embodiments of the present disclosure, the transmission method further includes: in response to receiving the effective image data signals, performing AND operation on the non-sum-row effective signals of the j pixel-level delay row effective signals to obtain a second operation result, wherein j is a positive integer; and in response to the second operation result being equal to 1, the valid image data signal is the image data signal of the j-th column.

For example, by judging whether the expression (hact ≡ (| hact_d1))= 1 holds, it can be judged whether the current image data signal is located in the 1 st column of the image, and hact_d1 is a 1-pixel delayed line valid signal. If (hact & (| hact_d1))= 1, the valid image data signal (i.e., the current image data signal) is 1 st column, and if (hact & (| hact_d1)) is not equal to 1 st column, the current image data signal is not 1 st column, and the determination of whether the current image data signal is 2 nd column is continued. In a similar principle, whether the current image data signal is the second column of the image is determined by whether the expression (hact_d1 & (|hact_d2))= 1 holds, and hact_d2 is a 2-pixel delayed row valid signal. If (hact_d1 & (| hact_d2))= 1, the current image data signal is the second column of the image. By analogy, if (hact_d (j-1) & (| hact_dj))= 1, the valid image data signal (i.e., the current column) is the image data signal of the j-th column. Similarly, it may be determined whether the valid image data signal is the jth column, and will not be described again.

The embodiment can judge the image data signal of which column the current image data signal is by carrying out logic operation through the row effective signal and the pixel level delay row effective signal, does not need a counter to count, and simplifies design complexity and logic resources.

The image sensor has a master mode (master) and a slave mode (slave), and under the slave, if the number of row driving signals (the number of active levels) provided by the master is greater than the total number of rows of one frame of the image sensor specification, a discontinuous row synchronization signal may occur between frames. In addition, there is a process of capturing an image of the image sensor before the image signal is processed, and some schemes mask the line synchronization signal hsync of the blanking area. In this case, the line frequency is unstable. In the line delay process, logic resources may be increased. Even under different application scenario requirements, new problems may be derived. The embodiment of the disclosure provides a concept of periodic wireless circulation of a video stream control signal, and after the image sensor signal is required to be acquired, the restored video stream control signal can be circulated infinitely according to the characteristics of the acquired image sensor signal, so that hardware implementation of an image algorithm is facilitated.

In real products, there may be a need to expand the size of the blanking area due to the needs of the scene. For example, when the image sensor is used as a slave, and the externally generated line driving signal is larger than the data size of the line in the specification of the image sensor, a phenomenon that the line synchronization signal is discontinuous between two frames of images occurs. For example, in the example of fig. 2, the driving signals generated by the image signal processing device 120 include row driving signals, the number of active levels of the row driving signals is greater than the number of rows in the image sensor specification, so that after a row delay is accumulated to exceed a certain number, the image is in a fault phenomenon, as shown in the following figure, after the image row delay, the row synchronization signal hsync and the row active signal after the current frame are insufficient, resulting in a signal that can borrow a next frame.

Fig. 6 shows a timing chart after the image data signal line is delayed in the case where the line synchronization signal is discontinuous.

In the example of fig. 6, the signal located above the broken line B-B 'is the source signal received by the image signal processing sub-module 1221, and the signal located below the broken line B-B' is the signal after the line delay of the signal.

As shown in fig. 6, the source signal includes a source line synchronization signal (i.e., a line synchronization signal hsync) and a line valid signal vact, and the line synchronization signal hsync and the line valid signal vact are discontinuous signals, i.e., a discontinuity occurs in the line synchronization signal hsync between a transition edge of a last line of a first frame and a transition edge of a first line of a second frame in the line synchronization signal hsync. As shown in fig. 6, a Line synchronization signal hsync is interrupted between a transition edge of a Line synchronization signal corresponding to a last Line LineN of a first frame and a transition edge of a Line synchronization signal corresponding to a first Line0 of a second frame, i.e., a blank area is formed in the Line synchronization signal hsync.

If 2 lines of delay are performed on the field valid signal vsync ', the field valid signal vact, the data valid signal den ' and the image data signal data ', a signal of the next frame (i.e., the second frame) is borrowed due to the insufficient Line synchronization signal hsync and the Line valid signal after the current frame (i.e., the first frame), which results in a larger gap between Line1 and Line2 data in the first frame. This problem may be derived from other problems in special cases. To address this problem, in some embodiments of the present disclosure, after the image data signal data' is acquired, the row synchronization signal hsync is restored according to the characteristics of the row driving signal, so that the row synchronization signal hsync is restored to a periodic wireless-circulated signal.

In some embodiments of the present disclosure, two adjacent transition edges of a line synchronization signal are counted to obtain a beat number of a clock signal between every two adjacent transition edges, when recovering a data signal transmitted by an image sensor, the number of transition edges of the line synchronization signal recovered according to the data signal is counted, and for a blank area where the transition edges of the line synchronization signal cannot be recovered according to the data signal, the transition edges of the line synchronization signal are recovered according to the beat number of the clock signal until a host specified line number is reached.

For example, the image sensor has 1125 rows of pixels as a slave, the host driving the image sensor 1128 rows, counting the clock signal after recovering 1125 transition edges of the row synchronization signal by using the data signal provided by the image sensor, generating one transition edge of the row synchronization signal when the count value reaches the above-mentioned beat number, thereby recovering the transition edge of the row synchronization signal of 1126 rows, continuing counting the clock signal, and generating the transition edge of the row synchronization signal of 1127 rows when the count value reaches the above-mentioned beat number again; and continuing to count the clock signals, and generating a jump edge of the 1128-row line synchronizing signal when the count value reaches the beat number again. Until the number of the jump edges of the recovered line synchronization signal is consistent with the driving line number of the host, the jump edges of the line synchronization signal are not recovered according to the number of beats of the clock signal, and then the line synchronization signal of the next frame is recovered by utilizing the data signal provided by the image sensor.

According to the periodic characteristics of the VBUS video stream bus, the problem of larger gap between two rows caused by discontinuous row synchronous signals is considered, and the periodic wireless cyclic row synchronous signals are restored through simple counting and operation. In some other bus interfaces, the case of a discontinuous row synchronization signal is not considered.

In some embodiments of the present disclosure, the transmission method further includes acquiring a switch indication signal; and judging whether a break exists between the effective jump edge of the last line of the first frame and the effective jump edge of the first line of the second frame of the source line synchronous signal according to the switch indication signal. The method sets the switch indication signal so that a user can control whether to start the function of recovering the line synchronization signal. This is because in some situations the line sync signal hsync and the line valid signal are not insufficient, i.e. there is no space, for example when the externally generated line drive signal is equal to the data size of the line in the specification of the image sensor, the line sync signal and the line valid signal are not in space, at which time the function of recovering the line sync signal can be turned off to save resources.

In some embodiments of the present disclosure, the user may input a switch indication signal or control the switch indication signal through a button. For example, when the button is turned off, the function of recovering the line synchronization signal is turned off, and when the button is turned on, the function of recovering the line synchronization signal is turned on.

The VBUS video stream bus provided by the embodiment of the disclosure is used for processing image signals, the video stream interfaces of all modules are according to the VBUS video stream bus specification, the independence of each module is strong, the development is convenient, and the system is easy to integrate. Meanwhile, the complexity of the design can be reduced, and the stability of the whole design is high.

Fig. 7 illustrates a schematic block diagram of a signal transmission apparatus 700 provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 7, the signal transmission apparatus 700 includes an acquisition unit 710, a line synchronization signal generation unit 720, a field synchronization signal generation unit 730, a first transmission unit 740, and a second transmission unit 750.

The acquisition unit 710 is configured to acquire a source signal including at least an image data signal. . The acquisition unit 710 may perform step S301 described in fig. 3A, for example.

The line synchronization signal generation unit 720 is configured to periodically generate a target line synchronization signal for indicating the start of transmission of one line of image data signals.

The row synchronization signal generation unit 720 may perform, for example, step S302 described in fig. 3A.

The field sync signal generating unit 730 is configured to generate a target field sync signal indicating the start of transmission of one frame of image data signal based on the target line sync signal, the active transition edge of the target field sync signal is synchronized with the active transition edge of the target line sync signal, and the time length of the active level of the target field sync signal is m times the period length of the target line sync signal, and m is a positive integer.

The field sync signal generation unit 730 may perform, for example, step S303 described in fig. 3A.

The first transmitting unit 740 is configured to provide the target line synchronization signal and the target field synchronization signal to the second image signal processing module.

The first transmitting unit 740 may perform, for example, step S304 described in fig. 3A.

The second transmitting unit 750 is configured to supply an image data signal to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal.

The second transmitting unit 750 may perform step S305 described in fig. 3A, for example.

For example, the acquisition unit 710, the line synchronization signal generation unit 720, the field synchronization signal generation unit 730, the first transmission unit 740, and the second transmission unit 750 may be hardware, software, firmware, and any feasible combination thereof. For example, the acquisition unit 710, the row synchronization signal generation unit 720, the field synchronization signal generation unit 730, the first transmission unit 740, and the second transmission unit 750 may be dedicated or general-purpose circuits, chips, devices, or the like, or may be a combination of a processor and a memory. With respect to the specific implementation forms of the respective units described above, the embodiments of the present disclosure are not limited thereto.

It should be noted that, in the embodiment of the present disclosure, each unit of the signal transmission apparatus 700 corresponds to each step of the foregoing signal transmission method, and the specific function of the signal transmission apparatus 700 may refer to the related description of the signal transmission method, which is not repeated herein. The components and structures of the signal transmission device 700 shown in fig. 7 are exemplary only and not limiting, and the signal transmission device 700 may include other components and structures as desired.

At least one embodiment of the present disclosure also provides an electronic device, and fig. 8 shows a schematic block diagram of an electronic device 800 provided by at least one embodiment of the present disclosure.

As shown in fig. 8, the electronic device 800 includes a first image signal processing module 810 and a second image signal processing module 820. The first image signal processing module includes the signal transmission device provided in any of the embodiments of the present disclosure, and the second image signal processing module is coupled to the first image signal processing module to receive the target line synchronization signal, the target field synchronization signal, and the image data signal provided by the first image signal processing module.

For example, the electronic device 800 includes the image signal processing apparatus 120 shown in fig. 2. The image signal processing apparatus 120 includes a signal receiving and converting module 121 and an image signal processing module 122. The signal receiving and converting module 121 may be used as the first image signal processing module 810, and any sub-module in the image signal processing module 122 may be used as the first image signal processing module 810. Any sub-module of the image signal processing module 122 for receiving the VBUS video stream bus signal may be used as the second image signal processing module 820.

The electronic equipment can realize unification of video stream interfaces of different image signal processing sub-modules, has good compatibility among different units and is convenient for system integration; and the bus is easy to understand aiming at the characteristic of realizing image signal processing of hardware logic, and reduces design complexity and logic resources to a certain extent.

The following points need to be described:

(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A signal transmission method applied to a first image signal processing module, the method comprising:

acquiring a source signal, wherein the source signal at least comprises an image data signal;

generating a target line synchronization signal, wherein the target line synchronization signal is a periodic signal and is used for indicating the start of transmitting a line of image data signals;

Generating a target field synchronizing signal based on the target line synchronizing signal, wherein the target field synchronizing signal is used for indicating the start of transmitting a frame of image data signal, a jump edge of the target field synchronizing signal is synchronous with an effective jump edge of the target line synchronizing signal, the time length of the effective level of the target field synchronizing signal is m times of the period length of the target line synchronizing signal, and m is a positive integer;

providing the target line synchronization signal and the target field synchronization signal to a second image signal processing module; and

the image data signal is provided to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal.

2. The method of claim 1, wherein the source signal comprises a source field sync signal,

generating the target field sync signal based on the target row sync signal, comprising:

and under the condition that the first image processing module carries out k line delay on the image data signal, carrying out k line delay on the source field synchronous signal based on the target line synchronous signal to obtain the target field synchronous signal, wherein k is a positive integer.

3. The method of claim 2, wherein k-line-delaying the source field sync signal based on the target line sync signal to obtain the target field sync signal comprises:

carrying out one clock period delay on the source field synchronous signal to obtain a beat delay field synchronous signal; and

sampling the target field synchronizing signal with k-1 line delay at the effective jump edge of the target line synchronizing signal to obtain the target field synchronizing signal with k line delay, wherein the field synchronizing signal with 0 line delay is the beat delay field synchronizing signal.

4. The method of claim 1, wherein the source signals comprise a source field sync signal and a source row sync signal,

periodically generating the target row synchronization signal, comprising:

under the condition that the first image signal processing module carries out pixel-level delay on the image data signal, carrying out pixel-level delay on the source line synchronous signal to obtain the target line synchronous signal;

and sampling the source field synchronizing signal at the effective jump edge of the target line synchronizing signal to obtain the target field synchronizing signal.

5. The method of any one of claims 1-4, further comprising:

and providing a target data valid signal to the second image signal processing module, wherein the target data valid signal is used for indicating whether the image data signal is valid or not.

6. The method of claim 5, further comprising:

providing a target field effective signal to the second image signal processing module, wherein an effective transition edge and an ineffective transition edge of the target field effective signal are respectively aligned with two effective transition edges of the target line synchronous signal; and

a row valid signal is periodically provided, wherein the row valid signal and the target data valid signal coincide during an active level of the target field valid signal in the case that the target data valid signal is continuous.

7. The method of claim 6, wherein the source signal further comprises a source field effective signal,

providing a target field effective signal to the second image signal processing module, comprising:

and under the condition that the first image signal processing module carries out k line delay on the image data signals, carrying out k line delay on the source field effective signals to obtain the target field effective signals, wherein k is a positive integer.

8. The method of claim 7, wherein the source data signal further comprises a source field valid signal,

performing k-line delay on the source field effective signal to obtain the target field effective signal, including:

performing one clock period delay on the source field effective signal to obtain a beat delay field effective signal; and

sampling the k-1 line delay field effective signal at the effective jump edge of the target line synchronous signal to obtain the k line delay target field effective signal, wherein the 0 line delay field effective signal is the beat delay field effective signal.

9. The method of claim 8, wherein providing the second image signal processing module with a target data valid signal comprises:

and performing AND operation on the target field effective signal and the row effective signal to obtain the target data effective signal.

10. The method of claim 8, further comprising:

in response to receiving an effective image data signal, performing an AND operation on a non-sum i-1 th row delay field effective signal of an i row delay field effective signal to obtain a first operation result, wherein i is a positive integer, and a 0 row delay field effective signal is the beat delay field effective signal; and

And responding to the first operation result being equal to 1, wherein the effective image data signal is the image data signal of the ith row.

11. The method of claim 8, further comprising:

responding to receiving effective image data signals, performing AND operation on the non-sum of j pixel-level delay line effective signals and the j-1 pixel-level delay line effective signals to obtain a second operation result, wherein j is a positive integer; and

and responding to the second operation result being equal to 1, wherein the effective image data signal is the image data signal of the j-th column.

12. The method of claim 1, wherein the source signal comprises a source row synchronization signal, and periodically generating a target row synchronization signal comprises:

and recovering the jump edge of the source line synchronizing signal in the interruption period to obtain the target line synchronizing signal under the condition that the source line synchronizing signal is interrupted between the jump edge of the last line of the first frame and the jump edge of the first line of the second frame in the target line synchronizing signal.

13. The method of claim 12, further comprising:

acquiring a switch indication signal;

and judging whether the break exists between the effective jump edge of the last line of the first frame and the effective jump edge of the first line of the second frame of the source line synchronous signal according to the switch indication signal.

14. A signal transmission apparatus applied to a first image signal processing module, the apparatus comprising:

an acquisition unit configured to acquire a source signal, wherein the source signal includes at least an image data signal;

a line synchronization signal generation unit configured to periodically generate a target line synchronization signal for indicating a start of transmission of a line of image data signals;

a field synchronizing signal generating unit configured to generate a target field synchronizing signal based on the target line synchronizing signal, wherein the target field synchronizing signal is used for indicating the start of transmitting a frame of image data signal, an effective transition edge of the target field synchronizing signal is synchronized with an effective transition edge of the target line synchronizing signal, and a time length of an effective level of the target field synchronizing signal is m times a period length of the target line synchronizing signal, and m is a positive integer;

a first transmitting unit configured to provide the target line synchronization signal and the target field synchronization signal to a second image signal processing module; and

and a second transmitting unit configured to supply the image data signal to the second image signal processing module based on the target line synchronization signal and the target field synchronization signal.

15. An electronic device, comprising:

a first image signal processing module comprising the signal transmission device of claim 14; and

and a second image signal processing module coupled to the first image signal processing module for receiving the target line synchronization signal, the target field synchronization signal and the image data signal provided by the first image signal processing module.