CN116387364A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

Info

Publication number
CN116387364A
CN116387364A CN202310450456.7A CN202310450456A CN116387364A CN 116387364 A CN116387364 A CN 116387364A CN 202310450456 A CN202310450456 A CN 202310450456A CN 116387364 A CN116387364 A CN 116387364A
Authority
CN
China
Prior art keywords
layer
gate
electrode
oxide
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310450456.7A
Other languages
Chinese (zh)
Inventor
顾婷婷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202310450456.7A priority Critical patent/CN116387364A/en
Publication of CN116387364A publication Critical patent/CN116387364A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof. Wherein the semiconductor structure comprises: a semiconductor substrate; a first electrode layer, a first barrier layer, a support layer, a second barrier layer, and a second electrode layer sequentially stacked in a vertical direction on a semiconductor substrate; the first electrode layer, the first barrier layer, the supporting layer, the second barrier layer and the second electrode layer are internally provided with filling spaces, and the filling spaces extend into the first electrode layer from the top surface of the second electrode layer along the vertical direction; an oxide semiconductor layer located on an inner wall of the filling space; a gate oxide layer on the oxide semiconductor layer; and the grid electrode is positioned in the filling space between the grid oxide layers. The semiconductor structure of the embodiment of the disclosure can improve the ratio of on-state current to off-state current and improve the electrical performance.

Description

Semiconductor structure and preparation method thereof
Technical Field
The disclosure relates to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor structure and a manufacturing method thereof.
Background
With the development of semiconductor technology, capacitor-free DRAM (Dynamic Random Access Memory ) has great potential in realizing high-density 3D (3D Dimensions) DRAM, such as 2T0C (2Transistors 0Capacitor) thin film transistors, without storage capacitors, and can increase the density of DRAM.
However, in the related art, the requirements on the electrical performance of the semiconductor are increasing, and thus the ratio of the on-state current to the off-state current of the capacitor-free DRAM is to be improved.
The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and thus it may include information that does not form a related art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can improve the ratio of on-state current to off-state current and improve the electrical performance of the semiconductor structure.
Embodiments of the present disclosure provide a semiconductor structure, comprising: a semiconductor substrate, a first electrode layer, a first barrier layer, a support layer, a second barrier layer and a second electrode layer, an oxide semiconductor layer, a gate oxide layer and a gate electrode which are stacked in this order in a vertical direction on the semiconductor substrate.
Wherein the first electrode layer, the first barrier layer, the support layer, the second barrier layer and the second electrode layer have a filling space therein, the filling space extending from a top surface of the second electrode layer into the first electrode layer along the vertical direction; the oxide semiconductor layer is positioned on the inner wall of the filling space; a gate oxide layer on the oxide semiconductor layer; and a grid electrode is positioned in the filling space between the grid oxide layers.
In some embodiments of the present disclosure, the semiconductor structure further comprises: and the graphene layer is positioned between the grid electrode and the grid oxide layer.
In some embodiments of the present disclosure, the gate includes: a first gate electrode located in the filling space between the gate oxide layers and extending from the bottom of the filling space to a position between the first barrier layer and the second barrier layer; and the second grid electrode is positioned in the filling space on the first grid electrode.
In some embodiments of the present disclosure, the gate oxide layer comprises a high-K dielectric material comprising TiO 2 And HfO 2 At least one of them.
In some embodiments of the present disclosure, the material of the first barrier layer and the material of the second barrier layer each comprise Si 3 N 4 。
In some embodiments of the present disclosure, in the vertical direction, a projection of the first electrode layer onto the semiconductor substrate is within a projection of the first barrier layer onto the semiconductor substrate, and a projection of the second electrode layer onto the semiconductor substrate is within a projection of the second barrier layer onto the semiconductor substrate.
The embodiment of the disclosure also provides a method for preparing the semiconductor structure, which comprises the following steps: providing a semiconductor substrate; forming a first electrode layer, a first barrier layer, a support layer, a second barrier layer and a second electrode layer stacked in order in a vertical direction on the semiconductor substrate; forming a filling space in the first electrode layer, the first barrier layer, the support layer, the second barrier layer and the second electrode layer, the filling space extending from a top surface of the second electrode layer into the first electrode layer in the vertical direction; forming an oxide semiconductor layer on an inner wall of the filling space; forming a gate oxide layer on the oxide semiconductor layer; and filling and forming a gate in the residual space of the filling space in which the gate oxide layer is formed.
In some embodiments of the present disclosure, after forming the gate oxide layer, the method further comprises: forming a graphene layer on the gate oxide layer; and filling and forming the grid electrode in the residual space of the filling space formed with the graphene layer.
In some embodiments of the present disclosure, filling the remaining space of the filling space to form the gate includes: forming a first gate in a remaining space of the filling space; etching back the first gate such that a top surface of the first gate is located between the first barrier layer and the second barrier layer; a second gate is formed on the first gate.
In some embodiments of the present disclosure, forming a first electrode layer, a first barrier layer, a support layer, a second barrier layer, and a second electrode layer stacked in order in a vertical direction on the semiconductor substrate includes: forming an oxide layer on the semiconductor substrate; etching back the oxide layer to form an accommodating space; forming the first electrode layer in the accommodating space such that a top surface of the first electrode layer is flush with the oxide layer; forming the first barrier layer on the first electrode layer and on the oxide layer; forming the support layer on the oxide layer and on the first barrier layer; forming the second barrier layer on the support; the second electrode layer is formed on the second barrier layer.
As can be seen from the above technical solutions, the semiconductor structure according to the embodiments of the present disclosure has at least one of the following advantages and positive effects:
in the embodiment of the disclosure, in the semiconductor structure, the first barrier layer and the second barrier layer are located between the first electrode layer and the second electrode layer and surround the oxide semiconductor layer, and when annealing is performed after the oxide semiconductor layer is formed, the defect density of the oxide semiconductor layer can be reduced, so that the off-state current is reduced, and meanwhile, the contact resistance between the first electrode layer and the oxide semiconductor layer, between the second electrode layer and the oxide semiconductor layer is reduced, and the on-state current is improved, so that the ratio of the on-state current to the off-state current is finally improved, and the electrical performance of the semiconductor structure is improved.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure;
fig. 2-15 are cross-sectional schematic views of semiconductor structures during fabrication according to some embodiments of the present disclosure.
Reference numerals illustrate:
1. a semiconductor substrate; 2. an oxide layer; 3. a first electrode layer; 4. a first barrier layer; 5. a support layer; 6. a second barrier layer; 7. a second electrode layer; 8. an oxide semiconductor layer; 9. a gate oxide layer; 10. a graphene layer; 11. a gate; 111. a first gate; 112. a second gate; s, filling a space; C. an accommodation space; y, vertical direction.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the directions of examples in the drawings. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of structures to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not intended to limit the numerals of their objects.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
In addition, in the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.
With the development of semiconductor technology, capacitor-free DRAM (Dynamic Random Access Memory ) has great potential in realizing high-density 3D (3D Dimensions) DRAM, such as 2T0C (2Transistors 0Capacitor) thin film transistors, realizing a cell architecture of two Indium Gallium Zinc Oxide (IGZO) thin film transistors without capacitance, capable of improving the density of DRAM, and capable of avoiding charge leakage.
Still taking a 2T0C thin film transistor as an example, the 2T0C thin film transistor has an oxide semiconductor layer therein, the oxide semiconductor layer serving as a channel. In the preparation process of the 2T0C thin film transistor, thermal annealing is required in an oxygen atmosphere after the oxide semiconductor layer is formed, so that the concentration of carriers in the oxide semiconductor layer is unstable, the defect density is increased, the off-state current is increased, and the ratio of the on-state current to the off-state current of the transistor is abnormal.
Based on this, the embodiment of the present disclosure provides a semiconductor structure including a semiconductor substrate 1, a first electrode layer 3, a first barrier layer 4, a second barrier layer 6 and a second electrode layer 7, an oxide semiconductor layer 8, a gate oxide layer 9 and a gate electrode 11, which are sequentially stacked in a vertical direction Y on the semiconductor substrate 1, as shown in fig. 15.
Wherein the first electrode layer 3, the first barrier layer 4, the support layer 5, the second barrier layer 6 and the second electrode layer 7 have a filling space S therein. The filling space S extends from the top surface of the second electrode layer 7 into the first electrode layer 3 in the vertical direction Y. The oxide semiconductor layer 8 is located on the inner wall of the filling space S. A gate oxide layer 9 is located on the oxide semiconductor layer 8. The gate electrode 11 is located in the filling space S between the gate oxide layers 2. The vertical direction Y is understood to be the direction perpendicular to the semiconductor substrate 1.
Since the first barrier layer 4 and the second barrier layer 6 are located between the first electrode layer 3 and the second electrode layer 7 and surround the oxide semiconductor layer 8, when annealing is performed after the oxide semiconductor layer 8 is formed, the carrier concentration of the oxide semiconductor layer 8 can be stabilized, the defect density of the oxide semiconductor layer 8 is reduced, and then the off-state current is reduced, and meanwhile, the contact resistance between the first electrode layer 3 and the oxide semiconductor layer 8, the contact resistance between the second electrode layer 7 and the oxide semiconductor layer 8 are reduced, and the on-state current is improved, so that the ratio of the on-state current to the off-state current is finally improved, and the electrical performance of the semiconductor structure is improved.
In some embodiments, the material of the oxide semiconductor layer 8 may be In 2 O 3 (indium oxide), znO (zinc oxide), IZO (indium zinc oxide ), IGZO (indium gallium zinc oxide, indium Gallium Zinc Oxide), IZTO (indium tin zinc oxide, including indium oxide, tin oxide, and zinc oxide), znON (zinc oxynitride), or a combination of two or more thereof.
In some embodiments, the gate 11 includes a first gate 111 and a second gate 112. The first gate 111 is located in the filling space S between the gate oxide layers 9 and extends from the bottom of the filling space S to a position between the first barrier layer 4 and the second barrier layer 6. The second gate electrode 112 is located in the filling space S on the first gate electrode 111.
Specifically, as shown in fig. 15, the gate electrode 11 is located in the filling space S between the gate oxide layers 9, and fills the filling space S. The gate 11 includes two gate structures having different materials, i.e., a first gate 111 and a second gate 112. The work function of the second gate 112 is smaller than that of the first gate 111, and the contact resistance between the gate 11 and the external electrode can be reduced. The interface of the first gate 111 and the second gate 112 is located at a position between the first barrier layer 4 and the second barrier layer 6. Since the second gate electrode 112 has a low work function, and the interface between the second gate electrode 112 and the first gate electrode 111 is located between the first barrier layer 4 and the second barrier layer 6, the top surface of the first gate electrode 111 does not reach the height position of the second electrode layer 7, and thus the area between the first gate electrode 111 and the corresponding portion of the second electrode layer 7 in the vertical direction Y can be reduced, and parasitic capacitance can be reduced. The Gate 11 in the embodiment of the disclosure has the structure of the first Gate 111 and the second Gate 112 with different work functions, and the work functions of the first Gate 111 and the second Gate 112 are different, so that the GIDL (Gate-Induced Drain Leakage, gate induced drain leakage current) effect can be improved, and the off-state current can be reduced.
The arrangement of the gate 11 as the first gate 111 and the second gate 112 of different materials allows the gate 11 to be formed as a gate 11 of a bi-metallic material, allows tunneling of electrons of a semiconductor structure (e.g., a field effect thin film transistor GAA MOSFET of a ring gate structure) from the Valence Band Edge (VBE) to the Conduction Band Edge (CBE) to be cut off, reduces inter-band tunneling, and has a higher drain current, a higher transconductance and a higher output conductance, and also allows a Subthreshold Slope (SS) to approach an ideal value, increases the ratio of the on-state currents (I on /I off )。
In some embodiments, the material of the first gate 111 includes Ni and the material of the second gate 112 includes TiN.
In some embodiments, the gate oxide layer 9 comprises a high-K dielectric material comprising TiO 2 And HfO 2 At least one of them.
The material of the gate oxide layer 9 is selected to be a high-K dielectric material, so that gate tunneling current can be suppressed, and the density of stored charges can be improved, thereby simplifying the structure of the gate oxide layer 9. However, when heterogeneous interfaces are coupled to each other, the difference in work function between the heterogeneous interfaces forms a built-in electric field at the interfaces, which in turn affects the electrical performance of the semiconductor structure, and in the embodiments of the present disclosure the high-K dielectric material further comprises TiO 2 And HfO 2 The first gate 111 material comprises Ni and the second gate 112 material comprises TiN, thereby tuning the hetero-interface work function of the gate 11 (metal) and gate oxide 9 (high K dielectric material).
Specifically, in some embodiments, the high-K dielectric material is selected to be HfO 2 ，Ni/HfO 2 The work function of (2) depends on the interface microstructure, ni replaces interface Hf, and interface Hf vacancies increase the interface work function of Hf-Ni, wherein O vacancies lower the O-Ni interface work function. TiN/HfO 2 Work function dependence onInterface bonding, wherein the order of the work functions of the three interfaces is Ti-O>Ti-O-O>N-Hf. The N-substituted O at the interface reduces the interface work function of the N-Hf; while interface N, O vacancy increases its work function, reduces the work function of the Ti-O interface, while interface O vacancy increases its work function to a lesser extent, by the adjustment of the above elements, the interface work function of gate 11 and gate oxide 9 is improved, improving the electrical properties of the semiconductor structure.
In other embodiments, the high-K dielectric material is selected to be TiO 2 The semiconductor structure (such as a thin film transistor with the indium gallium zinc oxide layer as a channel) has higher catalytic activity current, and can greatly improve the electron mobility of the indium gallium zinc oxide layer, thereby improving the on-state current of the semiconductor structure.
In some embodiments, as shown in fig. 15, the semiconductor structure further comprises a graphene layer 10, between the gate 11 and the gate oxide layer 9.
In the above embodiment, although the materials of the gate electrode 11 and the gate oxide layer 9 are selected and the interface work function between them is improved, there are point defects at the hetero interface of the two. A graphene layer 10 is arranged between the gate electrode 11 and the gate oxide layer 9, which is equivalent to inserting an interface control layer between the gate electrode 11 and the gate oxide layer 9, thereby improving Ni/HfO 2 The quality of the whole system is reduced, point defects are reduced, O vacancies and C vacancies exist at the interface of the three, and the Ni/Gr (graphene)/HfO can be effectively modulated 2 Is a work function of the interface of the (c).
In some embodiments, the material of the first barrier layer 4 and the material of the second barrier layer 6 may each comprise Si 3 N 4 。
The material of the first barrier layer 4 and the second barrier layer 6 is selected to be Si 3 N 4 In the preparation process of the semiconductor structure, the oxide semiconductor layer 8 is enabled to increase the stability of the concentration of carriers during annealing, effectively reduce the defect density of a channel region, reduce off-state leakage current, and simultaneously enable the defect density of a contact region of a source drain (the first electrode layer 3 and the second electrode layer 7) to be less affected, so that the contact resistance of the source drain is reduced, and the on-state current of the semiconductor structure is raisedThe electrical properties of the semiconductor structure are improved.
In some embodiments, as shown in fig. 15, the projection of the first electrode layer 3 onto the semiconductor substrate 1 is located within the projection of the first barrier layer 4 onto the semiconductor substrate 1, and the projection of the second electrode layer 7 onto the semiconductor substrate 1 is located within the projection of the second barrier layer 6 onto the semiconductor substrate 1 in the vertical direction Y.
As shown in fig. 15, in the vertical direction Y, the first barrier layer 4 completely covers the first electrode layer 3, and the second barrier layer 6 also completely covers the second electrode layer 7, i.e., the top surface of the second barrier layer 6 completely covers the bottom surface of the second electrode layer 7. In this way, the stability of the carrier concentration of the oxide semiconductor layer 8 during annealing can be further improved, and off-state leakage current can be reduced.
In some embodiments, with continued reference to fig. 15, the semiconductor structure further comprises an oxide layer 2 located between the semiconductor substrate 1 and the support layer 5, the oxide layer 2 having a receiving space C in which the first electrode layer 3 is located.
In fact, the oxide layer 2 has not only the function of accommodating the first electrode layer 3 for insulation, but also the supporting function, as shown in fig. 15, that is, at least part of the supporting layer 5 and the first barrier layer 4 are both located on the oxide layer 2, i.e., the oxide layer 2 further plays the role of supporting the first barrier layer 4 and the supporting layer 5.
In summary, the semiconductor structure in the embodiment of the disclosure can improve the ratio of the on-state current to the off-state current, and improve the electrical performance of the semiconductor structure.
The embodiment of the disclosure also provides a preparation method of the semiconductor structure, which is used for preparing the semiconductor structure described in any embodiment. As shown in fig. 1, the preparation method includes the following steps S110 to S160.
S110: a semiconductor substrate 1 is provided.
Fig. 2 shows a schematic view of a semiconductor substrate 1. In some embodiments, the material of the semiconductor substrate 11 may be silicon, silicon carbide, silicon-on-insulator, silicon-germanium-on-insulator, or the like. The semiconductor substrate 11 may also be implanted with certain dopant particles to change electrical parameters according to design requirements.
Shallow trench isolations (not shown) may be formed on the semiconductor substrate 11, with active regions between the shallow trench isolations, and semiconductor devices may be disposed in the active regions. For convenience of description and more clearly showing the preparation method of the semiconductor structure according to the embodiments of the present disclosure, the shallow trench isolation and the active region are not shown in the semiconductor substrate 11 in the drawings, but various structures in the semiconductor substrate 11 can be known to those skilled in the art according to the known technology, and will not be repeated here.
S120: a first electrode layer 3, a first barrier layer 4, a support layer 5, a second barrier layer 6, and a second electrode layer 7, which are sequentially stacked, are formed on the semiconductor substrate 1 in the vertical direction Y.
Specifically, S120 may include the following contents A1 to A7.
A1: an oxide layer 2 is formed on a semiconductor substrate 1.
As shown in fig. 2, an oxide layer 2 may be formed on a semiconductor substrate 1 using a deposition process. The height of the oxide layer 2 in the vertical direction Y is greater than the height of the subsequently formed first electrode layer 3, so that the subsequent first electrode layer 3 can be formed in the oxide layer 2.
In some embodiments, the oxide layer 2 is an insulating layer, and the material of the oxide layer 2 may be at least one of silicon oxide and silicon oxynitride.
In some embodiments, the deposition process for forming the first oxide layer 22 may include at least one of a chemical vapor deposition process (e.g., a plasma enhanced chemical vapor deposition process, plasma Enhanced Chemical Vapor Deposition, PECVD), a physical vapor deposition process, and an atomic layer deposition process, without particular limitation herein.
A2: the oxide layer 2 is etched back to form the accommodating space C.
Specifically, as shown in fig. 2, a mask layer having a pattern forming the accommodating space C thereon may be formed on the oxide layer 2, and the accommodating space C may be formed by etching back the oxide layer 2 using an etching process through the mask layer. As shown in fig. 2, the accommodating space C is for accommodating a subsequently formed first electrode layer 3.
In some embodiments, the etching process may be a dry etching process or a wet etching process. The dry etching process can be a plasma etching process, etching gas adopted in the plasma etching process can be chlorine, and the etching degree can be controlled by controlling the using amount of the etching gas; the wet etching process can use concentrated sulfuric acid and hydrogen peroxide as etching agents, and can also control the etching degree by adjusting the concentration of the etching agents.
A3: the first electrode layer 3 is formed in the accommodating space C such that the top surface of the first electrode layer 3 is flush with the oxide layer 2.
Specifically, as shown in fig. 3, the first electrode layer 3 may be filled in the accommodating space C using a deposition process. The top of the first electrode layer 3 may then be polished using a chemical mechanical polishing process (Chemical Mechanical Polish, CMP) to expose the top surface of the oxide layer 2 and to make the top surface of the first electrode layer 3 level with the top surface of the oxide layer 2, i.e. to inlay the first electrode layer 3 into the oxide layer 2 and to expose the top surface thereof.
In some embodiments, the material of the first electrode layer 3 may be at least one of tungsten, titanium, nickel, aluminum, and platinum, which is not limited herein. The first electrode layer 3 may be connected to a Word line
A4: a first barrier layer 4 is formed on the first electrode layer 3 and on the oxide layer 2.
As shown in fig. 4, a first barrier layer 4 may be formed on the first electrode layer 3 and the oxide layer 2 using a deposition process. Then, a part of the first barrier layer 4 is etched away by an etching process so that the first barrier layer 4 can entirely cover the first electrode layer 3 in the vertical direction Y.
In some embodiments, the first barrier layer 4 may be made of Si 3 N 4 . The deposition process may be a plasma enhanced chemical vapor deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD).
A5: a support layer 5 is formed on the oxide layer 2 and on the first barrier layer 4.
As shown in fig. 5, the support layer 5 may be formed on the oxide layer 2 and on the first barrier layer 4 using a deposition process. The support layer 5 mainly plays a role in supporting the subsequently formed second barrier layer 6 and second electrode layer 7 while separating the first barrier layer 4 from the second barrier layer 6, and thus, the height of the second barrier layer 6 in the vertical direction Y is at least greater than the height of the first barrier layer 4.
In some embodiments, the supporting layer 5 is an insulating layer, and the material of the supporting layer 5 may be at least one of silicon oxide and silicon oxynitride. After the support layer 5 is deposited, if the top surface of the support layer 5 is uneven, the top surface may be polished flat by a chemical mechanical polishing process so as to form the second barrier layer 6 thereon later.
In some embodiments, the deposition process may be a plasma enhanced chemical vapor deposition Process (PECVD).
A6: a second barrier layer 6 is formed on the support layer 5.
As shown in fig. 6, a second barrier layer 6 may be formed on the top surface of the support layer 5 using a deposition process. The second barrier layer 6 may be made of Si 3 N 4 The first barrier layer 4 and the second barrier layer 6 are the same in material, so that material replacement in the preparation process can be avoided, and the process is simplified.
In some embodiments, the deposition process may be a plasma enhanced chemical vapor deposition Process (PECVD).
A7: a second electrode layer 7 is formed on the second barrier layer 6.
Specifically, as shown in fig. 7, a second electrode layer 7 may be formed on the second barrier layer 6 using a deposition process. In some embodiments, the deposition process may be a plasma enhanced chemical vapor deposition Process (PECVD).
In some embodiments, the material of the second electrode layer 7 may be at least one of tungsten, titanium, nickel, aluminum, and platinum, which is not limited herein. The second electrode layer 7 may be connected to a Bit line (Bit line).
S130: a filling space S is formed in the first electrode layer 3, the first barrier layer 4, the support layer 5, the second barrier layer 6, and the second electrode layer 7, the filling space S extending from the top surface of the second electrode layer 7 into the first electrode layer 3 in the vertical direction Y.
As shown in fig. 8, a mask layer having a pattern filling the space S may be formed on the second electrode layer 7, and the second electrode layer 7, the second barrier layer 6, the support layer 5, the first barrier layer 4, and portions of the first electrode layer 3 may be sequentially etched downward in the vertical direction Y from the surface of the second electrode layer 7 according to the pattern by an etching process, as shown in fig. 8, the etching process is stopped at the first electrode layer 3, and a portion of the first electrode layer 3 remains in the vertical direction Y, and the formed filling space S extends from the top surface of the second electrode layer 7 into the first electrode layer 3 in the vertical direction Y. The remaining first electrode layer 3 may be used as a first electrode connection word line, and the remaining second electrode layer 7 may be used as a second electrode connection bit line, however, the first electrode layer 3 and the second electrode layer 7 may be connected to other metals, and the present invention is not limited thereto.
S140: an oxide semiconductor layer 8 is formed on the inner wall of the filling space S.
Specifically, as shown in fig. 9, the oxide semiconductor layer 8 may be conformally formed on the inner wall of the filling space S using a deposition process. Wherein "conformally formed" may be understood as being formed along the contour of the inner wall.
In some embodiments, the material of the oxide semiconductor layer 8 may be In 2 O 3 (indium oxide), znO (zinc oxide), IZO (indium zinc oxide ), IGZO (indium gallium zinc oxide, indium Gallium Zinc Oxide), IZTO (indium tin zinc oxide, including indium oxide, tin oxide, and zinc oxide), znON (zinc oxynitride), or a combination of two or more thereof.
The oxide semiconductor layer 8 may serve as a channel, and the first electrode layer 3 and the second electrode layer 7 may serve as a source and a drain in contact therewith.
After the formation of the oxide semiconductor layer 8, the oxide semiconductor layer 8 needs to be thermally annealed in an oxygen atmosphere so that the formation of the oxide semiconductor layer 8 is more stable. However, when annealing, for example, when the oxide semiconductor layer 8 is an IGZO layer, the carrier concentration of IGZO is unstableResulting in an abnormal ratio of on-state current to off-state current of the semiconductor structure. However, since the first barrier layer 4 and the second barrier layer 6 are formed around the portions where the source and drain electrodes (the first electrode layer 3 and the second electrode layer 7) are in contact with the oxide semiconductor layer 8, respectively, are formed in the above steps in the embodiment of the present disclosure, and the materials of the first barrier layer 4 and the second barrier layer 6 are selected to be Si 3 N 4 The carrier concentration of the oxide semiconductor layer 8 can be stabilized, the defect density of the oxide semiconductor layer 8 is reduced, the off-state current is reduced, the contact resistance between the first electrode layer 3 and the oxide semiconductor layer 8, the contact resistance between the second electrode layer 7 and the oxide semiconductor layer 8 are reduced, and the on-state current is improved, so that the ratio of the on-state current to the off-state current is finally improved, and the electrical performance of the semiconductor structure is improved. Accordingly, defects generated when the oxide semiconductor layer 8 is annealed are no longer present in the semiconductor structure formed in the embodiments of the present disclosure.
In some embodiments, the oxide semiconductor layer 8 may be formed by an atomic layer deposition process, however, other deposition processes are also possible, and are not particularly limited herein.
In addition, the oxide semiconductor layer 8 may be formed on the surface of the second electrode layer 7 at the same time, so as to facilitate subsequent processing.
S150: a gate oxide layer 9 is formed on the oxide semiconductor layer 8.
As shown in fig. 10, the gate oxide layer 9 may be conformally formed on the oxide semiconductor layer 8 using a deposition process (e.g., an atomic layer deposition process).
In some embodiments, the material of the gate oxide layer 9 may be selected to be a high-K dielectric material, so that the gate tunneling current can be suppressed, and the density of stored charges can be increased, thereby simplifying the structure of the gate oxide layer 9. The high-K dielectric material further comprises TiO 2 And HfO 2 At least one of them.
S160: the gate electrode 11 is filled in the remaining space of the filling space S in which the gate oxide layer 9 is formed.
Specifically, S160 may include the following contents B1 to B3.
B1: the first gate 111 is formed in the remaining space of the filling space S where the gate oxide layer 9 is formed.
As shown in fig. 12 (ignoring the graphene layer 10), the first gate electrode 111 may be deposited in the filling space S using a deposition process. The filling space S has a first position between the first barrier layer 4 and the second barrier layer 6 in the vertical direction Y, and the height of the first gate 111 is greater than the height of the first position in the vertical direction Y, i.e., the top surface of the first gate 111 is located above the first position.
B2: the first gate 111 is etched back such that the top surface of the first gate 111 is located between the first barrier layer 4 and the second barrier layer 6.
As shown in fig. 13 (ignoring the graphene layer 10), the first gate 111 may be etched back using a dry etching process or a wet etching process such that the top surface of the first gate 111 is located at the first position described above, i.e., between the first barrier layer 4 and the second barrier layer 6.
In some embodiments, the material of the first gate 111 may be Ni.
B3: a second gate 112 is formed on the first gate 111.
As shown in fig. 14 (ignoring the graphene layer 10), a second gate electrode 112 is formed in the filling space S where the first gate electrode 111 is formed using a deposition process. While a second gate electrode 112 is deposited on the gate oxide layer 9 outside the filling space S.
In some embodiments, the material of the second gate 112 may be TiN.
The different materials are selected for the first gate 111 and the second gate 112, so that the inter-band tunneling effect of the semiconductor structure can be reduced, the subthreshold slope is close to an ideal value, and the ratio of the on-off currents is increased.
And since the gate oxide layer 9 is made of a high-K dielectric material, such as TiO 2 Or HfO 2 The material of the first gate 111 is Ni, and the material of the second gate 112 is TiN, so that the hetero-interface work function of the gate 11 and the gate oxide layer 9 can be adjusted, and the electrical performance of the semiconductor structure can be improved.
In some embodiments, as shown in fig. 11, after forming the gate oxide layer 9, the preparation method further includes: a graphene layer 10 is formed on the gate oxide layer 9, and the gate electrode 11 is filled in the remaining space of the filling space S in which the graphene layer 10 is formed.
Specifically, as shown in fig. 11, a graphene layer 10 may be conformally formed on the gate oxide layer 9 using a deposition process (may be an atomic layer deposition process, for example), and the gate electrode 11 is formed to be filled in the remaining space of the filling space S where the graphene layer 10 is formed, such that the graphene layer 10 is located between the gate electrode 11 and the gate oxide layer 9.
A graphene layer 10 is formed between the gate electrode 11 and the gate oxide layer 9, which corresponds to an interface control layer interposed between the gate electrode 11 and the gate oxide layer 9, thereby improving Ni/HfO 2 The quality of the whole system reduces point defects at the interface, and further effectively adjusts the interface work functions of the grid electrode 11, the graphene layer 10 and the grid oxide layer 9.
On the basis of the above-described embodiment of forming the graphene layer 10, S160 may further include the following contents C1 to C3.
C1: the first gate electrode 111 is formed in the remaining space of the filling space S where the graphene layer 10 is formed.
As shown in fig. 12, the first gate electrode 111 may be formed by deposition in the filling space S using a deposition process. The filling space S has a first position between the first barrier layer 4 and the second barrier layer 6 in the vertical direction Y, and the height of the first gate 111 is greater than the height of the first position in the vertical direction Y, i.e., the top surface of the first gate 111 is located above the first position.
C2: the first gate 111 is etched back such that the top surface of the first gate 111 is located between the first barrier layer 4 and the second barrier layer 6.
As shown in fig. 13, the first gate 111 may be etched back using a dry etching process or a wet etching process such that the top surface of the first gate 111 is located at the first position described above, i.e., between the first barrier layer 4 and the second barrier layer 6.
In some embodiments, the material of the first gate 111 may be Ni.
And C3: a second gate 112 is formed on the first gate 111.
As shown in fig. 14, the second gate electrode 112 is formed in the filling space S where the first gate electrode 111 is formed using a deposition process. While a second gate electrode 112 is deposited on the gate oxide layer 9 outside the filling space S.
In some embodiments, the material of the second gate 112 may be TiN.
As shown in fig. 15, after the second gate electrode 112 is formed, the oxide semiconductor layer 8, the gate oxide layer 9, and the second gate electrode 112, which are partially over the second electrode layer 7, may be removed using an etching process to form transistors separated from each other. In some embodiments, the removed portions of the oxide semiconductor layer 8, the gate oxide layer 9, and the second gate 112 may be filled with an insulating isolation material in a subsequent process to form a shallow trench isolation (Shallow Trench Isolation, STI) structure.
In summary, in the method for manufacturing a semiconductor structure according to the embodiments of the present disclosure, the first barrier layer 4 and the second barrier layer 6 are formed between the first electrode layer 3 and the second electrode layer 7, and surround the oxide semiconductor layer 8, when annealing is performed after the oxide semiconductor layer 8 is formed, the defect density of the oxide semiconductor layer 8 can be reduced, and then the off-state current is reduced, and meanwhile, the contact resistance between the first electrode layer 3 and the oxide semiconductor layer 8, and between the second electrode layer 7 and the oxide semiconductor layer 8 is reduced, so that the on-state current is improved, and therefore, the ratio of the on-state current to the off-state current can be improved, and the electrical performance of the semiconductor structure is improved.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the disclosure. The disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a semiconductor substrate;
a first electrode layer, a first barrier layer, a support layer, a second barrier layer, and a second electrode layer sequentially stacked in a vertical direction on the semiconductor substrate; wherein the first electrode layer, the first barrier layer, the support layer, the second barrier layer and the second electrode layer have a filling space therein, the filling space extending from a top surface of the second electrode layer into the first electrode layer along the vertical direction;
an oxide semiconductor layer located on an inner wall of the filling space;
a gate oxide layer on the oxide semiconductor layer;
and the grid electrode is positioned in the filling space between the grid oxide layers.
2. The semiconductor structure of claim 1, further comprising:
and the graphene layer is positioned between the grid electrode and the grid oxide layer.
3. The semiconductor structure of claim 1, wherein the gate comprises:
a first gate electrode located in the filling space between the gate oxide layers and extending from the bottom of the filling space to a position between the first barrier layer and the second barrier layer;
and the second grid electrode is positioned in the filling space on the first grid electrode.
4. The semiconductor structure of claim 1, wherein the gate oxide layer comprises a high-K dielectric material comprising TiO 2 And HfO 2 At least one of them.
5. The semiconductor structure of claim 1, wherein the material of the first barrier layer and the material of the second barrier layer each comprise Si 3 N 4 。
6. The semiconductor structure of any one of claims 1-5, wherein a projection of the first electrode layer onto the semiconductor substrate is within a projection of the first barrier layer onto the semiconductor substrate and a projection of the second electrode layer onto the semiconductor substrate is within a projection of the second barrier layer onto the semiconductor substrate in the vertical direction.
7. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate;
forming a first electrode layer, a first barrier layer, a support layer, a second barrier layer and a second electrode layer stacked in order in a vertical direction on the semiconductor substrate;
forming a filling space in the first electrode layer, the first barrier layer, the support layer, the second barrier layer and the second electrode layer, the filling space extending from a top surface of the second electrode layer into the first electrode layer in the vertical direction;
forming an oxide semiconductor layer on an inner wall of the filling space;
forming a gate oxide layer on the oxide semiconductor layer;
and filling and forming a gate in the residual space of the filling space in which the gate oxide layer is formed.
8. The method of claim 7, wherein after forming the gate oxide layer, the method further comprises:
forming a graphene layer on the gate oxide layer;
and filling and forming the grid electrode in the residual space of the filling space formed with the graphene layer.
9. The method according to claim 7 or 8, wherein filling the remaining space of the filling space to form the gate electrode includes:
forming a first gate in a remaining space of the filling space;
etching back the first gate such that a top surface of the first gate is located between the first barrier layer and the second barrier layer;
a second gate is formed on the first gate.
10. The method according to claim 7 or 8, wherein forming a first electrode layer, a first barrier layer, a support layer, a second barrier layer, and a second electrode layer stacked in this order in a vertical direction on the semiconductor substrate, comprises:
forming an oxide layer on the semiconductor substrate;
etching back the oxide layer to form an accommodating space;
forming the first electrode layer in the accommodating space such that a top surface of the first electrode layer is flush with the oxide layer;
forming the first barrier layer on the first electrode layer and on the oxide layer;
forming the support layer on the oxide layer and on the first barrier layer;
forming the second barrier layer on the support;
the second electrode layer is formed on the second barrier layer.
CN202310450456.7A 2023-04-23 2023-04-23 Semiconductor structure and preparation method thereof Pending CN116387364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310450456.7A CN116387364A (en) 2023-04-23 2023-04-23 Semiconductor structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310450456.7A CN116387364A (en) 2023-04-23 2023-04-23 Semiconductor structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116387364A true CN116387364A (en) 2023-07-04

Family

ID=86978813

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310450456.7A Pending CN116387364A (en) 2023-04-23 2023-04-23 Semiconductor structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116387364A (en)

Similar Documents

Publication Publication Date Title
US10103152B2 (en) Semiconductor device and method for fabricating the same
US8716120B2 (en) High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology
CN102498569B (en) Dual dielectric tri-gate field effect transistor
TWI552354B (en) Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
US8729617B2 (en) Semiconductor memory device and method for manufacturing the same
JP2007243105A (en) Semiconductor device and method for manufacturing the same
CN101442074B (en) Trench MOSFET and manufacturing method thereof
EP1697982A1 (en) Method of manufacturing a trench-gate semiconductor device
US11588034B2 (en) Field effect transistor including gate insulating layer formed of two-dimensional material
US6975001B2 (en) Semiconductor device and method of fabricating the same
CN112466945A (en) Semiconductor structure and forming method thereof
US20210343846A1 (en) Method for manufacturing buried gate and method for manufacturing semiconductor device
CN113782534A (en) Semiconductor structure, manufacturing method thereof and memory
CN110880472A (en) Semiconductor device with shallow trench isolation structure and preparation method thereof
US7851329B2 (en) Semiconductor device having EDMOS transistor and method for manufacturing the same
JP5170958B2 (en) Field effect transistor and manufacturing method thereof
US8455308B2 (en) Fully-depleted SON
CN116387364A (en) Semiconductor structure and preparation method thereof
CN111508841A (en) Semiconductor structure and manufacturing method thereof
KR20170066914A (en) Semiconductor device and Method for fabricating the same
WO2022016985A1 (en) Buried gate electrode and manufacturing method therefor
CN115274670A (en) Semiconductor structure, manufacturing method thereof and memory
US20190088488A1 (en) Method for manufacturing semiconductor device
CN113643971B (en) Preparation method of buried gate structure and buried gate structure
CN115117160B (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination