CN116386556A

CN116386556A - Driving circuit of display panel

Info

Publication number: CN116386556A
Application number: CN202211736818.0A
Authority: CN
Inventors: 苏忠信
Original assignee: Sitronix Technology Corp
Current assignee: Sitronix Technology Corp
Priority date: 2022-12-31
Filing date: 2022-12-31
Publication date: 2023-07-04

Abstract

The invention provides a driving circuit of a display panel, which comprises a driving signal generating circuit for generating a driving signal in a frame period to drive a display element of the display panel, wherein the driving signal has at least one first on pulse width, at least one first off pulse width, at least one second on pulse width and at least one second off pulse width, the first on pulse width is larger than the second on pulse width, and the first off pulse width is smaller than the second off pulse width. The driver can reduce electromagnetic interference and improve display quality.

Description

Driving circuit of display panel

Technical Field

The present invention relates to a driving circuit, and more particularly to a driving circuit for a display panel.

Background

The display device has become an essential equipment of electronic products for displaying information. Display devices have evolved from liquid crystal display devices to sub-millimeter light emitting diode (Mini LED) display devices and Micro light emitting diode (Micro LED) display devices. The LED is used as a display element, so that the display quality of the display device can be improved. The known technique of driving the light emitting diode causes high electromagnetic interference (Electromagnetic Interference, EMI), which affects the display quality.

In view of the above, the present invention provides a driving circuit for a display panel, which can reduce EMI and improve display quality.

Disclosure of Invention

An objective of the present invention is to provide a driving circuit of a display panel, which converts the frequency of a driving signal for driving a display element during a frame period, so as to reduce electromagnetic interference and improve display quality.

The invention provides a driving circuit of a display panel, which comprises a driving signal generating circuit, wherein the driving signal generating circuit generates a driving signal in a frame period to drive a display element of the display panel, and the driving signal is provided with at least one first pulse width, at least one second pulse width and at least one third pulse width, the first pulse width is larger than the second pulse width and the third pulse width, and the second pulse width is larger than the third pulse width. The driving signal generating circuit generates a second pulse width at a time within the frame period, and then generates a first pulse width or a third pulse width.

The invention further provides a driving circuit of a display panel, which comprises a driving signal generating circuit, wherein the driving signal generating circuit generates a driving signal in a frame period to drive a display element of the display panel, the driving signal has at least one first on pulse width, at least one first off pulse width, at least one second on pulse width and at least one second off pulse width, the first on pulse width is larger than the second on pulse width, and the first off pulse width is smaller than the second off pulse width.

The invention also provides a driving circuit of a display panel, which comprises a driving signal generating circuit, wherein the driving signal generating circuit generates a driving signal with a plurality of first pulse widths in an F-1 frame period to drive a display element of the display panel, and generates a driving signal with a plurality of second pulse widths in an F frame period to drive the display element. The second pulse widths are different from the first pulse widths, the time during the F-1 frame and the time during the F frame are the same, and F is an integer greater than 2.

Drawings

FIG. 1 is a schematic diagram of a driving architecture according to an embodiment of the present invention;

FIG. 2 is a block diagram of a driver and display device according to an embodiment of the present invention;

FIG. 3 is a block diagram of one embodiment of a controller and driver according to the present invention;

FIG. 4 is a block diagram of a driving circuit according to an embodiment of the invention;

FIG. 5 is a schematic diagram of a first embodiment of a driving signal;

FIG. 6 is a diagram of a second embodiment of a driving signal;

FIG. 7 is a diagram of a third embodiment of a driving signal;

FIG. 8 is a diagram of a fourth embodiment of a driving signal;

FIG. 9 is a schematic diagram of a fifth embodiment of a driving signal;

FIG. 10 is a diagram of a sixth embodiment of a driving signal;

fig. 11 to 13 are schematic diagrams of seventh to ninth embodiments of driving signals, respectively.

Detailed Description

For a further understanding and appreciation of the features and advantages of the invention, and in view of the description of the embodiments and the accompanying drawings, the description will be as follows:

certain terms are used throughout the description and claims to refer to particular components, however, it will be appreciated by those skilled in the art that manufacturers may refer to a component by different names, and that the description and claims do not rely on differences in names to distinguish between components, but rather use differences in the overall technology of the components as a distinguishing criterion. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" as used herein includes any direct or indirect connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.

Please refer to a first diagram and a second diagram, wherein the first diagram is a schematic diagram of an embodiment of a driving architecture of the present invention, and the second diagram is a block diagram of an embodiment of a driver and a display device of the present invention. As shown in the figure, the driving architecture includes a controller 1 and a plurality of drivers 2 for driving a plurality of pixels of the display panel 10 to display images. The drivers 2 are arranged in a plurality of rows, and each driver 2 is coupled to a plurality of display elements 4 to drive the display elements 4 to emit light. In an embodiment of the present invention, the display elements 4 may be sub-millimeter leds or micro-leds. The controller 1 is coupled to the drivers 2 and transmits an input data Din, a timing signal DCK, a clock signal PWMCLK and an enable signal EN to the drivers 2. In an embodiment of the present invention, the controller 1 may be a separate chip. Since the drivers 2 are arranged in a plurality of rows, the pixels arranged in rows and columns on the display panel 10 can be controlled.

Please refer to a third diagram illustrating an embodiment of a controller and driver according to the present invention. As shown, each driver 2 includes an enable circuit 6, a storage circuit 7, and a driving circuit 9. The enable circuit 6 receives the enable signal EN, and the enable storage circuit 7 receives the input data Din according to the timing signal DCK according to the enable signal EN. The driving circuit 9 is coupled to the storage circuit 7 and the display elements 4, and generates a plurality of driving signals according to the input data Din and the clock signal PWMCLK received by the storage circuit 7 to drive the display elements 4 to generate light, so as to display images. After the first driver 2 drives the display elements 4, the enable circuit 6 of the first driver 2 disables the storage circuit 7 of the first driver 2 and sends the enable signal EN to the enable circuit 6 of the second driver 2 to perform the above-mentioned operations, thereby driving the display elements 4 coupled to the second driver 2, and so on.

Please refer to a fourth diagram, which is a block diagram of an embodiment of the driving circuit of the present invention. As shown in the figure, the storage circuit 7 is coupled to the enable circuit 6 and receives the input data Din and a timing signal DCK, and the enable circuit 6 enables the storage circuit 7 according to the received enable signal, drives the storage circuit 7 to receive the input data Din according to the timing signal DCK, and stores the input data Din. The driving circuit 9 includes a driving signal generating circuit including a plurality of comparing circuits 91, a counter 93, and a plurality of level converting circuits 95. The comparing circuits 91 are coupled to the storage circuit 7 and the counter 93. The counter 93 receives the clock signal PWMCLK and outputs a count signal according to the count of the clock signal PWMCLK, the count signal being changed according to the count of the counter 93. Each comparison circuit 91 receives the count signal and the pixel data of the input data Din stored in the storage circuit 7, and compares the count signal with the pixel data, and when the pixel data is larger than the count signal, the comparison circuit 281 outputs a driving signal with a driving level, such as a high level. In another embodiment of the present invention, when the pixel data is smaller than the count signal, the comparison circuit 91 outputs the driving signal with the driving level. The level conversion circuits 95 are coupled to the comparison circuits 91 and convert the driving signals outputted from the comparison circuits 91. In one embodiment of the present invention, the level shifter 95 may not be required. One end of the display elements 4 is coupled to a supply voltage VDD, a switch MOS is coupled between the other end of the display elements R, G, B and a ground, and a driving signal generated by the comparing circuit 9 is used to control the switch MOS to drive current to flow through the display elements 4 to generate light. As can be seen from the above description, the time for the comparison circuit 91 to continuously generate the driving level of the driving signal is the driving time, i.e. the driving time of the display device 4, which determines the brightness of the display device 4.

Please refer to a fifth diagram, which is a schematic diagram of an embodiment of the driving signal. As shown, the driving signal has a turn-on pulse width (high level) and a turn-off pulse width (low level) in one frame period, and the turn-on pulse width determines the time of generating light from the display device 4.

Please refer to a sixth diagram, which is a schematic diagram of another embodiment of the driving signal. As shown in the figure, the driving signal has a plurality of on pulse widths and a plurality of off pulse widths in one frame period, and the driving signal shown in the sixth figure is superior to the driving signal shown in the fifth figure, which can reduce the flicker phenomenon of the display element 4. The display element is driven to display for 0.1 second, and the frame period is 0.2 second, and the display element is driven to continuously light for 0.1 second and not light for 0.1 second when the driving signal of the fifth diagram is driven, so that flicker is easily generated. If the driving signal shown in the sixth graph has 10 pulse widths, that is, 0.1 second is divided into 10 pulse widths, the display device is driven to display for 0.01 second, so that the display device is still bright for 0.1 second during the frame period, but flicker can be reduced. However, there is a higher electromagnetic interference to drive the display device with the same width of the on pulse.

Please refer to a seventh diagram, which is a schematic diagram of a third embodiment of the driving signal. As shown in the drawing, the driving circuit 9 generates a driving signal in a frame period, the driving signal has a plurality of first pulse widths and a plurality of second pulse widths, the first pulse widths are larger than the second pulse widths, which indicates that the frequency of the clock signal PWMCLK received by the driving circuit 9 is the first frequency f1 or the second frequency f2, the driving circuit 9 generates the first pulse widths according to the clock signal PWMCLK having the first frequency, and generates the second pulse widths according to the clock signal PWMCLK having the second frequency. The first frequency f1 is smaller than the second frequency f2. Since the frequency of the driving signal is changed within one frame period, the electromagnetic interference can be reduced. The counter 91 counts based on a fixed number of clocks to generate a first pulse width and a second pulse width, e.g., the counter 91 counts again each time the clock PWMCLK is counted to 4096.

Please refer to an eighth diagram, which is a diagram of a fourth embodiment of the driving signal. As shown in the drawing, the driving circuit 9 generates a driving signal in a frame period, the driving signal has a plurality of first pulse widths, a plurality of second pulse widths, and a plurality of third pulse widths, the first pulse widths are larger than the second pulse widths and the third pulse widths, the second pulse widths are larger than the third pulse widths, which indicates that the frequency of the clock signal PWMCLK received by the driving circuit 9 is the first frequency f1, the second frequency f2, or the third frequency f3, the driving circuit 9 generates the first pulse widths according to the clock signal PWMCLK having the first frequency f1, and generates the second pulse widths according to the clock signal PWMCLK having the second frequency f2, and the driving circuit 9 generates the third pulse widths according to the clock signal PWMCLK having the third frequency f 3. The first frequency f1 is smaller than the second frequency f2 and the third frequency f3, and the third frequency f3 is smaller than the second frequency f2. In an embodiment of the present invention, at a certain time in the frame period, the second pulse width is generated first, and then the first pulse width or the third pulse width is generated, that is, the second pulse width is generated according to the second frequency, and then the first pulse width or the third pulse width is generated according to the first frequency or the third frequency. The counter 91 counts based on a fixed number of clocks to generate a third pulse width.

In an embodiment of the invention, the driving signal generating circuit sequentially generates N first pulse widths of the first pulse widths, P second pulse widths of the second pulse widths, and Q third pulse widths of the third pulse widths within the frame period and outside a certain time, wherein N, P, Q is an integer greater than 0, i.e., the first, second or third pulse widths can be continuously generated. Or, Q third pulse widths of the third pulse widths, P second pulse widths of the second pulse widths and N first pulse widths of the first pulse widths are sequentially generated.

The driving circuit 9 of the present invention generates driving signals in a plurality of frame periods, and the time of the frame periods is the same, the driving signals have at least one of the first, second and third pulse widths. That is, a driving signal is generated in an F-1 frame period, an F frame period, and an f+1 frame period, the driving signal having at least one of a first pulse width, a second pulse width, and a third pulse width, the time of the F-1 frame period, the time of the F frame period, and the time of the f+1 frame period being the same, and F being an integer greater than 2.

Please refer to a ninth diagram, which is a diagram of a fifth embodiment of the driving signal. As shown, during a frame period, the frequency of the clock signal PWMCLK is changed from the first frequency f1 to the second frequency f2 over time, and then changed from the second frequency f2 to the first frequency f1 over time, such that the driving circuit generates the first on pulse width and the first off pulse width according to the clock signal PWMCLK during the period when the frequency of the clock signal PWMCLK is changed from the first frequency f1 to the second frequency f1, and generates the second on pulse width and the second off pulse width according to the clock signal PWMCLK during the period when the frequency of the clock signal PWMCLK is changed from the second frequency f2 to the first frequency f 1. The first on pulse width is greater than the second on pulse width, and the first off pulse width is less than the second off pulse width. The first on pulse width is equal to the second off pulse width, and the second on pulse width is equal to the first off pulse width. The first on pulse width is equal to the second off pulse width, and the second on pulse width is equal to the first off pulse width. The counter 91 counts based on a fixed number of clocks to generate a first on pulse width, a first off pulse width, a second on pulse width, and a second off pulse width.

Please refer to a tenth diagram, which is a schematic diagram of a sixth embodiment of a driving signal. As shown in the figure, during a frame period, the frequency of the clock signal PWMCLK is changed from the first frequency f1 to the third frequency f3, then to the second frequency f2, then to the third frequency f3, and then to the first frequency f1, so that the driving circuit generates a driving signal with a variable pulse width, which is similar to the embodiment of the ninth figure.

Referring to the eleventh to thirteenth embodiments, the driving circuit 9 of the present invention generates driving signals in a plurality of frame periods, and the frame periods have the same time to drive the same display device, the driving signals generated in each frame period have the same pulse width, but the pulse widths in different frame periods are different, which means that the driving circuit generates the driving signals in different frame periods according to the three clock signals PWMCLK with different frequencies. For example, the eleventh diagram is in the frame F-1, the twelfth diagram is in the frame F, the thirteenth diagram is in the frame f+1, the driving signals respectively have the first pulse width, the second pulse width and the third pulse width, the time of the frame F-1, the time of the frame F and the time of the frame f+1 are the same, and F is an integer greater than 2.

However, the foregoing description is only one embodiment of the present invention and is not intended to limit the scope of the present invention, so equivalent changes and modifications in terms of structure, characteristics and spirit of the present invention are intended to be included in the scope of the present invention.

Claims

1. A driving circuit of a display panel, comprising:

a driving signal generating circuit for generating a driving signal in a frame period to drive a display element of the display panel, wherein the driving signal has at least one first pulse width, at least one second pulse width and at least one third pulse width, the first pulse width is larger than the second pulse width and the third pulse width, and the second pulse width is larger than the third pulse width;

the driving signal generating circuit generates the second pulse width at a time within the frame period, and then generates the first pulse width or the third pulse width.

2. The driving circuit of claim 1, wherein the driving signal generating circuit generates the second pulse width first, then generates the first pulse width, and then generates the third pulse width during the time of the frame.

3. The driving circuit of claim 1, wherein the driving signal generating circuit generates the second pulse width first, then generates the third pulse width, and then generates the first pulse width during the time of the frame.

4. The driving circuit of claim 1, wherein the driving signal generating circuit generates the first pulse width, the second pulse width and the third pulse width according to a fixed number of a plurality of clocks.

5. The driving circuit of claim 4, wherein the driving signal generating circuit generates the driving signal according to a clock signal, the clock signal having a plurality of clocks, the clock signal having a frequency of a first frequency, a second frequency or a third frequency, the driving signal generating circuit generating the first pulse width according to the clock signal having the first frequency, the second pulse width according to the clock signal having the second frequency, and the third pulse width according to the clock signal having the third frequency.

6. The driving circuit of claim 1, wherein the at least one first pulse width comprises a plurality of first pulse widths, the at least one second pulse width comprises a plurality of second pulse widths, the at least one third pulse width comprises a plurality of third pulse widths, the driving signal generating circuit sequentially generates N first pulse widths of the first pulse widths, P second pulse widths of the second pulse widths, Q third pulse widths of the third pulse widths within the frame period and outside the frame period, N, P, Q is greater than an integer of 0.

7. The driving circuit of claim 1, wherein the at least one first pulse width comprises a plurality of first pulse widths, the at least one second pulse width comprises a plurality of second pulse widths, the at least one third pulse width comprises a plurality of third pulse widths, the driving signal generating circuit sequentially generates Q third pulse widths of the third pulse widths, P second pulse widths of the second pulse widths, N first pulse widths of the first pulse widths within the frame period and outside the frame period, N, P, Q is an integer greater than 0.

8. The driving circuit of claim 1, wherein the frame period is an F-1 frame period, the driving signal generating circuit generates the driving signal in an F-1 frame period and an f+1 frame period, the driving signal having at least one of the first pulse width, the second pulse width and the third pulse width, the time of the F-1 frame period, the time of the F frame period and the time of the f+1 frame period being the same, F being an integer greater than 2.

9. A driving circuit of a display panel, comprising:

the driving signal generating circuit generates a driving signal in a frame period to drive a display element of the display panel, wherein the driving signal has at least one first on pulse width, at least one first off pulse width, at least one second on pulse width and at least one second off pulse width, the first on pulse width is larger than the second on pulse width, and the first off pulse width is smaller than the second off pulse width.

10. The driving circuit of claim 9, wherein the first on pulse width is equal to the second off pulse width, and the second on pulse width is equal to the first off pulse width.

11. The driving circuit of claim 9, wherein the first on pulse width is equal to the second off pulse width, and the second on pulse width is equal to the first off pulse width.

12. The driving circuit of claim 9, wherein the driving signal generating circuit generates the first pulse width and the second pulse width according to a fixed number of a plurality of clocks.

13. The driving circuit of claim 12, wherein the driving signal generating circuit generates the driving signal according to a clock signal, the clock signal has a plurality of clocks, a frequency of the clock signal is changed from a first frequency to a second frequency over time, and then is changed from the second frequency to the first frequency over time, the second frequency is higher than the first frequency, during the period that the frequency of the clock signal is changed from the first frequency to the second frequency, the driving signal generating circuit generates the first on pulse width and the first off pulse width according to the clock signal, and during the period that the frequency of the clock signal is changed from the second frequency to the first frequency, the second on pulse width and the second off pulse width according to the clock signal.

14. A driving circuit of a display panel, comprising:

a driving signal generating circuit for generating a driving signal having a plurality of first pulse widths to drive a display element of the display panel during an F-1 frame period and generating the driving signal having a plurality of second pulse widths to drive the display element during an F frame period;

the second pulse widths are different from the first pulse widths, the time of the F-1 frame period and the time of the F frame period are the same, and F is an integer greater than 2.

15. The driving circuit of claim 14, wherein the driving signal generating circuit generates the driving signal having a plurality of third pulse widths in an f+1 frame period to drive the display device, the third pulse widths being different from the first pulse widths and the second pulse widths, the time during the F-1 frame period, the time during the F frame period, and the time during the f+1 frame period being the same.

16. The driving circuit of claim 15, wherein the driving signal generating circuit generates the first pulse widths, the second pulse widths, and the third pulse widths according to a fixed number of clocks.

17. The driving circuit of claim 16, wherein the driving signal generating circuit generates the driving signal according to a clock signal, the clock signal having a plurality of clocks, the clock signal having a frequency of a first frequency, a second frequency or a third frequency, the driving signal generating circuit generating the first pulse widths according to the clock signal having the first frequency, the second pulse widths according to the clock signal having the second frequency, and the third pulse widths according to the clock signal having the third frequency.