CN116383584A - Model calculation method, system and storage medium based on fractional order system - Google Patents
Model calculation method, system and storage medium based on fractional order system Download PDFInfo
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Abstract
The application discloses a model calculation method, a system and a storage medium based on a fractional order system, which relate to the technical field of FPGA hardware control, wherein the method comprises the following steps: acquiring a first state signal, a fractional step length and an order vector at the current moment, and performing array calculation according to the first state signal, the fractional step length, the order vector and a preset model dimension at the current moment to obtain a differential signal; acquiring a control input signal at the current moment, and performing matrix multiplication calculation according to the control input signal at the current moment, a first state signal, a preset first state space matrix, a second state space matrix and a discrete step length vector to obtain a state differential signal; and performing matrix four-rule calculation according to the first state signal, the control input signal, the preset third state space matrix and the preset fourth state space matrix at the current moment to obtain a system output signal. The model calculation method based on the fractional order system can effectively improve the calculation efficiency.
Description
Technical Field
The present application relates to the field of FPGA hardware control technologies, and in particular, to a method, a system, and a storage medium for model calculation based on a fractional order system
Background
The fractional order system is widely applied to the fields of economy, biological medicine, chemical synthesis, signal safety and the like due to the characteristics of global property and long-time memory, the hardware circuit implementation of the multi-element fractional order state space model is a premise that the fractional order system is applied to more process practice, but a large number of logic operations exist in the multi-element fractional order state space model, and in the related art, the computation is usually carried out in a pipeline mode on a large number of logic operations corresponding to the multi-element fractional order state space model, so that the computation efficiency is low in the computation mode, and therefore, a computation method is needed to be capable of improving the computation efficiency of the model of the fractional order system.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the method, the system and the storage medium for calculating the model based on the fractional order system can effectively improve the calculation efficiency.
In order to solve the technical problems, the application provides the following technical scheme:
an embodiment of a first aspect of the present application provides a method for calculating a model based on a fractional order system, which is applied to a fractional order system model, and includes:
acquiring a first state signal, a fractional step length and an order vector at the current moment, and performing array calculation according to the first state signal, the fractional step length, the order vector and a preset model dimension at the current moment to obtain a differential signal;
Acquiring a control input signal at the current moment, and performing matrix multiplication calculation according to the control input signal at the current moment, the first state signal, a preset first state space matrix, a preset second state space matrix and a preset discrete step length vector to obtain a state differential signal;
performing matrix four-rule calculation according to the first state signal, the control input signal, a preset third state space matrix and a preset fourth state space matrix at the current moment to obtain a system output signal; the array calculation, the matrix multiplication calculation and the matrix four calculation are executed in parallel;
subtracting the differential signal from the state differential signal to obtain a second state signal;
outputting the second state signal and the system output signal as a fractional order model at the current moment;
and taking the second state signal as a first state signal input at the next moment to perform array calculation and matrix multiplication calculation.
The model calculation method based on the fractional order system according to the embodiment of the first aspect of the application has at least the following beneficial effects: according to the model calculation method based on the fractional order system, the model of the fractional order system is split into three parts, and the three parts are subjected to parallel operation, so that the second state signal and the system output signal can be synchronously calculated and obtained while differential signals are calculated according to the fractional order step length, the order vector and the second state signal.
According to some embodiments of the first aspect of the present application, the performing array calculation according to the first state signal, the fractional step size, the order vector and a preset model dimension at the current moment to obtain a differential signal includes:
performing addition calculation, multiplication calculation and subtraction calculation on the fractional step length and the order vector to obtain a quadratic term coefficient;
according to the time interval between a discrete step length computing system input signal and the system input signal, multiplying the system input signal and the quadratic term coefficient to obtain a first calculus operator at the current moment; the discrete step size is obtained by squaring the discrete step size vector and the order vector;
accumulating the first calculus operator at the current moment and the first calculus operator obtained by calculation at the previous moment to obtain a current calculus operator;
and calculating the order vector, the current calculus operator, the model dimension and the first state signal to obtain a differential signal at the current moment.
According to some embodiments of the first aspect of the present application, the performing addition, multiplication and subtraction on the fractional step size and the order vector to obtain a quadratic coefficient includes:
Executing counting operation according to the fractional step length and a preset starting signal, and calculating the fractional step length to obtain a calculation factor;
and carrying out addition calculation, multiplication calculation and subtraction calculation on the calculation factors, the order vectors and preset input values to obtain quadratic term coefficients.
According to some embodiments of the first aspect of the present application, the performing array calculation according to the first state signal, the fractional step length, the order vector and a preset model dimension at the current moment to obtain a differential signal further includes:
updating and calculating the order vector to obtain a plurality of quadratic term fitting coefficients;
selecting a limited window length according to the convergence degree of a plurality of quadratic term fitting coefficients, and respectively performing accumulation calculation, mean value calculation and multiplication calculation according to the limited window length, a plurality of quadratic term fitting coefficients, the system input signal and the discrete step length to obtain an error compensation signal;
and carrying out error compensation on the differential signal according to the error compensation signal.
According to some embodiments of the first aspect of the present application, the performing matrix multiplication calculation according to the control input signal, the first state signal, and a preset first state space matrix, a second state space matrix, and a discrete step vector at the current time to obtain a state differential signal includes:
Performing cross multiplication and addition calculation on the first state space matrix, the first state signal, the second state space matrix and the control input signal to obtain a matrix multiplication signal;
and performing point multiplication calculation on the matrix multiplication signal and the discrete step length vector to obtain a state differential signal.
An embodiment of a second aspect of the present application provides an FPGA-based state space model system including a plurality of input ports, the FPGA-based state space model system including:
the array module is used for acquiring a first state signal, a fractional step length and an order vector input by one of the input ports at the current moment, and performing array calculation according to the first state signal, the fractional step length, the order vector and a preset model dimension at the current moment to obtain a differential signal;
the matrix module is connected with the array module and is used for acquiring the differential signal, a first state signal input by one input port at the current moment and a control input signal input by the other input port, and respectively carrying out matrix multiplication calculation and matrix four-rule calculation according to the differential signal, the first state signal, the control input signal, a preset first state space matrix, a second state space matrix, a third state space matrix, a fourth state space matrix and a discrete step size vector to obtain a second state signal and a system output signal, wherein the matrix calculation, the matrix multiplication calculation and the matrix four-rule calculation are executed in parallel.
According to some embodiments of the second aspect of the present application, the matrix module comprises:
the first state differential arithmetic unit is used for performing matrix cross multiplication calculation and addition calculation according to the control input signal, the first state space matrix and the second state space matrix to obtain a matrix multiplication signal;
the first state differential operator is electrically connected with the second state differential operator and is used for performing point multiplication calculation according to the matrix multiplication signal and the discrete step-length vector to obtain a state differential signal;
and the third state differential arithmetic unit is used for performing matrix cross multiplication calculation and addition calculation according to the first state signal, the control input signal, the third state space matrix and the fourth state space matrix to obtain a system output signal.
According to some embodiments of the second aspect of the present application, the FPGA-based state space model system further comprises:
the subtracter is electrically connected with the output port of the array module and the output port of the matrix module and is used for performing subtraction calculation according to the differential signal and the state differential signal to obtain the second state signal;
The fractional order system output end is connected with the subtracter and the third state differential arithmetic unit and is used for outputting the second state signal and the system output signal as a fractional order model at the current moment;
the selection register is connected with the fractional order system output end, the input end of the array module and the input end of the matrix module, and the selection register is used for taking the second state signal as a first state signal input at the next moment to perform array calculation and matrix multiplication calculation.
An embodiment of a third aspect of the present application provides an electronic device, including:
at least one memory;
at least one processor;
at least one program;
the program is stored in the memory, and the processor executes at least one of the programs to implement the fractional order system based model calculation method according to any one of the embodiments of the first aspect of the present application.
Embodiments of a fourth aspect of the present application provide a computer-readable storage medium storing a computer-executable signal for performing a fractional order system-based model calculation method according to any one of the embodiments of the first aspect of the present application.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
Additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a main flow chart of a model calculation method based on a fractional order system according to an embodiment of the present application;
FIG. 2 is a sub-flowchart of a fractional order system-based model calculation method according to an embodiment of the present application;
FIG. 3 is a sub-flowchart of a fractional order system-based model calculation method according to an embodiment of the present application;
FIG. 4 is a sub-flowchart of a fractional order system-based model calculation method according to an embodiment of the present application;
FIG. 5 is a sub-flowchart of a fractional order system-based model calculation method according to an embodiment of the present application;
FIG. 6 is a schematic structural diagram of a FPGA-based state space model system according to an embodiment of the present application;
FIG. 7 is a schematic block diagram of the interior of an FPGA-based state space model system according to one embodiment of the present application;
FIG. 8 is a schematic block diagram of the inside of a serial output device according to an embodiment of the present disclosure;
FIG. 9 is a schematic block diagram of the inside of a fractional order operator device according to an embodiment of the present application;
fig. 10 is a block diagram of an electronic device according to an embodiment of the present application.
Reference numerals: an array module 1000; fractional order operator means 1100; a serial output section 1110; a calculation factor program 1111; a multiplier 1112; adder 1113; a binomial coefficient register 1120; a first data buffer 1130; a second data buffer 1140; a matrix multiplication module 2000; a first state differential operator 2100; a second state differential operator 2200; a third state differential operator 2300; a processor 3000; memory 4000.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It should be noted that although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different from that in the flowchart. The terms and the like in the description and in the claims, and in the above-described drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In the description of the present application, the description of the first and second is only for the purpose of distinguishing technical features, and should not be construed as indicating or implying relative importance or implying the number of technical features indicated or the precedence of the technical features indicated.
In the description of the present application, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present application can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical solution.
It can be understood that the fractional order system is widely applied to the fields of economy, biological medicine, chemical synthesis, signal safety and the like due to the characteristics of global property and long-term memory, the implementation of the hardware circuit of the multi-element fractional order state space model is the premise that the fractional order system is applied to more process practice, but a great amount of logic operation exists in the multi-element fractional order state space model, meanwhile, in order to ensure the accuracy of the logic operation, the processing period of the hardware circuit is greatly increased, so that limited logic resources are wasted, and the calculation efficiency is reduced.
Referring to fig. 1, in a first aspect, an embodiment of the present application provides a fractional system-based model calculation method, which is applied to a fractional system model, including but not limited to step S110, step S120, step S130, step S140, step S150, and step S160.
Step S110, a first state signal, a fractional step length and an order vector at the current moment are obtained, and array calculation is carried out according to the first state signal, the fractional step length, the order vector and a preset model dimension at the current moment to obtain a differential signal;
step S120, a control input signal at the current moment is obtained, and matrix multiplication calculation is carried out according to the control input signal at the current moment, a first state signal, a preset first state space matrix, a second state space matrix and a discrete step vector to obtain a state differential signal;
step S130, performing matrix four-rule calculation according to the first state signal and the control input signal at the current moment and a preset third state space matrix and a preset fourth state space matrix to obtain a system output signal; the array calculation, the matrix multiplication calculation and the matrix four calculation are executed in parallel;
step S140, performing subtraction calculation according to the differential signal and the state differential signal to obtain a second state signal;
step S150, outputting the second state signal and the system output signal as a fractional order model at the current moment;
in step S160, the second state signal is used as the first state signal input at the next time to perform the array calculation and the matrix multiplication calculation.
It should be noted that, in some embodiments, the fractional order system-based model calculation method of the present application is based on a field programmable gate array (Field Programmable Gate Array, FPGA), and adopts a parallel operation method, so that a differential signal can be obtained by calculation according to a fractional order step length, an order vector and a first state signal at a current moment, and a second state signal and a system output signal can be obtained by calculation, so that a pipelined operation mode is changed into a concurrent operation, a calculation period of the system is reduced, and a calculation efficiency is improved. Meanwhile, the characteristics of rich operation resources, high-speed transportation and flexible programming of the FPGA are exerted. Meanwhile, the array module 1000 and the matrix multiplication module 2000 are arranged to further refine calculation, so that the calculation precision is improved, and the period and the precision of logic operation in the multi-element fractional order state space model are effectively balanced. In other embodiments, the computing methods of the present application may be implemented in software. Preferably, the present application is implemented in hardware.
Taking hardware implementation of the above method as an example, referring to fig. 6, fig. 6 is a schematic structural diagram of an FPGA-based state space model system according to an embodiment of the present application; the present application is applicable to a state space model with multiple fractional orders, and according to one embodiment of the present application, the input parameters of the FPGA-based state space model system include a clock signal clk, a reset signal rst_n, a start signal start, a request signal req_u, an order vector alpha, a control input signal u, an initial state signal x 0 Fractional step L and discrete step vector h α Etc., output as the second state signal x n And a system output signal y. Specifically, the state space model system based on the FPGA can perform iterative operation according to input parameters, and continuously output different second state signals and system output signals according to parameter updating and current time updating, wherein the discrete step vector is a constant parameter, and the first state signals and the control input signals are changed along with the iterative processing of the signals by the state space model system based on the FPGA. Specifically, referring to fig. 7, the FPGA-based state space model system includes an array module 1000 and a matrix multiplication module 2000, where the array module 1000 includes r GLFdiff, GLFdiff fractional order operator devices 1100, r is the state space to be calculatedThe dimension of the model, while the GLFdiff module also includes Gen_w i I.e. a serial output block 1110, wherein fractional order operators are used for fractional order differentiation of one element of the state vector x, and the serial output block 1110 is used for generating corresponding quadratic term coefficients of different fractional orders.
According to one embodiment of the present application, during the iterative loop of the FPGA-based state space model system, further comprising: and initializing a state space model system based on the FPGA according to the input parameters. Specifically, the initial state signal, the fractional step length, the model dimension and the order vector at the current moment need to be acquired first, the serial input component in each fractional operator 1100 starts to calculate the quadratic term coefficient according to the input parameters such as the fractional step length, the model dimension and the order vector, and after the calculation is completed, the result is stored for application when the fractional calculus is calculated later, and meanwhile, a first completion signal is output to inform the multiple fractional state space model that the array module 1000 has completed the initialization operation. Meanwhile, the matrix multiplication module 2000 acquires the unchanged parameters, namely, acquires the first state space matrix, the second state space matrix, the third state space matrix, the fourth state space matrix and the discrete step vector, and outputs a second completion signal after the unchanged parameters are acquired so as to inform the multi-element fractional order state space model, the matrix multiplication module 2000 completes the initialization operation, and at the moment, the multi-element fractional order state space model completes all the initialization operations and starts to enter the calculation state of the system cycle. More specifically, the initial state signal is only in the initial stage of the system, and is used as the state signal at the current moment in the initial stage of the system as input, and after the system completes all the initialization operations, the first state signal is output, and formally enters a loop calculation state, and at the moment, the first state signal is updated into the state signal at the current moment and is used as the input of the next iteration operation.
According to another embodiment of the present application, after the first completion signal and the second completion signal are obtained and the system initialization is completed, the FPGA-based state space model system of the present application reads the variable parameters of the matrix multiplication module 2000, i.e. acquiresThe first state signal and the control input signal are simultaneously divided into two different calculation paths for parallel calculation. One of the calculation paths is that the array module 1000 performs array calculation according to the input fractional step length, the order vector and the first state signal to obtain a differential signal dx_q, and at the same time, the matrix multiplication module 2000 performs matrix multiplication calculation by combining the differential signal, the first state signal and the control input signal to obtain a second state signal x n The calculated second state signal is input into the state space model system based on the FPGA again as the updated first state signal, and the next cycle calculation is carried out. Meanwhile, the other calculation path is that the matrix multiplication module 2000 performs matrix four-rule calculation according to the first state signal and the control input signal, so as to obtain a system output signal y. Specifically, array calculation, matrix multiplication calculation and matrix four calculation are executed in parallel, the dependence of a multi-element fractional state space model on a memory is reduced through algorithm design, design parameters are flexible and variable, calculation is more accurate, the application range is wider, the time of a single calculation period is effectively reduced, meanwhile, the calculation precision is improved through the arrangement of a plurality of calculation modules and a plurality of registers, and the relation between the calculation period and the precision is balanced. Moreover, the present application controls the orderly operation and processing of each unit and module by employing a unified global clock and data bus.
According to another embodiment of the present application, after obtaining the second state signal, the second state signal is used as an input of the FPGA-based state space model system, that is, is used as the updated first state signal to perform the next calculation, and the differential signal, the second state signal and the system output signal are updated to obtain the differential signal, the second state signal and the system output signal at each moment.
Referring to fig. 2, in a first aspect, an embodiment of the present application provides a method for calculating a model based on a fractional order system, including but not limited to step S210, step S220, step S230, and step S240.
Step S210, carrying out addition calculation, multiplication calculation and subtraction calculation on the fractional step length and the order vector to obtain a quadratic term coefficient;
step S220, according to the time interval between the system input signal and the system input signal, multiplying the system input signal and the quadratic term coefficient to obtain a first calculus operator at the current moment; the discrete step is obtained by performing evolution calculation on a discrete step vector and an order vector;
step S230, accumulating the first calculus operator at the current moment and the first calculus operator obtained by calculation at the previous moment to obtain the current calculus operator;
Step S240, the order vector, the current calculus operator, the model dimension and the first state signal are calculated to obtain a differential signal at the current moment.
Referring to fig. 9, fig. 9 is a schematic block diagram of an interior of a fractional order operator device 1100 according to an embodiment of the present application; it should be noted that, in engineering practice, the discrete approximation processing of the fractional calculus operator is generally represented by formula 1:
wherein alpha (0.ltoreq.alpha.ltoreq.1) represents a fractional order vector, L represents a finite window length, h α Represents a discrete step vector, h represents a discrete step, the discrete step vector is obtained by performing evolution calculation according to the discrete step and the order vector, and W j (α) Representing the quadratic coefficient, the calculation process is as formula 2:
wherein, the relation between the discrete step length and the discrete step length vector is:
the array module 1000 of the present application is used to process the quadratic term coefficient ω at each time instant j And system input signal f i Is calculated by the computer. Let equation 1From t 0 The calculation is started at the moment, n times are calculated in total, and as the number of times of calculation increases, multiplication and addition operations need to be carried out more than the previous calculation for each calculation, so that the dependence of the fractional order operator on the physical memory is extremely high. In order to solve the problem that the occupation of computing resources increases infinitely with the increase of iteration times, the method adopts a finite window method, and limits the complexity of each computation to L multiplications and L-1 additions, such as t L At the moment, if L is large enough, the quadratic coefficient w at this time l Is small enough, f 0 The effect on the current time sequence is negligible. Specifically, the calculation of the current time sequence requires at most f at L times i And L quadratic term coefficients omega j Multiplication calculation and addition are respectively carried out; after the secondary sequencing, each time sequence only needs to input f at the corresponding time i And L quadratic term coefficients W j Multiplying and storing in corresponding register, and then completing addition and data transfer operation by designing corresponding register group.
According to one embodiment of the present application, the finite window length is a fractional step length, and according to formula 1 and formula 2, the serial output unit 1110 performs array calculation on the fractional step length, the order vector and the first state signal to obtain a quadratic coefficient, and after obtaining the quadratic coefficient, the quadratic coefficient register 1120 stores the quadratic coefficient to facilitate the next multiplication calculation. Because of the system input signal f i I.e. f (t-jh) is a variable parameter, so that it is also necessary to calculate the system input signal according to discrete step length and input it into the array module 1000, so that the system input signal and the quadratic term coefficient are multiplied by the multiplier 1112 to obtain the current calculus operator d i And stored by the first data buffer 1130 for the next accumulation calculation. The quadratic term coefficient and the system input signal in the state space model system based on the FPGA are updated along with the time sequence, so that the quadratic term coefficient and the system input signal are also required to be updated according to the current time, the updated quadratic term coefficient and the system input signal are repeatedly multiplied to obtain a first calculus operator, and the first calculus operator and the calculus obtained at the last time sequence are obtainedThe division operators are accumulated to obtain updated current division operators, and the first data buffer 1130 stores the updated division operators. According to formula 1, after obtaining the current calculus operator, the present application further needs to calculate the discrete step vector, the order vector, the current calculus operator and the first state signal by using the fractional order operator device 1100, so as to obtain a differential signal. Specifically, the differential signal participates in the calculation in the form of a matrix in the logic operation process of the application, wherein the calculation formula of the i element of the differential signal is as follows:
wherein alpha represents an order vector, x i ， n-j The first state signal is expressed as,
and expressing the current calculus operator.
According to another embodiment of the present application, at system initialization, the data in the register set is reset to 0, and the system input signal f is input in the first calculation cycle 0 And quadratic term coefficient w 0 、w 1 、w 2 、w 3 Respectively multiplying and then calculus operator w 0 f 0 And outputting, namely transferring the data of the other 3 registers, adding the data with the product of the next moment, and repeating the steps in the subsequent iteration process. This design structure will have a quadratic coefficient omega j And system input signal f i The operation between the two windows is averaged to L windows, and each register only needs to complete 1 multiplication, one addition and data movement operation in each calculation period, so that the design improves the system operation efficiency and reduces the design difficulty.
Referring to fig. 3, in a first aspect, an embodiment of the present application provides a fractional order system-based model calculation method, which includes, but is not limited to, step S310 and step S320.
Step S310, counting operation is carried out according to the fractional step length and a preset starting signal, and the fractional step length is calculated to obtain a calculation factor;
in step S320, the addition calculation, multiplication calculation and subtraction calculation are performed on the calculation factor, the order vector and the preset input value, so as to obtain a quadratic term coefficient.
Referring to fig. 8, fig. 8 is a schematic block diagram of the inside of a serial output component 1110 according to an embodiment of the present application; it should be noted that, the array module 1000 includes r GLFdiff, GLFdiff fractional order operator devices 1100, r is the dimension of the state space model to be calculated, and the GLFdiff module further includes gen_w i I.e., serial output section 1110 includes a calculation factor section, a number of adders 1113, a number of multipliers 1112, a counter, a data transmission channel, and a data valid flag bit. Specifically, after the state space model system based on the FPGA starts to operate, a start signal start is set, a counter enters a counting mode according to an input fractional step size and a start signal, so that a calculation factor program 1111gen_1/j starts to calculate, a calculation factor is output, the calculation factor and an input order vector are calculated through a plurality of multipliers 1112 and adders 1113, a quadratic term coefficient is obtained, each quadratic term coefficient result is serially output through a data transmission channel wj_reg and a data valid flag bit tvalid, and when the array module 1000 judges to generate a quadratic term coefficient with a sufficient length required by calculation according to discrete step sizes, a program function of the serial output component 1110 is completely realized.
Referring to fig. 4, in a first aspect, an embodiment of the present application provides a method for calculating a model based on a fractional order system, including but not limited to step S410, step S420, and step S430.
Step S410, updating and calculating the order vector to obtain a plurality of quadratic term fitting coefficients;
step S420, selecting a limited window length according to the convergence degree of a plurality of quadratic term fitting coefficients, and respectively performing accumulation calculation, mean value calculation and multiplication calculation according to the limited window length, the plurality of quadratic term fitting coefficients, the system input signal and the discrete step length to obtain a current error compensation signal;
step S430, performing error compensation on the differential signal according to the error compensation signal.
Referring to fig. 9, an error is calculated by the finite window method, and in order to compensate the error, it is necessary to design a correlation structure to compensate the error. The hardware implementation idea of the finite window method is based on the same f i Using different ω j The parameters are multiplied, the structural optimization thought of the GLFdiff module is opposite to the parameters, and the same omega is fitted j By f at different moments i Multiplying it.
According to one embodiment of the application, error compensation is performed through quadratic term fitting coefficients, wherein the calculation formula of the quadratic term fitting coefficients is as follows: 
Wherein alpha (0.ltoreq.alpha.ltoreq.1) represents a fractional order vector, L represents a finite window length, i.e. fractional order step size, where the selection criterion of the finite window length L refers to the quadratic coefficient +.>
At a convergence speed of 0<α<At 0.8, the quadratic coefficient is chosen>
Reaching a value of 10-4 is used as a basis for the window length L, and generally the corresponding window length is 40-60 at this time, but is 0.8 at this time<α<In the case of 1, the quadratic coefficient changes rapidly, so that the window length can be properly selected to be between 30 and 40, and the window length is not too small. Specifically, the implementation method considers the influence of different fractional orders on the window length, the design is more flexible, and on the other hand, the design and implementation process of error compensation in a hardware circuit is simplified by the method of unequal grouping and averaging, and the calculation precision is greatly improved.
According to one embodiment of the present application, n quadratic term fitting coefficients are first calculated according to the order vector, and the quadratic term fitting coefficients are stored through the second data buffer 1140, and then according to the quadratic termThe convergence degree of the fitting coefficient selects a proper limited window length L, and the fitting coefficient of the quadratic term outside the window is divided into 8 groups of data with the length of 8,32,64,128,256 and the length of the residual sequence. Then, the system input signal f i And finally, the current error compensation signal and the differential signal finish accumulation calculation through the register, thereby realizing the error compensation of a limited window and improving the calculation precision.
Specifically, the method can update the quadratic term fitting coefficient and the system input signal according to the current moment, repeat the steps, perform multiplication operation on the updated quadratic term fitting coefficient and the system input signal to obtain an iteration value, and perform addition operation on the current error compensation signal and the iteration value to obtain an updated error compensation signal; and finally, performing error compensation on the differential signal according to the updated error compensation signal.
Referring to fig. 5, in a first aspect, an embodiment of the present application provides a method for calculating a model based on a fractional order system, including but not limited to step S510 and step S520.
Step S510, performing cross multiplication and addition calculation on the first state space matrix, the first state signal, the second state space matrix and the control input signal to obtain a matrix multiplication signal;
Step S520, performing point multiplication calculation on the matrix multiplication signal and the discrete step vector to obtain a state differential signal.
It should be noted that, the formula for calculating the second state signal and the system output signal is as follows:
y(t)＝Cx(t)+Du(t).
wherein a represents a first state space matrix, B represents a second state space matrix, C represents a third state space matrix, D represents a fourth state space matrix, x (t) represents a first state signal, and u (t) represents a control input signal.
According to another embodiment of the present application, the formula for calculating the second status signal and the system output signal further comprises:
wherein A represents a first state space matrix, B represents a second state space matrix, C represents a third state space matrix, D represents a fourth state space matrix, and x n Express the second status signal, u n Express control input signal, y n Express system input signal, x n-1 Express the first status signal, u n-1 A control input signal h representing the input at the previous time α Expressing the discrete step size vector, expressing the order vector by alpha, and expressing the fractional step size by L.
It should be noted that, according to an embodiment of the present application, the first state space matrix is a state space model system matrix, the second state space matrix is a state space model control matrix, the third state space matrix is a state space model output matrix, and the fourth state space matrix is a state space model direct transfer matrix.
Referring to the formula, the present application uses a parallel computing method to simultaneously apply the first state space matrix a and the first state signal x through the first state differential operator 2100 n-1 The second state space matrix B and the control input signal are subjected to cross multiplication operation, and the result is accumulated through an addition register to obtain a matrix multiplication signal; after the matrix multiplication signal is obtained, the second state differential arithmetic unit 2200 module performs dot multiplication calculation on the matrix multiplication signal and the discrete step size vector to obtain a state differential signal; finally, the state differential signal and the differential signal are subtracted through the register to obtain a second state signal.
The vector point multiplication operation is a process of multiplying two vectors according to elements of corresponding indexes to obtain a new vector, and is as follows: [ a ] 1 a 2 …a n ] T ⊙[b 1 b 2 …b n ] T ＝[a 1 b 1 a n b 2 …a n b n ] T ；
It will be appreciated that the matrix multiplication module 2000 further includes a third state differential operator 2300 module, which is configured to calculate the first state signal and the control input signal to obtain a system output signal, and includes: the third state space matrix C, the first state signal, the fourth state space matrix D, and the control input signal are subjected to a cross multiplication and addition operation by the third state differential operator 2300, to obtain a system output signal.
Referring to fig. 7, the process of calculating the system output signal is performed simultaneously with the process of calculating the second state signal, and the third state space matrix C and the first state signal x are simultaneously calculated by the third state differential operator 2300 with reference to the formula of the system output signal n-1 And performing cross multiplication operation on the fourth state space matrix D and the control input signals, accumulating the results through an addition register to obtain a system output signal, performing iterative loop, and outputting state vectors and system output signals at all times of system simulation.
According to one embodiment of the present application, the iterative update process of the present application is: setting a second state signal obtained at present as an updated first state signal through a selection register, and updating a control input signal at the same time; performing array calculation according to the fractional step length, the order vector and the first state signal to obtain an updated differential signal; simultaneously combining the differential signals to calculate the first state signal and the control input signal to obtain an updated second state signal; and calculating the first state signal and the control input signal to obtain an updated system output signal. Specifically, at this time, the system is in a cyclic calculation stage, after the second state signal is obtained, the second state signal is used as input of the multi-element fractional order state space model, that is, is used as the first state signal to perform next calculation, and meanwhile, the control input signal is updated, the steps of calculating the differential signal of the previous time sequence, the second state signal and the system output signal are repeated, array calculation is performed according to the fractional order step length, the order vector and the first state signal, and meanwhile, the first state signal and the control input signal are calculated, and the differential signal, the second state signal and the system output signal are updated circularly until the cycle of the multi-element fractional order space model is ended.
In a second aspect, an embodiment of the present application provides an FPGA-based state space model system, where the FPGA-based state space model system includes a plurality of input ports, and the FPGA-based state space model system includes:
the array module 1000 is configured to obtain a first state signal, a fractional step size, and an order vector input by one of the input ports at a current moment, and perform array calculation according to the first state signal, the fractional step size, the order vector, and a preset model dimension at the current moment to obtain a differential signal;
the matrix module is connected with the array module 1000, and is used for obtaining a differential signal, a first state signal input by one input port at the current moment and a control input signal input by the other input port, and respectively performing matrix multiplication calculation and matrix four-rule calculation according to the differential signal, the first state signal, the control input signal, a preset first state space matrix, a second state space matrix, a third state space matrix, a fourth state space matrix and a discrete step vector to obtain a second state signal and a system output signal, wherein the matrix multiplication calculation and the matrix four-rule calculation are executed in parallel.
It should be noted that, in the present application, the first completion signal is output through the array module 1000, and the second completion signal is output through the matrix multiplication module 2000, so as to reduce the period of the system, specifically, the present application performs modularized design processing on each operation unit according to different functions, performs parallel processing on the unit module operation of the system according to the trend of the data stream, and adopts the modularized multichannel parallel operation method of the system functional unit, so that the pipelined operation model is changed into concurrent operation, and the operation efficiency is improved.
According to one embodiment of the present application, the initial state signal, the fractional step size, the model dimension and the order vector of the current moment need to be acquired first, the serial input component in each fractional operator device 1100 starts to calculate the quadratic term coefficient according to the input parameters such as the fractional step size, the model dimension and the order vector, after the calculation is completed, the result is stored for being applied when the fractional calculus is calculated later, and meanwhile, a first completion signal is output to inform the multiple fractional state space model, and the array module 1000 completes the initialization operation. Meanwhile, the matrix multiplication module 2000 acquires the unchanged parameters, namely, acquires the first state space matrix, the second state space matrix, the third state space matrix, the fourth state space matrix and the discrete step vector, and outputs a second completion signal after the unchanged parameters are acquired so as to inform the multi-element fractional order state space model, the matrix multiplication module 2000 completes the initialization operation, and at the moment, the multi-element fractional order state space model completes all the initialization operations and starts to enter the calculation state of the system cycle.
Referring to fig. 7, it can be understood that the matrix module includes: a first state differential operator 2100, configured to perform matrix cross multiplication calculation and addition calculation according to the control input signal, the first state space matrix, and the second state space matrix, to obtain a matrix multiplication signal; a second state differential operator 2200, the first state differential operator 2100 and the second state differential operator 2200 being electrically connected for performing a dot product calculation according to the matrix multiplication signal and the discrete step vector to obtain a state differential signal; and the third state differential operator 2300 is configured to perform matrix cross multiplication calculation and addition calculation according to the first state signal, the control input signal, the third state space matrix, and the fourth state space matrix, so as to obtain a system output signal.
It should be noted that, the formula for calculating the second state signal and the system output signal is as follows:
y(t)＝Cx(t)+Du(t).
wherein a represents a first state space matrix, B represents a second state space matrix, C represents a third state space matrix, D represents a fourth state space matrix, x (t) represents a first state signal, and u (t) represents a control input signal.
According to another embodiment of the present application, the formula for calculating the second status signal and the system output signal further comprises:
Wherein A represents a first state space matrix, B represents a second state space matrix, C represents a third state space matrix, D represents a fourth state space matrix, and x n Express the second status signal, u n Express control input signal, y n Express system input signal, x n-1 Express the first status signal, u n-1 A control input signal h representing the input at the previous time α Expressing the discrete step size vector, expressing the order vector by alpha, and expressing the fractional step size by L.
Referring to the formula, the present application uses a parallel computing method to simultaneously apply the first state space matrix a and the first state signal x through the first state differential operator 2100 n-1 The second state space matrix B and the control input signal are subjected to cross multiplication operation, and the result is accumulated through an addition register to obtain a matrix multiplication signal; after the matrix multiplication signal is obtained, the second state differential arithmetic unit 2200 module performs dot multiplication calculation on the matrix multiplication signal and the discrete step size vector to obtain a state differential signal; finally, the state differential signal and the differential signal are subtracted through the register to obtain a second state signal.
According to another embodiment of the present application, the matrix multiplication module 2000 further includes a third state differential operator 2300 module, which is configured to calculate the first state signal and the control input signal to obtain a system output signal, and includes: the third state space matrix C, the first state signal, the fourth state space matrix D, and the control input signal are subjected to a cross multiplication and addition operation by the third state differential operator 2300, to obtain a system output signal.
Referring to fig. 7, it can be appreciated that the FPGA-based state space model system further includes: the subtracter is electrically connected with the output port of the array module 1000 and the output port of the matrix module, and is used for performing subtraction calculation according to the differential signal and the state differential signal to obtain a second state signal; the fractional order system output end is connected with the subtracter and the third state differential arithmetic unit 2300 and is used for outputting the second state signal and the system output signal as a fractional order model at the current moment; the selection register is connected with the output end of the fractional order system, the input end of the array module 1000 and the input end of the matrix module, and is used for taking the second state signal as the first state signal input at the next moment to perform array calculation and matrix multiplication calculation.
In a third aspect, referring to fig. 10, an embodiment of the present application provides an electronic device, including:
at least one memory 4000;
at least one processor 3000;
at least one program;
the program is stored in the memory 4000, and the processor 3000 executes at least one program to realize:
a method for model calculation based on a fractional order system according to any one of the embodiments of the first aspect of the present application.
The processor 3000 and the memory 4000 may be connected by a bus or other means.
The processor 3000 executes non-transitory software instructions, and signals stored in the memory 4000 to thereby perform various functional applications and data processing, i.e., to implement the fractional order system-based model calculation method of the above-described first aspect embodiment.
The non-transitory software instructions and instructions required to implement the fractional order system-based model calculation method of the above embodiment are stored in the memory 4000, and when executed by the processor 3000, perform the fractional order system-based model calculation method of the first aspect of the embodiment of the present application, for example, perform the method steps S110 to S160 in fig. 1, the method steps S210 to S240 in fig. 2, the method steps S310 to S320 in fig. 3, the method steps S410 to S430 in fig. 4, and the method steps S510 to S520 in fig. 5 described above.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing computer-executable signals for performing:
a method of model calculation based on a fractional order system according to any one of the embodiments of the first aspect of the application.
For example, the above-described method steps S110 to S160 in fig. 1, method steps S210 to S240 in fig. 2, method steps S310 to S320 in fig. 3, method steps S410 to S430 in fig. 4, and method steps S510 to S520 in fig. 5 are performed.
The apparatus embodiments described above are merely illustrative, wherein elements illustrated as separate elements may or may not be physically separate, and elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
From the description of the embodiments above, those skilled in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable signals, data structures, instruction modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable signals, data structures, instruction modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and may include any information delivery media.
The embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present application.
Claims (10)
1. A fractional order system-based model calculation method, wherein the method is applied to a fractional order system model, the method comprising:
acquiring a first state signal, a fractional step length and an order vector at the current moment, and performing array calculation according to the first state signal, the fractional step length, the order vector and a preset model dimension at the current moment to obtain a differential signal;
acquiring a control input signal at the current moment, and performing matrix multiplication calculation according to the control input signal at the current moment, the first state signal, a preset first state space matrix, a preset second state space matrix and a preset discrete step length vector to obtain a state differential signal;
performing matrix four-rule calculation according to the first state signal, the control input signal, a preset third state space matrix and a preset fourth state space matrix at the current moment to obtain a system output signal; the array calculation, the matrix multiplication calculation and the matrix four calculation are executed in parallel;
Subtracting the differential signal from the state differential signal to obtain a second state signal;
outputting the second state signal and the system output signal as a fractional order model at the current moment;
and taking the second state signal as a first state signal input at the next moment to perform array calculation and matrix multiplication calculation.
2. The method for calculating a model based on a fractional order system according to claim 1, wherein the performing array calculation according to the first state signal, the fractional order step length, the order vector and a preset model dimension at the current moment to obtain a differential signal includes:
performing addition calculation, multiplication calculation and subtraction calculation on the fractional step length and the order vector to obtain a quadratic term coefficient;
according to the time interval between a discrete step length computing system input signal and the system input signal, multiplying the system input signal and the quadratic term coefficient to obtain a first calculus operator at the current moment; the discrete step size is obtained by squaring the discrete step size vector and the order vector;
accumulating the first calculus operator at the current moment and the first calculus operator obtained by calculation at the previous moment to obtain a current calculus operator;
And calculating the order vector, the current calculus operator, the model dimension and the first state signal to obtain a differential signal at the current moment.
3. The fractional order system-based model calculation method according to claim 2, wherein the performing addition calculation, multiplication calculation and subtraction calculation on the fractional order step size and the order vector to obtain quadratic term coefficients includes:
executing counting operation according to the fractional step length and a preset starting signal, and calculating the fractional step length to obtain a calculation factor;
and carrying out addition calculation, multiplication calculation and subtraction calculation on the calculation factors, the order vectors and preset input values to obtain quadratic term coefficients.
4. The fractional order system-based model calculation method according to claim 2, wherein the performing array calculation according to the first state signal, the fractional order step length, the order vector and a preset model dimension at the current moment to obtain a differential signal further comprises:
updating and calculating the order vector to obtain a plurality of quadratic term fitting coefficients;
selecting a limited window length according to the convergence degree of a plurality of quadratic term fitting coefficients, and respectively performing accumulation calculation, mean value calculation and multiplication calculation according to the limited window length, a plurality of quadratic term fitting coefficients, the system input signal and the discrete step length to obtain an error compensation signal;
And carrying out error compensation on the differential signal according to the error compensation signal.
5. The fractional order system-based model calculation method according to claim 2, wherein the performing matrix multiplication calculation according to the control input signal, the first state signal, and a preset first state space matrix, a second state space matrix, and a discrete step vector at the current time to obtain a state differential signal includes:
performing cross multiplication and addition calculation on the first state space matrix, the first state signal, the second state space matrix and the control input signal to obtain a matrix multiplication signal;
and performing point multiplication calculation on the matrix multiplication signal and the discrete step length vector to obtain a state differential signal.
6. An FPGA, the FPGA comprising a plurality of input ports, the FPGA comprising:
the array module is used for acquiring a first state signal, a fractional step length and an order vector input by one of the input ports at the current moment, and performing array calculation according to the first state signal, the fractional step length, the order vector and a preset model dimension at the current moment to obtain a differential signal;
The matrix module is connected with the array module and is used for acquiring the differential signal, a first state signal input by one input port at the current moment and a control input signal input by the other input port, and respectively carrying out matrix multiplication calculation and matrix four-rule calculation according to the differential signal, the first state signal, the control input signal, a preset first state space matrix, a second state space matrix, a third state space matrix, a fourth state space matrix and a discrete step size vector to obtain a second state signal and a system output signal, wherein the matrix calculation, the matrix multiplication calculation and the matrix four-rule calculation are executed in parallel.
7. The FPGA of claim 6 wherein the matrix module comprises:
the first state differential arithmetic unit is used for performing matrix cross multiplication calculation and addition calculation according to the control input signal, the first state space matrix and the second state space matrix to obtain a matrix multiplication signal;
the first state differential operator is electrically connected with the second state differential operator and is used for performing point multiplication calculation according to the matrix multiplication signal and the discrete step-length vector to obtain a state differential signal;
And the third state differential arithmetic unit is used for performing matrix cross multiplication calculation and addition calculation according to the first state signal, the control input signal, the third state space matrix and the fourth state space matrix to obtain a system output signal.
8. The FPGA-based state space model system of claim 7, further comprising:
the subtracter is electrically connected with the output port of the array module and the output port of the matrix module and is used for performing subtraction calculation according to the differential signal and the state differential signal to obtain the second state signal;
the fractional order system output end is connected with the subtracter and the third state differential arithmetic unit and is used for outputting the second state signal and the system output signal as a fractional order model at the current moment;
the selection register is connected with the fractional order system output end, the input end of the array module and the input end of the matrix module, and the selection register is used for taking the second state signal as a first state signal input at the next moment to perform array calculation and matrix multiplication calculation.
9. An electronic device, comprising:
at least one memory;
at least one processor;
at least one program;
the programs are stored in the memory, and the processor executes at least one of the programs to implement the fractional order system-based model calculation method of any one of claims 1 to 5.
10. A computer-readable storage medium storing a computer-executable signal for performing the fractional order system-based model calculation method of any one of claims 1 to 5.
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