CN116383118A - Data transmission system and method - Google Patents

Data transmission system and method Download PDF

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Publication number
CN116383118A
CN116383118A CN202310194139.3A CN202310194139A CN116383118A CN 116383118 A CN116383118 A CN 116383118A CN 202310194139 A CN202310194139 A CN 202310194139A CN 116383118 A CN116383118 A CN 116383118A
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China
Prior art keywords
data
ethernet
npu
cpu
conversion unit
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CN202310194139.3A
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Chinese (zh)
Inventor
孔庆宇
林湖
王坚
徐康
黄歆
韩超
王雪
朱峰
张海桥
白文娟
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China Automotive Innovation Co Ltd
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China Automotive Innovation Co Ltd
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Priority to CN202310194139.3A priority Critical patent/CN116383118A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The system comprises a first CPU, a second CPU, a first NPU, a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit and an Ethernet switch chip; the PCIE bus which is easy to cause single-point faults can be isolated by adopting the data transmission method of the data transmission system, the corresponding NPU is not invalid under the condition of single CPU fault, or the corresponding CPU is not invalid under the condition of single NPU fault, so that the influence of single functional module invalidation on other functional modules is reduced, the modules of the data transmission system are further decoupled, the stability of data transmission is ensured, the influence of single module fault on the whole system is reduced, and the safety and stability of the whole data transmission system are improved.

Description

Data transmission system and method
Technical Field
The present disclosure relates to the field of automated driving computing power architecture, and in particular, to a data transmission system and method.
Background
In the field of power architecture in the automatic driving field, a controller generally consists of a plurality of SoC (system on chip) cascades, data transmission with a larger bandwidth is required between the socs, such as video streaming data transmission, laser radar point cloud data transmission, and the like, the existing multi-SoC data cascades generally perform data transmission through ethernet cascades, and for data transmission with a larger bandwidth, PCIE (peripheral component interconnect express) cascades are generally required to complete data transmission.
In the prior art, whether the Ethernet cascade or the PCIE cascade is used, the Ethernet cascade has a corresponding use scene, the Ethernet cascade is widely used, the original data is required to be packaged and transmitted according to an Ethernet protocol, the delay aspect is weaker than that of the PCIE cascade, the PCIE cascade is suitable for point-to-point cascade and one master-slave cascade, the PCIE cascade has a larger data bandwidth and lower delay, but in the prior art, due to the inherent characteristics of a PCIE bus, when the CPU and the NPU perform data transmission based on PCIE bus standards, the problem that a single CPU or the NPU fails to cause the corresponding NPU or the CPU fails to cause that the data transmission between SoCs cannot be completed, and the system is restarted due to the fact that the single module fails to cause the overall system failure of the CPU and the NPU, so that the overall function safety of the system is not facilitated.
Disclosure of Invention
The disclosure provides a data transmission method, a device, equipment and a storage medium, so as to at least solve the problems that in the related art, a single CPU fails to cause a corresponding NPU failure, or a single NPU fails to cause a corresponding CPU failure, and a single module fails to cause the restarting of the whole data transmission system. The technical scheme of the present disclosure is as follows:
according to an aspect of the embodiments of the present disclosure, there is provided a data transmission control system including:
the system comprises a first CPU, a second CPU, a first neutral network processor NPU, a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit and an Ethernet switching chip; the first conversion unit, the second conversion unit, the third conversion unit and the fourth conversion unit are respectively connected with the Ethernet switching chip based on the respectively corresponding Ethernet buses; the first CPU is connected with the first conversion unit based on a first high-speed serial computer expansion bus standard PCIE bus, the second CPU is connected with the second conversion unit based on a second PCIE bus, the first NPU is connected with the third conversion unit based on a third PCIE bus, and the second NPU is connected with the fourth conversion unit based on a fourth PCIE bus;
Under the condition that the first NPU fails, the first CPU is used for calculating first target transmission data to obtain first PCIE data; the first conversion unit is configured to convert the first PCIE data into first ethernet data, and the ethernet switching chip is configured to transmit the first ethernet data to the fourth conversion unit; the fourth conversion unit is configured to convert the first ethernet data into the first PCIE data, and the second NPU is configured to process the first PCIE data;
under the condition that the first CPU fails, the second CPU is used for calculating the first target transmission data to obtain the first PCIE data; the second conversion unit is configured to convert the first PCIE data into the first ethernet data, the ethernet switching chip is configured to transmit the first ethernet data to the third conversion unit or the fourth conversion unit, the third conversion unit is configured to convert the first ethernet data into the first PCIE data, and the first NPU is configured to process the first PCIE data; or the fourth conversion unit is configured to convert the first ethernet data into the first PCIE data, and the second NPU is configured to process the first PCIE data.
According to an aspect of the embodiments of the present disclosure, there is provided a data transmission control method, including:
the first CPU performs operation on the first target transmission data to obtain first PCIE data, and sends the first PCIE data to the first conversion unit based on the first PCIE bus;
the first conversion unit converts the first PCIE data into first Ethernet data and sends the first Ethernet data to an Ethernet switching chip based on a corresponding Ethernet bus;
the Ethernet switching chip transmits the first Ethernet data to a fourth conversion unit under the condition that a first NPU fails;
the fourth conversion unit converts the first ethernet data into the first PCIE data, and sends the first PCIE data to the second NPU based on a fourth PCIE bus;
and the second NPU processes the first PCIE data.
According to an aspect of the embodiments of the present disclosure, there is provided another data transmission control method, including:
under the condition that a first CPU fails, a second CPU calculates first target transmission data to obtain first PCIE data, and sends the first PCIE data to a second conversion unit based on a second PCIE bus;
The second conversion unit converts the first PCIE data into first Ethernet data and sends the first Ethernet data to an Ethernet switching chip based on a corresponding Ethernet bus;
the Ethernet switching chip transmits the first Ethernet data to a third conversion unit or a fourth conversion unit;
the third conversion unit converts the first ethernet data into the first PCIE data, and sends the first PCIE data to the first NPU based on a third PCIE bus;
the first NPU processes the first PCIE data;
the fourth conversion unit converts the first ethernet data into the first PCIE data, and sends the first PCIE data to the second NPU based on a fourth PCIE bus;
and the second NPU processes the first PCIE data.
The technical scheme provided by the embodiment of the disclosure at least brings the following beneficial effects:
the data transmission system comprises a first CPU, a second CPU, a first NPU, a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit and an Ethernet exchange chip, when the data transmission system is used for enabling two CPUs to carry out data transmission with two NPUs based on PCIE bus standards, isolation of all main functional modules is achieved through Ethernet conversion, decoupling between modules can be achieved, namely under the condition that a single CPU (such as the first CPU) fails, failure of the corresponding NPU (such as the second NPU) cannot be caused, or under the condition that a single NPU (such as the first NPU) fails, failure of the corresponding CPU (such as the second CPU) cannot be caused, other modules which can be normally used in the data transmission system are utilized to continuously complete data transmission work, influence of the failure of the single functional module on other functional modules is reduced, and accordingly reliability of data transmission between the CPU and the NPU is improved, meanwhile restarting of the whole data transmission system due to the failure of the single module is avoided, and stability of the system is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure and do not constitute an undue limitation on the disclosure.
FIG. 1 is a schematic diagram of a data transmission system according to an exemplary embodiment;
FIG. 2 is a schematic diagram of another data transmission system shown in accordance with an exemplary embodiment;
FIG. 3 is a schematic diagram of another data transmission system shown in accordance with an exemplary embodiment;
FIG. 4 is a flow chart illustrating another data transmission method according to an exemplary embodiment;
FIG. 5 is a flow chart illustrating another data transmission method according to an exemplary embodiment;
FIG. 6 is a schematic diagram of an application environment, shown in accordance with an exemplary embodiment;
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.
It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
It should be noted that, the user information (including, but not limited to, user equipment information, user personal information, etc.) and the data (including, but not limited to, data for presentation, analyzed data, etc.) related to the present disclosure are information and data authorized by the user or sufficiently authorized by each party.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a data transmission system according to an exemplary embodiment, and the system may include a first CPU (central processing unit), a second CPU, a first NPU (Neural-network processing unit), a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit, and an ethernet switch chip.
In an optional embodiment, the first conversion unit, the second conversion unit, the third conversion unit, and the fourth conversion unit are respectively connected to an ethernet switch chip based on respective corresponding ethernet buses, and specifically, the first conversion unit, the second conversion unit, the third conversion unit, and the fourth conversion unit may be conversion chips including PCIE (PeripheralComponent InterconnectExpress, high-speed serial computer expansion bus standard) interfaces and multiple groups of ethernet interfaces, and specifically, the conversion chips are integrated circuit chips capable of implementing mutual conversion between PCIE data and ethernet data; the first CPU is connected to the first conversion unit based on a first PCIE bus, the second CPU is connected to the second conversion unit based on a second PCIE bus, the first NPU is connected to the third conversion unit based on a third PCIE bus, the second NPU is connected to the fourth conversion unit based on a fourth PCIE bus, specifically, the first CPU and the second CPU are central processing units capable of operating on first target transmission data to obtain first PCIE data, specifically, the first target transmission data are to-be-transmitted data, in practical application, the to-be-transmitted data may be AI visual algorithm data or video stream data, etc., the first PCIE data are data generated based on the first target transmission data and transmitted through the PCIE bus, and the first NPU and the second NPU are neural network processors capable of operating on the first PCIE data.
In practical applications, the first conversion unit, the second conversion unit, the third conversion unit and the fourth conversion unit may implement mutual conversion between PCIE data and ethernet data, and because the bandwidth required for PCIE data transmission is greater than the bandwidth required for ethernet data transmission, each of the first to fourth conversion units may have a PCIE interface and multiple groups of ethernet interfaces, where the multiple groups of ethernet interfaces may use multiple groups of RGMII (reduced gigabit media independent interfaces) or multiple groups of SGMII (serial gigabit media independent interfaces), so that the data bandwidth transmitted by the multiple groups of ethernet interfaces matches the bandwidth of PCIE interface transmission data; the first CPU and the second CPU may be selected from a vehicle-mounted CPU chip with corresponding data processing capabilities, and optionally, an operating system carried on the vehicle-mounted CPU chip may include, but is not limited to, an android operating system, a QNX (Quick Unix-like real-time operating system) or an RTOS (real-time operating system), by carrying a corresponding operating system, the first CPU and the second CPU may support processing of first target transmission data in an autopilot process to obtain first PCIE data, where the first target transmission data may be AI visual algorithm data or video stream data, etc., and the first CPU and the second CPU may also support processing of data with larger resource occupation in an autopilot process, where the resource occupation is larger data, for example: laser radar data, equipment management data, central centralized operation data, man-machine interaction function data and the like; the first NPU and the second NPU may be selected from a vehicle-mounted NPU chip with corresponding data processing capability, and optionally, an operating system carried on the vehicle-mounted NPU chip may include, but is not limited to, linux (GNU/Linux, unix-like operating system), and by carrying corresponding operating systems, the first NPU and the second NPU support processing of the received first PCIE data in an automatic driving process.
In an optional embodiment, in case of a failure of the first NPU, the first CPU may be configured to operate on the first target transmission data to obtain first PCIE data; the first conversion unit may be configured to convert the first PCIE data into first ethernet data, and the ethernet switching chip is configured to transmit the first ethernet data to the fourth conversion unit; the fourth conversion unit is used for converting the first Ethernet data into first PCIE data, and the second NPU is used for processing the first PCIE data, so that the second NPU is called under the condition that the first NPU fails, and data transmission between the first CPU and the second NPU is performed.
In an optional embodiment, under the condition that the first CPU fails, the second CPU may perform an operation on the first target transmission data to obtain first PCIE data; the second conversion unit is used for converting the first PCIE data into first Ethernet data, the Ethernet switching chip is also used for transmitting the first Ethernet data to the third conversion unit or the fourth conversion unit, the third conversion unit is used for converting the first Ethernet data into first PCIE data, and the first NPU is used for processing the first PCIE data; or the fourth conversion unit is used for converting the first Ethernet data into the first PCIE data, and the second NPU is used for processing the first PCIE data, so that the second CPU is called under the condition that the first CPU fails, and data transmission between the second CPU and the first NPU is performed or data transmission between the second CPU and the second NPU is performed.
In the above embodiment, the data transmission system includes the first CPU, the second CPU, the first NPU, the second NPU, the first conversion unit, the second conversion unit, the third conversion unit, the fourth conversion unit, and the ethernet switching chip, when the two CPUs and the two NPUs perform data transmission based on the PCIE bus standard, the data transmission system is used to implement isolation of each main functional module through ethernet conversion, so that decoupling between modules can be implemented, that is, failure of the corresponding NPU is not caused when a single CPU fails, failure of the corresponding CPU is not caused when a single NPU fails, and data transmission work can be continuously completed through a module that can be normally used in the data transmission system, thereby improving reliability of data transmission between the CPU and the NPU, avoiding influence on the whole data transmission system due to failure of the single module, avoiding restarting of the data transmission system, and further improving stability of the data transmission system.
Referring to fig. 2, fig. 2 is a schematic diagram of another data transmission system shown in an exemplary embodiment, in an alternative embodiment, the first CPU may be connected to the ethernet switch chip based on a corresponding ethernet bus, and the first CPU is further configured to send second ethernet data to the first NPU or the second NPU, where a data bandwidth of the second ethernet data is smaller than a data bandwidth of the first ethernet data, and in an actual application, the second ethernet data may be communication data sent by the first CPU to the first NPU or communication data sent by the first CPU to the second NPU; the second CPU is connected with the Ethernet switching chip based on a corresponding Ethernet bus, and is further used for sending third Ethernet data to the first NPU or the second NPU, specifically, the bandwidth of the third Ethernet data is smaller than the data bandwidth of the first Ethernet data, and in practical application, the second Ethernet data can be communication data sent by the second CPU to the first NPU or communication data sent by the second CPU to the second NPU; the first NPU is connected with the Ethernet switching chip based on a corresponding Ethernet bus, and is also used for sending fourth Ethernet data to the first CPU or the second CPU, and specifically, the fourth Ethernet data can be working data fed back to the first CPU or the second CPU by the first NPU; the second NPU is connected with the Ethernet switching chip based on the corresponding Ethernet bus, and is also used for sending fifth Ethernet data to the first CPU or the second CPU, and the fifth Ethernet data can be working data fed back to the first CPU or the second CPU by the second NPU.
In the above embodiment, the first CPU, the second CPU, the first NPU, and the second NPU are directly connected to the ethernet chip based on the ethernet buses respectively corresponding to each other, so that the two CPUs may transmit communication data to the two NPUs through the ethernet buses respectively corresponding to each other, and the two NPUs may also feed back working data to the two CPUs through the ethernet buses respectively corresponding to each other, so that transmission resources of the first to fourth PCIE buses are not occupied, data transmission resources are reasonably allocated, and further data transmission efficiency may be improved.
Referring to fig. 3, fig. 3 is a schematic diagram of another data transmission system shown in an exemplary embodiment, in an alternative embodiment, the data transmission system may further include a logic detection unit and a micro control unit, where the logic detection unit is respectively connected to the first CPU, the second CPU, the first NPU, and the second NPU, and specifically, the logic detection unit is configured to generate a first fault signal when the first NPU fails, and send the first fault signal to the micro control unit, or is configured to generate a second fault signal when the first CPU fails, and send the second fault signal to the micro control unit, or is configured to generate a third fault signal when the first CPU and the second CPU fail, and send the third fault signal to the micro control unit;
Specifically, the micro control unit is connected to the ethernet switching chip, and is configured to send a first switching instruction to the ethernet switching chip based on a first fault signal, so that the ethernet switching chip forwards the first ethernet data to the fourth switching unit, or is configured to send a second switching instruction to the ethernet switching chip based on a second fault signal, so that the ethernet switching chip forwards the first ethernet data to the third switching unit or the fourth switching unit, or is configured to send a control instruction to an external device connected to the data transmission system based on the third fault signal, so as to change an operating state of the external device, and send a restart instruction to the ethernet switching chip, so that the ethernet switching chip is restarted.
In practical applications, the logic detection unit may be a CPLD (complex programmable logic device), the micro control unit may be a vehicle-mounted MCU (micro control unit) carrying a low automatic driving level regulation algorithm, the external device may be an automatic driving vehicle, the first, second and third fault signals sent to the micro control unit by the logic monitoring unit may be interrupt signals or level signals, or may be bus signals such as an SPI (serial peripheral interface) signal or an I2C (bidirectional synchronous serial bus) signal, the logic detection unit detects a fault condition of the data transmission system, generates a fault signal according to the fault condition and sends a corresponding signal to the micro control unit, and the micro control unit sends a first, second switching instruction or a restarting instruction to the external device based on the received fault signal, and sends a control instruction to the external device based on the third fault signal, for example: the vehicle-mounted MCU (micro control unit) starts an automatic driving degradation instruction to an automatic driving vehicle (external equipment) so as to change the automatic driving vehicle in running from L4-level high-automatic driving to L2-level partial automatic driving.
In the above embodiment, by setting the logic detection unit and the micro control unit in the data transmission system, the working state of the data transmission system can be monitored in real time, and when the first NPU fails, the logic detection unit can generate a first failure signal and send the signal to the micro control unit, and the micro control unit sends a first switching instruction to the ethernet switching chip according to the first failure signal; or under the condition that the first CPU fails, the logic detection unit generates a second failure signal and sends the signal to the micro control unit, and the micro control unit sends a second switching instruction to the Ethernet switching chip according to the second failure signal; or under the condition that the first CPU and the second CPU are in fault, the logic detection unit generates a third fault signal and sends a signal to the micro control unit, the micro control unit sends a restarting instruction to the Ethernet exchange chip according to the third fault signal, and meanwhile, the micro control unit sends a control instruction to external equipment; the logic detection unit generates corresponding fault signals based on different fault conditions and sends the fault signals to the micro control unit, and the micro control unit sends instructions corresponding to the fault signals to the Ethernet exchange chip and the external equipment according to the different fault signals, so that various fault conditions of the data transmission system can be timely dealt with, and the stability and the safety of the data transmission system are improved.
Those skilled in the art will appreciate that the structures shown in fig. 1, 2, or 3 are merely block diagrams of portions of system structures associated with the disclosed aspects and are not limiting of the system structures to which the disclosed aspects may be applied, and that a particular data transmission system may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
An embodiment of a data transmission method based on the above data transmission system is described below, as shown in fig. 4, fig. 4 is a flowchart illustrating a data transmission method according to an exemplary embodiment, and the method may include the steps of:
in step S401, the first CPU performs an operation on the first target transmission data to obtain first PCIE data, and sends the first PCIE data to the first conversion unit based on the first PCIE bus.
Specifically, the first target transmission data may be AI visual algorithm data or video stream data, and the first PCIE data may be data that is generated by the first CPU based on the first target transmission data and may be transmitted through a PCIE bus, and after the first CPU computes the first target transmission data to generate the first PCIE data, the first CPU sends the first PCIE data to the first conversion unit based on the first PCIE bus.
In step S403, the first conversion unit converts the first PCIE data into first ethernet data, and sends the first ethernet data to the ethernet switch chip based on the corresponding ethernet bus.
Specifically, the first conversion unit is an integrated circuit chip capable of implementing mutual conversion between PCIE data and ethernet data, the first PCIE data may be converted into first ethernet data by the first conversion unit, and the first conversion unit sends the first ethernet data to the ethernet switching chip, and specifically, the ethernet switching chip is configured to forward the first ethernet data to the third conversion unit or the fourth conversion unit.
In step S405, the ethernet switching chip transmits the first ethernet data to the fourth conversion unit in the case of a failure of the first NPU.
Specifically, under the condition that the first NPU fails, the first CPU is not directly connected with the first NPU through the PCIE bus due to isolation between the first conversion unit and the second conversion unit, so that normal operation of the corresponding first CPU is not affected when the first NPU fails, at this time, the first CPU in the data transmission system may normally generate first PCIE data and transmit the first PCIE data to the first conversion unit based on the first PCIE bus, the first conversion unit converts the first PCIE data into first ethernet data, and after the first ethernet data is sent to the ethernet chip, the ethernet exchange chip may forward the first ethernet data originally to be forwarded to the third conversion unit to the fourth conversion unit, so that the second NPU in a state of normal operation may receive the first PCIE data for processing.
In step S407, the fourth converting unit converts the first ethernet data into first PCIE data, and sends the first PCIE data to the second NPU based on the fourth PCIE bus.
Specifically, the fourth conversion unit is an integrated circuit chip capable of implementing mutual conversion between PCIE data and ethernet data, the first ethernet data may be converted back into the first PCIE data by the fourth conversion unit, and the fourth conversion unit sends the first PCIE data to the second NPU.
In step S409, the second NPU processes the first PCIE data.
Specifically, the second NPU is configured to process the first PCIE data, call the second NPU in a normal running state when the first NPU fails, so that data transmission between the first CPU and the second NPU may be completed, in practical application, the second NPU may process the first PCIE data, generate a corresponding control instruction, and send the corresponding instruction to an external device, for example, in a running process of an autopilot vehicle, the second NPU generates a display screen group control instruction and a camera group control instruction based on the first PCIE data, and sends the corresponding instruction to a display screen group and a camera group of the autopilot vehicle, so as to change working states of the display screen group and the camera group.
In the above embodiment, under the condition that the first NPU fails, the first CPU may send the first PCIE data to the second NPU, where the data sequentially passes through the first and fourth conversion units, is first converted into ethernet data, and then is converted back into PCIE data, and finally reaches the first NPU, so as to complete transmission, prevent the corresponding CPU from failing due to failure of the single NPU, affect the whole system, and improve stability of the system.
In an alternative embodiment, the method further comprises:
determining the total data bandwidth of the Ethernet switching chip;
allocating data bandwidth for the first virtual local area network and the second virtual local area network based on the total data bandwidth;
specifically, the first virtual local area network is a virtual local area network among the first CPU, the second NPU, the first conversion unit, the fourth conversion unit and the Ethernet switching chip; the second virtual local area network is a virtual local area network among the second CPU, the second NPU, the second conversion unit, the fourth conversion unit and the Ethernet switching chip.
In the above embodiment, because the forwarding capability of the ethernet switching chip is limited, the first virtual local area network is added to the data path between the first CPU and the second NPU, and the second virtual local area network is added to the data path between the second CPU and the second NPU, so that the two data paths do not preempt the data bandwidth or preempt the data transmission priority when transmitting data, thereby ensuring the data transmission delay and the transmission quality.
In an alternative embodiment, the method further comprises:
the logic detection unit generates a first fault signal under the condition that the first NPU breaks down;
the logic detection unit sends a first fault signal to the micro control unit;
the micro control unit sends a first switching instruction to the Ethernet switching chip based on the first fault signal so that the Ethernet switching chip forwards the first Ethernet data to the fourth conversion unit.
In the above embodiment, the logic detection unit may monitor the working state of the data transmission system in real time, and when the logic detection unit detects that the first NPU fails, send a first failure signal to the micro control unit, and based on the signal, the micro control unit sends a first switching instruction to the ethernet switching chip, and timely invokes the second NPU that can normally operate, thereby completing data transmission between the first CPU and the second NPU, and improving stability and security of the data transmission system.
Another embodiment of a data transmission method based on the above data transmission system is described below, as shown in fig. 5, and fig. 5 is a flowchart illustrating a data transmission method according to an exemplary embodiment, where the method may include the following steps:
In step S501, when the first CPU fails, the second CPU performs an operation on the first target transmission data to obtain first PCIE data, and sends the first PCIE data to the second conversion unit based on the second PCIE bus.
Specifically, under the condition that the first CPU fails, the first CPU and the first NPU are not directly connected through the PCIE bus due to isolation between the first conversion unit and the second conversion unit, so that normal operation of the corresponding first NPU is not affected when the first CPU fails, and at this time, the second CPU and the second NPU are still in a normal operation state, the second CPU may be invoked first, the second CPU performs operation on the first target transmission data to obtain first PCIE data, the first target transmission data may be AI visual algorithm data or video stream data, etc., the first PCIE data may be data that is generated by the second CPU based on the first target transmission data and transmitted through the PCIE bus, and after the first CPU performs operation on the first target transmission data to generate the first PCIE data, the first PCIE data is sent to the second conversion unit based on the second PCIE bus.
In step S503, the second converting unit converts the first PCIE data into first ethernet data, and sends the first ethernet data to the ethernet switching chip based on the corresponding ethernet bus.
Specifically, the second conversion unit is an integrated circuit chip capable of implementing mutual conversion between PCIE data and ethernet data, the first PCIE data may be converted into first ethernet data by the second conversion unit, and the second conversion unit sends the first ethernet data to the ethernet switching chip, and specifically, the ethernet switching chip is configured to forward the first ethernet data to the third conversion unit or the fourth conversion unit.
In step S505, the ethernet switching chip transmits the first ethernet data to the third conversion unit or the fourth conversion unit.
Specifically, under the condition that the first CPU fails, the first CPU and the first NPU are not directly connected through the PCIE bus, so that normal operation of the first NPU is not affected, and at this time, the first NPU and the second NPU in the data transmission system can both receive the first PCIE data, so that the second conversion unit converts the first PCIE data into first ethernet data, and sends the first ethernet data to the ethernet chip, and after the ethernet chip sends the first ethernet data to be forwarded by the first CPU to the third conversion unit, the ethernet switching chip can forward the first ethernet data to the third conversion unit or the fourth conversion unit, so that the first NPU in a normal operation state can receive the first PCIE data for processing, or the second NPU in a normal operation state can receive the first PCIE data for processing.
In step S507, the third converting unit converts the first ethernet data into first PCIE data, and sends the first PCIE data to the first NPU based on the third PCIE bus.
Specifically, the third conversion unit is an integrated circuit chip capable of implementing mutual conversion between PCIE data and ethernet data, the first ethernet data may be converted back into first PCIE data by the third conversion unit, and the third conversion unit sends the first PCIE data to the second NPU.
In step S509, the first NPU processes the first PCIE data.
Specifically, the first NPU is configured to process the first PCIE data, call the second CPU to generate the first PCIE data when the first CPU fails, and transmit the data to the first NPU in a normal running state to process the first PCIE data, so as to complete data transmission between the second CPU and the first NPU.
In step S511, the fourth converting unit converts the first ethernet data into first PCIE data, and sends the first PCIE data to the second NPU based on the fourth PCIE bus.
Specifically, the fourth conversion unit is an integrated circuit chip capable of implementing mutual conversion between PCIE data and ethernet data, the first ethernet data may be converted back into the first PCIE data by the fourth conversion unit, and the fourth conversion unit sends the first PCIE data to the second NPU.
In step S513, the second NPU processes the first PCIE data.
Specifically, the second NPU is configured to process the first PCIE data, and call the second CPU to generate the first PCIE data when the first CPU fails, and may further transmit the data to the second NPU in a normal running state to process the first PCIE data, so that data transmission between the second CPU and the second NPU is completed.
In the above embodiment, when the first CPU fails, the second CPU may send the first PCIE data to the first NPU, where the data sequentially passes through the first and third conversion units, is converted into ethernet data first, and then is converted back into PCIE data, and reaches the first NPU, so as to complete data transmission between the second CPU and the first NPU; or the second CPU can send the first PCIE data to the second NPU, the data sequentially pass through the second conversion unit and the fourth conversion unit, are firstly converted into Ethernet data and then are converted back into PCIE data, the Ethernet data reach the second NPU, the data transmission between the second CPU and the second NPU is completed, the failure of the corresponding NPU caused by the failure of the single CPU is prevented, the influence of the failure of the single CPU on the whole system is avoided, and the stability of the system is improved.
In an alternative embodiment, the method further comprises:
determining the total data bandwidth of the Ethernet switching chip;
allocating data bandwidths for the third virtual local area network and the fourth virtual local area network based on the total data bandwidth;
the third virtual local area network is a virtual local area network among the second CPU, the first NPU, the second conversion unit, the third conversion unit and the Ethernet switching chip; the fourth virtual local area network is a virtual local area network among the second CPU, the second NPU, the second conversion unit, the fourth conversion unit and the Ethernet switching chip.
In the embodiment, the third virtual local area network is additionally arranged on the data path from the second CPU to the first NPU, and the fourth virtual local area network is additionally arranged on the data path from the second CPU to the second NPU, so that the two data paths cannot mutually occupy the data bandwidth or the data transmission priority when transmitting data, and the data transmission delay and the transmission quality are ensured.
In an alternative embodiment, the method further comprises:
in case of failure of the first CPU, the logic detection unit generates a second failure signal;
the logic detection unit sends a second fault signal to the micro control unit;
the micro control unit sends a second switching instruction to the Ethernet switching chip based on the second fault signal so that the Ethernet switching chip forwards the first Ethernet data to the third conversion unit or the fourth conversion unit.
In the above embodiment, when the logic detection unit detects that the first CPU fails, the logic detection unit sends a second failure signal to the micro control unit, and the micro control unit sends a second switching instruction to the ethernet switching chip based on the second failure signal, so that the ethernet switching chip forwards the first ethernet data to the third switching unit or the fourth switching unit, so that the second CPU that normally operates can call the first NPU or the second NPU, thereby completing data transmission between the second CPU and the first NPU, or between the second CPU and the second NPU, and improving stability of the data transmission system.
In an alternative embodiment, the method further comprises:
in case of failure of the first CPU and the second CPU, the logic detection unit generates a third failure signal;
the logic detection unit sends a third fault signal to the micro control unit;
the micro control unit sends a restarting instruction to the Ethernet switching chip based on the third fault signal so as to restart the Ethernet switching chip;
the micro control unit sends a control instruction to the external device connected with the data transmission system based on the third fault signal so as to change the working state of the external device.
In the above embodiment, when the logic detection unit detects that both the first CPU and the second CPU are faulty, a third fault signal is sent to the micro control unit, and the micro control unit sends a restart instruction to the ethernet switch chip based on the third fault signal, so that the ethernet switch chip is restarted, and at the same time, the micro control unit sends a control instruction to the external device based on the third fault signal to change the working state of the external device, where the external device may be an autopilot vehicle, for example: the micro control unit sends a safe parking instruction to the automatic driving vehicle.
Taking an autopilot scenario as an example, an embodiment of a data transmission method based on the above data transmission system is described, as shown in fig. 6, fig. 6 is a schematic view of an application environment according to an exemplary embodiment, specifically, the data transmission system may be mounted on an autopilot vehicle that uses centralized domain control management of cabin driving, where the data transmission system may perform data communication with a display screen group and a first camera group of the autopilot vehicle through a first CPU and a second CPU, and perform data communication with a second camera group of the autopilot vehicle through a first NPU and a second NPU, and meanwhile, a micro control unit of the data transmission system may send a control command to a vehicle control unit (external device) of the autopilot vehicle to change a driving state of the autopilot vehicle.
Specifically, under the condition that each module is in a normal working state, the first CPU can receive first video data sent by the first camera group and generate first target transmission data based on the first video data, wherein the first video data can be front-view driving video data and side-view driving video data shot by the first camera group; further, the first CPU performs operation on the first target transmission data to obtain first PCIE data, and sends the first PCIE data to the first conversion unit based on the first PCIE bus; further, the first conversion unit converts the first PCIE data into first ethernet data, and sends the first ethernet data to the ethernet switching chip based on the corresponding ethernet bus; the first switching unit is used for converting the first Ethernet data into first PCIE data, sending the first PCIE data to the first NPU based on the third PCIE bus, receiving the first PCIE data by the first NPU, thereby completing data transmission between the first CPU and the first NPU, and simultaneously, processing the received first PCIE data by the first NPU, wherein in practical application, the first NPU processes the first PCIE data, can generate working data (fourth Ethernet data) and feeds back the working data to the first CPU through a corresponding Ethernet bus, so that the first CPU generates corresponding control instructions and sends corresponding control instructions to an automatic driving vehicle, for example, in the driving process of the automatic driving vehicle, the first CPU generates a first camera group control instruction based on the fourth Ethernet data and sends the first camera group control instruction to the first camera group of the automatic driving vehicle, so as to change the working state of the first camera group;
Correspondingly, the second CPU can receive second video data sent by the second camera group and display screen data sent by the display screen group, and generate second target transmission data, wherein the second video data can be all-round driving video data, parking driving video data and in-cabin video data shot by the second camera group; further, the second CPU performs operation on the second target transmission data to obtain second PCIE data, and sends the second PCIE data to the second conversion unit based on the second PCIE bus; the second conversion unit converts the second PCIE data into sixth Ethernet data and sends the sixth Ethernet data to the Ethernet switch chip based on the corresponding Ethernet bus; further, the ethernet switching chip transmits the sixth ethernet data to the fourth conversion unit, so that the fourth conversion unit converts the sixth ethernet data into the second PCIE data, and sends the second PCIE data to the second NPU based on the fourth PCIE bus, the second NPU receives the second PCIE data to complete data transmission between the second CPU and the second NPU, and at the same time, the second NPU processes the second PCIE data, in practical application, the second NPU may process the second PCIE data, generate working data (fifth ethernet data) and feed back the working data to the second CPU through the corresponding ethernet bus, so that the second CPU generates a corresponding control instruction and sends a corresponding instruction to the autonomous driving vehicle, for example, in a driving process of the autonomous driving vehicle, the second CPU generates a second camera group control instruction and a display screen control instruction based on the fifth ethernet data fed back by the first NPU, and sends a corresponding instruction group to the second camera group and the display screen group of the autonomous driving vehicle, so as to change a working state of the second camera group and the display screen group.
Through the method, under the condition that each module is in a normal working state, data transmission is carried out between the first CPU and the first NPU, AI operation processing can be carried out on forward-looking and side-looking driving videos of the automatic driving vehicle, data transmission is carried out between the second CPU and the second NPU, AI operation processing can be carried out on data of the video and the display screen in the surrounding, parking and driving cabins of the automatic driving vehicle, the data to be processed are transmitted by utilizing two data paths, and the local resources are reasonably allocated and utilized, so that the data transmission efficiency is improved.
Optionally, determining the total data bandwidth of the ethernet switching chip under the condition that each module is in a normal working state; allocating data bandwidth for the fifth virtual local area network and the sixth virtual local area network based on the total data bandwidth; the fifth virtual local area network is a virtual local area network among the first CPU, the first NPU, the first conversion unit, the third conversion unit and the Ethernet switching chip; the sixth virtual local area network is a virtual local area network among the second CPU, the second NPU, the second conversion unit, the fourth conversion unit and the Ethernet switching chip.
Optionally, when the first NPU fails, the logic detecting unit generates a first failure signal and sends the first failure signal to the micro control unit, and the micro control unit sends a first switching instruction to the ethernet switching chip based on the first failure signal, so that the ethernet switching chip forwards the first ethernet data to the fourth switching unit, the first CPU sends first PCIE data to the second NPU, the data may sequentially pass through the first and fourth switching units, and is firstly converted into ethernet data and then converted back into the first PCIE data, and finally reaches the first NPU to complete data transmission between the first CPU and the second NPU, and meanwhile, the second CPU may send second PCIE data to the second NPU, and the data sequentially passes through the second and fourth switching units, is firstly converted into ethernet data and then converted back into second PCIE data, reaches the second NPU to complete data transmission between the first CPU and the second NPU, and is correspondingly responsible for processing the first PCIE data and the second PCIE data;
Further, a first virtual local area network is additionally arranged on a data path between the first CPU and the second NPU, and a second virtual local area network is additionally arranged on a data path between the second CPU and the second NPU, so that the two data paths cannot mutually occupy data bandwidth or data transmission priority when transmitting data, and data transmission delay and transmission quality are ensured.
Optionally, when the first CPU fails, the logic detecting unit generates a second failure signal and sends the second failure signal to the micro control unit, and the micro control unit sends a second switching instruction to the ethernet switching chip based on the second failure signal, so that the ethernet switching chip forwards the first ethernet data to the third switching unit, the second CPU sends first PCIE data to the first NPU, the data sequentially passes through the first switching unit and the third switching unit, and is firstly converted into ethernet data and then is converted back into the first PCIE data, so as to reach the first NPU, complete data transmission between the second CPU and the first NPU, and meanwhile, the second CPU can send second PCIE data to the second NPU, and the data sequentially passes through the second switching unit and the fourth switching unit, is firstly converted into ethernet data and then is converted back into second PCIE data, so as to reach the second NPU, complete data transmission between the second CPU and the second NPU, and the first NPU is correspondingly responsible for processing the received first PCIE data, and the second NPU is responsible for processing the received second PCIE data;
Or under the condition that the first CPU fails, the logic detection unit generates a second failure signal and sends the second failure signal to the micro control unit, the micro control unit sends a second switching instruction to the Ethernet switching chip based on the second failure signal, so that the Ethernet switching chip forwards the first Ethernet data to the fourth conversion unit, the second CPU can send first PCIE data to the second NPU, the data sequentially passes through the second conversion unit and the fourth conversion unit, the data are firstly converted into Ethernet data and then are converted back into the first PCIE data, the first PCIE data reaches the second NPU, the data transmission between the second CPU and the second NPU is completed, meanwhile, the second CPU can send second PCIE data to the second NPU, the data sequentially passes through the second conversion unit and the fourth conversion unit, the data are firstly converted into Ethernet data and then are converted back into second PCIE data, the second NPU is reached, and data transmission between the second CPU and the second NPU is completed, and the second NPU is correspondingly responsible for processing the first PCIE data and the second PCIE data;
further, a third virtual local area network is additionally arranged on a data path from the second CPU to the first NPU, and a fourth virtual local area network is additionally arranged on a data path from the second CPU to the second NPU, so that the two data paths cannot mutually occupy data bandwidth or data transmission priority when transmitting data, and data transmission delay and transmission quality are guaranteed.
In the above embodiment, on the one hand, the PCIE bus that easily causes a single point of failure may be isolated by using an ethernet conversion manner to implement isolation of each main functional module, so that the influence caused by failure of a single functional module on other functional modules is reduced, and the modules are further decoupled, so as to ensure stable data transmission.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (10)

1. A data transmission system, the system comprising:
the system comprises a first CPU, a second CPU, a first neutral network processor NPU, a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit and an Ethernet switching chip; the first conversion unit, the second conversion unit, the third conversion unit and the fourth conversion unit are respectively connected with the Ethernet switching chip based on the respectively corresponding Ethernet buses; the first CPU is connected with the first conversion unit based on a first high-speed serial computer expansion bus standard PCIE bus, the second CPU is connected with the second conversion unit based on a second PCIE bus, the first NPU is connected with the third conversion unit based on a third PCIE bus, and the second NPU is connected with the fourth conversion unit based on a fourth PCIE bus;
under the condition that the first NPU fails, the first CPU is used for calculating first target transmission data to obtain first PCIE data; the first conversion unit is configured to convert the first PCIE data into first ethernet data, and the ethernet switching chip is configured to transmit the first ethernet data to the fourth conversion unit; the fourth conversion unit is configured to convert the first ethernet data into the first PCIE data, and the second NPU is configured to process the first PCIE data;
Under the condition that the first CPU fails, the second CPU is used for calculating the first target transmission data to obtain the first PCIE data; the second conversion unit is configured to convert the first PCIE data into the first ethernet data, the ethernet switching chip is further configured to transmit the first ethernet data to the third conversion unit or the fourth conversion unit, the third conversion unit is configured to convert the first ethernet data into the first PCIE data, and the first NPU is configured to process the first PCIE data; or the fourth conversion unit is configured to convert the first ethernet data into the first PCIE data, and the second NPU is configured to process the first PCIE data.
2. The system of claim 1, wherein the system further comprises:
the first CPU is connected with the Ethernet switching chip based on a corresponding Ethernet bus, and is further used for sending second Ethernet data to the first NPU or the second NPU, and the data bandwidth of the second Ethernet data is smaller than that of the first Ethernet data;
the second CPU is connected with the Ethernet switching chip based on a corresponding Ethernet bus, and is further used for sending third Ethernet data to the first NPU or the second NPU, and the bandwidth of the third Ethernet data is smaller than that of the first Ethernet data;
The first NPU is connected with the Ethernet switching chip based on a corresponding Ethernet bus, and is also used for sending fourth Ethernet data to the first CPU or the second CPU, wherein the fourth Ethernet data is working data fed back to the first CPU or the second CPU by the first NPU;
the second NPU is connected with the Ethernet switching chip based on a corresponding Ethernet bus, and is further used for sending fifth Ethernet data to the first CPU or the second CPU, wherein the fifth Ethernet data is working data fed back to the first CPU or the second CPU by the second NPU.
3. The system of claim 1, wherein the system further comprises:
the logic detection unit is respectively connected with the first CPU, the second CPU, the first NPU and the second NPU, and is used for generating a first fault signal when the first NPU breaks down and sending the first fault signal to the micro control unit, or is used for generating a second fault signal when the first CPU breaks down and sending the second fault signal to the micro control unit, or is used for generating a third fault signal when the first CPU and the second CPU break down and sending the third fault signal to the micro control unit;
The micro control unit is connected with the Ethernet switch chip, and is used for sending a first switching instruction to the Ethernet switch chip based on the first fault signal so that the Ethernet switch chip forwards the first Ethernet data to the fourth switching unit, or is used for sending a second switching instruction to the Ethernet switch chip based on the second fault signal so that the Ethernet switch chip forwards the first Ethernet data to the third switching unit or the fourth switching unit, or is used for sending a control instruction to an external device connected with the data transmission system based on the third fault signal so as to change the working state of the external device, and sending a restarting instruction to the Ethernet switch chip so that the Ethernet switch chip is restarted.
4. A data transmission method based on the data transmission system according to any one of claims 1 to 3, characterized in that the method comprises:
the first CPU performs operation on the first target transmission data to obtain first PCIE data, and sends the first PCIE data to the first conversion unit based on the first PCIE bus;
The first conversion unit converts the first PCIE data into first Ethernet data and sends the first Ethernet data to an Ethernet switching chip based on a corresponding Ethernet bus;
the Ethernet switching chip transmits the first Ethernet data to a fourth conversion unit under the condition that a first NPU fails;
the fourth conversion unit converts the first ethernet data into the first PCIE data, and sends the first PCIE data to the second NPU based on a fourth PCIE bus;
and the second NPU processes the first PCIE data.
5. The method according to claim 4, wherein the method further comprises:
determining the total data bandwidth of the Ethernet switching chip;
allocating data bandwidths for the first virtual local area network and the second virtual local area network based on the total data bandwidth;
the first virtual local area network is a virtual local area network among the first CPU, the second NPU, the first conversion unit, the fourth conversion unit and the Ethernet switching chip; the second virtual local area network is a virtual local area network among a second CPU, the second NPU, a second conversion unit, the fourth conversion unit and the Ethernet switching chip.
6. The method according to claim 4, wherein the method further comprises:
the logic detection unit generates a first fault signal under the condition that the first NPU breaks down;
the logic detection unit sends the first fault signal to the micro control unit;
and the micro control unit sends a first switching instruction to the Ethernet switching chip based on the first fault signal so that the Ethernet switching chip forwards the first Ethernet data to the fourth conversion unit.
7. A data transmission method based on the data transmission system according to any one of claims 1 to 3, characterized in that the method comprises:
under the condition that a first CPU fails, a second CPU calculates first target transmission data to obtain first PCIE data, and sends the first PCIE data to a second conversion unit based on a second PCIE bus;
the second conversion unit converts the first PCIE data into first Ethernet data and sends the first Ethernet data to an Ethernet switching chip based on a corresponding Ethernet bus;
the Ethernet switching chip transmits the first Ethernet data to a third conversion unit or a fourth conversion unit;
The third conversion unit converts the first ethernet data into the first PCIE data, and sends the first PCIE data to the first NPU based on a third PCIE bus;
the first NPU processes the first PCIE data;
the fourth conversion unit converts the first ethernet data into the first PCIE data, and sends the first PCIE data to the second NPU based on a fourth PCIE bus;
and the second NPU processes the first PCIE data.
8. The method of claim 7, wherein the method further comprises:
determining the total data bandwidth of the Ethernet switching chip;
allocating data bandwidths for the third virtual local area network and the fourth virtual local area network based on the total data bandwidth;
the third virtual local area network is a virtual local area network among the second CPU, the first NPU, the second conversion unit, the third conversion unit and the Ethernet switching chip; the fourth virtual local area network is a virtual local area network among the second CPU, the second NPU, the second conversion unit, the fourth conversion unit and the Ethernet switching chip.
9. The method of claim 7, wherein the method further comprises:
The logic detection unit generates a second fault signal under the condition that the first CPU fails;
the logic detection unit sends the second fault signal to the micro control unit;
and the micro control unit sends a second switching instruction to the Ethernet switching chip based on the second fault signal so that the Ethernet switching chip forwards the first Ethernet data to the third conversion unit or the fourth conversion unit.
10. The method of claim 7, wherein the method further comprises:
in the case that the first CPU and the second CPU fail, the logic detection unit generates a third failure signal;
the logic detection unit sends the third fault signal to the micro control unit;
the micro control unit sends a restarting instruction to the Ethernet switching chip based on the third fault signal so as to restart the Ethernet switching chip;
and the micro control unit sends a control instruction to external equipment connected with the data transmission system based on the third fault signal so as to change the working state of the external equipment.
CN202310194139.3A 2023-02-28 2023-02-28 Data transmission system and method Pending CN116383118A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116701287A (en) * 2023-08-09 2023-09-05 西安甘鑫科技股份有限公司 PCIE-based multi-device compatible device expansion method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116701287A (en) * 2023-08-09 2023-09-05 西安甘鑫科技股份有限公司 PCIE-based multi-device compatible device expansion method
CN116701287B (en) * 2023-08-09 2023-12-08 西安甘鑫科技股份有限公司 PCIE-based multi-device compatible device expansion method

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